HMT112U7AFR6C-H8 - SK Hynix

Rev. 0.1 / Dec 2008 1

240pin DDR3 SDRAM Unbuffered DIMMs

** Contents are subject to change without prior notice.

DDR3 SDRAM Unbuffered DIMMs

Based on 1Gb A version

HMT164U6AFP(R)6C

HMT112U6AFP(R)8C

HMT112U7AFP(R)8C

HMT125U6AFP(R)8C

HMT125U7AFP(R)8C

Rev. 0.1 / Dec 2008 2

HMT164U6AFP(R)6C

HMT112U6(7)AFP(R)8C

HMT125U6(7)AFP(R)8C

Revision History

Revision No. History Draft Date Remark

0.01 Initial draft for internal review Nov. 2007 Preliminary

0.02 Added IDD & Halogen-free products Mar. 2008 Preliminary

0.1 Initial Specification Release.

Corrected typo on package ball feature. Dec 2008

Rev. 0.1 / Dec 2008 3

HMT164U6AFP(R)6C

HMT112U6(7)AFP(R)8C

HMT125U6(7)AFP(R)8C

Table of Contents

1. Description

1.1 Device Features and Ordering Information

1.1.1 Features

1.1.2 Ordering Information

1.2 Speed Grade & Key Parameters

1.3 Address Table

2. Pin Architecture

2.1 Pin Definition

2.2 Input/Output Functional Description

2.3 Pin Assignment

3. Functional Block Diagram

3.1 512MB, 64Mx64 Module(1Rank of x16)

3.2 1GB, 128Mx64 Module(1Rank of x8)

3.3 1GB, 128Mx72 ECC Module(1Rank of x8)

3.4 2GB, 256Mx64 Module(2Rank of x8)

3.5 2GB, 256Mx72 ECC Module(2Rank of x8)

4. Address Mirroring Feature

4.1 DRAM Pin Wiring for Mirroring

5. Absolute Maximum Ratings

5.1 Absolute Maximum DC Ratings

5.2 Operating Temperature Range

6. AC & DC Operating Conditions

6.1 Recommended DC Operating Conditions

6.2 DC & AC Logic Input Levels

6.2.1 For Single-ended Signals

6.2.2 For Differential Signals

6.2.3 Differential Input Cross Point

6.3 Slew Rate Definition

6.3.1 For Ended Input Signals

6.3.2 For Differential Input Signals

6.4 DC & AC Output Buffer Levels

6.4.1 Single Ended DC & AC Output Levels

6.4.2 Differential DC & AC Output Levels

6.4.3 Single Ended Output Slew Rate

6.4.4 Differential Ended Output Slew Rate

6.5 Overshoot/Undershoot Specification

6.6 Input/Output Capacitance & AC Parametrics

6.7 IDD Specifications & Measurement Conditions

7. Electrical Characteristics and AC Timing

7.1 Refresh Parameters by Device Density

7.2 DDR3 Standard speed bins and AC para

8. DIMM Outline Diagram

8.1 512MB, 64Mx64 Module(1Rankx16)

8.2 1GB, 128Mx64 Module(1Rank of x8)

8.3 1GB, 128Mx72 ECC Module(1Rank of x8)

8.4 2GB, 256Mx64 Module(2Rank of x8)

8.5 2GB, 256Mx72 ECC Module(2Rank of x8)

Rev. 0.1 / Dec 2008 4

HMT164U6AFP(R)6C

HMT112U6(7)AFP(R)8C

HMT125U6(7)AFP(R)8C

1. Description

This Hynix unbuffered Dual In-Line Memory Module(DIMM) series consists of 1Gb A version. DDR3 SDRAMs in Fine

Ball Grid Arr ay(FBGA) packages on a 240 pin glass-epoxy substrate. This DDR3 Unbuffe red DIMM series based on 1Gb

A ver. provide a high performance 8 byte interface in 133.35mm width form factor of industry standard. It is suitable

for easy interchange and addition.

1.1 Device Features & Ordering Information

1.1.1 Features

• VDD=VDDQ=1.5V

• VDDSPD=3.3V to 3.6V

• Fully differential clock inputs (CK, /CK) operation

• Differential Data Strobe (DQS, /DQS)

• On chip DLL align DQ, DQS and /DQS transition with

CK tr ansitio n

• DM masks write data-in at the both rising and falling

edges of the data strobe

• All addresses and control inputs except data, data

strobes and data masks latched on the rising edges of

the clock

• Programmable CAS latency 5, 6, 7 , 8, 9, 10, and (11)

supported

• Programmabl e a d dit i ve l a tency 0 , C L-1, and C L- 2 sup

ported

• Programmable CAS Write latency (CWL) = 5, 6, 7, 8

• Programmable burst length 4/8 with both nibble

sequential and interleave mode

• BL switch on the fly

• 8banks

• 8K refresh cycles /64ms

• DDR3 SDRAM Package: JEDEC standard 78ball

FBGA(x4/x8), 96ball FBGA(x16) with support balls

• Driver strength selected by EMRS

• Dynamic On Die Termination supported

• Asynchronous RESET pin supported

• ZQ calibration supported

• TDQS (Termination Data Strobe) supported (x8 only)

• Write Levelization supported

• Auto Self Refresh supported

• On Die Thermal Sensor supported (JEDEC optional)

Rev. 0.1 / Dec 2008 5

HMT164U6AFP(R)6C

HMT112U6(7)AFP(R)8C

HMT125U6(7)AFP(R)8C

1.1.2 Ordering Information

Part Name Density Org. # of

DRAMs # of

ranks Materials ECC TS

HMT164U6AFP6C-S6/S5/G8/G7/H9/H8 512MB 64Mx64 4 1 Lead-free None No

HMT164U6AFR6C-S6/S5/G8/G7/H9/H8 512MB 64Mx64 4 1 Halogen-free None No

HMT112U6AFP8C-S6/S5/G8/G7/H9/H8 1GB 128Mx64 8 1 Lead free None No

HMT112U6AFR8C-S6/S5/G8/G7/H9/H8 1GB 128Mx64 8 1 Halogen-free None No

HMT112U7AFP8C-S6/S5/G8/G7/H9/H8 1GB 128Mx72 9 1 Lead free ECC Yes

HMT112U7AFR8C-S6/S5/G8/G7/H9/H8 1GB 128Mx72 9 1 Halogen-free ECC Yes

HMT125U6AFP8C-S6/S5/G8/G7/H9/H8 2GB 256Mx64 16 2 Lead free None No

HMT125U6AFR8C-S6/S5/G8/G7/H9/H8 2GB 256Mx64 16 2 Halogen-free None No

HMT125U7AFP8C-S6/S5/G8/G7/H9/H8 2GB 256Mx72 18 2 Lead free ECC Yes

HMT125U7AFR8C-S6/S5/G8/G7/H9/H8 2GB 256Mx72 18 2 Halogen-free ECC Yes

Rev. 0.1 / Dec 2008 6

HMT164U6AFP(R)6C

HMT112U6(7)AFP(R)8C

HMT125U6(7)AFP(R)8C

1.2 Speed Grade & Key Parameters

1.3 Address Table

MT/S DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Unit

Grade -S6 -S5 -G8 -G7 -H9 -H8 -P1 -P9

tCK(min) 2.5 1.875 1.5 1.25 ns

CAS Latency 658798109tCK

tRCD(min) 15 12.5 15 13.125 13.5 12 12.5 11.25 ns

tRP(min) 15 12.5 15 13.125 13.5 12 12.5 11.25 ns

tRAS(min) 37.5 37.5 37.5 37.5 36 36 35 35 ns

tRC(min) 52.5 50 52.5 50.625 49.5 48 47.25 46.25 ns

CL-tRCD-tRP 6-6-6 5-5-5 8-8-8 7-7-7 9-9-9 8-8-8 10-10-10 9-9-9 tCK

512MB 1GB 1GB 2GB 2GB

Organization 64M x 64 128M x 64 128M x 72 256M x 64 256M x 72

Refresh Method 8K/64ms 8K/64ms 8K/64ms 8K/64ms 8K/64ms

Row Address A0-A12 A0-A13 A0-A13 A0-A13 A0-A13

Column Address A0-A9 A0-A9 A0-A9 A0-A9 A0-A9

Bank Address BA0-BA2 BA0-BA2 BA0-BA2 BA0-BA2 BA0-BA2

Page Size 2KB 1KB 1KB 1KB 1KB

# of Rank 11122

# of Device 4 8 9 16 18

Rev. 0.1 / Dec 2008 7

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HMT112U6(7)AFP(R)8C

HMT125U6(7)AFP(R)8C

2. Pin Architecture

2.1 Pin Definition

Pin Name Description Pin Name Description

A0–A13 SDRAM address bus SCL I2C serial bus clock for EEPROM

BA0–BA2 SDRAM bank select SDA I2C serial bus data line for EEPROM

RAS SDRAM row address strobe SA0–SA2 I2C slave address select for EEPROM

CAS SDRAM column address strobe VDD*SDRAM core power supply

WE SDRAM write enable VDDQ*SDRAM I/O Driver power supply

S0–S1 DIMM Rank Select Lines VREFDQ SDRAM I/O reference supply

CKE0–CKE1 SDRAM clock enable lines VREFCA SDRAM command/address reference

supply

ODT0–ODT1 On-die termination control lines VSS Power supply return (ground)

DQ0–DQ63 DIMM memory data bus VDDSPD Serial EEPROM positive power supply

CB0–CB7 DIMM ECC check bits NC Spare pins (no connect)

DQS0–DQS8 SDRAM data strobes

(positive line of differential pair) TEST Memory bus analysis tools

(unused on memory DIMMS)

DQS0–DQS8SDRAM data strobes

(negative line of differential pair) RESET Set DRAMs to Known State

DM0–DM8 SDRAM data masks/high data strobes

(x8-based x72 DIMMs)

SDRAM I/O termination supply

CK0–CK1 SDRAM clocks

(positive line of differential pair) RFU Reserved for future use

CK0–CK1SDRAM clocks

(negative line of differential pair) - -

*The VDD and VDDQ pins are tied common to a single power-plane on these designs

Rev. 0.1 / Dec 2008 8

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HMT112U6(7)AFP(R)8C

HMT125U6(7)AFP(R)8C

2.2 Input/Output Functional Description

Symbol Type Polarity Function

CK0–CK1

CK0–CK1SSTL Differential

crossing

CK and CK are differential clock inputs. All the DDR3 SDRAM addr/cntl

inputs are sampled on the crossing of positive edge of CK and negative

edge of CK. Output (read) data is reference to the crossing of CK and CK

(Both directions of crossing).

CKE0–CKE1 SSTL Active High Activates the SDRAM CK signal when high and deactivates the CK signal

when low. By deactivating the clocks, CKE low initiates the Power Down

mode, or the Self Refresh mode.

S0–S1SSTLActive Low

Enables the associated SDRAM command decoder when low and disables

the command decoder when high. When the command decoder is dis-

abled, new commands are ignored but previous operations continue. This

signal provides for external rank selection on systems with multiple ranks.

RAS, CAS, WE SSTL Active Low RAS, CAS, and WE (ALONG WITH S) define the command being entered.

ODT0–ODT1 SSTL Active High When high, termination resistance is enabled for all DQ, DQS, DQS and DM

pins, assuming this function is enabled in the Mode Register 1 (MR1).

VREFDQ Supply Reference voltage for SSTL15 I/O inputs.

VREFCA Supply Reference voltage for SSTL 15 command/address inputs.

VDDQ Supply Power supply for the DDR3 SDRAM output buffers to provide improved

noise immunity. For all current DDR3 unbuffered DIMM designs, VDDQ

shares the same power plane as VDD pins.

BA0–BA2 SSTL — Selects which SDRAM ba nk of eight is activated.

A0–A13 SSTL —

During a Bank Activate command cycle, Address input defines the row

address (RA0–RA15).

During a Read or Write command cycle, Address input defines the column

address. In addition to the column address, AP is used to invoke autopre-

charge operation at the end of the burst read or write cycle. If AP is high,

autoprecharge is selected and BA0, BA1, BA2 defines the bank to be pre-

charged. If AP is low, autoprecharge is disabled. During a Precharge com-

mand cycle, AP is used in conjunction with BA0, BA1, BA2 to control which

bank(s) to precharge. If AP is high, a ll banks will be precharged regardles s

of the state of BA0, BA1 or BA2. If AP is low, BA0, BA1 and BA2 are used to

define which bank to precharge. A12(BC) is sampled during READ and

WRITE commands to determine if burst chop (on-the-fly) will be per-

formed (HIGH, no burst chop; LOW, burst chopped).

DQ0–DQ63,

CB0–CB7 SSTL — Data and Check Bit Input/Output pins.

DM0–DM8 SSTL Active High

DM is an input mask signal for write data. Input data is masked when DM

is sampled High coincident with that input data during a write access. DM

is sampled on both edges of DQS. Although DM pins are inpu t only, the DM

loading matches the DQ and DQS loading.

VDD, VSS Supply Power and ground for the DDR3 SDRAM input buffers, and core logic. VDD

and VDDQ pins are tied to VDD/VDDQ planes on these modules.

Rev. 0.1 / Dec 2008 9

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HMT112U6(7)AFP(R)8C

HMT125U6(7)AFP(R)8C

2.3 Pin Assignment

DQS0–DQS8

DQS0–DQS8SSTL Differential

crossing Data strobe for input and output data.

SA0–SA2 — These signals are tied at the system planar to either VSS or VDDSPD to con-

figure the serial SPD EEPROM address range.

SDA — This bidirectional pin is used to transfer data into or out of the SPD

EEPROM. An external resistor may be connected from the SDA bus line to

VDDSPD to act as a pullup on the system board.

SCL — This signal is used to clock data into and out of the SPD EEPROM. An

external resistor may be connected from the SCL bus time to V DDSPD to act

as a pullup on the system board.

VDDSPD Supply Power supply for SPD EEP ROM. This supply is sep arate from the VDD/VDDQ

power plane. EEPROM supply is operable from 3.0V to 3.6V.

Front Side(left 1–60) Back Side(right 121–180) Front Side(left 61–120) Back Side(right 181–240)

#x64

Non-ECC x72

ECC Pin

#x64

Non-ECC x72

ECC Pin

#x64

Non-ECC x72

ECC Pin

#x64

Non-ECC x72

ECC

REFDQ VREFDQ 121

61 A2 A2 181 A1 A1

122 DQ4 DQ4 62 VDD VDD 182 VDD VDD

3 DQ0 DQ0 123 DQ5 DQ5 63 CK1 CK1 183 VDD VDD

4DQ1 DQ1124

64 CK1CK1184 CK0 CK0

125 DM0 DM0 65 VDD VDD 185 CK0CK0

6DQS0DQS0 126 NC NC 66 VDD VDD 186 VDD VDD

7 DQS0 DQS0 127

67 VREFCA VREFCA 187 NC NC

128 DQ6 DQ6 68 NC NC 188 A0 A0

9 DQ2 DQ2 129 DQ7 DQ7 69 VDD VDD 189 VDD VDD

10 DQ3 DQ3 130

70 A10 A10 190 BA12BA12

131 DQ12 DQ12 71 BA02BA02191 VDD VDD

12 DQ8 DQ8 132 DQ13 DQ13 72 VDD VDD 192 RAS RAS

13 DQ9 DQ9 133

73 WE WE 193 S0S0

134 DM1 DM1 74 CAS CAS 194 VDD VDD

15 DQS1DQS1 135 NC NC 75 VDD VDD 195 ODT0 ODT0

16 DQS1 DQS1 136

76 S1 S1 196 A13 A13

NC = No Connect; RFU = Reserved Future Use

1. NC pins should not be connected to anything on the DIMM, including bussing within the NC group.

2. Address pins A3–A8 and BA0 and BA1 can be mirrored or not mirrored. Please refer to Section 4.1 for more

information on mirrored addresses.

Symbol Type Polarity Function

Rev. 0.1 / Dec 2008 10

HMT164U6AFP(R)6C

HMT112U6(7)AFP(R)8C

HMT125U6(7)AFP(R)8C

137 DQ14 DQ14 77 ODT1 ODT1 197 VDD VDD

18 DQ10 DQ10 138 DQ15 DQ15 78 VDD VDD 198 NC NC

19 DQ11 DQ11 139

79 NC NC 199

140 DQ20 DQ20 80

200 DQ36 DQ36

21 DQ16 DQ16 141 DQ21 DQ21 81 DQ32 DQ32 201 DQ37 DQ37

22 DQ17 DQ17 142

82 DQ33 DQ33 202

143 DM2 DM2 83

203 DM4 DM4

24 DQS2DQS2144 NC NC 84 DQS4DQS4 204 NC NC

25 DQS2 DQS2 145

85 DQS4 DQS4 205

146 DQ22 DQ22 86

206 DQ38 DQ38

27 DQ18 DQ18 147 DQ23 DQ23 87 DQ34 DQ34 207 DQ39 DQ39

28 DQ19 DQ19 148

88 DQ35 DQ35 208

149 DQ28 DQ28 89

209 DQ44 DQ44

30 DQ24 DQ24 150 DQ29 DQ29 90 DQ40 DQ40 210 DQ45 DQ45

31 DQ25 DQ25 151

91 DQ41 DQ41 211

152 DM3 DM3 92

212 DM5 DM5

33 DQS3DQS3 153 NC NC 93 DQS5DQS5 213 NC NC

34 DQS3 DQS3 154

94 DQS5 DQS5 214

155 DQ30 DQ30 95

215 DQ46 DQ46

36 DQ26 DQ26 156 DQ31 DQ31 96 DQ42 DQ42 216 DQ47 DQ47

37 DQ27 DQ27 157

97 DQ43 DQ43 217

158 NC CB4 98

218 DQ52 DQ52

39 NC CB0 159 NC CB5 99 DQ48 DQ48 219 DQ53 DQ53

40 NC CB1 160

100 DQ49 DQ49 220

161 DM8 DM8 101

221 DM6 DM6

42 NC DQS8 162 NC NC 102 DQS6DQS6 222 NC NC

43 NC DQS8 163

103 DQS6 DQS6 223

164 NC CB6 104

224 DQ54 DQ54

45 NC CB2 165 NC CB7 105 DQ50 DQ50 225 DQ55 DQ55

46 NC CB3 166

106 DQ51 DQ51 226

167 NC NC 107

227 DQ60 DQ60

Front Side(left 1–60) Back Side(right 121–180) Front Side(left 61–120) Back Side(right 181–240)

#x64

Non-ECC x72

ECC Pin

#x64

Non-ECC x72

ECC Pin

#x64

Non-ECC x72

ECC Pin

#x64

Non-ECC x72

ECC

NC = No Connect; RFU = Reserved Future Use

1. NC pins should not be connected to anything on the DIMM, including bussing within the NC group.

2. Address pins A3–A8 and BA0 and BA1 can be mirrored or not mirrored. Please refer to Section 4.1 for more

information on mirrored addresses.

Rev. 0.1 / Dec 2008 11

HMT164U6AFP(R)6C

HMT112U6(7)AFP(R)8C

HMT125U6(7)AFP(R)8C

48 NC NC 168 Reset Reset 108 DQ56 DQ56 228 DQ61 DQ61

KEY KEY 109 DQ57 DQ57 229

49 NC NC 169 CKE1/NC CKE1/NC 110

230 DM7 DM7

50 CKE0 CKE0 170 VDD VDD 111 DQS7DQS7 231 NC NC

51 VDD VDD 171 NC NC 112 DQS7 DQS7 232

52 BA2 BA2 172 NC NC 113

233 DQ62 DQ62

53 NC NC 173 VDD VDD 114 DQ58 DQ58 234 DQ63 DQ63

54 VDD VDD 174 A12 A12 115 DQ59 DQ59 235

55 All All 175 A9 A9 116

236 VDDSPD VDDSPD

56 A72A72176 VDD VDD 117 SA0 SA0 237 SA1 SA1

57 VDD VDD 177 A82A82118 SCL SCL 238 SDA SDA

58 A52A52178 A62A62119

SA2 SA2

239

59 A42A42179 VDD VDD 120 VTT VTT 240 VTT VTT

60 VDD VDD 180 A32A32

Front Side(left 1–60) Back Side(right 121–180) Front Side(left 61–120) Back Side(right 181–240)

#x64

Non-ECC x72

ECC Pin

#x64

Non-ECC x72

ECC Pin

#x64

Non-ECC x72

ECC Pin

#x64

Non-ECC x72

ECC

NC = No Connect; RFU = Reserved Future Use

1. NC pins should not be connected to anything on the DIMM, including bussing within the NC group.

2. Address pins A3–A8 and BA0 and BA1 can be mirrored or not mirrored. Please refer to Section 4.1 for more

information on mirrored addresses.

Rev. 0.1 / Dec 2008 12

HMT164U6AFP(R)6C

HMT112U6(7)AFP(R)8C

HMT125U6(7)AFP(R)8C

3. Functional Block Diagram

3.1 512MB, 64Mx64 Module(1Rank of x16)

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

I/O 0

I/O 1

I/O 2

I/O 3

DM0

I/O 4

I/O 5

I/O 6

I/O 7

DQ12

DQ13

DQ14

DQ8

DQ9

DQ10

DQ11

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

DM1

A0–A14 A0–A14: SDRAMs D0–D3 A0

Serial PD

SA0 SA1

SDA

RAS RAS: SDRAMs D0–D3

CAS CAS: SDRAMs D0–D3

CKE0 CKE: SDRAMs D0–D3

WE WE: SDRAMs D0–D3

BA0–BA2 BA0–BA2: SDRAMs D0–D3

DQS0

DQS1

DQ15 I/O 15

D0–D3

REF

Notes:

1. DQ-to-I/O wiring is show n as recom-

mended but may be changed.

2. DQ/DQS/DQS/ODT/DM/CKE/S relation-

ships must be maintained as shown.

3. DQ,DM,DQS,DQS resistors;Refer to asso-

ciated topology diagram.

4. Refer to the appropriate clock wiring

topology under the DIMM wiring detai ls

section of this document.

5. The pair CK1 and CK1# is terminated in

75ohm but is not used on the modul e.

6. A15 is not routed on the module.

7. For each DRAM, a unique ZQ resistor is

connected to ground.The ZQ resistor is

240ohm+-1%

8. One SPD exists per module.

SCL WP

SPD

DDSPD

ODT0

DQS0

DQS1

ODT: SDRAMs D0–D3

CK0 CK: SDRAMs D0–D3

SA2

D0–D3

REF

CK0CK: SDRAMs D0–D3

LDQS

LDM

UDQS

UDM

DQ20

DQ21

DQ22

DQ23

DQ16

DQ17

DQ18

DQ19

I/O 0

I/O 1

I/O 2

I/O 3

DM2

I/O 4

I/O 5

I/O 6

I/O 7

DQ28

DQ29

DQ30

DQ24

DQ25

DQ26

DQ27

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

DM3

DQS2

DQS3

DQ31 I/O 15

DQS2

DQS3

LDQS

LDM

UDQS

UDM

DQ36

DQ37

DQ38

DQ39

DQ32

DQ33

DQ34

DQ35

I/O 0

I/O 1

I/O 2

I/O 3

DM4

I/O 4

I/O 5

I/O 6

I/O 7

DQ44

DQ45

DQ46

DQ40

DQ41

DQ42

DQ43

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

DM5

DQS4

DQS5

DQ47 I/O 15

DQS4

DQS5

LDQS

LDM

UDQS

UDM

DQ52

DQ53

DQ54

DQ55

DQ48

DQ49

DQ50

DQ51

I/O 0

I/O 1

I/O 2

I/O 3

DM6

I/O 4

I/O 5

I/O 6

I/O 7

DQ60

DQ61

DQ62

DQ56

DQ57

DQ58

DQ59

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

DM7

DQS6

DQS7

DQ63 I/O 15

DQS6

DQS7

LDQS

LDM

UDQS

UDM

RESET RESET:SDRAMs D0-D3

ZQ ZQ

Rev. 0.1 / Dec 2008 13

HMT164U6AFP(R)6C

HMT112U6(7)AFP(R)8C

HMT125U6(7)AFP(R)8C

3.2 1GB, 128Mx64 Module(1Rank of x8)

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

I/O 0

I/O 1

I/O 2

I/O 3

DM0

I/O 4

I/O 5

I/O 6

I/O 7

DQ12

DQ13

DQ14

DQ8

DQ9

DQ10

DQ11

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

DM1

DQ20

DQ21

DQ22

DQ23

DQ16

DQ17

DQ18

DQ19

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM2

DQ28

DQ29

DQ30

DQ31

DQ24

DQ25

DQ26

DQ27

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM3

DQ36

DQ37

DQ38

DQ39

DQ32

DQ33

DQ34

DQ35

I/O 0

I/O 1

I/O 2

I/O 3

DM4

I/O 4

I/O 5

I/O 6

I/O 7

DQ44

DQ45

DQ46

DQ47

DQ40

DQ41

DQ42

DQ43

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM5

DQ52

DQ53

DQ54

DQ55

DQ48

DQ49

DQ50

DQ51

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ60

DQ61

DQ62

DQ63

DQ56

DQ57

DQ58

DQ59

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM7

A0–A15 A0–A15: SDRAMs D0–D7

Serial PD

SA0 SA1

SDA

RAS RAS: SDRAMs D0–D7

CAS CAS: SDRAMs D0–D7

CKE0 CKE: SDRAMs D0–D7

WE WE: SDRAMs D0–D7

CS CS

BA0–BA2 BA0–BA2: SDRAMs D0–D7

DQS0

DQS

DQS4

DQS1 DQS5

DQS

DQS2

DQS

DQS3

DQS

DM6

DQS6

DQS7

DQ15 I/O 7

DQS

D0–D7

REF

SCL WP

SPD

DDSPD

ODT0

DQS0

DQS DQS

DQS4

DQS1

DQS

DQS2

DQS

DQS3

DQS

DQS5

DQS6

DQS

DQS7

DQS

ODT: SDRAMs D0–D7

CK0 CK: SDRAMs D0–D7

SA2

D0–D7

REF

CK0CK: SDRAMs D0–D7

RESET RESET:SDRAMs D0-D7

Notes:

1. DQ-to-I/O wiring is shown as recom-

mended but may be changed.

2. DQ/DQS/DQS/ODT/DM/CKE/S relation-

ships must be maintained as shown.

3. DQ,DM,DQS/DQS resistors ;Refer to

associated topolo gy diagram.

4. Refer to t he appropriate clock wiring

topology under the DIMM wiring details

section of this document.

5. Re fer to Section 3.1 of this docu ment for

details on address mirroring.

6. For each DRAM, a unique ZQ resistor is

connected to ground.The ZQ resistor is

240ohm+-1%

7. One SPD exists per module.

Rev. 0.1 / Dec 2008 14

HMT164U6AFP(R)6C

HMT112U6(7)AFP(R)8C

HMT125U6(7)AFP(R)8C

3.3 1GB, 128Mx72 Module(1Rank of x8)

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

I/O 0

I/O 1

I/O 2

I/O 3

DM0

I/O 4

I/O 5

I/O 6

I/O 7

DQ12

DQ13

DQ14

DQ8

DQ9

DQ10

DQ11

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

DM1

DQ20

DQ21

DQ22

DQ23

DQ16

DQ17

DQ18

DQ19

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM2

DQ28

DQ29

DQ30

DQ31

DQ24

DQ25

DQ26

DQ27

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM3

DQ36

DQ37

DQ38

DQ39

DQ32

DQ33

DQ34

DQ35

I/O 0

I/O 1

I/O 2

I/O 3

DM4

I/O 4

I/O 5

I/O 6

I/O 7

DQ44

DQ45

DQ46

DQ47

DQ40

DQ41

DQ42

DQ43

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM5

DQ52

DQ53

DQ54

DQ55

DQ48

DQ49

DQ50

DQ51

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ60

DQ61

DQ62

DQ63

DQ56

DQ57

DQ58

DQ59

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM7

A0–A15 A0–A15: SDRAMs D0–D8

SPD(TS integrated)

SA0 SA1

SDA

RAS RAS: SDRAMs D0–D8

CAS CAS: SDRAMs D0–D8

CKE0 CKE: SDRAMs D0–D8

WE WE: SDRAMs D0–D8

CS CS

BA0–BA2 BA0–BA2: SDRAMs D0–D8

DQS0

DQS

DQS4

DQS1 DQS5

DQS

DQS2

DQS

DQS3

DQS

DM6

DQS6

DQS7

DQ15 I/O 7

CB4

CB5

CB6

CB7

CB0

CB1

CB2

CB3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS8

DM8

DQS

VSS

D0–D8

VDD/VDDQ

D0–D8

REF

SCL

EVENT

SPD

VDDSPD

ODT0 ODT: SDRAMs D0–D8

DQS0

DQS DQS

DQS4

DQS1

DQS

DQS2

DQS

DQS3

DQS

DQS8

DQS

DQS5

DQS6

DQS

DQS7

DQS

CK0 CK: SDRAMs D0–D8

SA2

VREFCA

D0–D8

CK0CK: SDRAMs D0–D8

RESET RESET:SDRAMs D0-D8

Notes:

1. DQ-to-I/O wiring is shown as recom-

mended but may be changed.

2. DQ/DQS/DQS/ODT/DM/CKE/S rela-

tionships must be maint a ined as

shown.

3. DQ,CB,DM,DQS/DQS resistors;Refer

to associated topology diagram.

4. Refer to the appropriate clock wiring

topology under the DIMM wiring

details sec ti on of this documen t.

5. For each DRAM, a unique ZQ resistor

is connecte d t o ground.The ZQ resis-

tor is 240ohm+-1%

6. One SPD exists per module.

EVENT

Rev. 0.1 / Dec 2008 15

HMT164U6AFP(R)6C

HMT112U6(7)AFP(R)8C

HMT125U6(7)AFP(R)8C

3.4 2GB, 256Mx64 Module(2Rank of x8)

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

I/O 0

I/O 1

I/O 2

I/O 3

DM0

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ12

DQ13

DQ14

DQ8

DQ9

DQ10

DQ11

I/O 0

I/O 1

I/O 2

I/O 3

D1 D9

I/O 4

I/O 5

I/O 6

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

DM1

DQ20

DQ21

DQ22

DQ23

DQ16

DQ17

DQ18

DQ19

I/O 0

I/O 1

I/O 2

I/O 3

D2 D10

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM2

DQ28

DQ29

DQ30

DQ31

DQ24

DQ25

DQ26

DQ27

I/O 0

I/O 1

I/O 2

I/O 3

D3 D11

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM3

DQ36

DQ37

DQ38

DQ39

DQ32

DQ33

DQ34

DQ35

I/O 0

I/O 1

I/O 2

I/O 3

DM4

D12

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ44

DQ45

DQ46

DQ47

DQ40

DQ41

DQ42

DQ43

I/O 0

I/O 1

I/O 2

I/O 3

D5 D13

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM5

DQ52

DQ53

DQ54

DQ55

DQ48

DQ49

DQ50

DQ51

I/O 0

I/O 1

I/O 2

I/O 3

D6 D14

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ60

DQ61

DQ62

DQ63

DQ56

DQ57

DQ58

DQ59

I/O 0

I/O 1

I/O 2

I/O 3

D7 D15

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM7

A0–A15 A0-A15: SDRAMs D0–D15

Serial PD

SA0 SA1

SDA

RAS RAS: SDRAMs D0–D 15

CAS CAS: SDRAMs D0–D 15

WE WE: SDRAMs D0–D15

S0 S1

CKE1 CKE: SDRAMs D8–D15

BA0–BA2 BA0–BA2: SDRAMs D0–D1 5

DQS0

DQS

DQS4

DQS1 DQS5

DQS2

DQS3

DM6

DQS6

DQS7

DQ15 I/O 7 I/O 7

D0–D15

QD0–D15

D0–D15

REF

SCL

SPD

DDSPD

DQS

DM CS DQS DQS

DM CS DQS DQSDM CS DQS DQS

DM CS DQS DQS DM CS DQS DQS

DM CS DQS DQS

DQS0DQS4

DQS1 DQS5

DQS2DQS6

DQS3DQS7

ODT0 ODT: SDRAMs D0–D7

ODT1 ODT: SDRAMs D8–D15

CKE0 CKE: SDRAMs D0–D7

CK0 CK: SDRAMs D0–D7

CK0CK: SDRAMs D0–D7

SA2

D0–D15

REF

CK1 CK: SDRAMs D8–D15

CK1CK: SDR AMs D8–D15

ZQ ZQ

RESET RESET:SDRAMs D0-D3

Notes:

1. DQ-to-I/O wiring is shown as recom-

mended but may be changed.

2. DQ/DQS/DQS/ODT/DM/CKE/S relation-

ships must be maintained as shown.

3. DQ,DM,DQS,DQS resistors;Refer to

associated topology diagram.

4. R efer to Section 3.1 of this document for

details on address mirroring.

5. For each DRAM, a unique ZQ resistor is

connected to ground.The ZQ resistor is

240ohm+-1%

6. One SPD exists per module.

Rev. 0.1 / Dec 2008 16

HMT164U6AFP(R)6C

HMT112U6(7)AFP(R)8C

HMT125U6(7)AFP(R)8C

3.5 2GB, 256Mx72 Module(2Rank of x8)

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

I/O 1

I/O 2

I/O 3

D0 D9

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ12

DQ13

DQ14

DQ8

DQ9

DQ10

DQ11

I/O 0

I/O 1

I/O 2

I/O 3

D1 D10

I/O 4

I/O 5

I/O 6

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

DQ20

DQ21

DQ22

DQ23

DQ16

DQ17

DQ18

DQ19

I/O 0

I/O 1

I/O 2

I/O 3

D2 D11

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ28

DQ29

DQ30

DQ31

DQ24

DQ25

DQ26

DQ27

I/O 0

I/O 1

I/O 2

I/O 3

D3 D12

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ36

DQ37

DQ38

DQ39

DQ32

DQ33

DQ34

DQ35

I/O 0

I/O 1

I/O 2

I/O 3

D4 D13

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ44

DQ45

DQ46

DQ47

DQ40

DQ41

DQ42

DQ43

I/O 0

I/O 1

I/O 2

I/O 3

D5 D14

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ52

DQ53

DQ54

DQ55

DQ48

DQ49

DQ50

DQ51

I/O 0

I/O 1

I/O 2

I/O 3

D6 D15

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ60

DQ61

DQ62

DQ63

DQ56

DQ57

DQ58

DQ59

I/O 0

I/O 1

I/O 2

I/O 3

D7 D16

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

A0–A15 A0-A15: SDRAMs D0–D17

RAS RAS: SDRAMs D0–D17

CAS CAS: SDRAMs D0–D17

WE WE: SDRAMs D0–D17

CKE1 CKE: SDRAMs D9–D17

BA0–BA2 BA0-BA2: SDRAMs D0–D17

DQ15 I/O 7 I/O 7

CB4

CB5

CB6

CB7

CB0

CB1

CB2

CB3

I/O 0

I/O 1

I/O 2

I/O 3

D8 D17

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS8

DM8

Vss D0–D17

QD0–D17

D0–D17

REF

SPD

DDSPD

DM CS DQS DQS DM

DQS DQS DM CS DQS DQS DM

DQS DQS

DM CS DQS DQS DM

DQS DQS DM CS DQS DQS DM

DQS DQS

DM CS DQS DQS DM

DQS DQS DM CS DQS DQS DM

DQS DQS

DM CS DQS DQS DM

DQS DQS DM CS DQS DQS DM

DQS DQS

DM CS DQS DQS DM

DQS DQS

I/O 0

DM0 DM4

S0 S1

DQS0 DQS4

DQS0DQS4

DM1 DM5

DQS1 DQS5

DQS1DQS5

DM2

DQS2 DM6

DQS6

DQS2

DM3 DM7

DQS3 DQS7

DQS3DQS7

DQS6

DQS8

ODT0 ODT: SDRAMs D0–D8

ODT1 ODT: SDRAMs D9–D17

CKE0 CKE: SDRAMs D0–D8 CK0 CK: SDRAMs D0–D8

CK0CK: SDRAMs D0–D8

D0–D17

REF

CK1 CK: SDRAMs D9–D17

CK1CK: SDRAMs D9–D17

ZQ ZQ

ZQ ZQ ZQ ZQ

ZQ ZQ

RESET RESET:SDRAMs D0-D17

Notes:

1. DQ-to-I/O wiring is shown as recom-

mended but may be changed.

2. DQ/DQS/DQS/ODT/DM/CKE/S relation-

ships must be maintained as shown.

3. DQ,CB,DM/DQS/DQS resistors;Refer to

associated topology diagram.

4. Refer to Section 3.1 of this document for

details on address mirroring.

5. For each DRAM, a unique ZQ resistor is

connected to ground.The ZQ resistor is

240ohm+-1%

6. One SPD exists per module.

SPD(TS integrated)

SA0 SA1

SDA

SCL

EVENT

SA2

EVENT

Rev. 0.1 / Dec 2008 17

HMT164U6AFP(R)6C

HMT112U6(7)AFP(R)8C

HMT125U6(7)AFP(R)8C

4. Address Mirroring Feature

There is a via grid located under the SDRAMs for wiring the CA signals (address, bank ad dress, command, and control

lines) to the SDRAM pins. The length of the traces from the via to the SDRAMs places limitations on the bandwidth of

the module. The shorter these traces, the higher the bandwidth. To extend the bandwidth of the CA bus for DDR3

modules, a scheme was defined to reduce the length of these traces.T he pins o n the SD RAM are defined in a m ann er

that allows for these short trace lengths. The CA bus pins in Columns 2 and 8, ignoring the mechanical support pins,

do not have any special functions (secondary functions). This allows the most flexibility with these pins. These are

address pins A3, A4, A5, A6, A7, A8 and bank address pins BA0 and BA1. Refer to Table . Rank 0 SDRAM pins are

wired straight, with no mismatch between the connector pin as signment and th e SDRAM pin assignment. Some of the

Rank 1 SDRAM pins are cross wired as defined in the table. Pins not listed in the table are wired straight.

4.1 DRAM Pin Wiring for Mirroring

The table 4.1 illustrates the wiring in both the mirrored and non-mirrored case.

The lengths of the traces to the SDRAM pins, is obviously shorter. The via grid is smaller as well.

Connector Pin SDRAM Pin

Rank 0 Rank 1

A3 A3 A4

A4 A4 A3

A5 A5 A6

A6 A6 A5

A7 A7 A8

A8 A8 A7

BA0 BA0 BA1

BA1 BA1 BA0

Rev. 0.1 / Dec 2008 18

HMT164U6AFP(R)6C

HMT112U6(7)AFP(R)8C

HMT125U6(7)AFP(R)8C

< Figure 4.1: Wiring Differences for Mirrored and Non-Mirrored Addresses >

Since the cross-wired pins have no secondary functions, there is no problem in normal operation. Any data written is

read the same way. There are limitations however. When writing to the internal registers with a "load mode" opera-

tion, the specific address is required. This requires the controll er to know if the rank is mirrored or not. This requires a

few rules. Mirroring is done on 2 rank modules and can only be done on the second rank. There is not a requirement

that the second rank be mirrored. There is a bit assignment in the SPD that indicates whether the module has been

designed with the mirrored feature or not. See the DDR3 UDIMM SPD specification for these details. The controller

must read the SPD and have the capability of de-mirroring the address when accessing the second rank.

No Mirroring Mirroring

Rev. 0.1 / Dec 2008 19

HMT164U6AFP(R)6C

HMT112U6(7)AFP(R)8C

HMT125U6(7)AFP(R)8C

5. ABSOLUTE MAXIMUM RATINGS

5.1 Absolute Maximum DC Ratings

5.2 DRAM Component Operating Temperature Range

Symbol Parameter Rating Units Notes

VDD Voltage on VDD pin relative to Vss - 0.4 V ~ 1.975 V V ,3

VDDQ Voltage on VDDQ pin relative to Vss - 0.4 V ~ 1.975 V V ,3

VIN, VOUT Voltage on any pin relative to Vss - 0.4 V ~ 1.975 V V

TSTG Storage Temperature -55 to +100 ℃℃, 2

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional operation of the device at these or any other conditions

above those indicated in the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement

conditions, please refer to JESD51-2 standard.

3. VDD and VDDQ must be within 300mV of each other at all times;and VREF must be not greater than

0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.

Symbol Parameter Rating Units Notes

TOPER Normal Temperature Range 0 to 85 ℃,2

Extended Temperature Range 85 to 95 ℃1,3

1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM.

For measurement conditions, please refer to the JEDEC document JESD51-2.

2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported.

During operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating

conditions

3. Some applications require operation of the DRAM in the Extended Temperature Range between 85°… and

95°… case temperature.

Full specifications are guaranteed in this range, but the following additiona l conditions apply:

a) Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs.

(This double refresh requirement may not apply for some devices.) It is also possible to specify a component

with 1X refresh (tREFI to 7.8µs) in the Extended Temperature Range. Please refer to supplier data sheet and/

or the DIMM SPD for option avail ability.

b) If Self-Refresh operation is required in the Extended Temperature Range, than it is mandatory to either use the

Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0band MR2 A7 = 1b) or

enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b).

Rev. 0.1 / Dec 2008 20

HMT164U6AFP(R)6C

HMT112U6(7)AFP(R)8C

HMT125U6(7)AFP(R)8C

6. AC & DC Operating Conditions

6.1 Recommended DC Operating Conditions

6.2 DC & AC Logic Input Levels

6.2.1 DC & AC Logic Input Levels for Single-Ended Signals

The dc-tolerance limits and ac-noise limits for the reference voltages VRefCA and VRefDQ are illustrated in figure

6.2.1. It shows a valid reference voltage VRef(t) as a function of time. (VRef stands for VRefCA and VRefDQ like-

wise).VRef(DC) is the linear average of VRef(t) over a very long period of time (e.g. 1 sec). This average has to meet

the min/max requirements in Table 1. Furthermor e VRef(t) may temporarily deviate from VRef(DC) by no more than

+/- 1% VDD.

Symbol Parameter Rating Units Notes

Min. Typ. Max.

VDD Supply Voltage 1.425 1.500 1.575 V 1,2

VDDQ Supply Voltage for Output 1.425 1.500 1.575 V 1,2

1. Under all conditions, VDDQ must be less than or equal to VDD.

2. VDDQ tracks with VDD. AC parameters are measured with VDD abd VDDQ tied together.

Symbol Parameter DDR3-800, DDR3-1066, DDR3-1333, DDR3-1600 Unit Notes

Min Max

VIH(DC) DC input logic high Vref + 0.100 - V 1, 2

VIL(DC) DC input logic low Vref - 0.100 V 1, 2

VIH(AC) AC input logic high Vref + 0.175 - V 1, 2

VIL(AC) AC input logic low Vref - 0.175 V 1, 2

VRefDQ(DC) R eference V o ltag e f or

DQ, DM inputs 0.49 * VDD 0.51 * VDD V 3, 4

VRefCA(DC) Reference Voltage for

ADD, CMD inputs 0.49 * VDD 0.51 * VDD V 3, 4

VTT Terminat ion volt age for

DQ, DQS outputs VDDQ/2 - TBD VDDQ/2 + TBD V

1. For DQ and DM, Vref = VrefDQ. For input ony pins except RESET#, Vref = VrefCA.

2. The “t.b.d.” entries might change based on overshoot and undershoot specification.

3. The ac peak noise on VRef may not allow VRef to deviate from VRef(DC) by more than +/-1% VDD

(for reference: approx. +/- 15 mV).

For reference: approx. VDD/2 +/- 15 mV.

Rev. 0.1 / Dec 2008 21

HMT164U6AFP(R)6C

HMT112U6(7)AFP(R)8C

HMT125U6(7)AFP(R)8C

< Figure 6.2.1: Illustration of Vref(DC) tolerance and Vref AC-noise limits >

The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on

VRef. "VRef " shall be understood as VRef(DC), as defined in Figure 6.2.1

This clarifies, that dc-variations of VRef affect the absolute v oltage a signal has to reach to ach ieve a v alid high or low

level and therefor e the time to which setup and hold is measured. S ystem timing and voltage budgets need to account

for VRef(DC) deviations from the optimum position within the data-eye of the input signals.

This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associ-

ated with VRef ac-noise. Timing and voltage effects due to ac-noise on VRef up to the specified limit (+/-1% of VDD)

are included in DRAM timings and their associated deratings.

6.2.2 DC & AC Logic Input Levels for Differential Signals

Note1:

Refer to “Overshoot and Undershoot Specification section 6.5 on 26 page

Symbol Parameter DDR3-800, DDR3-1066, DDR3-1333, DDR3-1600 Unit Notes

Min Max

VIHdiff Differential input logic high + 0.200 - V 1

VILdiff Differential input lo gic lo w - 0.200 V 1

VDD

VSS

VDD/2

VRef(DC)

VRef ac-noise

voltage

time

VRef(DC)max

VRef(DC)min

VRef(t)

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6.2.3 Differential Input Cross Point Voltage

To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each

cross point voltage of differential input signals (CK, CK# and DQS, DQS#) must meet the requirements in Table 6.2.3

The differential input cr oss point voltage VI X is measured fr om the actual cross point of true and complement signal to

the midlevel between of VDD and VSS.

< Figure 6.2.3 Vix Definition >

< Table 6.2.3: Cross point voltage for differential input signals (CK, DQS) >

Symbol Parameter DDR3- 800, DDR3-1066, DDR3-1333, DDR3-1600 Unit Notes

Min Max

VIX Differential Input Cross Point

Voltage relative to VDD/2 - 150 + 150 mV

VDD

VSS

VDD/2

VIX

CK#, DQS#

CK, DQS

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6.3 Slew Rate Definitions

6.3.1 For Single Ended Input Signals

- Input Slew Rate for Input Setup Time (tIS) and Data Setup Time (tDS)

Setup (tIS and tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VRef

and the first crossing of VIH(AC)min. Setup (tIS and tDS) nominal slew rate fo r a falling signal is defined as the slew

rate between the last crossing of VRef and the first crossing of VIL(AC)max.

- Input Slew Rate for Input Hold Time (tIH) and Data Hold Time (tDH)

Hold nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and

the first crossing of VRef. Hold (tIH and tDH) nominal slew rate for a falling signal is defined as the slew rate

between the last crossing of VIH(DC)min and the first crossing of VRef.

< Table 6.3.1: Single-Ended Input Slew Rate Defi nition >

Description Measured Defined by Applicable for

Min Max

Input slew rate for rising edge Vref VIH(AC)min VIH(AC)min-Vref

Delta TRS Setup

(tIS, tDS)

Input slew rate for falling edge Vref VIL(AC)max Vref-VIL(AC)max

Delta TFS

Input slew rate for rising edge VIL(DC)max Vref Vref-VIL(DC)max

Delta TFH Hold

(tIH, tDH)

Input slew rate for falling edge VIH(DC)min Vref VIH(DC)min-Vref

Delta TRH

Delta TFS

Delta TRS

vIH(AC)min

vIH(DC)min

vIL(DC)max

vIL(AC)max

vRefDQ or

vRefCA

Part A: Set up

Single Ended input Voltage(DQ,ADD, CMD)

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< Figure 6.3.1: Input Nominal Slew Rate Definition for Single-Ended Signals >

6.3.2 Differential Input Signals

Input slew rate for differential signals (CK, CK# and DQS, DQS#) are defined and measured a s shown in below Table

and Figure .

Note:

The differential signal (i.e. CK-CK and DQS-DQS) must be linear between these thresholds.

Description Measured Defined by

Min Max

Differential input slew rate for rising edge

(CK-CK and DQS-DQS) VILdiffmax VIHdiffmin VIHdiffmin-VILdiffmax

DeltaTRdiff

Differential inp ut slew r ate f or f alling edge

(CK-CK and DQS-DQS) VIHdiffmin VILdiffmax VIHdiffmin-VILdiffmax

DeltaTFdiff

Part B: Hold

Delta TFH

Delta TRH

vIH(AC)min

vIH(DC)min

vIL(DC)max

vIL(AC)max

vRefDQ or

vRefCA

Single Ended input Voltage(DQ,ADD, CMD)

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< Figure 6.3.2: Differential Input Slew Rate Definition for DQS,DQS# and CK,CK# >

6.4 DC & AC Output Buffer Levels

6.4.1 Single Ended DC & AC Output Levels

Below table shows the output levels used for measurements of single ended signals.

Symbol Parameter DDR3-800, 1066, 1333 and 1600 Unit Notes

VOH(DC) DC output high measurement level

(for IV curve linearity) 0.8 x VDDQ V

VOM(DC) DC output mid measurement level

(for IV curve linearity) 0.5 x VDDQ V

VOL(DC) DC output low measurement level

(for IV curve linearity) 0.2 x VDDQ V

VOH(AC) AC output high measurement level

(for output SR) VTT + 0.1 x VDDQ V 1

VOL(AC) AC output low measurement level

(for output SR) VTT - 0.1 x VDDQ V 1

1. The swing of ±0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing

with a driver impedance of 40Ω and an effective test load of 25Ω to VTT = VDDQ / 2.

Delta

TFdiff

Delta

TRdiff

vIHdiffmin

vILdiffmax

Differential Input Voltage (i.e. DQS-DQS; CK-CK)

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6.4.2 Differential DC & AC Output Levels

Below table shows the output levels used for measurements of differential signals.

6.4.3 Single Ended Output Slew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and

measured between VOL(AC) and VOH(AC) for single ended signals as shown in below Table and Figure 6.4.3.

Note:

Output slew rate is verified by design and characterization, and may not be subject to production test.

< Figure 6.4.3: Single Ended Output Slew Rate Definition >

Symbol Parameter DDR3-800, 1066, 1333 and 1600 Unit Notes

VOHdiff

(AC) AC differential output high

measurement level (for output SR) + 0.2 x VDDQ V 1

VOLdiff

(AC) AC differential output low

measurement level (for output SR) - 0.2 x VDDQ V 1

1. The swing of °æ 0.2 x VDDQ is based on approximately 50% of the static differential output high

or low swingwith a driver impedance of 40ßŸ and an effective test load of 25ßŸ to VTT = VDDQ/2 at each of

the differential output

Description Measured Defined by

From To

Single ended output slew rate for rising edge VOL(AC) VOH(AC) VOH(AC)-VOL(AC)

DeltaTRse

Single ended output slew rate for falling edge VOH(AC) VOL(AC) VOH(AC)-VOL(AC)

DeltaTFse

Delta TFse

Delta TRse

vOH(AC)

vOL(AC)

V∏

Single Ended Output Voltage(l.e.DQ)

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*** Description:

SR: Slew Rate

Q: Query Output (like in DQ, which stands for Data-in, Query-Output)

For Ron = RZQ/7 setting

< Table 6.4.3: Output Slew Rate (single-ended) >

6.4.4 Differential Output Slew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and mea-

sured between VOLdiff(AC) and VOHdiff(AC) for differential signals as shown in below Table and Figure 6.4.4

Note: Output slew rate is verified by design and characterization, and may not be subject to production test.

< Figure 6.4.4: Differential Output Slew Rate Definition >

Parameter Symbol DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Units

Min Max Min Max Min Max Min Max

Single-ended Output Slew Rate SRQse 2.5 5 2.5 5 2.5 5 TBD 5 V/n s

Description Measured Defined by

From To

Differential output slew rate for rising edge VOLdiff(AC) VOHdiff(AC) VOHdiff(AC)-VOLdiff(AC)

DeltaTRdiff

Differential output slew rate for falling edge VOHdiff(AC) VOLdiff(AC) VOHdiff(AC)-VOLdiff(AC)

DeltaTFdiff

Delta

TFdiff

Delta

TRdiff

vOLdiff(AC)

Differential Output Voltage(i.e. DQS-DQS)

vOHdiff(AC)

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***Description:

SR: Slew Rate

Q: Query Output (like in DQ, which stands for Data-in, Query-Output)

diff: Differential Signals

For Ron = RZQ/7 setting < Table 6.6.4: Differential Output Slew Rate >

6.5 Overshoot and Undershoot Specifications

6.5.1 Address and Control Overshoot and Undershoot Specifications

< Table 6.5.1: AC Overshoot/Undershoot Specification for Address and Control Pins >

< Figure 6.5.1: Address and Control Overshoot and Undershoot Definition >

Parameter Symbol DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Units

Min Max Min Max Min Max Min Max

Differential Output Slew Rate SRQdiff 5 10 5 10 5 10 TBD 10 V/ns

Description Specification

DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600

Maximum peak amplitude allowed for

overshoot area (see Figure) 0.4V 0.4V 0.4V 0.4V

Maximum peak amplitude allowed for

undershoot area (see Figure) 0.4V 0.4V 0.4V 0.4V

Maximum overshoot area above VDD

(See Figure) 0.67 V-ns 0.5 V-ns 0.4 V-ns 0.33 V-ns

Maximum undershoot area below VSS

(See Figure) 0.67 V-ns 0.5 V-ns 0.4 V-ns 0.33 V-ns

Maximum Amplitude

Overshoot Area

VDD

VSS

Volts

(V)

Maximum Amplitude Undershoot Area

Time (ns)

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6.5.2 Clock,Data,Strobe and Mask Overshoot and Undershoot Specifications

< Table 6.5.2: AC Overshoot/Undershoot Specification for Clock, Data, Strobe and Mask >

< Figure 6.5.2: Clock, Data, Strobe and Mask Overshoot and Undershoot Definition >

Description Specification

DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600

Maximum peak amplitude allowed for

overshoot area (see Figure) 0.4V 0.4V 0.4V 0.4V

Maximum peak amplitude allowed for

undershoot area (see Figure) 0.4V 0.4V 0.4V 0.4V

Maximum overshoot area above VDDQ

(See Figure) 0.25 V-ns 0.19 V-ns 0.15 V-ns 0.13 V-ns

Maximum undershoot area below VSSQ

(See Figure) 0.25 V-ns 0.19 V-ns 0.15 V-ns 0.13 V-ns

Ma ximu m A mp litu de

O vershoot Area

VDDQ

VSSQ

Maximum Amplitude Undershoot Area

Tim e (ns)

Clock, Data Strobe and M ask Overshoot and Undershoot D efinition

Volts

(V)

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6.6 Pin Capacitance

Parameter Symbol DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Units Notes

Min Max Min Max Min Max Min Max

Input/output capacitance

(DQ, DM, DQS, DQS#, TDQS,

TDQS#) CIO 1.5 3.0 1.5 3.0 1.5 2.5 TBD TBD pF 1,2,3

Input capacitance, CK and

CK# CCK TBD 1.6 TBD 1.6 TBD TBD TBD TBD pF 2,3,5

Input capacitance delta

CK and CK# CDCK 0 0.15 0 0.15 TBD TBD TBD TBD pF 2,3,4

Input capacitance

(All other input-only pins) CITBD 1.5 TBD 1.5 TBD TBD TBD TBD pF 2,3,6

Input capacitance delta, DQS

and DQS# CDDQS 0 0.20 0 0.20 TBD TBD TBD TBD pF 2,3,12

Input capacitance delta

(All CTRL input-only pins) CDI_CTRL -0.5 0.3 -0.5 0.3 TBD TBD TBD TBD pF 2,3,7,8

Input capacitance delta

(All ADD/CMD input-only pins) CDI_ADD_

CMD -0.5 0.5 -0.5 0.5 TBD TBD TBD TBD pF 2,3,9,

Input/output capacitance delta

(DQ, DM, DQS, DQS#) CDIO -0.5 0.3 -0.5 0.3 TBD TBD TBD TBD pF 2,3,11

Notes:

1. TDQS/TDQS# are not necessarily input function but since TDQS is sharing DM pin and the parasitic

characterization of TDQS/TDQS# should be close as much as possible, Cio&Cdio requirement is applied

(recommend deleting note or changing to “Although the DM, TDQS and TDQS# pins have different functions,

the loading matches DQ and DQS.”)

2. This parameter is not subject to production test. It is ve rified by design and characterization. Input capacitance is

measured according to JEP 147(“PROCEDURE FOR MEASURING INPUT CAP ACITANCE USING A VECT OR NETWORK

ANALYZER(VNA)”) with VDD, VDDQ, VSS,VSSQ applied and all other pins floating ( except the pin under test, CKE,

RESET# and ODT as necessary). VDD=VDDQ=1.5V, VBIAS=VDD/2 and on-die termination off.

3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here

4. Absolute value of CCK-CCK#.

5. The minimum CCK will be equal to the minimum CI.

6. Input only pins include: ODT, CS, CKE, A0-A15, BA0-BA2, RAS#, CAS#, WE#.

7. CTRL pins defined as ODT, CS and CKE.

8. CDI_CTRL=CI(CNTL) - 0.5 * CI(CLK) + CI(CLK#))

9. ADD pins defined as A0-A15, BA0-BA2 and CMD pins are defined as RAS#, CAS# and WE#.

10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK#))

11. CDIO=CIO(DQ) - 0.5*(CIO(DQS)+CIO(DQS#))

12. Absolute value of CIO(DQS) - CIO(DQS#)

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6.7 IDD Specifications(TCASE: 0 to 95oC)

512MB, 64M x 64 U-DIMM: HMT164U6AFP6C

1GB, 128M x 64 U-DIMM: HMT112U6AFP8C

Symbol DDR3 800 DDR3 1066 DDR3 1333 Unit note

IDD0 360 420 480 mA

IDD1 480 540 580 mA

IDD2P(F) 100 120 140 mA

IDD2P(S) 40 40 40 mA

IDD2Q 180 240 280 mA

IDD2N 200 240 300 mA

IDD3P 140 180 200 mA

IDD3N 220 280 340 mA

IDD4W 700 880 1060 mA

IDD4R 700 860 1020 mA

IDD5B 740 780 840 mA

IDD6(D) 40 40 40 mA 1

IDD6(S) 24 24 24 mA 1

IDD7 1300 1420 1720 mA

Symbol DDR3 800 DDR3 1066 DDR3 1333 Unit note

IDD0 640 760 840 mA

IDD1 760 880 960 mA

IDD2P(F) 200 240 280 mA

IDD2P(S) 80 80 80 mA

IDD2Q 360 480 560 mA

IDD2N 400 480 600 mA

IDD3P 280 360 400 mA

IDD3N 440 560 680 mA

IDD4W 1120 1440 1560 mA

IDD4R 1040 1320 1680 mA

IDD5B 1480 1560 1720 mA

IDD6(D) 80 80 80 mA 1

IDD6(S) 48 48 48 mA 1

IDD7 1800 2000 2440 mA

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1GB, 128M x 72 U-DIMM: HMT112U7AFP8C

2GB, 256M x 64 U-DIMM: HMT125U6AFP8C

Symbol DDR3 800 DDR3 1066 DDR3 1333 Unit note

IDD0 720 855 945 mA

IDD1 855 990 1080 mA

IDD2P(F) 225 270 315 mA

IDD2P(S) 90 90 90 mA

IDD2Q 405 540 630 mA

IDD2N 450 540 675 mA

IDD3P 315 405 450 mA

IDD3N 495 630 765 mA

IDD4W 1260 1620 1755 mA

IDD4R 1170 1485 1890 mA

IDD5B 1665 1755 1935 mA

IDD6(D) 90 90 90 mA 1

IDD6(S) 54 54 54 mA 1

IDD7 2025 2250 2745 mA

Symbol DDR3 800 DDR3 1066 DDR3 1333 Unit note

IDD0 1040 1240 1440 mA

IDD1 1160 1360 1560 mA

IDD2P(F) 400 480 560 mA

IDD2P(S) 160 160 160 mA

IDD2Q 720 960 1120 mA

IDD2N 800 960 1200 mA

IDD3P 560 720 800 mA

IDD3N 880 1120 1360 mA

IDD4W 1520 1920 2160 mA

IDD4R 1440 1800 2280 mA

IDD5B 1880 2040 2320 mA

IDD6(D) 160 160 160 mA 1

IDD6(S) 96 96 96 mA 1

IDD7 2200 2480 3040 mA

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2GB, 256M x 72 U-DIMM: HMT125U7AFP8C

6.7 IDD Measurement Conditions

Within the tables provided further down, an overview about the IDD measurement conditions is

provided as follows:

Within the tables about IDD measurement conditions, the following definitions are used:

- LOW is defined as VIN <= VILAC(max.); HIGH is defined as VIN >= VIH AC(min.).

- STABLE is defined as inputs are stable at a HIGH or LOW level.

- FLOATING is defined as inputs are VREF = VDDQ / 2.

- SWITCHING is defined as described in the following 2 tables.

Symbol DDR3 800 DDR3 1066 DDR3 1333 Unit note

IDD0 1170 1395 1620 mA

IDD1 1305 1530 1755 mA

IDD2P(F) 450 540 630 mA

IDD2P(S) 180 180 180 mA

IDD2Q 810 1080 1260 mA

IDD2N 900 1080 1350 mA

IDD3P 630 810 900 mA

IDD3N 990 1260 1530 mA

IDD4W 1710 2160 2430 mA

IDD4R 1620 2025 2565 mA

IDD5B 2115 2295 2610 mA

IDD6(D) 180 180 180 mA 1

IDD6(S) 108 108 108 mA 1

IDD7 2475 2790 3420 mA

Table 1 — Overview of Tables providing IDD Measurement Conditions and DRAM Behavior

Table number Measurement Conditions

Table 5 on page 33 IDD0 and IDD1

Table 6 on page 36 IDD2N, IDD2Q, IDD2P(0), IDD2P(1)

Table 7 on page 38 IDD3N and IDD3P

Table 8 on page 39 IDD4R, IDD4W, IDD7

Table 9 on page 42 IDD7 for different Speed Grades and different tRRD, tFAW conditions

Table 10 on page 43 IDD5B

Table 11 on page 44 IDD6, IDD6ET

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Table 2 — Definition of SWITCHING for Address and Command Input Signals

SWITCHING for Address (row, column) and Command Signals (CS, RAS, CAS, WE) is defined as:

Address

(row, column):

If not otherwise mentioned the inputs are stable at HIGH or LOW during 4 clocks and change

then to the opposite value

(e.g. Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax.....

please see each IDDx definition for details

Bank address:If not otherwise mentioned the bank addresses should be switched like the row/column

addresses - please see each IDDx definition for details

Command

(CS, RAS, CAS, WE):

Define D = {CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW}

Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH,HIGH,HIGH}

Define Command Background Pattern = D D D D D D D D D D D D...

If other commands are necessary (e.g. ACT for IDD0 or Read for IDD4R), the Background

Pattern Command is substituted by the respective CS, RAS, CAS, WE levels of the necessary

command.

See each IDDx definition for details and figures 1,2,3 as examples.

Table 3 — Definition of SWITCHING for Data (DQ)

SWITCHING for Data (DQ) is defined as

Data (DQ)

Data DQ is changing between HIGH and LOW every other data transfer (once per clock)

for DQ signals, which means that data DQ is stable during one clock; see each IDDx

definition for exceptions from this rule and for further details.

See figures 1,2,3 as examples.

Data Masking (DM) NO Switching; DM must be driven LOW all the time

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Timing parameters are listed in the following table:

The following conditions apply:

- IDD specifications are tested after the device is properly initialized.

- Input slew rate is specified by AC Parametric test conditions.

- IDD parameters are specified with ODT and output buffer disabled (MR1 Bit A12).

Table 4 — For IDD testing the follow ing parameters are utilized.

Parameter

Bin DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Unit

5-5-5 6-6-6 6-6-6 7-7-7 8-8-8 7-7-7 8-8-8 9-9-9 8-8-8 9-9-9 101010

CKmin(IDD) 2.5 1.875 1.5 1.25 ns

CL(IDD) 566787898910clk

RCDmin(IDD) 12.5 15 11.25 13.13 15 10.5 12 13.5 10 11.25 12.5 ns

RCmin(IDD) 50 52.5 48.75 50.63 52.50 46.5 48 49.5 tbd tbd tbd ns

RASmin(IDD) 37.5 37.5 37.5 37.5 37.5 36 36 36 tbd tbd tbd ns

RPmin(IDD) 12.5 15 11.25 13.13 15 10.5 12 13.5 10 11.25 12.5 ns

FAW(IDD) x4/

x8 40 40 37.5 37.5 37.5 30 30 30 30 30 30 ns

x1650505050504545454040 40ns

RRD(IDD) x4/

x8 10 10 7.5 7.5 7.5 6.0 6.0 6.0 6.0 6.0 6.0 ns

x1610101010107.57.57.57.57.57.5ns

RFC(IDD) -

512Mb 90 90 90 90 90 90 90 90 90 90 90 ns

RFC(IDD) - 1

Gb 110 110 110 110 110 110 110 110 110 110 110 ns

RFC(IDD) - 2

Gb 160 160 160 160 160 160 160 160 160 160 160 ns

RFC(IDD) - 4

Gb tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns

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Table 5 — IDD Measurement Conditions for IDD0 and IDD1

Current

DD0

DD1

Name

Operating Current 0

-> One Bank Activate

-> Precharge

Operating Current 1

-> One Bank Activate

-> Read

-> Precharge

Measurement Condition

Timing Diagram Example Figure 1

CKE HIGH HIGH

External Clock on on

CKmin(IDD)

RCmin(IDD)

RAS

RASmin(IDD)

RCD n.a.

RCDmin(IDD)

RRD n.a. n.a.

CL n.a. CL(IDD)

AL n.a. 0

CS HIGH between. Activate and Precharge

Commands

HIGH between Activate, Read and

Precharge

Command Inputs

(CS,RAS, CAS, WE)

SWITCHING as described in Table 2

only exceptions are Activate and

Precharge commands; example of IDD0

pattern:

A0DDDDDDDDDDDDDD P0

(DDR3-800:

RAS = 37.5ns between

(A)ctivate and (P)recharge to bank 0;

Definition of D and D: see Table 2

SWITCHING as described in Table 2; only

exceptions are Activate, Read and

Precharge commands; example of IDD1

pattern:

A0DDDDR0DDDDDDDDD P0

(DDR3-800 -555:

RCD = 12.5ns between

(A)ctivate and (R)ead to bank 0;

Definition of D and D: see Table 2)

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Row, Column Addresses Row addresses SWITCHING as described

in Table 2;

Address Input A10 must be LOW all the

time!

Row addresses SWITCHING a s described

in Table 2;

Address Input A10 must be LOW all the

time!

Bank Addresses bank address is fixed (bank 0) bank address is fixed (bank 0)

Data I/O SWITCHING as described in Table 3 Read Data: output data switches every

clock, which means that Read data is

stable during one clock cycle.

To achieve Iout = 0mA, the output buffer

should be switched off by MR1 Bit A12 set

to “1”.

When there is no read data burst from

DRAM, the DQ I/O should be FLOATING.

Output Buffer DQ,DQS

/ MR1 bit A12

off / 1 off / 1

ODT

/ MR1 bits [A6, A2]

disabled

/ [0,0]

disabled

/ [0,0]

Burst length n.a. 8 fixed / MR0 Bits [A1, A0] = {0,0}

Active banks one

ACT-PRE loop

one

ACT-RD-PRE loop

Idle banks all other all other

Precharge Power Down Mode /

Mode Register Bit 12

n.a. n.a.

Table 5 — IDD Measurement Conditions for IDD0 and IDD1

Current

DD0

DD1

Name

Operating Current 0

-> One Bank Activate

-> Precharge

Operating Current 1

-> One Bank Activate

-> Read

-> Precharge

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< Figure 1. IDD1 Example > (DDR3-800-555, 512Mb x8): Data DQ is shown but the output buffer

should be switched off (per MR1 Bit A12 =”1”) to achieve Iout = 0mA. Address inputs are split into 3

parts.

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T12 T14 T16 T18

3FF 000 3FF 000 3F000

000

11 00 11 0000

ACT D#DD# RDDD# D# D D D# D# D D D# PRE D D D#

0 0 1 1 0 0 1 1

BA[2:0]

ADDR_a[9:0]

ADDR_b[10]

ADDR_c[12:11]

RAS

CAS

CMD

DM IDD1 M easurment Loop

a. In DDR3, the MRS Bit 12 defines DLL on/off behaviour ONLY for precharge power down. There are 2 different

Precharge Power Down states possible: one with DLL on (fast exit, bit 12 = 1) and one with DLL off

(slow exit, bit 12 = 0).

b. Because it is an exit after precharge power down, the valid commands are: Activate, Refresh, Mode-Register Set,

Enter - Self Refresh

Rev. 0.1 / Dec 2008 39

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HMT112U6(7)AFP(R)8C

HMT125U6(7)AFP(R)8C

Table 6 — IDD Measurement Conditions for IDD2N, IDD2P(1), IDD2P(0) and IDD2Q

Current

DD2N

DD2P(1) a

DD2P(0)

DD2Q

Name Precharge Standby

Current

Precharge Power

Down Current

Fast Exit -

MRS A12 Bit = 1

Precharge Power

Down Current

Slow Exit -

MRS A12 Bit = 0

Precharge Quiet

Standby Current

Measurement Condition

Timing Diagram

Example Figure 2

CKE HIGH LOW LOW HIGH

External Clockonononon

CKmin(IDD)

RC n.a. n.a. n.a. n.a.

RAS n.a. n.a. n.a. n.a.

RCD n.a. n.a. n.a. n.a.

RRD n.a. n.a. n.a. n.a.

CL n.a. n.a. n.a. n.a.

AL n.a. n.a. n.a. n.a.

CS HIGH STABLE STABLE HIGH

Bank Address, Row

Addr. and Command

Inputs

SWITCHING as

described in

Table 2 STABLE STABLE STABLE

Data inputs SWITCHING FLOATING FLOATING FLOATING

Output Buffer

DQ,DQS

/ MR1 bit A12 off / 1 off / 1 off / 1 off / 1

ODT

/ MR1 bits [A6, A2] disabled

/ [0,0] disabled

/ [0,0]

Burst length n.a. n.a. n.a. n.a.

Active banks none none none none

Idle banks all all all all

Precharge Power

Down Mode /

Mode Register Bit a n.a. Fast Exit / 1

(any valid command

after tXPb)

Slow Exit / 0

Slow exit (RD and

ODT commands must

satisfy tXPDLL-AL)

n.a.

Rev. 0.1 / Dec 2008 40

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HMT112U6(7)AFP(R)8C

HMT125U6(7)AFP(R)8C

<Figure 2. IDD2N / IDD3N Example > (DDR3-800-555, 512Mb x8)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

7 00

D# D# D D D# D# D D D# D#

FF 00 00 FF FF 00 00 FF FF 00 00 FF FF 00 00 FF FF 00 00 FF FF

BA[2:0]

ADDR[12:0]

RAS

CAS

CMD

DQ[7:0]

Rev. 0.1 / Dec 2008 41

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HMT125U6(7)AFP(R)8C

Table 7 — IDD Measurement Conditions for IDD3N and IDD3P(fast exit)

Current

DD3N

DD3P

Name Active Standby Current Active Power-Down Currenta

Always Fast Exit

a. DDR3 will offer only ONE active power down mode with D LL on (-> f ast exit). MRS bit 12 will not be used for active

power down. Instead bit 12 will be used to switch between two different precharge power down modes.

Measurement Condition

Timing Diagram Example Figure 2

CKE HIGH LOW

External Clock on on

CKmin(IDD)

RC n.a. n.a.

RAS n.a. n.a.

RCD n.a. n.a.

RRD n.a. n.a.

CL n.a. n.a.

AL n.a. n.a.

CS HIGH STABLE

Addr. and cmd Inputs SWITCHING as described in Table 2 STABLE

Data inputs SWITCHING as described in Table 3 FLOATING

Output Buffer DQ,DQS

/ MR1 bit A12 off / 1 off / 1

ODT

/ MR1 bits [A6, A2]

disabled

/ [0,0]

disabled

/ [0,0]

Burst length n.a. n.a.

Active banks all all

Idle banks none none

Precharge Power Down Mode /

Mode Register Bit an.a. n.a. (Active Power Down Mode is always

“Fast Exit” with DLL on

Rev. 0.1 / Dec 2008 42

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HMT112U6(7)AFP(R)8C

HMT125U6(7)AFP(R)8C

Table 8 — IDD Measurement Conditions for IDD4R, IDD4W and IDD7

Current

DD4R

DD4W

DD7

Name Operating Current

Burst Read Operating Current

Burst Write All Bank Interleave Read

Current

Measurement Condition

Timing Diagram

Example Figure 3

CKE HIGH HIGH HIGH

External Clock on on on

CKmin(IDD)

RC n.a. n.a.

RCmin(IDD)

RAS n.a. n.a.

RASmin(IDD)

RCD n.a. n.a.

RCDmin(IDD)

RRD n.a. n.a.

RRDmin(IDD)

CL CL(IDD) CL(IDD) CL(IDD)

AL 0 0

RCDmin - 1

CS HIGH btw. valid cmds HIGH btw. valid cmds HIGH btw. valid cmds

Command Inputs (CS,

RAS, CAS, WE)SWITCHING as described in

Table 2; exceptions are Read

commands => IDD4R

Pattern:

R0DDDR1DDDR2DDDR3.DD

D R4.....

Rx = Read from bank x;

Definition of D and D: see

Table 2

SWITCHING as described in

Table 2; exceptions are Write

commands => IDD4W

Pattern:

W0DDDW1DDDW2DDDW3

DDD W4...

Wx = Write to bank x;

Definition of D and D: see

Table 2

For patterns see Table 9

Rev. 0.1 / Dec 2008 43

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HMT112U6(7)AFP(R)8C

HMT125U6(7)AFP(R)8C

Row, Column

Addresses

column addresses

SWITCHING as described in

Table 2;

Address Input A10 must be

LOW all the time!

column addresses

SWITCHING as described in

Table 2;

Address Input A10 must be

LOW all the time!

STABLE during DESELECTs

Bank Addresses bank address cycling (0 -> 1 -

> 2 -> 3...)

bank address cycling (0 -> 1 -

> 2 -> 3...)

bank address cycling (0 -> 1 -

> 2 -> 3...), s ee pattern in

Table 9

DQ I/O

Seamless Read Data Burst

(BL8): output data switches

every clock, which means that

Read data is stable during one

clock cycle.

To achieve Iout = 0mA the

output buffer should be

switched off by MR1 Bit A12

set to “1”.

Seamless Write Data Burst

(BL8): input data switches

every clock, which means that

Write data is stable during one

clock cycle.

DM is low all the time.

Read Data (BL8 ): output data

switches every clock, which

means that Read data is

stable during one clock cycle.

To achieve Iout = 0mA the

output buffer should be

switched off by MR1 Bit A12

set to “1”.

Output Buffer

DQ,DQS

/ MR1 bit A12

off / 1 off / 1 off / 1

ODT

/ MR1 bits [A6, A2]

disabled

/ [0,0]

disabled

/ [0,0]

disabled

/ [0,0]

Burst length 8 fixed / MR0 Bits [A1, A0] =

{0,0}

8 fixed / MR0 Bits [A1, A0] =

{0,0}

8 fixed / MR0 Bits [A1, A0] =

{0,0}

Active banks all all all, rotational

Idle banks none none none

Precharge Power

Down Mode /

Mode Register Bit

n.a. n.a. n.a.

Table 8 — IDD Measurement Conditions for IDD4R, IDD4W and IDD7

Current

DD4R

DD4W

DD7

Name Operating Current

Burst Read Operating Current

Burst Write All Bank Interleave Read

Current

Rev. 0.1 / Dec 2008 44

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HMT125U6(7)AFP(R)8C

< Figure 3. IDD4R Example > (DDR3-800-555, 512Mb x8): data DQ is shown but the output buffer

should be switched off (per MR1 Bit A12=”1”) to achieve Iout = 0mA. Address inputs are split into 3

parts.

001 010 011

00 00 FF FF 00 00 FF FF 00 00 FF FF 00 00 FF FF

BA[2:0]

ADDR[12:0]

RAS

CAS

CMD[2:0]

DQ[7:0]

3FF 000 3FF

ADDR_b[10]

11 00 11

ADDR_c[12:11]

000

RD DD# D# RD DD# D# D# RDD# RD D

-> Start of M easurem ent Loop

Rev. 0.1 / Dec 2008 45

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HMT112U6(7)AFP(R)8C

HMT125U6(7)AFP(R)8C

Table 9 — IDD7 Pattern for different Speed Grades and different tRRD, tFAW conditions

Speed Bin Org. tFAW tFAW tRRD tRRD IDD7 Patterna

a. A0 = Activation of Bank 0; RA0 = Read with Auto-Precharge of Bank 0; D = Deselect

Mb/s [ns] [CLK] [ns] [CLK] (Note this entire sequence is repeated.)

800

all x4/x8 40 16 10 4 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D A4

RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D

all x16 50 20 10 4 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D

D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D

D D D D

1066

all x4/x8 37.5 20 7.5 4 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D

D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D

D D D D

all x16 50 27 10 6 A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D D D D A3

RA3 D D D D D D D A4 RA4 D D D D A5 RA5 D D D D

A6 RA6 D D D D A7 RA7 D D D D D D D

1333

all x4/x8 30 20 6 4 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D

D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D

D D D D

all x16 45 30 7.5 5 A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3 RA3 D

D D D D D D D D D D D D A4 RA4 D D D A5 RA5 D D

D A6 RA6 D D D A7 RA7 D D D D D D D D D D D D D

1600

all x4/x8 30 24 6 5 A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3 RA3 D

D D D D D D A4 RA4 D D D A5 RA5 D D D A6 RA6 D D

D A7 RA7 D D D D D D D

all x16 40 32 7.5 6

A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D D D D A3

RA3 D D D D D D D D D D D D A4 RA4 D D D D A5 RA5

D D D D A6 RA6 D D D D A7 RA7 D D D D D D D D D

D D D

Rev. 0.1 / Dec 2008 46

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HMT112U6(7)AFP(R)8C

HMT125U6(7)AFP(R)8C

Table 10 — IDD Measurement Conditions for IDD5B

Current

DD5B

Name Burst Refresh Current

Measurement Condition

CKE HIGH

External Clock on

CKmin(IDD)

RC n.a.

RAS n.a.

RCD n.a.

RRD n.a.

RFC

RFCmin(IDD)

CL n.a.

AL n.a.

CS HIGH btw. valid cmds

Addr. and cmd Inputs SWITCHING

Data inputs SWITCHING

Output Buffer DQ,DQS / MR1 bit A12 off / 1

ODT / MR1 bits [A6, A2] disabled / [0,0]

Burst length n.a.

Active banks Refresh command every tRFC=tRFCmin

Idle banks none

Precharge Power Down Mode / Mode Register Bit n.a.

Rev. 0.1 / Dec 2008 47

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HMT112U6(7)AFP(R)8C

HMT125U6(7)AFP(R)8C

Table 11 — IDD Measurement Conditions for IDD6 and IDD6ET

Current

DD6

DD6ET

Name Self-Refresh Current

Normal Temperature Range

CASE = 0. 85 °C

Self-Refresh Current

Extended Temperature Range a

CASE = 0. 95 °C

a. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3 SDRAM

devices support the following options or requirements referred to in this material.

Measurement Condition

Temperature

CASE = 85 °C

CASE = 95 °C

Auto Self Refresh (ASR) /

MR2 Bit A6 Disabled / “0” Disabled / “0”

Self Refresh Temperature

Range (SRT) /

MR2 Bit A7 Normal / “0” Extended / “1”

CKE LOW LOW

External Clock OFF; CK and CK at LOW OFF; CK and CK at LOW

CK n.a. n.a.

RC n.a. n.a.

RAS n.a. n.a.

RCD n.a. n.a.

RRD n.a. n.a.

CL n.a. n.a.

AL n.a. n.a.

CS FLOATING FLOATING

Command Inputs

(RAS, CAS, WE)FLOATING FLOATING

Row, Column Addresses FLOATING FLOATING

Bank Addresses FLOATING FLOATING

Data I/O FLOATING FLOATING

Output Buffer DQ,DQS

/ MR1 bit A12 off / 1 off / 1

ODT

/ MR1 bits [A6, A2] disabled

/ [0,0] disabled

/ [0,0]

Burst length n.a. n.a.

Active banks all during self-refresh actions all during self-refresh actions

Idle banks all btw. Self-Refresh actions all btw. Self-Refresh actions

Precharge Power Down Mode

/ MR0 bit A12 n.a. n.a.

Rev. 0.1 / Dec 2008 48

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HMT125U6(7)AFP(R)8C

7. Electrical Characteristics and AC Timing

7.1 Refresh Parameters by Device Density

7.2 DDR3 SDRAM Standard Speed Bins includ e tCK, tRCD, tRP, tRAS and tRC

for each corresponding bin

Parameter Symbol 512Mb 1Gb 2Gb 4Gb 8Gb Units

REF command to

ACT or REF

command time tRFC 90 110 160 300 350 ns

Average periodic

refresh interval tREFI 0 ×C < TCASE < 85 ×C 7.8 7.8 7.8 7.8 7.8 ms

85 ×C < TCASE < 95 ×C 3.9 3.9 3.9 3.9 3.9 ms

DDR3 800 Speed Bin DDR3-800D DDR3-800E

Unit Notes

CL - nRCD - nRP 5-5-5 6-6-6

Parameter Symbol min max min max

Internal read command to first data

AA 12.5201520ns

ACT to internal read or write delay time

RCD 12.5 — 15 — ns

PRE command period

RP 12.5 — 15 — ns

ACT to ACT or REF command period

RC 50 — 52.5 — ns

ACT to PRE command period

RAS 37.5 9 * tREFI 37.5 9 * tREFI ns

CL = 5 CWL = 5

CK(AVG) 2.5 3.3 Reserved ns 1)2)3)4)

CL = 6 CWL = 5

CK(AVG) 2.5 3.3 2.5 3.3 ns 1)2)3)

Supported CL Settings 5, 6 6

Supported CWL Settings 55

Rev. 0.1 / Dec 2008 49

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HMT125U6(7)AFP(R)8C

DDR3 1066 Speed Bin DDR3-1066E DDR3-1066F DDR3-1066G

Unit Note

CL - nRCD - nRP 6-6-6 7-7-7 8-8-8

Parameter Symbol min max min max min max

Internal read command to

first data

AA 11.25 20 13.125 20 15 20 ns

ACT to internal read or

write delay time

RCD 11.25 — 13.125 — 15 — ns

PRE command period

RP 11.25 — 13.125 — 15 — ns

ACT to ACT or REF

command period

RC 48.75 — 50.625 — 52.5 — ns

ACT to PRE command

period

RAS 37.5 9 * tREFI 37.5 9 * tREFI 37.5 9 * tREFI ns

CL = 5 CWL = 5

CK(AVG) 2.5 3.3 Reserved Reserved ns 1)2)3)4)6)

CWL = 6

CK(AVG) Reserved Reserved Reserved ns 4)

CL = 6 CWL = 5

CK(AVG) 2.5 3.3 2.5 3.3 2.5 3.3 ns 1)2)3)6)

CWL = 6

CK(AVG) 1.875 < 2.5 Reserved Reserved ns 1)2)3)4)

CL = 7 CWL = 5

CK(AVG) Reserved Reserved Reserved ns 4)

CWL = 6

CK(AVG) 1.875 < 2.5 1.875 < 2.5 Reserved ns 1)2)3)4)

CL = 8 CWL = 5

CK(AVG) Reserved Reserved Reserved ns 4)

CWL = 6

CK(AVG) 1.875 < 2.5 1.875 < 2.5 1.875 < 2.5 ns 1)2)3)

Supported CL Settings 5, 6, 7, 8 6, 7, 8 6, 8

Supported CWL Settings 5, 6 5, 6 5, 6

Rev. 0.1 / Dec 2008 50

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HMT112U6(7)AFP(R)8C

HMT125U6(7)AFP(R)8C

DDR3 1333 Speed Bin DDR3-1333F

(optional) DDR3-1333G DDR3-1333H DDR3-1333J

(optional)

Unit Note

CL - nRCD - nRP 7-7-7 8-8-8 9-9-9 10-10-10

Parameter Symbol min max min max min max min max

Internal read

command to first

AA 10.5 20 12 20 13.5 20 15 20 ns

ACT to internal read

or write delay time

RCD 10.5 — 12 — 13.5 — 15 — ns

PRE command period

RP 10.5 — 12 — 13.5 — 15 — ns

ACT to ACT or REF

command period

RC 46.5 — 48 — 49.5 — 51 — ns

ACT to PRE

command period

RAS 36 9 *

tREFI 36 9 *

tREFI ns

CL = 5 CWL = 5

CK(AVG) 2.5 3.3 2.5 3.3 Reserved Reserved ns 1,2,3,4,7

CWL = 6, 7

CK(AVG) Reserved Reserved Reserved Reserved ns 4

CL = 6

CWL = 5

CK(AVG) 2.5 3.3 2.5 3.3 2.5 3.3 2.5 3.3 ns 1,2,3,7

CWL = 6

CK(AVG) 1.875 < 2.5 Reserved Reserved Reserved ns 1,2,3,4,7

CWL = 7

CK(AVG) Reserved Reserved Reserved Reserved ns 4

CL = 7

CWL = 5

CK(AVG) Reserved Reserved Reserved Reserved ns 4

CWL = 6

CK(AVG) 1.875 < 2.5 1.875 < 2.5 Reserved Reserved ns 1,2,3,4,7

CWL = 7

CK(AVG) 1.5 <1.875 Reserved Reserved Reserved ns 1,2,3,4

CL = 8

CWL = 5

CK(AVG) Reserved Reserved Reserved Reserved ns 4

CWL = 6

CK(AVG) 1.875 < 2.5 1.875 < 2.5 1.875 < 2.5 1.875 < 2.5 ns 1,2,3,7

CWL = 7

CK(AVG) 1.5 <1.875 1.5 <1.875 Reserved Reserved ns 1,2,3,4

CL = 9 CWL = 5, 6

CK(AVG) Reserved Reserved Reserved Reserved ns 4

CWL = 7

CK(AVG) 1.5 <1.875 1.5 <1.875 1.5 <1.875 Reserved ns 1,2,3,4

CL = 10 CWL = 5, 6

CK(AVG) Reserved Reserved Reserved Reserved ns 4

CWL = 7

CK(AVG) 1.5 <1.875 1.5 <1.875 1.5 <1.875 1.5 <1.875 ns 1,2,3

(Optional) (Optional) (Optional) ns 5

Supported CL Settings 5, 6, 7, 8, 9 5, 6, 7, 8, 9 6, 8, 9 6, 8, 10

Supported CWL Settings 5, 6, 7 5, 6, 7 5, 6, 7 5, 6, 7

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DDR3 1600 Speed Bin DDR3-1600G

(optional) DDR3-1600H DDR3-1600J DDR3-1600K

(optional) Unit Note

CL - nRCD - nRP 8-8-8 9-9-9 10-10-10 11-11-11

Parameter Symbol min max min max min max min max

Internal read command

to first data

AA 10 20 11.25 20 12.5 20 13.75 20 ns

ACT to internal read or

write delay time

RCD 10 — 11.25 — 12.5 — 13.75 — ns

PRE command period

RP 10 — 11.25 — 12.5 — 13.75 — ns

ACT to ACT or REF

command period

RC 45 — 46.25 — 47.5 — 48.75 — ns

ACT to PRE command

period

RAS 35 9 *

tREFI 35 9 *

tREFI ns

CL = 5 CWL = 5

CK(AVG) 2.5 3.3 2.5 3.3 2.5 3.3 Reserved ns 1,2,3,4,8

CWL = 6, 7, 8

CK(AVG) Reserved Reserved Reserved Reserved ns 4

CL = 6

CWL = 5

CK(AVG) 2.5 3.3 2.5 3.3 2.5 3.3 2.5 3.3 ns 1,2,3,8

CWL = 6

CK(AVG) 1.875 < 2.5 1.875 < 2.5 Reserved Reserved ns 1,2,3,4,8

CWL = 7, 8

CK(AVG) Reserved Reserved Reserved Reserved ns 4

CL = 7

CWL = 5

CK(AVG) Reserved Reserved Reserved Reserved ns 4

CWL = 6

CK(AVG) 1.875 < 2.5 1.875 < 2.5 1.875 < 2.5 Reserved ns 1,2,3,4,8

CWL = 7

CK(AVG) 1.5 <1.875 Reserved Reserved Reserved ns 1,2,3,4,8

CWL = 8

CK(AVG) Reserved Reserved Reserved Reserved ns 4

CL = 8

CWL = 5

CK(AVG) Reserved Reserved Reserved Reserved ns 4

CWL = 6

CK(AVG) 1.875 < 2.5 1.875 < 2.5 1.875 < 2.5 1.875 < 2.5 ns 1,2,3,8

CWL = 7

CK(AVG) 1.5 <1.875 1.5 <1.875 Reserved Reserved ns 1,2,3,4,8

CWL = 8

CK(AVG) 1.25 < 1.5 Reserved Reserved Reserved ns 1,2,3,4

CL = 9

CWL = 5, 6

CK(AVG) Reserved Reserved Reserved Reserved ns 4

CWL = 7

CK(AVG) 1.5 <1.875 1.5 <1.875 1.5 <1.875 Reserved ns 1,2,3,4,8

CWL = 8

CK(AVG) 1.25 < 1.5 1.25 < 1.5 Reserved Reserved ns 1,2,3,4

CL = 10

CWL = 5, 6

CK(AVG) Reserved Reserved Reserved Reserved ns 4

CWL = 7

CK(AVG) 1.5 <1.875 1.5 <1.875 1.5 <1.875 1.5 <1.875 ns 1,2,3,8

CWL = 8

CK(AVG) 1.25 < 1.5 1.25 < 1.5 1.25 < 1.5 Reserved ns 1,2,3,4

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HMT125U6(7)AFP(R)8C

*Speed Bin Table Notes*

Absolute Specification (TOPER; VDDQ = VDD = 1.5V +/- 0.075 V);

Notes:

1. The CL setting and CWL se t ting re sult in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection

of tCK(AVG), both need to be fulfilled: Requirements from CL setting as well a s requirements from CWL set ting.

2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output ar e synchronized by the

DLL - all possible intermediate frequencies may not be guar anteed. An application should use the next smaller JEDEC

standard tCK(AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] = tAA [ns] / tCK(A VG) [ns],

rounding up to the next ‘Supported CL’.

3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CLSELECTED and round the resulting tCK(AVG) down to the

next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is tCK(AVG).MAX corresponding to

CLSELECTED.

4. ‘Reserved’ settings are not allowed. User must program a different value.

5. ‘Optional’ settings allow certain devices in the industry to support this setting, however, it is not a mandatory

feature. Refer to supplier’s data sheet and SPD information if and how this setting is supported.

6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are

not subject to Production Tests but verified by Design/Characterization.

7. Any DDR3-1333 speed bin also supports f unctional operation at lower frequencies as shown in the table which are

not subject to Production Tests but verified by Design/Characterization.

8. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table which are

not subject to Production Tests but verified by Design/Characterization.

CL = 11 CWL = 5, 6, 7

CK(AVG) Reserved Reserved Reserved Reserved ns 4

CWL = 8

CK(AVG) 1.25 < 1.5 1.25 < 1.5 1.25 < 1.5 1.25 < 1.5 ns 1,2,3

(Optional) (Optional) (Optional) ns 5

Supported CL Settings 5, 6, 7, 8, 9, 10 5, 6, 7, 8, 9, 10 5, 6, 7, 8, 9, 10 6, 8, 10, 11

Supported CWL Settings 5, 6, 7, 8 5, 6, 7, 8 5, 6, 7, 8 5, 6, 7, 8 nCK

Rev. 0.1 / Dec 2008 53

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HMT125U6(7)AFP(R)8C

8. Dimm Outline Diagram

8.1 164Mx64 - HMT164U6AFP(R)6C

9.50

30.00

17.30

Max R0.70

2.50 0.10±

Min 1.45

DETAIL-A DETAIL-B

2.10 0.15±

3.00 0.10±

2.30 0.10±

5.175 47.00 71.00

128.95

133.35

0.35

1.00

0.3~1.0

Detail - B

5.00

3.80

0.05

2.50 0.20±

0.80 0.05±

0.3 0.15±

1.50 0.10±

2.50 FULL R

Detail - A

1.27

0.10

3.18

Front

Back

Side

SPD

Note) All dimensions are in millimeters unless otherwise stated.

Rev. 0.1 / Dec 2008 54

HMT164U6AFP(R)6C

HMT112U6(7)AFP(R)8C

HMT125U6(7)AFP(R)8C

8.2 128Mx64 - HMT112U6AFP(R)8C

9.50

17.30

Max R0.70

2.50 0.10±

Min 1.45

DETAIL-A DETAIL-B

2.10 0.15±

3.00 0.10±

2.30 0.10±

5.175 47.00 71.00

128.95

133.35

0.35

1.00

0.3~1.0

Detail - B

5.00

3.80

0.05

2.50 0.20±

0.80 0.05±

0.3 0.15±

1.50 0.10±

2.50 FULL R

Detail - A

1.27

0.10

3.18

Back

Side

30.00

Front

SPD

Note) All dimensions are in millimeters unless otherwise stated.

Rev. 0.1 / Dec 2008 55

HMT164U6AFP(R)6C

HMT112U6(7)AFP(R)8C

HMT125U6(7)AFP(R)8C

8.3 128Mx72 - HMT112U7AFP(R)8C

9.50

17.30

Max R0.70

2.50 0.10±

Min 1.45

DETAIL-A DETAIL-B

2.10 0.15±

3.00 0.10±

2.30 0.10±

5.175 47.00 71.00

128.95

133.35

0.35

1.00

0.3~1.0

Detail - B

5.00

3.80

0.05

2.50 0.20±

0.80 0.05±

0.3 0.15±

1.50 0.10±

2.50 FULL R

Detail - A

1.27

0.10

3.18

Back

Side

30.00

Front

SPD

Note) All dimensions are in millimeters unless otherwise stated.

Rev. 0.1 / Dec 2008 56

HMT164U6AFP(R)6C

HMT112U6(7)AFP(R)8C

HMT125U6(7)AFP(R)8C

8.4 256Mx64 - HMT125U6AFP(R)8C

9.50

17.30

Max R0.70

2.50 0.10±

Min 1.45

DETAIL-A DETAIL-B

2.10 0.15±

3.00 0.10±

2.30 0.10±

5.175 47.00 71.00

128.95

133.35

0.35

1.00

0.3~1.0

Detail - B

5.00

3.80

0.05

2.50 0.20±

0.80 0.05±

0.3 0.15±

1.50 0.10±

2.50 FULL R

Detail - A

1.27

0.10

4.00

Back

Side

30.00

Front

SPD

Note) All dimensions are in millimeters unless otherwise stated.

Rev. 0.1 / Dec 2008 57

HMT164U6AFP(R)6C

HMT112U6(7)AFP(R)8C

HMT125U6(7)AFP(R)8C

8.5 256Mx72 - HMT125U7AFP(R)8C

9.50

17.30

Max R0.70

2.50 0.10±

Min 1.45

DETAIL-A DETAIL-B

2.10 0.15±

3.00 0.10±

2.30 0.10±

5.175 47.00 71.00

128.95

133.35

0.35

1.00

0.3~1.0

Detail - B

5.00

3.80

0.05

2.50 0.20±

0.80 0.05±

0.3 0.15±

1.50 0.10±

2.50 FULL R

Detail - A

1.27

0.10

4.00

Back

Side

30.00

Front

SPD

Note) All dimensions are in millimeters unless otherwise stated.