General Description
The MAX1232 microprocessor (µP) supervisory circuit
provides µP housekeeping and power-supply supervi-
sion functions while consuming only 1/10th the power of
the DS1232. The MAX1232 enhances circuit reliability
in µP systems by monitoring the power supply, monitor-
ing the software execution, and providing a debounced
manual reset input. The MAX1232 is a plug-in upgrade
of the Dallas DS1232.
A reset pulse of at least 250ms duration is supplied on
power-up, power-down, and low-voltage brownout
conditions (5% or 10% supply tolerances can be
selected digitally). Also featured is a debounced man-
ual reset input that forces the reset outputs to their
active states for a minimum of 250ms. A digitally pro-
grammable watchdog timer monitors software execu-
tion and can be programmed for timeout settings of
150ms, 600ms, or 1.2s. The MAX1232 requires no
external components.
Applications
Computers
Controllers
Intelligent Instruments
Automotive Systems
Critical µP Power Monitoring
Features
oConsumes 1/10th the Power of the DS1232
oPrecision Voltage Monitor—Adjustable +4.5V
or +4.75V
oPower-OK/Reset Pulse Width—250ms Min
oNo External Components
oAdjustable Watchdog Timer—150ms, 600ms,
or 1.2s
oDebounced Manual Reset Input for External
Override
oAvailable in 8-Pin PDIP/SO and 16-Pin Wide SO
Packages
MAX1232
Microprocessor Monitor
________________________________________________________________
Maxim Integrated Products
1
RST
RSTGND
1
2
8
7
VCC
STTD
TOL
PB RST
DIP/SO
TOP VIEW
3
4
6
5
MAX1232
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
N.C. N.C.
VCC
N.C.
ST
N.C.
RST
N.C.
RST
MAX1232
WIDE SO
PB RST
N.C.
TOL
TD
N.C.
N.C.
GND
Pin Configurations
Ordering Information
5%/10%
TOLERANCE
SELECT RESET
GENERATOR
DEBOUNCE
REF
TOL
V
CC
PB RST
RST
RST
STTD
GND
WATCHDOG
TIMEBASE
SELECT
WATCHDOG
TIMER
MAX1232
Typical Operating Circuit
19-3899; Rev 1; 11/05
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Ordering Information continued on last page.
*
Contact factory for dice specifications.
Devices in PDIP and SO packages are available in both leaded
and lead-free packaging. Specify lead free by adding the
+
symbol at the end of the part number when ordering. Lead free
not available for CERDIP package.
PART TEMP RANGE PIN-PACKAGE
MAX1232C/D 0°C to +70°C Dice*
MAX1232CPA 0°C to +70°C 8 PDIP
MAX1232CSA 0°C to +70°C 8 SO
MAX1232
Microprocessor Monitor
2_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Recommended DC Operating Conditions
(TA= TMIN to TMAX)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage on Any Pin (with respect to GND)……………-1V to +7V
Operating Temperature Range
C Suffix………………………………………………0°C to +70°C
E Suffix.……………………………………………-40°C to +85°C
M Suffix .…………………………………………-55°C to +125°C
Storage Temperature Range……………………-65°C to +160°C
Lead Temperature (soldering, 10s)………………………+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Voltage V
CC
4.5 5.0 5.5 V
ST and PBRST Input High Level
(Note 1) V
IH
2.0 V
CC
+
0.3 V
ST and PBRST Input Low Level V
IL
-0.3 +0.8 V
Capacitance (Note 4)
(TA= +25°C)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Capacitance ST, TOL C
IN
5pF
Output Capacitance RST, RST C
OUT
7pF
DC Electrical Characteristics
(VCC = +4.5V to +5.5V, TA= TMIN to TMAX)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Leakage ST, TOL I
IL
-1.0 +1.0 µA
Output Current RST I
OH
V
OH
= 2.4V -1.0 -12 mA
Output Current RST, RST I
OL
V
OL
= 0.4V 2.0 10 mA
Operating Current (Note 2) I
CC
50 200 µA
V
CC
5% Trip Point (Note 3) V
CCTP
TOL = GND 4.50 4.62 4.74 V
V
CC
10% Trip Point (Note 3) V
CCTP
TOL = V
CC
4.25 4.37 4.49 V
MAX1232
Pin Description
Microprocessor Monitor
_______________________________________________________________________________________ 3
Note 1: PBRST is internally pulled up to VCC with an internal impedance of typically 40kΩ.
Note 2: Measured with outputs open.
Note 3: All voltages referenced to GND.
Note 4: Guaranteed by desing.
Note 5: PBRST must be held low for a minimum of 20ms to guarantee a reset.
Note 6: tR= 5µs.
AC Electrical Characteristics
(VCC = +5V ±10%, TA= TMIN to TMAX)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
PBRST (Note 5) t
PB
Figure 3 20 ms
PBRST Delay t
PBD
Figure 3 1 4 20 ms
Reset Active Time t
RST
250 610 1000 ms
ST Pulse Width t
ST
Figure 4 75 ns
Figure 4, TD pin = 0V 62.5 150 250
TD pin = open 250 600 1000
ST Timeout Period t
TD
TD pin = V
CC
500 1200 2000
ms
V
CC
Fall Time (Note 4) t
F
Figure 5 10 µs
V
CC
Rise Time (Note 4) t
B
Figure 6 0 µs
V
CC
Detect to RST High and RST
Low t
BPD
Figure 7, V
CC
falling 100 ns
V
CC
Detect to RST Low and RST
Open (Note 6) t
BPU
Figure 8, V
CC
rising 250 610 1000 ms
PIN
WIDE SO DIP/SO NAME FUNCTION
1, 3, 5, 7, 10,
12, 14, 16 —N.C. No Connection
21PBRST Pushbutton Reset Input. A debounced active-low input that ignores pulses less than 1ms
in duration and is guaranteed to recognize inputs of 20ms or greater.
42TD
Time Delay Set. The watchdog timebase select input (t
TD
= 150ms for TD = 0V, t
TD
=
600ms for TD = open, t
TD
= 1.2s for TD = V
CC
).
63TOL Tolerance Input. Connect to GND for 5% tolerance or to V
CC
for 10% tolerance.
84GND Ground
95RST
Reset Output (Active High). Goes active:
(1) If VCC falls below the selected reset voltage threshold
(2) If PBRST is forced low
(3) If ST is not strobed within the minimum timeout period
(4) During power-up
11 6 RST Reset Output (Active Low, Open-Drain). See RST.
13 7 ST Strobe Input. Input for watchdog timer.
15 8 V
CC
The +5V Power-Supply Input
MAX1232
Detailed Description
Power Monitor
A voltage detector monitors VCC and holds the reset
outputs (RST and RST) in their active states whenever
VCC is below the selected 5% or 10% tolerance (4.62V
or 4.37V, typically). To select the 5% level, connect
TOL to ground. To select the 10% level, connect TOL to
VCC. The reset outputs will remain in their active states
until VCC has been continuously in-tolerance for a mini-
mum of 250ms (the reset active time) to allow the
power supply and µP to stabilize.
The RST output both sinks and sources current, while
the RST output, an open-drain MOSFET, sinks current
only and must be pulled high.
Pushbutton Reset Input
The MAX1232’s debounced manual reset input
(PBRST) manually forces the reset outputs into their
active states. The reset outputs go active after PBRST
has been held low for a time tPBD, the pushbutton reset
delay time. The reset outputs remain in their active
states for a minimum of 250ms after PBRST rises above
VIH (Figure 3).
A mechanical pushbutton or an active logic signal can
drive the PBRST input. The debounced input ignores
input pulses less than 1ms and is guaranteed to recog-
nize pulses of 20ms or greater. The PBRST input has
an internal pullup to VCC of about 100µA; therefore, an
external pullup resistor is not necessary.
Watchdog Timer
The microprocessor drives the ST input with an
input/output (I/O) line. The microprocessor must toggle
the ST input within a set period (as determined by TD)
to verify proper software execution. If a hardware or
software failure keeps ST from toggling within the mini-
mum timeout period—ST is activated only by falling
edges (a high-to-low transition)—the MAX1232 reset
outputs are forced to their active states for 250ms
(Figure 2). This typically initiates the microprocessor’s
power-up routine. If the interruption continues, new
reset pulses are generated each timeout period until ST
is strobed. The timeout period is determined by the TD
input connection. This timeout period is typically 150ms
with TD connected to GND, 600ms with TD floating, or
1200ms with TD connected to VCC.
The software routine that strobes ST is critical. The
code must be in a section of software that executes fre-
quently enough so the time between toggles is less
than the watchdog timeout period. One common tech-
nique controls the microprocessor I/O line from two
sections of the program. The software might set the I/O
line high while operating in the foreground mode, and
set it low while in the background or interrupt mode. If
both modes do not execute correctly, the watchdog
timer issues reset pulses.
Microprocessor Monitor
4_______________________________________________________________________________________
MICROPROCESSOR
RESET
PB RST
RST
+5V
V
CC
ST
TOLGND
TD
I/O
MAX1232
7805
3-TERMINAL
REGULATOR
MICROPROCESSOR
RESETRST
+8V +5V
10kΩ
+5V
V
CC
0.1µF
ST
TOL GNDTD
I/O
MAX1232
Figure 1. Pushbutton Reset Figure 2. Watchdog Timer
MAX1232
Microprocessor Monitor
_______________________________________________________________________________________ 5
tRST
tPBD
tPB
VIH
VIL
PB RST
RST
RST
t
ST
t
TD
ST
NOTE: t
SD
IS THE MAXIMUM ELAPSED TIME BETWEEN ST HIGH-TO-LOW
TRANSITIONS (ST IS ACTIVATED BY FALLING EDGES ONLY) WHICH WILL
KEEP THE WATCHDOG TIMER FROM FORCING THE RESET OUTPUTS
ACTIVE FOR A TIME OF t
RST
. t
TD
IS A FUNCTION OF THE VOLTAGE AT
THE TD PIN, AS TABULATED BELOW.
CONDITION
TD pin = 0V
TD pin = open
TD pin = V
CC
MIN
t
TD
TYP
150ms
250ms
1200ms
MAX
62.5ms
250ms
500ms
250ms
1000ms
2000ms
Figure 3. Pushbutton Reset. The debounced PBRST input
ignores input pulses less than 1ms and is guaranteed to rec-
ognize pulses of 20ms or greater.
Figure 4. Watchdog Strobe Input
t
F
V
CC
+4.75V
+4.25V
t
R
V
CC
+4.75V
+4.25V
Figure 5. Power-Down Slew Rate Figure 6. Power-Up Slew Rate
MAX1232
Microprocessor Monitor
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
6
_____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
©2005 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
Package Information
For the latest package outline information, go to
www.maxim-ic.com/packages.
t
RPD
V
CC
RST
V
CC
SLEW RATE = 1.66mV/µsec (0.5V/300µsec)
RST
+4.25V (10% TRIP POINT)
+4.5V (5% TRIP POINT)
V
OH
V
OL
0.099"
(2.51 mm)
0.070"
(1.78 mm)
ST
RST
RSTGND
TD
TOL
PB RST V
CC
t
RPU
V
CC
RST
RST
+4.75V (5% TRIP POINT)
+4.5V (10% TRIP POINT)
V
OH
V
OL
Figure 7. VCC Detect Reset Output Delay (Power-Down) Figure 8. VCC Detect Reset Output Delay (Power-Up)
Ordering Information (continued)
Chip Topography
Ordering Information continued on last page.
*
Contact factory for dice specifications.
Devices in PDIP and SO packages are available in both leaded
and lead-free packaging. Specify lead free by adding the
+
symbol at the end of the part number when ordering. Lead free
not available for CERDIP package.
PART TEMP RANGE PIN-PACKAGE
MAX1232CWE 0°C to +70°C 16 Wide SO
MAX1232EPA -40°C to +85°C 8 PDIP
MAX1232ESA -40°C to +85°C 8 SO
MAX1232EWE -40°C to +85°C 16 Wide SO
MAX1232MJA -55°C to +125°C 8 CERDIP
