This is information on a product in full production.
June 2014 DocID15232 Rev 7 1/30
VIPER16
Fixed frequency VIPer™ plus family
Datasheet
-
production data
Figure 1. Typical application
Features
•800 V avalanche rugged power section
•PWM operation with frequency jittering for low
EMI
•Operating frequency:
– 60 kHz for L type
– 115 kHz for H type
•No need of auxiliary winding for low power
application
•Standby power < 30 mW at 230 V
AC
•Limiting current with adjustable set point
•On-board soft-start
•Safe auto-restart after a fault condition
•Hysteretic thermal shutdown
Application
•Replacement of capacitive power supply
•Auxili ar y power suppl y for appli anc es ,
•Power metering
•LED drivers
Description
The device is an off-line converter with an 800 V
avalanche ruggedness power section, a PWM
controller, user defined overcurrent limit,
protection against feedback network
disconnection, hysteretic thermal protection, soft
start up and safe auto restart after any fault
condition. It is able to power itself directly from the
rectified mains, eliminating the need for an
auxiliary bias winding. Advance frequency jittering
reduces EMI filter cost. Burst mode operation and
the devices very low consumption both help to
meet the standard set by energy saving
regulations.
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Table 1. Device summary
Order codes Package Packaging
VIPER16LN DIP-7 Tube
VIPER16HN
VIPER16HD
SO16 narrow
Tube
VIPER16HDTR Tape and reel
VIPER16LD Tube
VIPER16LDTR Tape and reel
www.st.com
Contents VIPER16
2/30 DocI D15232 Rev 7
Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Typical power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.3 Elect rical characteristi c s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5 Typical electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6 Typical circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7 Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
8 High voltage current generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
9 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
10 Soft start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
11 Adjustable current limit set point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
12 FB pin and COMP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
13 Burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
14 Automatic auto restart after overload or short-circuit . . . . . . . . . . . . . 20
15 Open loop failure protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DocID15232 Rev 7 3/30
VIPER16 Contents
30
16 Layout guidelines and design recommendations . . . . . . . . . . . . . . . . 23
17 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Block diagram VIPER16
4/30 DocI D15232 Rev 7
1 Block diagram
2 Typical power
Figure 2. Block diagram
Table 2. Typical power
Part number 230 V
AC
85-265 V
AC
Adapter
(1)
1. Typical continuous power in non ventilated enclosed adapter measured at 50
°
C ambient.
Open frame
(2)
2. Maximum pract ical continuous power in an open frame design at 50
°
C ambient, with adequate heat
sinking.
Adapter
(1)
Open frame
(2)
VIPER16 9 W 10 W 5 W 6 W
DocID15232 Rev 7 5/30
VIPER16 Pin settings
30
3 Pin settings
Figure 3. Connection diagram (top view)
Note: The copper area for heat dissipation has to be designed under the DRAIN pins.
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Table 3. Pin description
Pin N. Name Function
DIP-7 SO16
11-2GND
Conne cted to the sour ce of the intern al power MOSFET and controlle r
ground reference.
-4N.A.
Not available for user. This pin is mechanically connected to the
control ler die p ad of the fram e. In order t o i mprove t he noise immuni ty,
is highly recommended connect it to GND (pin 1-2).
2 5 VDD Supply voltage of the control section. This pin provides the charging
current of the external capacitor.
36LIM
This pin allows setting the drain current limitation to a lower value
respect to I
Dlim
, which is the default one. The limit can be reduced by
connecting an external resistor between this pin and GND. In case of
high electric al noise, a capacitor could be connected between this pin
and GND, the capacitor value must be lower than 470 nF in order to
not impact the functionality of the pin. The pin can be left open if
default drain current limitation, I
Dlim
, is used.
47FB
Inverting input of the internal trans conductance error amplifier.
Connecting the converter output to this pin through a single resistor
results in an output voltage equal to the error amplifier reference
voltage (see V
FB_REF
on Table 8). An external resistors divider is
required for higher output volt ag es .
Pin settings VIPER16
6/30 DocI D15232 Rev 7
58COMP
Output of the internal trans conductance error amplifier. The
compe nsation network have to be place d between this pi n and GND to
achiev e st a bility and g ood dy nami c perfo rma nce o f the v olt age c ontr ol
loop. The pin is used also to directly control the PWM with an
optocoupler. The linear voltage range extends from V
COMPL
to
V
COMPH
(Table 8).
7,8 13-16 DRAIN Hi gh v oltage drai n pin. The bui lt-i n hi gh v ol t age sw it ch ed s tart-up bi as
current is drawn from this pin too.
Pins connected to the metal frame to facilitate heat dissipation.
Table 3. Pin description (continued)
Pin N. Name Function
DIP-7 SO16
DocID15232 Rev 7 7/30
VIPER16 Electrical data
30
4 Electrical data
4.1 Maximum ratings
4.2 Thermal data
Table 4. Absolute maximum ratings
Symbol Pin
(DIP-7) Parameter Value Unit
Min Max
V
DRAIN
7, 8 Drain-to-source (ground) voltage 800 V
E
AV
7, 8 Repetitive avalanche energy (limited by T
J
= 150 °C) 2 mJ
I
AR
7, 8 Repetitive avalanche current (limited by T
J
= 150 °C) 1 A
I
DRAIN
7, 8 Pulse drain current (limited by T
J
= 150 °C) 2.5 A
V
COMP
5 Input pin voltage -0.3 3.5 V
V
FB
4 Input pin voltage -0.3 4.8 V
V
LIM
3 Input pin voltage -0.3 2.4 V
V
DD
2 Supply voltage -0.3 Self
limited V
I
DD
2 In put cu rrent 20 mA
P
TOT
Power dissipation at T
A
< 40 °C (DIP-7) 1 W
Power dissipation at T
A
< 60 °C (SO16N) 1 W
T
J
Operating junction temperature range -40 150 °C
T
STG
Storage temperature -55 150 °C
ESD
(HBM)
1 to 8 Human body model 4 kV
ESD
(CDM)
1 to 8 Charge device model 1.5 kV
Table 5. Thermal data
Symbol Parameter Max value
SO16N Max value
DIP-7 Unit
R
thJP
Thermal resistance junction pin
(Dissipated power = 1 W) 35 40 °C/W
R
thJA
Thermal resistance junction ambi ent
(Dissipated power = 1 W) 90 110 °C/W
R
thJA
Thermal resistance junction ambi ent
(1)
(Dissipated power = 1 W)
1. When mounted on a standard single side FR4 board with 100 mm
2
(0.155 sq in) of Cu (35 μm thick)
80 90 °C/W
Electrical data VIPER16
8/30 DocI D15232 Rev 7
4.3 Electrical characteristics
(T
J
= -25 to 125 °C, V
DD
= 14 V
(a)
; unless otherwise specified)
a. Adjust V
DD
above V
DDon
start-up threshold before setting to 14 V
Table 6. Power section
Symbol Parameter Test condition Min Typ Max Unit
V
BVDSS
Break-down voltage I
DRAIN
= 1 mA,
V
COMP
= GND, T
J
= 25 °C 800 V
R
DS(on)
Drain-source on state resistance I
DRAIN
= 0.2 A, T
J
= 25 °C 20 24 Ω
I
DRAIN
= 0.2 A, T
J
= 125 °C 40 48 Ω
C
OSS
Effective (energy related) output capacitance V
DRAIN
= 0 to 640 V 10 pF
I
OFF
OFF state drain current
V
DRAIN
= 640 V
V
FB
= GND 60 μA
V
DRAIN
= 800 V
V
FB
= GND 75 μA
Table 7. Supply section
Symbol Parameter Test condition Min Typ Max Unit
Voltage
V
DRAIN_START Drain-source start voltage 40 50 60 V
IDDch1 Start up charging current VDRAIN = 100 V to 640 V,
VDD = 4 V -0.6 -1.8 mA
IDDch2 Charging current during operation VDRAIN = 100 V to 640 V,
VDD = 9 V falling edge -7 -14 mA
VDD Operati ng vo ltage rang e 11.5 23.5 V
VDDclamp VDD clamp voltage IDD = 15 mA 23.5 V
VDDon VDD start up threshold 12 13 14 V
VDDCSon VDD on internal high voltage current
generator threshold 9.5 10.5 11.5 V
VDDoff VDD under voltage shutdown threshold 7 8 9 V
DocID15232 Rev 7 9/30
VIPER16 Electrical data
30
Current
I
DD0
Operati ng supply curre nt, not swit ch ing F
OSC
= 0 kHz, V
COMP
= GND 0.6 mA
I
DD1
Operati ng supply curre nt, switching
V
DRAIN
= 120 V,
F
SW
= 60 kHz 1.3 mA
V
DRAIN
= 120 V,
F
SW
= 115 kHz 1.5 mA
I
DDoff
Operating supply current with V
DD
< V
DDoff
V
DD
< V
DDoff
0.35 mA
I
DDol
Open loop failure current threshold V
DD
= V
DDclamp
V
COMP
= 3.3 V, 4 mA
Table 7. Supply section (continued)
Symbol Parameter Test condition Min Typ Max Unit
Table 8. Controller section
Symbol Parameter Test condition Min Typ Max Unit
Error amplifier
V
REF_FB
FB reference voltage 3.2 3.3 3.4 V
I
FB_PULL UP
Current pull up -1 μA
G
M
Trans conductance 2 mA/V
Current setting (LIM) pin
V
LIM_LOW
Low level clamp voltage I
LIM
= -100 μA0.5V
Compensation (COMP) pin
V
COMPH
Upper saturation limit T
J
= 25 °C 3 V
V
COMPL
Burst mode threshold T
J
= 25 °C 1 1.1 1.2 V
V
COMPL_HYS
Burst mode hysteresis T
J
= 25 °C 40 mV
H
COMP
ΔV
COMP
/ ΔI
DRAIN
4 9 V/A
R
COMP(DYN)
Dynamic resistance V
FB
= GND 15
k
Ω
I
COMP
Source / sink current V
FB
> 100 mV 150 μA
Max source current V
COMP
= GND, V
FB
= GND 220 μA
Current limitation
I
Dlim
Drain current limitation I
LIM
= -10 μA, V
COMP
= 3.3 V ,
T
J
= 25 °C 0.38 0.4 0.42 A
t
SS
Soft-start time 8. 5 ms
T
ON_MIN
Minimum turn ON time 220 450 ns
I
Dlim_bm
Burst mode current limitation V
COMP
= V
COMPL
85 mA
Overload
t
OVL
Overload time 50 ms
t
RESTART
Restart time after fault 1 s
Electrical data VIPER16
10/30 DocID15232 Rev 7
Oscillator section
F
OSC
Switching frequency VIPer16L 54 60 66 kHz
VIPer16H 103 115 127 kHz
F
D
Mo dulation depth F
OSC
= 60 kHz ±4 kHz
F
OSC
= 115 kHz ±8 kHz
F
M
Modulation frequency 230 Hz
D
MAX
Maximum du ty cycle 70 80 %
Thermal shutdown
T
SD
Thermal shutdown temperature
(1)
150 160 °C
T
HYST
Thermal shutdown hysteresis
(1)
30 °C
1. Specification assured by design, characterization and statistical correlation.
Table 8. Controller section (continued)
Symbol Parameter Test condition Min Typ Max Unit
DocID15232 Rev 7 11/30
VIPER16 Typical electrical characteristics
30
5 Typical electrical characteristics
Figure 4. IDlim vs T
J
Figure 5. F
OSC
vs T
J
Figure 6. V
DRAIN_START
vs T
J
Figure 7. H
COMP
vs T
J
Figure 8. G
M
vs T
J
Figure 9. V
REF_FB
vs T
J
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12/30 DocID15232 Rev 7
Figure 10. I
COMP
vs T
J
Figure 11. Operating supply current
(no switching) vs T
J
Figure 12. Operating supply current (switching)
vs T
J
Figure 13. IDlim vs R
LIM
Figure 14. Power MOSFET on-resistance vs T
J
Figure 15. Power MOSFET break down voltage
vs T
J
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DocID15232 Rev 7 13/30
VIPER16 Typical electrical characteristics
30
Figure 16. Thermal shutdown
T
J
V
DD
I
DRAIN
VDDon
time
VDDCSon
VDDoff
TSD
time
time
TSD -THYST
Shut down after over temperature
Normal operation Normal operation
Typical circuit VIPER16
14/30 DocID15232 Rev 7
6 Typical circuit
Figure 17. Buck converter
Figure 18. Buck boost converter
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DocID15232 Rev 7 15/30
VIPER16 Typi cal circ u it
30
Figure 19. Flyback converter (primary regulation)
Figure 20. Flyback converter (non isolated)
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Power section VIPER16
16/30 DocID15232 Rev 7
7 Power section
The power section is implemented with an n-channel power MOSFET with a breakdown
voltage of 800 V min. and a typical R
DS(on)
of 20 Ω. It includes a SenseFET structure to
allow a virtually lossless current sensing and the thermal sensor.
The gate driver of the power MOSFET is designed to supply a controlled gate current during
both turn-ON and turn-OFF in order to minimize common mode EMI. During UVLO
conditions, an internal pull-down circuit holds the gate low in order to ensure that the power
MOSFET cannot be turned ON accidentally.
8 High voltage current generator
The high voltage current generator is supplied by the DRAIN pin. At the first start up of the
converter it is enabled when the voltage across the input bulk capacitor reaches the
V
DRAIN_START
threshold, sourcing a I
DDch1
current (see Table 7 on page 8); as the V
DD
voltage reaches the V
DDon
threshold, the power section starts switching and the high
voltage current generator is turned OFF. The VIPer16 is powered by the energy stored in
the V
DD
capacitor.
In steady state condition, if the self biasing function is used, the high voltage current
generator is activated between V
DDCSon
and V
DDon
(see Table 7 on page 8), deliv er in g
I
DDch2
, see Table 7 on page 8 to the V
DD
capacitor during the MOSFET off time (see
Figure 21 on page 16).
The device can also be supplied through the auxiliary winding; in this case the high voltage
current source is disabled during steady-state operation, provided that VDD is above
V
DDCSon
.
At converter power-down, the V
DD
voltage drops and the converter activity stops as it falls
below V
DDoff
threshold (see Table 7 on page 8).
Figure 21. Power on and power off
IDD
VDD
VDRAIN
V
DDon
t
t
t
t
VIN
V
DRAIN_START
t
t
Power-on Power-off
Normal operation
regulation is lost here
VIN < VDRAIN_START
HV startup is no more activated
With internal self-supply
Without internal self-supply
V
DDCSon
V
DDoff
I
DDch1
I
DDch2
DocID15232 Rev 7 17/30
VIPER16 Oscillator
30
9 Oscillator
The switching frequency is internally fixed at 60 kHz (part number VIPER16LN or LD) or 1 15
kHz (part number VIPER16HN or HD).
In both cases the switching frequency is modulated by approximately ±4 kHz (60 kHz
version) or ±8 kHz (115 kHz version) at 230 Hz (typical) rate, so that the resulting spread-
spectrum action distributes the energy of each harmonic of the switching frequency over a
number of sideband harmonics having the same energy on the whole but smaller
amplitudes.
10 Soft start-up
During the converters' start-up phase, the soft-start function progressively increases the
cycle-by-cycle drain current limit, up to the default value I
Dlim
. By this way the drain current
is further limited and the output voltage is progressively increased reducing the stress on the
secondary diode. The soft-start time is internally fixed to t
SS
, see ty pical value
on Table 8 on page 9, and the function is activated for any attempt of converter start-up and
after a fault event.
This function helps prevent transformers' saturation during start-up and short-circuit.
11 Adjustable current limit set point
The VIPer16 includes a current mode PWM controller: cycle by cycle the drain current is
sensed through the integrated resistor R
SENSE
and the voltage is applied to the non
inverting input of the PWM comparator, see Figure 2 on page 4. As soon as the sensed
voltage is equal to the voltage derived from the COMP pin, the power MOSFET is switched
OFF.
In parallel with the PWM operations, the comparator OCP, see Figure 2 on page 4, checks
the level of the drain current and switch OFF the power MOSFET in case the current is
higher than the threshold I
Dlim
, see Table 8 on page 9.
The level of the drain current limit, I
Dlim
, can be reduced depending from the sunk current
from the pin LIM. The resistor R
LIM
, between LIM and GND pins, fixes the current sunk and
than the level of the current limit, I
Dlim
, see Figure 13 on page 12.
When the LIM pin is left open or if the R
LIM
has an high value (i.e. > 80 kΩ) the current limit
is fixed to its default value , I
Dlim
, as reported on Table 8 on page 9.
FB pin and COMP pin VIPER16
18/30 DocID15232 Rev 7
12 FB pin and COMP pin
The device can be used both in non-isolated and in isolated topology. In case of non-
isolated topology, the feedback signal from the output voltage is applied directly to the FB
pin as inverting input of the internal error amplifier having the reference voltage, V
REF_FB,
see the Table 8 on page 9.
The output of the error amplifier sources and sinks the current, I
COMP
, respectively to and
from the compensation network connected on the COMP pin. This signal is then compared,
in the PWM comparator, with the signal coming from the SenseFET; the power MOSFET is
switched off when the two values are the same on cycle by cycle basis. See the Figure 2 on
page 4 and the Figure 22 on page 18.
When the power supply output voltage is equal to the error amplifier reference voltage,
V
REF_FB
, a single resistor has to be connected from the output to the FB pin. For higher
output voltages the external resistor divider is needed. If the voltage on FB pin is
accidentally left floating, an internal pull-up protects the c ontroller.
The output of the error amplifier is externally accessible through the COMP pin and it’s used
for the loop compensation: usually an RC network.
As reported on Figure 22 on page 18, in case of isolated power supply, the in ternal error
amplifier has to be disabled (FB pin shorted to GND). In this case an internal resistor is
connected between an internal reference voltage and the COMP pin, see the Figure 22 on
page 18. The current loop has to be closed on the COMP pin through the opto-transistor in
parallel with the compensation network. The V
COMP
dynamics ra nge s is betw een V
COMPL
and V
COMPH
as reported on Figure 23 on page 19 .
When the voltage V
COMP
drops below the voltage threshold V
COMPL
, the converter enters
burst mode, see Section 13 on page 19.
When the voltage V
COMP
rises above the V
COMPH
threshold, the peak drain current will
reach its limit, as well as the deliverable output power.
Figure 22. Feedback circuit
FB
COMP
Without Isolation:
switch open & E/A enabled
With Isolation:
switch closed & E/A disabled
No
Isolation
V
OUT
+
-
PWM stop
from R
SENSE
R
Isolation
R
L
nR
SW
V
REF
R
COMP
+
-
E/A
BUS
+
-
to PWM
V
COMPL
R
HV
REF_FB
DocID15232 Rev 7 19/30
VIPER16 Burst mode
30
13 Burst mode
When t he v olt a ge V
COMP
drops below the threshold, V
COMPL
, the power MOSFET is kept in
OFF state and the consumption is reduced to I
DD0
current, as reported on Table 7 on
page 8. As reaction at the energy delivery stop, the V
COMP
voltage increases and as soon
as it exceeds the threshold V
COMPL
+ V
COMPL_HYS
, the converter starts switching again with
consumption level equal to I
DD1
current. This ON-OFF operation mode, referred to as “burst
mode” and reported on Figure 24 on page 19, reduces the average frequency , which can go
down even to a few hundreds hertz, thus minimizing all frequency-related losses and
making it easier to comply with energy saving regulations. During the burst mode, the drain
current limit is reduced to the value I
Dlim_bm
(reported on Table 8 on page 9) in order to
avoid the audible noise issue.
Figure 24. Load-dependent operating modes: timing diagrams
Figure 23. COMP pin voltage versus I
DRAIN
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COMP
V
COMPL
+V
COMPL_HYS
V
COMPL
I
DD1
I
DD0
I
DD
I
DRAIN
I
Dlim_bm
Burst Mode
AM13269v1
Automatic auto restart after overload or short-circuit VIPER16
20/30 DocID15232 Rev 7
14 Automatic auto restart after overload or short-circuit
The overload protection is implemented in automatic way using the integrated up-down
counter . Every cycle, it is incremented or decremented depending if the current logic detects
the limit condition or not. The limit condition is the peak drain current, I
Dlim ,
reported on
Table 8 on page 9 or the one set by the user through the R
LIM
resistor, as reported in
Figure 13 on page 12. After the reset of the counter , if the peak drain current is continuously
equal to the level I
Dlim
, the counter will be incremented till the fixed time, t
OVL
, after that will
be disabled the power MOSFET switch ON. It will be activated again, through the soft start,
after the t
RESTART
time, see the Figure 25 and Figure 26 on page 20 and the mentioned
time values on Table 8 on page 9.
In case of overload or short-circuit event, the power MOSFET switching will be stopped after
a time that depends from the counter and that can be as maximum equal to t
OVL
. The
protection will occur in the same way until the overload condition is removed, see Figure 25
and Figure 26 on page 20. This protection ensures restart attempts of the converter with low
repetition rate, so that it works safely with extremely low power throughput and avoiding the
IC overheating in case of repeated overload events. If the overload is removed before the
protection tripping, the counter will be decremented cycle by cycle down to zero and the IC
will not be stopped.
Figure 25. Timing diagram: OLP sequence (IC externally biased)
Figure 26. Timing diagram: OLP sequence (IC internally biased)
AM13270v1
time
time
V
DD
V
DDon
V
DDCSon
I
DRAIN
I
Dlim_bm
t
1*
* The time t
1
can be lower or equal to the time t
OVL
t
RESTART
t
SS
t
OVL
t
RESTART
t
SS
t
OVL
t
RESTART
t
SS
SHORT CIRCUIT
OCCURS HERE
SHORT CIRCUIT
REMOVED HERE
AM13271v1
time
time
V
DD
V
DDon
V
DDCSon
I
DRAIN
I
Dlim_bm
t
1*
* The time t
1
can be lower than or equal to the time t
OVL
t
RESTART
t
SS
t
OVL
t
RESTART
t
SS
t
OVL
t
RESTART
t
SS
SHORT CIRCUIT
OCCURS HERE
SHORT CIRCUIT
REMOVED HERE
DocID15232 Rev 7 21/30
VIPER16 Open loop failure protection
30
15 Open loop failure protection
In case the power supply is built in fly-back topology and the VIPer16 is supplied by an
auxil iary windi ng, as sh own in Figure 27 on page 21 and Figure 28 on page 22, the
converter is protected against feedback loop failure or accidental disconnections of the
winding.
The following description is applicable for the schematics of Figure 27 on page 21 and
Figure 28 on page 22, respectively the non-isolated fly-back and the isolated fly-back.
If R
H
is opened or R
L
is shorted, the VIPer16 works at its drain current limitation. The output
voltage, V
OUT
, will increase and so the auxiliary voltage, V
AUX
, which is coupled with the
output through the secondary-to-auxiliary turns ratio.
As the auxiliary voltage increases up to the internal V
DD
active clamp, V
DDclamp
(the value is
reported on Table 8 on page 9) and the clamp current injected on VDD pin exceeds the latch
threshold, I
DDol
(the value is reported on Table 8 on page 9), a fault signal is internally
generated.
In order to distinguish an actual malfunction from a bad auxiliary winding design, both the
above conditions (drain current equal to the drain current limitation and current higher than
I
DDol
through VDD clamp) have to be verified to reveal the fault.
If R
L
is opened or R
H
is shorted, the output voltage, V
OUT
, will be clamped to the reference
voltage V
REF_FB
(in case of non isolated fly-back) or to the external TL voltage reference (in
case of isolated fly-back).
Figure 27. FB pin connection for non-isolated fly-back
VCOMPL
DAUX
nR
FB
VDD
V
AUX
COMP
+
-
to PWM
R
L
+
-
E/A
R
H
R
RAUX
CVDD
VOUT
RS
VREF_FB
from RSENSE
BUS
+
-
PWM stop
CS
CP
AM13272v1
Open loop failure protection VIPER16
22/30 DocID15232 Rev 7
Figure 28. FB pin connection for isolated fly-back
AM13273v1
VREF_FB
R
H
CCOMP
+
-
PWM stop
R3
R
TL
RAUX
RCOMP
CVDD
-
COMP
+
-
E/A
nR
R
L
VREF
CC
U5
Disabled
V
AUX
V
OUT
+
-to PWM
SW
FB
ROPTO
BUS
DAUX
VCOMPL
from RSENSE
RC
DocID15232 Rev 7 23/30
VIPER16 Layout guidelines and design recommendations
30
16 Layout guidelines and design recommendations
A proper printed circuit board layout is essential for correct operation of any switch-mode
converter and this is true for the VIPer16 as well. Also some trick can be used to make the
design rugged versus external influences.
Careful component placing, correct traces routing, appropriate traces widths and
compliance with isolation distances are the major issues.
The main reasons to have a proper PCB routing are:
– Provide a noise free path for the signal ground and for the internal references,
ensuring good immunity against external noises and switching noises
– Minimize the pulsed loops (both primary and secondary) to reduce the
electromagnetic interferences, both radiated and conducted and passing more
easily the EM C regulati on s.
The below list can be used as guideline when designing a SMPS using VIPer16.
– Signal ground routing should be routed separately from power ground and, in
general, from any pulsed high current loop;
– Connect all the signal ground traces to the power ground, using a single "star
point", placed close to the IC GND pin;
– With flyback topologies, when the auxiliary winding is used, it is suggested to
connect the VDD capacitor on the auxiliary return and then to the main GND using
a single track;
– The compensation network should be connected as close as possible to the
COMP pin, maintaining the trace for the GND as short as possible;
– A small bypass capacitor (a few hundreds pF up to 0.1 µF) to GND might be useful
to get a clean bias voltage for the signal part of the IC and protect the IC itself
during EFT/ESD tests. A low ESL ceramic capacitor should be used, placed as
close as possible to the VDD pin;
– When using SO16 package it is recommended to connect the pin 4 to GND pin,
using a signal track, in order to improve the noise immunity. This is highly
recommended in case of high nosily environment;
– An optional capacitor can be connected on the LIM pin in order to improve the IC
noise immunity. It is strongly recommended to don't exceed 470nF.
– The IC thermal dissipation takes place through the drain pins. An adequate heat
sink copper area has to be designed under the drain pins to improve the thermal
dissipation;
– It is not recommended to place large copper areas on the GND pins.
– Minimize the area of the pulsed loops (primary, RCD and secondary loops), in
order to reduce its parasitic self- inductance and the radiated electromagnetic
field: this will greatly reduce the electromagnetic interferences produced by the
power supply during the switching.
Layout guidelines and design recommendations VIPER16
24/30 DocID15232 Rev 7
Figure 29. Suggested routing for converter: flyback case
Figure 30. Sug gest ed ro uti ng for con verte r: buck cas e
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DocID15232 Rev 7 25/30
VIPER16 Package mechanical data
30
17 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
is an ST trademark.
Figure 31. DIP-7 package dimensions
Package mechanical data VIPER16
26/30 DocID15232 Rev 7
1- The leads size is comprehensive of the t hicknes s of the leads finishing material.
2- Dimensions do not include mold protrusion, not to exceed 0,25 mm in total (both side).
3- Package outline exclusive of metal burrs dimensions.
4- Datum plane “H” coincident with the bottom of lead, where lead exits body.
5- Ref. POA MOTHER doc. 0037880
6- Creepage distance > 800 V
7- Creepage distance 250 V
8- Creepage distance as shown in the 664-1 CEI / IEC standard.
Table 9. DIP-7 mechanical data
Dim. mm
Typ Min Max
A 5,33
A1 0,38
A2 3,30 2,92 4,95
b 0,46 0,36 0,56
b2 1,52 1,14 1,78
c 0,25 0,20 0,36
D 9,27 9,02 10,16
E 7,87 7,62 8,26
E1 6,35 6,10 7,11
e 2,54
eA 7,62
eB 10,92
L 3,30 2,92 3,81
M
(6)(8)
2,508
N 0,50 0,40 0,60
N1 0,60
O
(7)(8)
0,548
DocID15232 Rev 7 27/30
VIPER16 Package mechanical data
30
Figure 32. SO16N package dimensions
Package mechanical data VIPER16
28/30 DocID15232 Rev 7
Table 10. SO16N mechanical data
Dim. mm
Min Typ Max
A 1.75
A1 0.1 0.25
A2 1.25
b 0.31 0.51
c 0.17 0.25
D 9.8 9.9 10
E 5.866.2
E1 3.8 3.9 4
e 1.27
h 0.25 0.5
L 0.4 1.27
k 0 8
ccc 0.1
DocID15232 Rev 7 29/30
VIPER16 Revision history
30
18 Revision history
s
Table 11. Document revision history
Date Revision Changes
21-Jan-2009 1Initial rele as e
07-Dec-2009 2 Updated Figure 7 on pa ge 11
14-May-2010 3 Updated Figure 3 o n page 5 and Table 3 on page 5
26-Aug-2010 4 Updated Tabl e 3 on page 5, Figure 16 on page 13 and
Fig ure 21 on page 16
10-Oct-2011 5 Updated Figure 32 on page 27 and Table 7 on page 8
26-May-2014 6
Updated the features in cover page, Table 3: Pin description,
Table 4: Absolute maximum ratings, Table 6: Power section,
Table 7: Supply section.
Modified Figure 17, 18, 19 and 20.
Added Section 16: Layout guidelines and design
recommendations.
Minor text changes.
13-Jun-2014 7 Updated Table 3: Pin description and Table 6: Power section.
Minor text changes.
VIPER16
30/30 DocID15232 Rev 7
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