AK6512CM - Asahi Kasei Microsystems Co., Ltd. (AKM)

ASAHI KASEI [AK6510C/12C]

DAP02E-04 2005/03

- 1 -

AK6510C / 12C

SPI bus 32K/64Kbit Serial CMOS EEPROM

Features

 Advanced CMOS EEPROM Technology

 Single Voltage Supply: 1.8V to 5.5V

 AK6510C: 32Kbits; 4096 x 8 organization

AK6512C: 64Kbits; 8192 x 8 organization

 SPI Serial Interface Compatible

 Low Power Consumption

0.8µA Max. (Standby mode)

 High Reliability

Endurance: 1000K E/W cycles / Address

Data Retention: 10 Years

 Special Features

32 byte Page Write Mode

Block Write Protection (Protect 1/4,1/2 or Entire Array)

Automatic write cycle time-out with auto-ERASE

 Software and Hardware controlled Write Protection

 Self timed Programming Cycle: 5msec. Max.

 Ideal for Low Density Data Storage

Low cost, space saving, 8-pin SSOP/SONW package

Block Diagram

DATA

INSTRUCTION

DECODE,

CONTROL

AND

CLOCK

GENERATION

INSTRUCTION

AK6510C=32Kbit

SCK

HOLD

ADD.

BUFFERS

VREF VPP

GENERATOR

VPP SW

DECODER

R/W AMPS

AND

AU TO ERAS E

STATUS REGISTER

AK6512C=64Kbit

ASAHI KASEI [AK6510C/12C]

DAP02E-04 2005/03

- 2 -

General Description

The AK6510C/12C is a 32768/65536-bit, serial, read/write, non-volatile memory device fabricated

using an advanced CMOS EEPROM technology. The AK6510C/12C has 32768-bits/65536-bits of

memory organized as 4096/8192 registers of 8 bits each. The AK6510C/12C can operate all

function under wide operating voltage range: 1.8V to 5.5V. The charge up circuit for high voltage

generation needed for write operations is integrated.

The AK6510C/12C serial interface is compatible to a SPI bus. The AK6510C/12C has 6

instructions: READ, WRITE, WREN (write enable), WRDI (write disable), RDSR (read status

Each instruction is organized by an op-code (8bits), address (16bits), and data (8bits). When input

level of CS pin changed from high level to low level, AK6510C/12C can receive instructions.

 Pin Configurations

Pin name Functions

CS Chip Select input

SCK Serial Clock input

SI Serial Data input

SO Serial Data output

WP Write Protect input

HOLD Hold input

VCC Power Supply

GND Ground

 Type of Products

Model Memory size Temp. Range VCC Package

AK6510CM -40°C to +85° C 1.8V to 5.5V 8pin Plastic SSOP

AK6510CL 32K bits -40°C to +85° C 1.8V to 5.5V 8pin Plastic SONW

AK6512CM -40°C to +85° C 1.8V to 5.5V 8pin Plastic SSOP

AK6512CL 64K bits -40°C to +85° C 1.8V to 5.5V 8pin Plastic SONW

AK6510CL/12CL

8pin SONW

GND

VCC

HOLD

5SCK

GND

VCC

4SCK

AK6510CM/12CM

8pin SSOP

HOLD

ASAHI KASEI [AK6510C/12C]

DAP02E-04 2005/03

- 3 -

 Data Transfer

An IC that outputs the clock is called "MASTER", an IC that receives the clock is called "SLAVE".

The AK6510C/12C operates as a SLAVE. Data is written to the SI pin and read from SO pin. The

MSB is transmitted first.

After CS pin changes hi level to low level, AK6510C/12C receives the first data bit on the SI pin

synchronously with the rising edge of the input pulse of serial clock. While CS pin is high level, the

data input to the SI pin is don’t care and SO pin indicates Hi-Z.

All the functions are organized 8 bits of op-code, address, and data. If there is an invalid op-code,

the AK6510C/12C ignores the address and data information and SO pin indicates Hi-Z. In order to

input new op-code, CS pin should be toggled.

 Hold

AK6510C/12C has a HOLD pin that can hold the data transfer. When HOLD changes high to low

while SCK is low, the data transfer stops. After the HOLD pin changes low to High while SCK is

low, the data transfer starts again. While the data transfer is paused, AK6510C/12C ignores the

clock on the SCK line.

 Write Protect

AK6510C/12C has status registers. When the WPEN bit in the status registers is "1", Write Protect

function is enabled. When WPEN bit is "1" and WP pin is low level, the status register is protected

from write function. When WP pin becomes low level while the WRITE to the status register

instruction is written, the AK6510C/12C doesn’t accept the instruction. When the WP pin changes

low level while the internal programming, the programming function continues.

When the WPEN bit is "0", WP pin function is disabled. Even if WP pin is fixed to low level, the

WRITE function to the status register can be done. When the WP pin is high level, AK6510C/12C

can accept all of READ and WRITE functions.

ASAHI KASEI [AK6510C/12C]

DAP02E-04 2005/03

- 4 -

Pin Description

CS (Chip Select Input)

When CS changes high level to low level, the AK6510C/12C can receive the instructions.

CS should be kept low level while receiving op-code, address and data, and while outputting

data.

When CS is high level, SO indicate Hi-Z.

SCK (Serial Clock Input)

The SCK clock pin is the synchronous clock input for input/output data.

SI (Serial Data Input)

The op-code, address, and data are written to the SI pin.

SO (Serial Data Output)

The SO pin outputs the data from memory array and status register.

WP (Write Protect Input)

The WP pin controls the write function to the status register.

When the WPEN bit in the status register is "0", the function of WP pin becomes disable.

Then the status register can be programmable when the WEN bit in the status register is "1".

And it does not depend on the status of WP pin.

When the WPEN bit is "1", the function of WP is enabled. Then the status register can not

be programmable when the WEN bit is "1" and the status of WP pin is low.

When the WPEN bit is "1", WP pin is high and WEN bit is "1", AK6510C/12C can accept the

WRITE instruction to the status registers.

During the instruction input, WP pin should keep high or low level.

HOLD (Hold Input)

The HOLD pin can hold the data transfer. When the HOLD pin changes hi to low while the

SCK is low, the data transfer is held. And the transfer starts when the HOLD pin changes

low to high while the SCK is low. While the holding the data transfer, AK6510C/12C ignores

the clock signal on SCK pin.

ASAHI KASEI [AK6510C/12C]

DAP02E-04 2005/03

- 5 -

Function Description

AK6510C/12C has six instructions. The instruction can be input after the CS pin changes high to

low. All the instructions are MSB first.

Instruction Op-code Address Data Description

READ 0000 X011 X X X A12-A8 A7-A0 D7-D0 (out) Read from Memory Array

WRITE 0000 X010 X X X A12-A8 A7-A0 D7-D0 (in) Write to Memory Array

WREN 0000 X110 ------ ------ Write Enable

WRDI 0000 X100 ------ ------ Write Disable

RDSR 0000 X101 Bit7-Bit0 (out) ------ ------ Read Status Register

WRSR 0000 X001 Bit7-Bit0 (in) ------ ------ Write Status Register

X: don’t care

AK6510C: A12 is don’t care

Table 1. Instruction set for AK6510C/12C

WREN (WRITE ENABLE) / WRDI (WRITE DISABLE)

The WRITE function can be accepted only in the status of Write Enable. After VCC is applied,

AK6510C/12C is in the status of Write Disable. After the function of WRDI, AK6510C/12C cannot

accept any programming function.

WREN

WRDI

01234567

000000

Hi-Z

SO X = don’t care

01234567

000010

Hi-Z

SO X = don’t care

ASAHI KASEI [AK6510C/12C]

DAP02E-04 2005/03

- 6 -

RDSR (READ STATUS REGISTER)

The RDSR function is used to read the data in the STATUS register. The STATUS register has

RDY bit, WEN bit, BP0/BP1 bit and WPEN bit. RDSR function can be used to read READY/BUSY

status bit, WRITE ENABLE/DISABLE bit, and BLOCK PROTECT bit.

These bits can be set by WRSR function.

RDSR

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

WPEN X X X BP1 BP0 WEN RDY

WPEN

WP pin set bit (programmable)

See Table 3.

BP0 / BP1

Block Protect bit for EEPROM memory array (programmable)

See Table 4.

WEN

WRITE ENABLE / DISABLE bit (READ only)

This is set by WREN/WRDI function.

WEN=0 : WRITE DISABLE

WEN=1 : WRITE ENABLE

RDY

READY/BUSY status bit (READ only)

RDY=0 : READY

RDY=1 : BUSY

Table 2. Status Register Configuration

01234567891011121314

000001

Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0Bit7

Hi-Z

SCK

SO X = don’t care

ASAHI KASEI [AK6510C/12C]

DAP02E-04 2005/03

- 7 -

WRSR (WRITE STATUS REGISTER)

The WRSR instruction can set the Write Protect Block size of the memory array.

AK6510C/12C has 4 Blocks of memory arrays. Write Protect Block size can be selected from 1/4,

1/2 and whole memory array. The block, which is set by Write Protect, is Read only.

BP0 bit, BP1 bit, and WPEN bit are programmable with EEPROM memory cell bits. The

characteristics of those bits (WREN, tE/W, RDSR) are same as the EEPROM memory array.

WP pin function can be set by WPEN (WRITE PROTECT ENABLE) bit which is defined by WRSR

function. When WP pin is low level and WPEN bit is "1", the WRITE function to Status register,

which has WPEN bit and BP0/BP1 bit, and to Write Disable Block is not performed. Then WRITE

function is performed only to the Write enable block.

When WP pin is "1" or WPEN bit is "0", then the function of WP pin is disabled and WRITE function

to the Status Register is performed.

WREN function should be done before WRSR function. And after the Programming function,

AK6510C/12C becomes Write Disable status automatically.

WRSR

WPEN

Bit WP

Pin WEN

Bit Write Protected

Block Not Protected

Block Status Register

0 X 0 WRITE Disable WRITE Disable WRITE Disable

0 X 1 WRITE Disable WRITE Enable WRITE Enable

1 Low 0 WRITE Disable WRITE Disable WRITE Disable

1 Low 1 WRITE Disable WRITE Enable WRITE Disable

X High 0 WRITE Disable WRITE Disable WRITE Disable

X High 1 WRITE Disable WRITE Enable WRITE Enable

Table 3. WPEN function

Status Register bits Write Protected Block

BP1 BP0 AK6510C AK6512C

0 0 none none

0 1 C00h - FFFh 1800h - 1FFFh

1 0 800h - FFFh 1000h - 1FFFh

1 1 000h - FFFh 0000h - 1FFFh

Table 4. Write Protected Block Size

Hi-Z

0123456789101112131415

0000001 Bit1Bit2Bit3Bit4Bit5Bit6Bit7 Bit0

SO X = don’t care

ASAHI KASEI [AK6510C/12C]

DAP02E-04 2005/03

- 8 -

WRITE (WRITE SEQUENCE)

WRITE instruction can start the WRITE function to the memory cell array.

After CS pin changes high to low, op-code, address and data are input from SI pin. After the

instruction input, the internal programming cycle starts when CS pin changes low to high. After the

instructions are inputted, CS pin should change low to high after the last data bit (D0) inputs and

before next SCK clock rises. Write function can start only at this timing.

AK6510C/12C can indicate the BUSY status by using RDSR instruction and READ the RDY bit

(Bit0) in the status register. RDY is "1" indicates AK6510C/12C is in the programming cycle, and

RDY is "0" indicates AK6510C/12C is in the READY status. AK6510C/12C outputs the "FF" when

RDSR instruction executes during the programming cycle. Only RDSR instruction can be accepted

during programming cycle.

AK6510C/12C has Page Write mode, which can write the data within 32 bytes with one

programming cycle. The input data sent to the shift register within 32 bytes. If the number of

bytes exceeded 32, the address counter rolls over to the first address of the page.

Internal programming cycle starts after CS pin changes low to high.

After WRITE instruction, AK6510C/12C changes to Write Disable status automatically.

AK6510C/12C needs WREN instruction before every WRITE instruction. When WRITE instruction

is done while AK6510C/12C is in Write Disable status, WRITE instructions are ignored and

AK6510C/12C becomes standby status after CS changes to high. AK6510C/12C can accept the

next instruction after CS becomes low.

WRITE instruction cannot write the data into the address of the protected block.

WRITE

Hi-Z

32 33 34 35 36 37 38 39 40

012345678910111213 2322

0000010 A0A1A10

Hi-Z

A11

24 25 30 31

D0D1D6D7

Data(n)

SO X = don’t care

Data(n+1)

D0D1D6D7 D4D5 D3 D2D7

Data(n+31)

D0D0D1D6D7 D4D5 D3 D2

A12

AK6510C: A12 is don't care

ASAHI KASEI [AK6510C/12C]

DAP02E-04 2005/03

- 9 -

READ (READ SEQUENCE)

After CS changes high to low, the op-code and address are sent on SI pin and the data (D7-D0)

read from SO pin.

After 1 byte of data output, internal address register is incremented, and the next byte of data is

outputted. After READ the data in the highest address, the address register rolls over to the lowest

address. After the last bit of the address shift into the register, the input data on SI pin is ignored.

READ

012345678910111213 2322

0000011 A0A1A10

Hi-Z

A11

24 25 29 30

D0D1D2D6

X = don’t care

A12

AK6510C: A12 is don't care

ASAHI KASEI [AK6510C/12C]

DAP02E-04 2005/03

- 10 -

Absolute Maximum Ratings

Parameter Symbol Min Max Unit

Power Supply VCC -0.6 +6.5 V

All Input Voltages

with Respect to Ground VIO

-0.6

VCC+0.6

Ambient Storage Temperature Tst -65 +150 °C

Stress above those listed under "Absolute Maximum Ratings" may cause

permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in

the operational sections of the specification is not implied. Exposure to absolute

maximum conditions for extended periods may affect device reliability.

Recommended Operating Condition

Parameter Symbol Min Max Unit

Power Supply VCC 1.8 5.5 V

Ambient Operating Temperature Ta -40 +85 °C

ASAHI KASEI [AK6510C/12C]

DAP02E-04 2005/03

- 11 -

Electrical Characteristics

(1) D.C. ELECTRICAL CHARACTERISTICS

(1.8V≤VCC≤5.5V, -40°C≤Ta≤85°C, unless otherwise specified)

Parameter Symbol Condition Min. Max. Unit

ICC1 VCC=5.5V, fSCK=5.0MHz, *1 2.0 mA

Current Dissipation

(WRITE) ICC2 VCC=2.5V, fSCK=2.5MHz, *1 1.5 mA

ICC3 VCC=1.8V, fSCK=1.0MHz, *1 1.0 mA

ICC4 VCC=5.5V, fSCK=5.0MHz, *1 1.0 mA

Current Dissipation

(READ) ICC5 VCC=2.5V, fSCK=2.5MHz, *1 0.2 mA

ICC6 VCC=1.8V, fSCK=1.0MHz, *1 0.1 mA

Current Dissipation

(Standby) ICCS

VCC=5.5V *2

0.8

µA

VIH1 2.5V≤VCC≤5.5V 0.7xVCC VCC+0.5 V

Input High Voltage

VIH2 1.8V≤VCC<2.5V 0.8xVCC VCC+0.5 V

VIL1 2.5V≤VCC≤5.5V -0.3 0.3xVCC V

Input Low Voltage

VIL2 1.8V≤VCC<2.5V -0.3 0.2xVCC V

Output High Voltage

VOH1

4.5V≤VCC≤5.5V

IOH=-2mA VCC-0.5

VOH2

2.5V≤VCC<4.5V

IOH=-0.4mA VCC-0.2

VOH3

1.8V≤VCC<2.5V

IOH=-0.1mA VCC-0.2

Output Low Voltage

VOL1

4.5V≤VCC≤5.5V

IOL=3.0mA

0.4

VOL2

2.5V≤VCC<4.5V

IOL=1.6mA

0.4

VOL3

2.5V≤VCC<4.5V

IOL=1.0mA

0.2

VOL4

1.8V≤VCC<2.5V

IOL=1.0mA

0.2

ILI

VCC=5.5V, VIN=VCC/GND

±1.0

µA

Input Leakage

CS, SCK, DI pins

WP, HOLD pins

Output Leakage

SO pin ILO

VCC=5.5V,

VOUT=VCC/GND

±1.0

µA

*1: VIN=VIH/VIL, SO=open

*2: CS=VCC, VIN=VCC/GND, WP,HOLD=VCC, SO=open

(2) CAPACITANCE (Ta=25°C, fSCK=1MHz, VCC=5.0V)

Parameter Symbol Condition Min. Max. Unit

Output Capacitance

SO pin CO

VO=0V

8.0

Input Capacitance

CS, SCK, SI pins CIN

VIN=0V

6.0

Note: These parameters are not 100% tested. These are the sample value.

ASAHI KASEI [AK6510C/12C]

DAP02E-04 2005/03

- 12 -

(3) A.C. ELECTRICAL CHARACTERISTICS 1

(1.8V≤VCC≤5.5V, -40°C≤Ta≤85°C, unless otherwise specified)

Parameter Symbol Condition Min. Max. Unit

fSCK1 4.5V

≤

VCC

≤

5.5V 5.0 MHz

SCK Frequency

fSCK2 2.5V≤VCC<4.5V 2.5 MHz

fSCK3

1.8V≤VCC<2.5V 1.0 MHz

tSKSH1 4.5V≤VCC≤5.5V 50 ns

SCK Setup Time

tSKSH2 2.5V≤VCC<4.5V 50 ns

tSKSH3 1.8V≤VCC<2.5V 50 ns

tCSS1 4.5V≤VCC≤5.5V 90 ns

CS Setup Time

tCSS2 2.5V≤VCC<4.5V 200 ns

tCSS3

1.8V≤VCC<2.5V 400 ns

tSKW1 4.5V≤VCC≤5.5V 90 ns

SCK Pulse Width

tSKW2 2.5V≤VCC<4.5V 200 ns

tSKW3

1.8V≤VCC<2.5V 400 ns

SCK Rise Time *3 tRC 2 µs

SCK Fall Time *3 tFC 2 µs

tDIS1 4.5V≤VCC≤5.5V 20 ns

Data Setup Time

tDIS2 2.5V≤VCC<4.5V 40 ns

tDIS3

1.8V≤VCC<2.5V 60 ns

tDIH1 4.5V≤VCC≤5.5V 30 ns

Data Hold Time

tDIH2 2.5V≤VCC<4.5V 50 ns

tDIH3

1.8V≤VCC<2.5V 100 ns

Data Rise Time *3 tRD 2 µs

Data Fall Time *3 tFD 2 µs

tPD1 4.5V≤VCC≤5.5V 60 ns

SO pin Output Delay

tPD2 2.5V≤VCC<4.5V 150 ns

tPD3

1.8V≤VCC<2.5V 340 ns

tOZ1 4.5V≤VCC≤5.5V 100 ns

SO pin Hi-Z Time

tOZ2 2.5V≤VCC<4.5V 240 ns

tOZ3

1.8V≤VCC<2.5V 500 ns

SO pin Output Hold Time tOHD 0 ns

tCSH1 4.5V≤VCC≤5.5V 90 ns

CS Hold Time

tCSH2 2.5V≤VCC<4.5V 200 ns

tCSH3

1.8V≤VCC<2.5V 400 ns

tSKH1 4.5V≤VCC≤5.5V 50 ns

SCK Hold Time

tSKH2 2.5V≤VCC<4.5V 50 ns

tSKH3 1.8V≤VCC<2.5V 50 ns

tCS1 4.5V≤VCC≤5.5V 100 ns

CS High Time

tCS2 2.5V≤VCC<4.5V 200 ns

tCS3

1.8V≤VCC<2.5V 300 ns

*3: These parameters are not 100% tested. These are the sample value.

ASAHI KASEI [AK6510C/12C]

DAP02E-04 2005/03

- 13 -

(4) A.C. ELECTRICAL CHARACTERISTICS 2

(1.8V≤VCC≤5.5V, -40°C≤Ta≤85°C, unless otherwise specified)

Parameter Symbol Condition Min. Max. Unit

tHFS1 4.5V

≤

VCC

≤

5.5V 40 ns

HOLD Setup Time 1

tHFS2 2.5V≤VCC<4.5V 90 ns

tHFS3

1.8V≤VCC<2.5V 200 ns

tHFH1 4.5V≤VCC≤5.5V 40 ns

HOLD Hold Time 1

tHFH2 2.5V≤VCC<4.5V 90 ns

tHFH3

1.8V≤VCC<2.5V 200 ns

tHRS1 4.5V≤VCC≤5.5V 40 ns

HOLD Setup Time 2

tHRS2 2.5V≤VCC<4.5V 90 ns

tHRS3

1.8V≤VCC<2.5V 200 ns

tHRH1 4.5V≤VCC≤5.5V 40 ns

HOLD Hold Time 2

tHRH2 2.5V≤VCC<4.5V 90 ns

tHRH3 1.8V≤VCC<2.5V 200 ns

tHOZ1 4.5V≤VCC≤5.5V 100 ns

HOLD Low to Output Hi-Z

tHOZ2 2.5V≤VCC<4.5V 150 ns

tHOZ3

1.8V≤VCC<2.5V 250 ns

tHPD1 4.5V≤VCC≤5.5V 100 ns

HOLD High to Output Low-Z

tHPD2 2.5V≤VCC<4.5V 150 ns

tHPD3

1.8V≤VCC<2.5V 250 ns

Selftimed Programming Time tWR 5 ms

Endurance *4 5.5V, 25°C, Page Write 1,000,000 E/W

cycles /

Address

*4: These parameters are not 100% tested. These are the sample value.

 AC Measurement Condition

Load Capacitance CL=100pF

ASAHI KASEI [AK6510C/12C]

DAP02E-04 2005/03

- 14 -

Synchronous Data Timing

Instruction Input

Data Output (READ)

tCS tCSS

tSKSH

tDIS tDIH

000

Hi-Z

tRC tFC

SCK

tSKW tSKW

tFD tRD

tSKW tSKW

tDIS tDIH

Hi-Z D7 D6

"L"

"H"

tPD tPD

SCK

tOHD

ASAHI KASEI [AK6510C/12C]

DAP02E-04 2005/03

- 15 -

Data Output (READ)

Data Input (WRITE)

tOZ

SCK

tCS tCSS

tSKSH

tPD

tOHD Hi-Z

tSKHtCSH

Hi-Z

D2 D1 D0

tCSH

SCK

tSKH

ASAHI KASEI [AK6510C/12C]

DAP02E-04 2005/03

- 16 -

Hold

tHFS

tHOZ

n+1

Hi-Z

"L"

"H"

SCK

HOLD

tHFH

Dn+1 Dn

tHRS tHRH

tDIS

tHPD

n-1

Dn-1

IMPORTANT NOTICE

• These products and their specifications are subject to change without notice. Before considering any

use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized

distributor concerning their current status.

• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the

application or use of any information contained herein.

• Any export of these products, or devices or systems containing them, may require an export license

or other official approval under the law and regulations of the country of export pertaining to customs

and tariffs, currency exchange, or strategic materials.

• AKM products are neither intended nor authorized for use as critical components in any safety, life

support, or other hazard related device or system, and AKM assumes no responsibility relating to an y

such use, except with the express written consent of the Representative Director of AKM. As used

here:

(a) A hazard related device or system is one designed or intended for life support or maintenance of

safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its

failure to function or perform may reasonably be expected to result in loss of life or in significant

injury or damage to person or propert y.

(b) A critical component is one whose failure to function or perform may reasonably be expected to

result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or

system containing it, and which must therefore meet very high standards of performance and

reliability.

• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or

otherwise places the product with a third party to notify that party in advance of the above content

and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability

for and hold AKM harmless from any and all claims arising from the use of said product in the

absence of such notification.