Description
The ATS128LSE programmable, true power-on state (TPOS),
sensor IC is an optimized combination of Hall-effect IC and
rare-earth pellet that switches in response to magnetic signals
created by ferromagnetic targets in gear-tooth sensing and
proximity sensing applications.
These devices offer a wide programming range for the magnetic
operate point, BOP . A fixed hysteresis then sets the magnetic
release point, BRP , based on the selected BOP .
The devices are externally programmable. A wide range of
programmability is available on the magnetic operate point,
BOP , while the hysteresis remains fixed. This advanced
feature allows optimization of the sensor IC switchpoint and
can drastically reduce the effects of mechanical placement
tolerances found in production environments.
A proprietary dynamic offset cancellation technique, with
an internal high-frequency clock, reduces the residual offset
voltage, which is normally caused by device overmolding,
temperature dependencies, and thermal stress. Having the Hall
element and amplifier in a single chip minimizes many problems
normally associated with low-level analog signals.
This device is ideal for use in gathering speed or position
information using gear-tooth–based configurations, or for
proximity sensing with ferromagnetic targets.
The ATS128 is provided in a 4-pin SIP. It is lead (Pb) free,
with 100% matte tin leadframe plating.
ATS128LSE-DS, Rev. 1
MCO-0000595
Features and Benefits
• Chopper stabilization for stable switchpoints throughout
operating temperature range
• User-programmable:
▫Magneticoperatepointthroughthe
VCC
pin:
9 programming bits provide 4-gauss resolution
▫Outputpolarity
▫OutputfalltimeforreducedEMIin
automotive applications
• On-board voltage regulator for 3 to 24 V operation
• On-chip protection against:
▫Supplytransients
▫Outputshort-circuits
▫Reversebatterycondition
• True Zero-Speed Operation
• True Power-On State
Highly Programmable, Back-Biased, Hall-Effect Switch
with TPOS Functionality
Package: 4-pin SIP (suffix SE)
Functional Block Diagram
Not to scale
ATS128LSE
SwitchpointTC Trim
VCC
GND
VOUT
To all subcircuits
Regulator
Dynamic Offset
Cancellation
Trim Control
Signal Recovery
Amp
Program Control
Output Fall Time
Output Polarity
February 14, 2019
Highly Programmable, Back-Biased,
Hall-Effect Switch with TPOS Functionality
ATS128LSE
2
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Pin-out Diagram
Absolute Maximum Ratings
Characteristic Symbol Notes Rating Unit
Forward Supply Voltage VCC 28 V
Reverse Supply Voltage VRCC –18 V
Forward Output Voltage VOUT 28 V
Reverse Output Voltage VROUT –0.7 V
Output Current Sink IOUT(SINK)
Internal current limiting is intended to protect
the device from output short circuits, but is not
intended for continuous operation.
20 mA
Operating Ambient Temperature TAL temperature range –40 to 150 ºC
Maximum Junction Temperature TJ(max) 165 ºC
Storage Temperature Tstg –65 to 170 ºC
Terminal List Table
Number Name Function
1 VCC Input power supply
2 VOUT Output signal
3 NC No connect
4 GND Ground
Selection Guide
Part Number Packing*
ATS128LSETN-T 450 pieces per 13-in. reel
*Contact Allegro™ for additional packing options
2 431
Highly Programmable, Back-Biased,
Hall-Effect Switch with TPOS Functionality
ATS128LSE
3
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Electrical Characteristics
Supply Voltage VCC 3 12 24 V
Supply Current ICC No load on VOUT – – 5.5 mA
Supply Zener Clamp Voltage VZSUPPLY TA = 25°C, ICC = ICC(max) + 3 mA 28 – – V
Supply Zener Current IZSUPPLY VCC = 28 V – – 8.5 mA
Output Zener Clamp Voltage VZOUTPUT IOUT = 3 mA 28 – – V
Reverse Battery Current IRCC VCC = –18 V –5 – – mA
Chopping Frequency fC– 400 – kHz
Power-On Characteristics
Power-On Time1tPO TA = 25°C; CLOAD (PROBE) = 10 pF – – 30 µs
Power-On State2POS POL = 0 B < BRP
, t > ton – High – –
POL = 1 B < BRP
, t > ton – Low – –
Output Stage Characteristics
Output Saturation Voltage VOUT(sat) Output = On, IOUT = 20 mA – 175 400 mV
Output Leakage Current IOFF VOUT = 24 V; Output = Off – – 10 µA
Output Current Limit IOUT(lim) Short-Circuit Protection, Output = On 30 – 90 mA
Output Rise Time3tr
VCC = 12 V, RPU = 820 Ω, CLOAD = 10 pF,
see figure 1 – – 2 µs
VCC = 12 V, RPU = 2 kΩ, CLOAD = 4.7 nF,
see figure 1 – 21 – µs
Output Fall Time4tf
FALL = 0 VCC = 12 V, RLOAD = 820 Ω,
CLOAD = 10 pF, see figure 1 – – 2 µs
FALL = 1 VCC = 12 V, RLOAD = 2 kΩ,
CLOAD = 4.7 nF, see figure 1 5 – 10 µs
FALL = 3 VCC = 12 V, RLOAD = 2 kΩ,
CLOAD = 4.7 nF, see figure 1 8 – 13 µs
FALL = 4 VCC = 12 V, RLOAD = 2 kΩ,
CLOAD = 4.7 nF, see figure 1 10 – 16 µs
OPERATING CHARACTERISTICS Valid with TA = –40°C to 150°C, CBYPASS = 0.1 µF, VCC = 12 V, unless otherwise noted
Characteristics Symbol Test Conditions Min. Typ. Max. Unit
Continued on the next page…
tf
tr
V+ %
100
90
10
0
VOUT(High)
VOUT(Low)
Figure 1. Rise Time and Fall Time Definitions
Highly Programmable, Back-Biased,
Hall-Effect Switch with TPOS Functionality
ATS128LSE
4
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
OPERATING CHARACTERISTICS (continued) Valid with TA = –40°C to 150°C, CBYPASS = 0.1 µF, VCC = 12 V,
unless otherwise noted
Characteristics Symbol Test Conditions Min. Typ. Max. Unit
Output Stage Characteristics (continued)
Output Polarity2POL
POL = 0 B > BOP
, opposite tooth – Low – –
B < BRP , opposite valley – High – –
POL = 1 B > BOP , opposite tooth – High – –
B < BRP , opposite valley – Low – –
Magnetic Characteristics valid VCC = 3 to 24 V, TJ ≤ TJ(max), using Allegro 8X reference target, unless otherwise noted
Air Gap Setpoint Drift Over Temperature5 AGDrift Device programmed with air gap of 2.5 mm – ±0.2 – mm
Programming Characteristics
Switchpoint Magnitude Selection Bits BitBOPSEL – 8 – Bit
Switchpoint Polarity Bits BitBOPPOL – 1 – Bit
Output Polarity Bits BitPOL – 1 – Bit
Fall Time Bits BitFALL – 2 – Bit
Device Lock Bits BitLOCK – 1 – Bit
Programmable Air Gap Range6,7 AGRange
TA = 25°C, Minimum code (BOPPOL = 1,
BOPSEL = 255) 2.5 – – mm
TA = 25°C, Maximum code (BOPPOL = 0,
BOPSEL = 255) – – 1.5 mm
AGRange Programming Resolution ResAG
TA = 25°C, device programmed with air gap of
2.5 mm – 0.05 – mm
1Determined by design and device characterization.
2Output state when device configured as shown in figure 4.
3Output Rise Time is governed by external circuit tied to VOUT. Measured from 10% to 90% of steady state output.
4Measured from 90% to 10% of steady state output.
5Switchpoint varies with temperature, proportionally to the programmed air gap. This parameter is based on characterization data and is not a tested
parameter in production. The AGDrift value trends smaller as temperature increases.
6Switchpoint varies with temperature. A sufficient margin, obtained through customer testing, is recommended to ensure functionality across the
operating temperature range. Programming at larger air gaps leaves less margin for switchpoint drift.
7At the minimum code setpoint (BOPSEL = 255, BOPPOL = 1), the switchpoint can correspond to an air gap greater than 2.5 mm, and at maximum
code setpoint (BOPSEL = 255, BOPPOL = 0), the switchpoint can correspond to an air gap smaller than 1.5 mm.
Highly Programmable, Back-Biased,
Hall-Effect Switch with TPOS Functionality
ATS128LSE
5
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information
Characteristic Symbol Test Conditions* Value Units
Package Thermal Resistance RθJA
1-layer PCB with copper limited to solder pads 101 ºC/W
1-layer PCB with copper limited to solder pads and 3.57 in.2 (23.03 cm2)
of copper area each side 77 ºC/W
0
5
10
15
20
25
30
20 40 60 80 100 120 140 160 180
Temperature, T
A
(ºC)
Maximum Allowable V
CC
(V)
(R
θJA
= 101 ºC/W)
Pads Only PCB
(R
θJA
= 77 ºC/W)
1-Layer PCB
VCC(min)
VCC(max)
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
1300
1400
1500
1600
1700
1800
1900
20 40 60 80 100 120 140 160 180
Temperature, T
A
(°C)
Power Dissipation, P
D
(mW)
(RθJA = 101 ºC/W)
Pads-only PCB
(R
θJA
= 77 ºC/W)
1-layer PCB
*Additional information is available on the Allegro Web site.
Power Dissipation versus Ambient Temperature
Power Derating Curve
Highly Programmable, Back-Biased,
Hall-Effect Switch with TPOS Functionality
ATS128LSE
6
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Characteristic Performance
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
-50 -25 0 25 50 75 100 125 150
Programmed Switchpoints versus Temperature
at Various Air Gaps (8X Reference Target)
Temperature (°C)
Air Gap (mm)
Code: –16 (BRP)
Code: –32 (BRP)
Code: –32 (BOP)
Code: –16 (BOP)
Code: 32 (BRP)
Code: 64 (BRP)
Code: 64 (BOP)
Code: 128 (BOP)
Code: 128 (BRP)
Code: 32 (BOP)
Highly Programmable, Back-Biased,
Hall-Effect Switch with TPOS Functionality
ATS128LSE
7
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
500
400
300
200
100
0
Ambient Temperature, TA (°C)
Saturation Voltage, VOUT(sat) (V)
-50 -25 0 25 50 75 100 150125 175
VCC (V)
3.3
5
24
IOUT = 20 mA
Saturation Voltage versus Ambient Temperature
Ambient Temperature, TA (°C)
Supply Current, ICC (mA)
6
5
4
3
2
1
0
-50 -25 0 25 50 75 100 150125 175
VCC (V)
3.3
5
24
Supply Current (Off) versus Ambient Temperature
6
5
4
3
2
1
0
-50 -25 0 25 50 75 100 150125 175
Ambient Temperature, TA (°C)
Supply Current, ICC (mA)
VCC (V)
3.3
5
24
Supply Current (On) versus Ambient Temperature
Highly Programmable, Back-Biased,
Hall-Effect Switch with TPOS Functionality
ATS128LSE
8
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Functional Description
When the Output Polarity bit is not set (POL = 0), the ATS128
output switches on after the magnetic field at the Hall sensor IC
exceeds the operate point threshold, BOP
. When the magnetic field
is reduced to below the release point threshold, BRP , the device
output switches off. The difference between the magnetic operate
and release points is called the hysteresis of the device, BHYS.
In the alternative case, in which the Output Polarity bit is set
(POL = 1), the ATS128 output switches off when the magnetic
field at the Hall sensor IC exceeds the operate point threshold,
BOP . When the magnetic field is reduced to below the release
point threshold, BRP , the device output switches on.
BOP
BRP
BHYS
VOUT(off)
VOUT
VOUT(on)(sat)
Switch On
Switch Off
B+
V+
0
BOPinit
BRP
BOP
BHYS
VOUT(off)
VOUT
VOUT(on)(sat)
Switch On
Switch Off
0
V+
B–
VOUT(off)
VOUT
VOUT(on)(sat)
V+
BOP
BRP
BHYS
Switch Off
Switch On
B+0BOPinit
VOUT(off)
VOUT
VOUT(on)(sat)
V+
BRP
BOP
BHYS
Switch Off
Switch On
0 BOPinit
B–
(A) BOPPOL = 0
POL = 0
(C) BOPPOL = 1
POL = 0
(B) BOPPOL = 0
POL = 1
(D) BOPPOL = 1
POL = 1
BOPinit
Figure 2. Hysteresis Diagrams. These plots demonstrate the behavior of the ATS128 with the applied magnetic field
impinging on the branded face of the device case (refer to Package Outline Drawings section). On the horizontal axis,
the B+ direction indicates increasing south or decreasing north magnetic flux density, and the B– direction indicates
increasing north or decreasing south magnetic flux density.
Highly Programmable, Back-Biased,
Hall-Effect Switch with TPOS Functionality
ATS128LSE
9
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Air Gap Operating Range
The Programmable Air Gap Range, AGRange , can be pro-
grammed around the zero crossing point, within the range limits:
AGRange(min) and AGRange(max). The available programming
range for AGRange falls within the distributions of the initial,
minimum code setpoint (BOPSEL = 255, BOPPOL = 1), and the
maximum code setpoint (BOPSEL = 255, BOPPOL = 0). The
switchpoint can correspond to an air gap smaller than 1.5 mm or
larger than 2.5 mm, as shown in figure 3.
Typical initial value
before customer
programming
AG
Range
(min)
= 2.5 mm
AG
Range
(max)
= 1.5 mm
Programming range
(specified limits)
Distribution of values
resulting from maximum
programming code
Distribution of values
resulting from minimum
programming code
Air Gap, AG
Figure 3. On the horizontal axis, the operating air gap may exceed the
recommended range for switching. The maximum and minimum values
for the actual operating air gap range are described by distributions of the
maximum and minimum code setpoints.
Highly Programmable, Back-Biased,
Hall-Effect Switch with TPOS Functionality
ATS128LSE
10
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Application Information
Figure 4. Typical Application Circuit
Figure 5. Concept of Chopper Stabilization Technique
Chopper Stabilization Technique
When using Hall-effect technology, a limiting factor for
switchpoint accuracy is the small signal voltage developed across
the Hall element. This voltage is disproportionally small relative
to the offset that can be produced at the output of the Hall sensor
IC. This makes it difficult to process the signal while maintain-
ing an accurate, reliable output over the specified operating
temperature and voltage ranges. Chopper stabilization is a unique
approach used to minimize Hall offset on the chip. Allegro
employs a technique to remove key sources of the output drift
induced by thermal and mechanical stresses. This offset reduction
technique is based on a signal modulation-demodulation process.
The undesired offset signal is separated from the magnetic field-
induced signal in the frequency domain, through modulation.
The subsequent demodulation acts as a modulation process for
the offset, causing the magnetic field-induced signal to recover
its original spectrum at base band, while the DC offset becomes
a high-frequency signal. The magnetic-sourced signal then can
pass through a low-pass filter, while the modulated DC offset is
suppressed. In addition to the removal of the thermal and stress
related offset, this novel technique also reduces the amount of
thermal noise in the Hall sensor IC while completely removing
the modulated residue resulting from the chopper operation. The
chopper stabilization technique uses a high frequency sampling
clock. For demodulation process, a sample and hold technique is
used. This high-frequency operation allows a greater sampling
rate, which results in higher accuracy and faster signal-processing
capability. This approach desensitizes the chip to the effects
of thermal and mechanical stresses, and produces devices that
have extremely stable quiescent Hall output voltages and precise
recoverability after temperature cycling. This technique is made
possiblethroughtheuseofaBiCMOSprocess,whichallowsthe
use of low-offset, low-noise amplifiers in combination with high-
density logic integration and sample-and-hold circuits.
Amp
Regulator
Clock/Logic
Hall Element
Tuned
Filter
Anit-aliasing
LP Filter
2
VCC
1.2 kΩ
100 Ω
V+
IC Output
GND
VOUT
CBYPASS
0.1 µF
120 pF
RLOAD
CLOAD
ATS128
1
3
A
A
A
A
ATie to device pins using
traces as short as possible
Highly Programmable, Back-Biased,
Hall-Effect Switch with TPOS Functionality
ATS128LSE
11
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Target Flux Density versus Target Rotation
Allegro Reference Target 8X
0
200
400
600
800
1000
1200
1400
0 30 60 90 120 150 180 210 240 270 300 330 360
Rotation (º)
Relative Magnetic Flux Density
*
, B (G)
*
B measured relative to the baseline magnetic field; field polarity referenced to the branded face.
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
3.25
3.50
3.75
4.00
4.25
4.50
4.75
5.00
5.25
5.50
5.75
6.00
Air Gap
(mm)
REFERENCE TARGET 8X
Characteristic Symbol Test Conditions Typ. Units Symbol Key
Outside Diameter DoOutside diameter of target 120 mm
t
t
V
Ø
D
O
h
t
F
Branded Face
of Package
Air Gap
Face Width F Breadth of tooth, with respect to
branded face 6 mm
Circular Tooth Length tLength of tooth, with respect to
branded face; measured at Do
23.6 mm
Circular Valley Length tv
Length of valley, with respect to
branded face; measured at Do
23.6 mm
Tooth Whole Depth ht5 mm
Material CRS 1018 – –
Reference Target 8X
of Package
Branded Face
Target / Gear Parameters for Correct Operation
For correct operation, TPOS or continuous, the target must
generate a minimum difference between the applied flux den-
sity over a tooth and the applied flux density over a valley, at
the maximum installation air gap.
The following recommendations should be followed in the
design and specification of targets:
• FaceWidth,F≥5mm
• CircularToothLength,t≥5mm
• Circular Valley Length, tv > 13 mm
• Whole Tooth Depth, ht > 5 mm
1400
1200
1000
800
600
400
200
0
Reference Gear Magnetic Gradient Amplitude versus Air Gap
Air Gap (mm)
Opposite tooth
Opposite valley
Flux Density B (G)
0123456
Reference Target Characteristics
Highly Programmable, Back-Biased,
Hall-Effect Switch with TPOS Functionality
ATS128LSE
12
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Overview
Programming is accomplished by sending a series of input volt-
age pulses serially through the VCC (supply) pin of the device.
A unique combination of different voltage level pulses controls
the internal programming logic of the device to select a desired
programmable parameter and change its value. There are three
voltage levels that must be taken into account when program-
ming. These levels are referred to as high (VPH), mid (VPM), and
low (VPL).
The ATS128 features three programmable modes, Try mode,
Blow mode, and Read mode:
• In Try mode, programmable parameter values are set and mea-
sured simultaneously. A parameter value is stored temporarily,
and reset after cycling the supply voltage.
• In Blow mode, the value of a programmable parameter may
be permanently set by blowing solid-state fuses internal to the
device. Device locking is also accomplished in this mode.
• In Read mode, each bit may be verified as blown or not blown.
The programming sequence is designed to help prevent the device
from being programmed accidentally; for example, as a result of
noise on the supply line. Note that, for all programming modes, no
parameter programming registers are accessible after the device-
level LOCK bit is set. The only function that remains accessible is
the overall Fuse Checking feature.
Although any programmable variable power supply can be used
to generate the pulse waveforms, for design evaluations, Allegro
highly recommends using the Allegro Sensor IC Evaluation Kit,
available on the Allegro website On-line Store. The manual for
that kit is available for download free of charge, and provides
additional information on programming these devices. (Note: This
kit is not recommended for production purposes.)
Definition of Terms
Register The section of the programming logic that controls the
choice of programmable modes and parameters.
Bit Field The internal fuses unique to each register, represented
as a binary number. Changing the bit field settings of a particular
Programming Guidelines
Table 1. Programming Pulse Requirements, Protocol at TA = 25°C
Characteristics Symbol Notes Min. Typ. Max. Unit
Programming Voltage
VPL
Measured at the VCC pin
4.5 5 5.5 V
VPM 12.5 – 14 V
VPH 21 – 27 V
Programming Current IPP
VCC = 5 → 26 V, CBLOW = 0.1 µF (min); minimum supply current required to
ensure proper fuse blowing. 175 – – mA
Pulse Width
tLOW Duration of VPL separating pulses at VPM or VPH 20 – – µs
tACTIVE Duration of pulses at VPM or VPH for key/code selection 20 – – µs
tBLOW Duration of pulse at VPH for fuse blowing 90 100 – µs
Pulse Rise Time tPr VPL to VPM or VPL to VPH 5 – 100 µs
Pulse Fall Time tPf VPM to VPL or VPH to VPL 5 – 100 µs
Blow Pulse Slew Rate SRBLOW 0.375 – – V/µs
Figure 6. Programming pulse definitions (see table 1)
Supply Voltage, VCC
GND
(Supply
cycled)
Programming
pulses Blow
pulse
tACTIVE
tLOW
tLOW
tBLOW
tPr
tPf
VPH
VPM
VPL
Highly Programmable, Back-Biased,
Hall-Effect Switch with TPOS Functionality
ATS128LSE
13
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
register causes its programmable parameter to change, based on
the internal programming logic.
Key A series of voltage pulses used to select a register or mode.
Code The number used to identify the combination of fuses
activated in a bit field, expressed as the decimal equivalent of the
binary value. The LSB of a bit field is denoted as code 1, or bit 0.
Addressing Increasing the bit field code of a selected register
by serially applying a pulse train through the VCC pin of the
device. Each parameter can be measured during the addressing
process, but the internal fuses must be blown before the program-
ming code (and parameter value) becomes permanent.
Fuse Blowing Applying a high voltage pulse of sufficient
duration to permanently set an addressed bit by blowing a fuse
internal to the device. Once a bit (fuse) has been blown, it cannot
be reset.
Blow Pulse A high voltage pulse of sufficient duration to blow
the addressed fuse.
Cycling the Supply Powering-down, and then powering-up the
supply voltage. Cycling the supply is used to clear the program-
ming settings in Try mode.
Programming Procedure
Programming involves selection of a register and mode, and then
setting values for parameters in the register for evaluation or fuse
blowing. Figure 10 provides an overview state diagram.
Register Selection
Each programmable parameter can be accessed through a specific
register. To select a register, from the Initial state, a sequence of
voltage pulses consisting of one VPH pulse, one VPM pulse, and
then a unique combination of VPH and VPM pulses, is applied
serially to the VCC pin (with no VCC supply interruptions). This
sequence of pulses is called the key, and uniquely identifies each
register. An example register selection key is shown in figure 7.
To simplify Try mode, the ATS128 provides a set of four virtual
registers, one for each combination of: BOP selection (BOPSEL),
BOP polarity (BOPPOL), and a facility for transiting BOP magni-
tude values in an increasing or decreasing sequence. These reg-
isters also allow wrapping back to the beginning of the register
after transiting the register.
Mode Selection
The same physical registers are used for all programming modes.
To distinguish the Blow mode and Read mode, when selecting
the registers an additional pulse sequence consisting of eleven
VPM pulses followed by one VPH pulse is added to the key. The
combined register and mode keys are shown in table 3.
Try Mode
In Try mode, the bit field addressing is accomplished by apply-
ing a series of VPM pulses to the VCC pin of the device, as shown
in figure 7. Each pulse increases the total bit field value of the
selected parameter, increasing by one on the falling edge of each
additional VPM pulse. When addressing a bit field in Try mode,
the number of VPM pulses is represented by a decimal number
called a code. Addressing activates the corresponding fuse loca-
tions in the given bit field by increasing the binary value of an
internal DAC, up to the maximum possible code. As the value
of the bit field code increases, the value of the programmable
parameterchanges.MeasurementscanbetakenaftereachVPM
pulse to determine if the desired result for the programmable
parameter has been reached. Cycling the supply voltage resets
all the locations in the bit field that have un-blown fuses to their
initial states. This should also be done before selection of a differ-
ent register in Try mode.
When addressing a parameter in Try mode, the bit field address
(code) defaults to the value 1, on the falling edge of the final reg-
ister selection key VPH pulse (see figure 8). A complete example
is shown figure 12. Note that, in the four BOP selection virtual
registers, after the maximum code is entered, the next VPM pulse
wraps back to the beginning of the register, and selects code 0.
Figure 7. Example of Try mode register selection pulses, for the BOP
Negative Trim, Up-Counting register.
Figure 8. Try mode bit field addressing pulses.
V
PH
V
PM
V
PL
GND
VCC
V
PH
V
PM
V
PL
GND
VCC
Code 2
Code 1
Code 3
Code 2
n
–2
Code 2
n
–1
Highly Programmable, Back-Biased,
Hall-Effect Switch with TPOS Functionality
ATS128LSE
14
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
The four BOP selecting virtual registers allow the programmer
to adjust the BOP parameter for use with a wide magnetic field
range. In addition, values can be traversed from low to high, or
from high to low. Figure 12 shows the relationship between the
BOP parameter and the different Try mode registers. Note: See the
Output Polarity section for information about setting the POL bit
before using Try mode.
The FALL and POL fields are in the same register (FALL is
bits 1:0, and POL is bit 2). Therefore, in Try mode both can be
programmed simultaneously by adding the codes for the two
parameters, and send the sum as the code. For example, sending
code 7 (111) sets FALL to 3 (x11) and sets POL (1xx).
Blow Mode
After the required code is determined for a given parameter, its
value can be set permanently by blowing individual fuses in the
appropriate register bit field. Blowing is accomplished by select-
ing the register and mode selection key, followed by the appro-
priate bit field address, and ending the sequence with a Blow
pulse. The Blow mode selection key is a sequence of eleven VPM
pulses followed by one VPH pulse. The Blow pulse consists of a
VPH pulse of sufficient duration, tBLOW
, to permanently set an
addressed bit by blowing a fuse internal to the device. The device
power must be cycled after each individual fuse is blown.
A0.1μFblowingcapacitor,CBLOW
, must be mounted between
the VCC pin and the GND pin during programming, to ensure
enough current is available to blow fuses. If programming in the
application, CBYPASS (see figure 4) can serve the same purpose.
Due to power requirements, the fuse for each bit in the bit field
must be blown individually. The ATS128 built-in circuitry allows
only one fuse at a time to be blown. During Blow mode, the bit
field can be considered a one-hot shift register. Table 2 illustrates
how to relate the number of VPM pulses to the binary and decimal
value for Blow mode bit field addressing. It should be noted that
the simple relationship between the number of VPM pulses and
the required code is:
2n = Code,
where n is the number of VPM pulses, and the bit field has an ini-
tial state of decimal code 1 (binary 00000001). To correctly blow
the required fuses, the code representing the required parameter
value must be translated to a binary number. For example, as
shown in figure 9, decimal code 5 is equivalent to the binary
number 101. Therefore bit 2 must be addressed and blown, the
device power supply cycled, and then bit 0 must be addressed
and blown. The order of blowing bits, however, is not impor-
tant. Blowing bit 0 first, and then bit 2 is acceptable. A complete
example is shown in figure 13.
Note: After blowing, the programming is not reversible, even
after cycling the supply power. Although a register bit field fuse
cannot be reset after it is blown, additional bits within the same
register can be blown at any time until the device is locked. For
example, if bit 1 (binary 10) has been blown, it is still possible to
blow bit 0. The end result would be binary 11 (decimal code 3).
Locking the Device
After the required code for each parameter is programmed, the
device can be locked to prevent further programming of any
parameters. To do so, perform the following steps:
1. Ensure that the CBLOW capacitor is mounted.
2. Select the Output/Lock Bit register key.
3. Select Blow mode selection key.
4. Address bit 4 (10000) by sending four VPM pulses.
5. Send one Blow pulse, at IPP and SRBLOW, and sustain it for
tBLOW.
6. Delay for a tLOW interval, then power-down.
7. Optionally check all fuses.
Figure 9. Example of code 5 broken into its binary components.
Table 2. Blow Mode Bit Field Addressing
Quantity of
VPM Pulses
Binary
Register Bit Field
Decimal Equivalent
Code
0 00000001 1
1 00000010 2
2 00000100 4
3 00001000 8
4 00010000 16
5 00100000 32
6 01000000 64
7 10000000 128
(Decimal Equivalent)
Code 5
Bit Field Selection
Address Code Format
Code in Binary
Fuse Blowing
Target Bits
Fuse Blowing
Address Code Format
(Binary)
1 0 1
Bit 2 Bit 0
Code 4 Code 1
(Decimal Equivalents)
Highly Programmable, Back-Biased,
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ATS128LSE
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Table 3. Programming Logic Table
Register Name
[Selection Key]
Bit Field Address (Code)
Notes
Binary
(MSB→LSB)
Decimal
Equivalent
Try Mode Register Selections1
BOP Positive, Trim Up-Counting
[ 2 × VPH ]
00000000 0 Increase BOP (South field), wraps back to code 0.
11111111 255 BOP selection is at maximum value.
BOP Negative, Trim Up-Counting
[ VPH → VPM → 2 × VPH ]
00000000 0 Increase BOP (North field), wraps back to code 0.
11111111 255 BOP selection is at maximum value.
BOP Positive, Trim Down-Counting
[ 2 × VPH → 4 × VPM → VPH ]
11111111 0 Decrease BOP (South field), wraps back to code 0. Code is automatically
inverted (code 1 selects BOP selection maximum value minus 1.)
00000000 255 BOP selection is at minimum value.
BOP Negative, Trim Down-Counting
[VPH → VPM → 2 × VPH
→ 4 × VPM → VPH ]
11111111 0 Decrease BOP (North field), wraps back to code 0. Code is automatically
inverted (code 1 selects BOP selection maximum value minus 1.)
00000000 255 BOP selection is at minimum value.
Output / Fuse Checking
[ VPH → 3 × VPM → VPH ]
x01 1 Output Fall Time (FALL). Least significant bit.
x11 3 Output Fall Time (FALL). Most significant bit.
0xx 0 Output Polarity Bit (POL). Default, no fuse blowing required.
POL = 0, VOUT = Low opposite target tooth.
1xx 4 Output Polarity Bit (POL).
POL = 1, VOUT = High opposite target tooth. Code references a single bit only.
1000 8 Fuse Threshold Low Register. Checks un-blown fuses. Code references a
single bit only.
1001 9 Fuse Threshold High Register. Checks blown fuses.
Blow or Read Mode Register Selections2
BOP Selection
(BOPSEL)
[ 2 × VPH
→ 11 × VPM → VPH ]
00000000 0 BOP magnitude selection. Default, no fuse blowing required.
Minimum value, corresponding to AGRange(max).
11111111 255 BOP magnitude selection. Maximum value, corresponding to AGRange(min).
BOP Polarity
(BOPPOL)
[ VPH → VPM → VPH
→ 11 × VPM → VPH ]
0 0 South field polarity. Default, no fuse blowing required.
1 1 North field polarity.
Output / Lock Bit
[ VPH → 3 × VPM → VPH
→ 11 × VPM → VPH ]
00 0 Output Fall Time (FALL). Default, no fuse blowing required.
11 3 Output Fall Time (FALL) selection is at maximum value.
000 0 Output Polarity Bit (POL). Default, no fuse blowing required.
POL = 0, VOUT = Low opposite target tooth.
100 4 Output Polarity Bit (POL). Code refers to bit 2 only. POL = 1, VOUT = High
opposite target tooth.
10000 16 Lock bit (LOCK). Locks access to all registers with exception of Fuse
Threshold registers. Code refers to bit 5 only.
0 to 1111111 –Read mode bit values. Sequentially selects each bit in selected Blow mode register
for reading bit status as blown or not blown. Monitor VOUT after each pulse.
1Code 1 is automatically selected after the falling edge of the final VPH in the register key. Each subsequent VPM in the bit field addresses the next
decimal code.
2Bit 0, or code 1, is automatically selected after the falling edge of the final VPH in the register key. Each subsequent VPM in the bit field addresses the
next bit.
Highly Programmable, Back-Biased,
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VPH
VPH
(Blow Pulse)
VPH
(Blow Pulse)
VPH
(Blow Pulse)
[Read fuse status on VOUT]
[Optional: test output or check fuse integrity]
VPM
→VPH
VPM VPM
3 × VPM
→VPH
3 × VPM
→VPH
→11×VPM
→VPH
→11×VPM
→VPH
→11×VPM
→VPH
VPH VPH
Register Selection
Try Mode
Read Mode
Initial State
(BOPSEL)
BOP
Selection
(BOPPOL)
BOP
Polarity
VPM
→VPH
→VPH
VPH
→4 × VPM
→ VPH
VPM
→2 × VPH
→4 × VPM
→ VPH
BOP
Positive
Trim Up
BOP
Negative
Trim Up
Code 0
BOP
Positive
Trim Down
BOP
Negative
Trim Down
Output/
Lock Bit
Output/
Fuse
Checking
VPM
Power-up
User power-down
required
Code 2 Code 2n–1
VPM VPM
Code 1
Bit 1 Bit n-1
VPM
Yes
VPM
Bit 0
Bit 1 Bit n-1
VPM VPM
Bit 0
Blow Mode
Blow Fuse
BOP Trim
register?
Figure 10. Programming State Diagram
Highly Programmable, Back-Biased,
Hall-Effect Switch with TPOS Functionality
ATS128LSE
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Fuse Checking
Incorporated in the ATS128 is circuitry to simultaneously check
the integrity of the fuse bits. The fuse checking feature is enabled
by using the Fuse Checking registers, and while in Try mode,
applying the codes shown in table 3. The register is only valid
in Try mode and is available before or after the programming
LOCK bit is set.
Selecting the Fuse Threshold High register checks that all blown
fuses are properly blown. Selecting the Fuse Threshold Low
register checks all un-blown fuses are properly intact. The supply
current, ICC,increasesby250μAifamarginalfuseisdetected.
If all fuses are correctly blown or fully intact, there will be no
change in supply current.
Output Polarity
When selecting the BOP registers in Try mode, the output polarity
is determined by the value of the Output Polarity bit (POL). The
default value is POL = 0 (fuse un-blown). For applications that
require the output states defined by POL = 1 (see Operating Char-
acteristics table), it is recommended to first permanently blow the
POL bit by selecting the Output / Lock bit register, and code 4.
The output is then defined by POL = 1 when selecting the BOP
Try mode registers. See table 3 for parameter details.
Additional Guidelines
The additional guidelines in this section should be followed to
ensure the proper behavior of these devices:
• The power supply used for programming must be capable of
delivering at least VPH and IPP
.
• Be careful to observe the tLOW delay time before powering
down the device after blowing each bit.
• Set the LOCK bit (only after all other parameters have been
programmed and validated) to prevent any further programming
of the device.
Read Mode
The ATS128 features a Read mode that allows the status of each
programmable fuse to be read back individually. The status,
blown or not blown, of the addressed fuse is determined by moni-
toring the state of the VOUT pin. A complete example is shown
in figure 11.
Read mode uses the same register selection keys as Blow mode
(see table 3), allowing direct addressing of the individual fuses in
the BOPPOL and BOPSEL registers (do not inadvertently send a
Blow pulse while in Read mode). After sending the register and
mode selection keys, that is, after the falling edge of the final VPH
pulse in the key, the first bit (the LSB) is selected. Each addi-
Figure 11. Read mode example. Pulse sequence for accessing the BOP Selection register
(BOPSEL) and reading back the status of each of the eight bit fields. In this example, the code
(blown fuses) is 2 + 22 +25 + 27 = 166 (10100110). After each address pulse is sent, the voltage
on the VOUT pin will be at GND for un-blown fuses and at VCC (at VPL or VPM) for blown fuses.
V
PH
V
PM
V
PL
V
PH
V
PM
V
PL
GND
Register (and Mode) Selection Key Bit Field (Fuse) Address Codes
Read-out on VOUT pin
1234567 1234567891011
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 0 Un-Blown
Bit 1 Blown
Bit 2 Blown
Bit 3 Un-Blown
Bit 4 Un-Blown
Bit 5 Blown
Bit 6 Un-Blown
Bit 7 Blown
GND Fuse intact
Fuse blown
VOUT VCC
Don’t Care
Highly Programmable, Back-Biased,
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ATS128LSE
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tional VPM pulse addresses the next bit in the selected register, up
totheMSB.ReadmodeisavailableonlybeforetheLOCKbit
has been set.
After the final VPH key pulse, and after each VPM address pulse,
if VOUT is high, the corresponding fuse can be considered blown
(the status of the Output Polarity bit, POL, does not affect Read
mode output values, allowing POL to be tested also). If the output
state is low, the fuse can be considered un-blown. During Read
mode VOUT must be pulled high using a pull-up resistor (see
RLOAD in the Typical Application Circuit diagram).
Figure 13. Example of Blow mode programming pulses applied to the VCC pin. In this example, the BOP Magnitude
Selection register (BOPSEL) is addressed to code 8 (bit 3, or 3 VPM pulses) and its value is permanently blown.
Figure 12. Example of Try mode programming pulses applied to the VCC pin. In this example, BOP Positive Trim, Down-
Counting register is addressed to code 12 by the eleven VPM pulses (code 1 is selected automatically at the falling edge
of the register-mode selection key).
V
PH
V
PM
V
PL
GND
Register (and Mode) Selection Key
Bit Field (Fuse)
Address Codes
1 2 3 4 5 6 7 1 2 38 9 10 11
VCC
Bit 1
Bit 2
Bit 3
Blow
Pulse
t
LOW
Code 8
V
PH
V
PM
V
PL
GND
Register (and Mode)
Selection Key
Bit Field
Address Codes
1 2 3 4 1 2 3 4 5 6 7 8 9 10 11
VCC
Code 7
Code 8
Code 9
Code 10
Code 11
Code 12
Code 4
Code 5
Code 6
Code 1
Code 2
Code 3
Highly Programmable, Back-Biased,
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ATS128LSE
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BOP Selection
The ATS128 allows accurate trimming of the magnetic operate
point, BOP , within the application. This programmable feature
reduces effects due to mechanical placement tolerances and
improves performance when used in proximity or gear tooth sens-
ing applications.
BOP can be set to any value within the range allowed by the
BOPSEL registers. This includes switchpoints of south or north
polarity, and switchpoints at or near the zero crossing point for
B. However, switching is recommended only within the air gap
limits specified in the Operating Characteristics table.
Trimming of BOP is typically done in two stages. In the first
stage, BOP is adjusted temporarily using the Try mode program-
ming features, to find the fuse value that corresponds to the
optimum BOP . After a value is determined, then it can be perma-
nently set using the Blow mode features.
As an aid to programming the ATS128 has several options avail-
ableinTryModeforadjustingtheBOP parameter. As shown in
figure 14, these allow trimming of BOP for operation in north or
south polarity magnetic fields. In addition the BOP parameter can
either trim-up, start at the BOP minimum value and increase to
the maximum value, or trim-down, starting at the BOP maximum
value and decreasing to the minimum value.
The Trim Up-Counting and Trim Down-Counting features can
simplify switchpoint calibration by allowing the user to find
the codes for both the magnetic operation point, BOP , and the
magnetic release point, BRP
. As an example, consider using the
ATS128 as a proximity sensor to detect rotational displacement
of a ferromagnetic target (see figure 15). When the ferromagnetic
target is centered opposite the device branded face, its location
is considered homed (0 mm displacement). If the target rotates
acertaindistance,±θ,ineitherdirection,thesensorICoutput
should change state.
(A) BOP Positive, Trim Up-Counting Register (B) BOP Positive, Trim Down-Counting Register
(C) BOP Negative, Trim Up-Counting Register (D) BOP Negative, Trim Down-Counting Register
BOP(max)
B+ (south)
B– (north)
BOP(max)
B+ (south)
B– (north)
B+ (south)
B– (north)
B+ (south)
B– (north)
BOP(min)
BOP(max) BOP(max)
BOP(min)
BOP(min) BOP(min)
Try Mode, Bit Field Code
Magnetic Field Intensity, B (G)
00
0255
Try Mode, Bit Field Code
Magnetic Field Intensity, B (G)
0255
Try Mode, Bit Field Code
Magnetic Field Intensity, B (G)
0255
Try Mode, Bit Field Code
Magnetic Field Intensity, B (G)
00
0255
BOP Setpoint BOP Setpoint
BOP Setpoint
BOP Setpoint
Figure 14. BOP profiles for each of the four BOP Selection virtual registers available in Try mode.
Highly Programmable, Back-Biased,
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B+
B–
Target Displacement from Home Position, θ (°)
Magnetic Field Intensity, B (G)
0–θ θ
BOP
Home
Position Displaced
Clockwise
Displaced
Counterclockwise
Target BRP
Figure 15 shows a plot of the example, indicating magnetic field
density versus displacement, at a fixed air gap. For the example,
the magnetic field is assumed to be positive (south). At the Home
position the device output will be in a state defined by B > BOP ,
low (assuming POL = 0) . In a position at a displacement greater
than±θ,theoutputwillbeinthestatedefinedbyB<BRP
, high.
To achieve the required result, BOP is programmed to a level such
thatthesensorICchangesstatefromlowtohighat±θ.
First, the target is located at the corresponding switchpoint loca-
tion,the–θ°or+θ°position.Next,thedevicePositiveTrim,Up-
Counting register is selected and the output is monitored while
the addressed code is increased. When the register is entered, the
default magnitude (code 1) of BOP is lower than the magnetic flux
density, Bactual, and output is low. (See A in figure 16.)
As the code is increased, BOP is increased. When BOP is increased
to a level where BOP point is greater than Bactual, the output
changes state from low to high. The code value when the device
switched from low to high corresponds to the BRP point (record
this for later reference). (See B in figure 16.)
To find the code that corresponds to BOP , the device Positive
Trim, Down-Counting register is selected, and the output is moni-
tored while the addressed code is increased. When the register
is entered, the default magnitude (code 1) BOP is higher than the
ambient field flux density, Bactual, (because the codes are inverted
for down-counting) and output is high. (See C in figure 17.)
Figure 15. Example of magnetic flux density versus target displacement. In an
application, an increasing B value could indicate either an increasing intensity of a
south field or a decreasing intensity of a north field.
Highly Programmable, Back-Biased,
Hall-Effect Switch with TPOS Functionality
ATS128LSE
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Allegro MicroSystems, LLC
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Figure 16. Positive Trim, Up-Counting to find BRP
. Figure 17. Positive Trim, Down-Counting to find BOP
.
BOP Positive, Trim Up-Counting Register BOP Positive, Trim Down-Counting Register
BOP(max)
B(actual) B(actual)
B+ (south)
B– (north)
BOP(max)
B+ (south)
B– (north)
BOP(min)
High
Low
High
Low
BOP(min)
Try Mode, Bit Field Code
t
Magnetic Field Intensity, B (G)Device Output, VOUT (V)
00
0255
Try Mode, Bit Field Code
Magnetic Field Intensity, B (G)
0255
t
Device Output, VOUT (V)
A
C
D
B
BRP
BOP Setpoint
BRP
BOP Setpoint
BRP
BOP Setpoint
BRP
BOP Setpoint
As the code is increased, BOP is decreased. When BOP is less
than Bactual the output changes state from high to low. (See D in
figure 17.) Record the BOP selection for later use. Because when
using the Down-Counting register the BOP selection is automati-
cally inverted, therefore the recorded value is equal to the maxi-
mum value minus the addressed code.
The air gap mechanical position is also a factor in determining
the magnetic switchpoints. As seen in figure 18, at smaller air
gaps the change in flux density versus change in displacement
is large, represented by a steeply sloped function, and there is
relatively little difference between the target displacements at BOP
and BRP
. At larger air gaps, however, the change function is shal-
Highly Programmable, Back-Biased,
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Allegro MicroSystems, LLC
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Figure 18. Example switchpoints versus mechanical location.
B+ (south)
B– (north)
Target Displacement from Home Position, θ (°)
Magnetic Field Intensity, B (G)
–θ
Smaller Air Gap
(Steeper slope)
Larger Air Gap
(Shallower slope)
BRP
BRP
BOP
B
OP
lower, and therefore the difference between BOP and BRP must
be considered. If BRP is more appropriate as the actual device
switchpoint, the code determined using the Up-Counting register
in the example can be programmed and set. If BOP is more appro-
priate as the switchpoint, the code determined using the Down-
Counting register can be programmed and set.
It should be noted that in the proximity sensor example given
above, the magnetic field was defined as positive (south) and
the BOP Positive, Trim Up- and Trim Down-Counting registers
were used. If in the application the magnetic field is negative,
the BOP Negative, Trim Up- and Trim Down-Counting registers
should be used as shown in figures 14C and 14D. The procedure
for programming these registers is the same as discussed in the
proximity sensor example. Note the purpose of the example is to
show how to use some of the ATS128 BOP programming options
and is not based on any reference design.
Highly Programmable, Back-Biased,
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Allegro MicroSystems, LLC
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The device must be operated below the maximum junction
temperature of the device, TJ(max) . Under certain combina-
tions of peak conditions, reliable operation may require derating
supplied power or improving the heat dissipation properties of
the application. This section presents a procedure for correlating
factors affecting operating TJ. (Thermal data is also available on
theAllegroMicroSystemswebsite.)
The Package Thermal Resistance, RθJA, is a figure of merit sum-
marizing the ability of the application and the device to dissipate
heat from the junction (die), through all paths to the ambient air.
Its primary component is the Effective Thermal Conductivity,
K, of the printed circuit board, including adjacent devices and
traces. Radiation from the die through the device case, RθJC, is
relatively small component of RθJA. Ambient air temperature,
TA, and air motion are significant external factors, damped by
overmolding.
The effect of varying power levels (Power Dissipation, PD), can
be estimated. The following formulas represent the fundamental
relationships used to estimate TJ, at PD.
PD = VIN × IIN
(1)
 ΔT = PD × RθJA (2)
TJ = TA+ΔT (3)
For example, given common conditions such as: TA= 25°C,
VIN = 12 V, IIN = 4 mA, and RθJA =140°C/W,then:
PD = VIN × IIN = 12 V × 4 mA = 48 mW
ΔT = PD × RθJA = 48 mW × 140°C/W=7°C
TJ = TA+ΔT=25°C+7°C=32°C
A worst-case estimate, PD(max) , represents the maximum allow-
able power level, without exceeding TJ(max) , at a selected RθJA
and TA.
Example: Reliability for VCC at TA
=
150°C,packageSE,usinga
single-layer PCB.
Observe the worst-case ratings for the device, specifically:
RθJA=
101°C/W,TJ(max) =
165°C, VCC(max)
=
24
V, and
ICC(max) = 5.5 mA.
Calculate the maximum allowable power level, PD(max) . First,
invert equation 3:
ΔTmax = TJ(max) – TA = 165
°C
–
150
°C=15
°C
This provides the allowable increase to TJ resulting from internal
power dissipation. Then, invert equation 2:
PD(max) = ΔTmax ÷ RθJA=15°C÷101°C/W=149mW
Finally, invert equation 1 with respect to voltage:
 VCC(est) = PD(max) ÷ ICC(max) = 149 mW ÷ 5.5 mA = 27 V
The result indicates that, at TA, the application and device can
dissipateadequateamountsofheatatvoltages≤VCC(est) .
Compare VCC(est) to VCC(max) . If VCC(est) ≤VCC(max) , then
reliable operation between VCC(est) and VCC(max) requires
enhanced RθJA. If VCC(est) ≥VCC(max) , then operation
between VCC(est) and VCC(max) is reliable under these condi-
tions.
Power Derating
Highly Programmable, Back-Biased,
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ATS128LSE
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Allegro MicroSystems, LLC
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Package SE 4-Pin SIP
1.0 REF
0.9±0.1
1.3±0.1
4.9±0.1
3.3±0.1
10.00±0.05
7.00±0.05
6.23±0.10
11.60±0.10
0.60±0.10
24.65±0.10
0.71±0.10 0.71±0.10
1.60±0.10
1.27±0.10
5.50±0.10
2.00±0.10
1.0 REF
For Reference Only, not for tooling use (reference DWG-9001)
Dimensions in millimeters
2 43
1
A
A
A
B
C
C
D
D
B
Dambar removal protrusion (16X)
Metallic protrusion, electrically connected to pin 4 and substrate (both sides)
Thermoplastic Molded Lead Bar for alignment during shipment
Standard Branding Reference View
LLLLLLL
YYWW
NNN
Branded
Face
= Supplier emblem
L = Lot identifier
N = Last three numbers of device part number
and optional subtype codes
Y = Last two digits of year of manufacture
W = Week of manufacture
Branding scale and appearance at supplier discretion
0.38 +0.06
–0.04
E
E
F
F
Active Area Depth, 0.43 mm
Hall element (not to scale)
Highly Programmable, Back-Biased,
Hall-Effect Switch with TPOS Functionality
ATS128LSE
25
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
For the latest version of this document, visit our website:
www.allegromicro.com
Revision History
Number Date Description
– May 4, 2013 Initial release
1 February 14, 2019 Minor editorial updates
Copyright ©2019, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
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The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
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