1000B-5002FNL - PULSE ELECTRONICS

April, 2016 − Rev. 3 1Publication Order Number:

NCP81071/D

NCP81071

Dual 5 A High Speed

Low-Side MOSFET Drivers

with Enable

NCP81071 is a high speed dual low−side MOSFETs driver. It is

capable of providing large peak currents into capacitive loads. This

driver can deliver 5 A peak current at the Miller plateau region to help

reduce the Miller effect during MOSFETs switching transition. This

driver also provides enable functions to give users better control

capability in different applications. ENA and ENB are implemented

on pin 1 and pin 8 which were previously unused in the industry

standard pin−out. They are internally pulled up to driver’s input

voltage for active high logic and can be left open for standard

operations. This part is available in MSOP8−EP package, SOIC8

package and WDFN8 3 mm x 3 mm package.

Features

•High Current Drive Capability ±5 A

•TTL/CMOS Compatible Inputs Independent of Supply Voltage

•Industry Standard Pin−out

•High Reverse Current Capability (6 A) Peak

•Enable Functions for Each Driver

•8 ns Typical Rise and 8 ns Typical Fall Times with 1.8 nF Load

•Typical Propagation Delay Times of 20 ns with Input Falling and

20ns with Input Rising

•Input Voltage from 4.5 V to 20 V

•Dual Outputs can be Paralleled for Higher Drive Current

•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

Applications

•Server Power

•Telecommunication, Datacenter Power

•Synchronous Rectifier

•Switch Mode Power Supply

•DC/DC Converter

•Power Factor Correction

•Motor Drive

•Renewable Energy, Solar Inverter

See detailed ordering and shipping information in the packag

dimensions section on page 11 of this data sheet.

ORDERING INFORMATION

MARKING

DIAGRAMS

www.onsemi.com

SOIC−8

D SUFFIX

CASE 751

XXXX

ALYW

PIN CONNECTIONS

INA

ENA 18

(Top View)

XX = Specific Device Code

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

M = Date Code

G= Pb−Free Package

(Note: Microdot may be in either location)

OUTB

VDD

OUTA

ENB

INB

GND

MSOP−8

Z SUFFIX

CASE 846AM

WDFN8

MN SUFFIX

CASE 511CD

XXXX

AYW

XX MG

NCP81071

www.onsemi.com

VDD

Ref

Logic

A Channel

Logic

B Channel

UVLO

VDD

INA

ENA

GND

INB

ENB

OUTA

OUTB

VDD

Figure 1. NCP81071 Block Diagram

NCP81071A NCP81071B

NCP81071C

VDD

Ref

Logic

A Channel

Logic

B Channel

UVLO

VDD

INA

ENA

GND

INB

ENB

OUTA

OUTB

VDD

Ref

Logic

A Channel

Logic

B Channel

UVLO

VDD

INA

ENA

GND

INB

ENB

OUTA

OUTB

VDD

Table 1. PIN DESCRIPTION

Pin No. Symbol Description

1 ENA Enable input for the driver channel A with logic compatible threshold and hysteresis. This pin is used to en-

able and disable the driver output. It is internally pulled up to VDD with a 200 kW resistor for active high op-

eration. The output of the pin when the device is disabled will be always low.

2 INA Input of driver channel A which has logic compatible threshold and hysteresis. If not used, this pin should be

connected to either VDD or GND. It should not be left unconnected.

3 GND Common ground. This ground should be connected very closely to the source of the power MOSFET.

4 INB Input of driver channel B which has logic compatible threshold and hysteresis. If not used, this pin should be

connected to either VDD or GND. It should not be left unconnected.

5 OUTB Output of driver channel B. The driver is able to provide 5 A drive current to the gate of the power MOSFET.

6 VDD Supply voltage. Use this pin to connect the input power for the driver device.

7 OUTA Output of driver channel A. The driver is able to provide 5 A drive current to the gate of the power MOSFET.

8 ENB Enable input for the driver channel B with logic compatible threshold and hysteresis. This pin is used to en-

able and disable the driver output. It is internally pulled up to VDD with a 200 kW resistor for active high op-

eration. The output of the pin when the device is disabled will be always low.

NCP81071

www.onsemi.com

TYPICAL APPLICATION CIRCUIT

INA

ENA

GND

INB

ENB

OUTA

OUTB

VDD

NCP81071

Table 2. ABSOLUTE MAXIMUM RATINGS

Value

Unit

Min Max

Supply Voltage VDD −0.3 24 V

Output Current (DC) Iout_dc 0.3 A

Reverse Current (Pulse< 1 ms) 6.0 A

Output Current (Pulse < 0.5 ms) Iout_pulse 6.0 A

Input Voltage INA, INB −6.0 VDD+0.3 V

Enable Voltage ENA, ENB −0.3 VDD+0.3

Output Voltage OUTA, OUTB −0.3 VDD+0.3 V

Output Voltage (Pulse < 0.5 ms) OUTA, OUTB −3.0 VDD+3.0 V

Junction Operation Temperature TJ−40 150 °C

Storage Temperature Tstg −65 160

Electrostatic Discharge Human body model, HBM 4000 V

Charge device model, CDM 1000

OUTA OUTB Latch−up Protection 500 mA

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be af fected.

Table 3. RECOMMENDED OPERATING CONDITIONS

Parameter Rating Unit

VDD supply Voltage 4.5 to 20 V

INA, INB input voltage −5.0 to VDD V

ENA, ENB input voltage 0 to VDD V

Junction Temperature Range −40 to +140 °C

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

Table 4. THERMAL INFORMATION

Package qJA (5C/W) qJC (5C/W)

SOIC−8 115 50

MSOP−8 EP 39 4.7

WDFN8 3x3 39 4.7

NCP81071

www.onsemi.com

Table 5. INPUT/OUTPUT TABLE

ENA ENB INA INB

NCP81071A NCP81071B NCP81071C

OUTA OUTB OUTA OUTB OUTA OUTB

H H L L H H L L H L

H H L H H L L H H H

H H H L L H H L L L

H H H H L L H H L H

L L Any Any L L L L L L

Any Any x (Note 1) x (Note 1) L L L L L L

x (Note 1) x (Note 1) L L H H L L H L

x (Note 1) x (Note 1) L H H L L H H H

x (Note 1) x (Note 1) H L L H H L L L

x (Note 1) x (Note 1) H H L L H H L H

1. Floating condition, internal resistive pull up or pull down configures output condition

PRODUCT MATRIX

NCP81071A NCP81071B NCP81071C

NCP81071

www.onsemi.com

Table 6. ELECTRICAL CHARACTERISTICS

(Typical values: VDD =12 V, 1 mF from VDD to GND, TA = TJ = −40°C to 140°C, typical at TAMB = 25°C, unless otherwise specified)

Parameter Symbol Test Conditions Min Typ Max Units

SUPPLY VOLTAGE

VDD Under Voltage Lockout (rising) VCCR VDD rising 3.5 4.0 4.5 V

VDD Under Voltage Lockout

(hysteresis) VCCH 400 mV

Operating Current (no switching) IDD INA = 0, INB = 5 V, ENA = ENB = 0

INA = 5 V, INB = 0, ENA = ENB = 0

INA = 0, INB = 5 V, ENA = ENB = 5 V

INA = 5 V, INB = 0, ENA = ENB = 5 V

1.4 3 mA

VDD Under Voltage Lockout to Output

Delay (Note 2) VDD rising 10 ms

INPUTS

High Threshold VthH Input rising from logic low 1.8 2.0 2.2 V

Low Threshold VthL Input falling from logic high 0.8 1.0 1.2 V

INA, INB Pull−Up Resistance OUTA = OUTB = Inverter Configuration 200 kW

INA, INB Pull−Down Resistance OUTA = OUTB = Buffer Configuration 200 kW

OUTPUTS

Output Resistance High ROH IOUT = −10 mA 0.8 2 W

Output Resistance Low ROL IOUT = +10 mA 0.8 2 W

Peak Source Current (Note 3) ISource OUTA/OUTB = GND

200 ns Pulse 5 A

Miller Plateau Source Current (Note 3) ISource OUTA/OUTB = 5.0 V

200 ns Pulse 4.5 A

Peak Sink Current (Note 3) ISink OUTA/OUTB = VDD

200 ns Pulse 5 A

Miller Plateau Sink Current (Note 3) ISink OUTA/OUTB = 5.0 V

200 ns Pulse 3.5 A

ENABLE

High−Level Input Voltage VIN_H Low to High Transition 1.8 2.0 2.2 V

Low−Level Input Voltage VIN_L High to Low Transition 0.8 1.0 1.2 V

ENA, ENB pull−up resistance 200 kW

Propagation Delay Time (EN to OUT)

(Notes 2, 4) td3 CLoad = 1.8 nF 16 20 29 ns

Propagation Delay Time (EN to OUT)

(Notes 2, 4) td4 CLoad = 1.8 nF 16 20 29 ns

SWITCHING CHARACTERISTICS

Propagation Delay Time Low to High,

IN Rising (IN to OUT) (Notes 2, 4) td1 CLoad = 1.8 nF 16 20 29 ns

Propagation Delay Time High to Low,

IN Falling (IN to OUT) (Notes 2, 4) td2 CLoad = 1.8 nF 16 20 29 ns

Rise Time (Note 4) trCLoad = 1.8 nF 8 15 ns

Fall Time (Note 4) tfCLoad = 1.8 nF 8 15 ns

Delay Matching between 2 Channels

(Note 5) tmINA = INB, OUTA and OUTB at 50%

Transition Point 1 4 ns

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

2. Guaranteed by design.

3. Not production tested, guaranteed by design and statistical analysis.

4. See timing diagrams in Figure 2, Figure 3, Figure 4 and Figure 5.

5. Guaranteed by characterization.

NCP81071

www.onsemi.com

td3 td4

Input

Enable

Output

2 V

1 V

90%

10%

td3 td4

Input

Enable

Output

2 V

1 V

90%

10%

Figure 2. Enable Function for

Non−inverting Input Driver Operation Figure 3. Enable Function for Inverting

Input Driver Operation

td1 td2

Input

Enable

Output

2 V

1 V

90%

10%

trtftd1 td2

Input

Enable

Output

2 V

1 V

90%

10%

Figure 4. Non−inverting Input Driver Operation Figure 5. Inverting Input Driver Operation

NCP81071

www.onsemi.com

TYPICAL CHARACTERISTICS

Figure 6. Supply Current vs. Switching

Frequency (VDD = 4.5 V) Figure 7. Supply Current vs. Switching

Frequency (VDD = 8 V)

FREQUENCY (kHz) FREQUENCY (kHz)

20001400120010008004002000

100

12501000750 20005002500

100

120

140

180

Figure 8. Supply Current vs. Switching

Frequency (VDD = 12 V) Figure 9. Supply Current vs. Switching

Frequency (VDD = 15 V)

FREQUENCY (kHz) FREQUENCY (kHz)

Figure 10. Supply Current vs. Switching

Frequency (VDD = 18 V) Figure 11. Supply Current vs. Supply Voltage

(CLOAD = 2.2 nF)

FREQUENCY (kHz) SUPPLY VOLTAGE (V)

1816141210864

100

120

SUPPLY CURRENT (mA)

600 1600 1800

80 VDD = 4.5 V

470 pF

1 nF

2.2 nF

4.7 nF

10 nF

VDD = 8.0 V

470 pF

1 nF

2.2 nF

4.7 nF

10 nF

1500 1750

160

12501000750 20005002500

120

150

180

210

270

VDD = 12 V

470 pF

1 nF

2.2 nF

4.7 nF

10 nF

1500 1750

240

12501000750 20005002500

120

150

180

210

270

VDD = 15 V

470 pF

1 nF

2.2 nF

4.7 nF

10 nF

1500 1750

240

12501000750 20005002500

120

150

180

210

270

VDD = 18 V

470 pF

1 nF

2.2 nF

4.7 nF

10 nF

1500 1750

240

CLOAD = 2.2 nF

50 kHz

2 MHz

1 MHz

500 kHz

200 kHz

100 kHz

NCP81071

www.onsemi.com

TYPICAL CHARACTERISTICS

Figure 12. Supply Current vs. Supply Voltage

(CLOAD = 4.7 nF) Figure 13. Supply Current vs. Supply Voltage

(NCP81071A)

SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)

1816141210864

120

140

160

1816141210864

0.2

0.4

0.8

1.0

1.4

1.8

2.0

Figure 14. Supply Current vs. Supply Voltage

(NCP81071B) Figure 15. Supply Current vs. Supply Voltage

(NCP81071C)

Figure 16. Rise Time vs. Temperature Figure 17. Fall Time vs. Temperature

TEMPERATURE (°C)

1201008060200−20−40

SUPPLY CURRENT (mA)

tr, RISE TIME (ns)

100

CLOAD = 4.7 nF

50 kHz

2 MHz

1 MHz

500 kHz

200 kHz

100 kHz

0.6

1.2

1.6 Input = GND

Input = VDD

SUPPLY VOLTAGE (V)

1816141210864

0.2

0.4

0.8

1.0

1.4

1.8

2.0

SUPPLY CURRENT (mA)

0.6

1.2

1.6 Input = GND

Input = VDD

SUPPLY VOLTAGE (V)

1816141210864

0.2

0.4

0.8

1.0

1.4

1.8

2.0

SUPPLY CURRENT (mA)

0.6

1.2

1.6 Input = GND

Input = VDD

40 140

VDD = 20 V

VDD = 15 V

VDD = 10 V VDD = 5 V

TEMPERATURE (°C)

1201008060200−20−40

tf, FALL TIME (ns)

40 140

VDD = 20 V

VDD = 15 V

VDD = 10 V VDD = 5 V

NCP81071

www.onsemi.com

TYPICAL CHARACTERISTICS

Figure 18. Propagation Delay td1 vs. Supply

Voltage Figure 19. Propagation Delay td2 vs. Supply

Voltage

VDD, SUPPLY VOLTAGE (V) VDD, SUPPLY VOLTAGE (V)

1816141210864

Figure 20. Fall Time tf vs. Supply Voltage Figure 21. Rise Time tr vs. Supply Voltage

VDD, SUPPLY VOLTAGE (V) VDD, SUPPLY VOLTAGE (V)

1816141210864

Figure 22. Output Behavior vs. Supply Voltage

NCP81071A (Inverting) 10 nF between Output

and GND, INA = GND, ENA = VDD

Figure 23. Output Behavior vs. Supply Voltage

NCP81071A (Inverting) 10 nF between Output

and GND, INA = GND, ENA = VDD

td1, DELAY TIME (ns)

td2, DELAY TIME (ns)

tf, FALL TIME (ns)

tr, RISE TIME (ns)

Output

VDD

Output

VDD

470 pF

1.0 nF 2.2 nF

4.7 nF

10 nF

470 pF

1.0 nF 2.2 nF

4.7 nF

10 nF

4.7 nF

2.2 nF

1.0 nF

470 pF

10 nF

4.7 nF

2.2 nF

1.0 nF

470 pF

NCP81071

www.onsemi.com

TYPICAL CHARACTERISTICS

Figure 24. Output Behavior vs. Supply Voltage

NCP81071A (Inverting) 10 nF between Output

and GND, INA = VDD, ENA = VDD

Figure 25. Output Behavior vs. Supply Voltage

NCP81071A (Inverting) 10 nF between Output

and GND, INA = VDD, ENA = VDD

Figure 26. Output Behavior vs. Supply Voltage

NCP81071B (Non−Inverting) 10 nF between

Output and GND, INA = VDD, ENA = VDD

Figure 27. Output Behavior vs. Supply Voltage

NCP81071B (Non−Inverting) 10 nF between

Output and GND, INA = VDD, ENA = VDD

Figure 28. Output Behavior vs. Supply Voltage

NCP81071B (Non−Inverting) 10 nF between

Output and GND, INA = GND, ENA = VDD

Figure 29. Output Behavior vs. Supply Voltage

NCP81071B (Non−Inverting) 10 nF between

Output and GND, INA = GND, ENA = VDD

Output

VDD

Output

VDD

Output

VDD

Output

VDD

Output

VDD

Output

VDD

NCP81071

www.onsemi.com

LAYOUT GUIDELINES

The switching performance of NCP81071 highly depends

on the design of PCB board. The following layout design

guidelines are recommended when designing boards using

these high speed drivers.

Place the driver as close as possible to the driven

MOSFET.

Place the bypass capacitor between VDD and GND as

close as possible to the driver to improve the noise filtering.

It is preferred to use low inductance components such as

chip capacitor and chip resistor. If vias are used, connect

several paralleled vias to reduce the inductance of the vias.

Minimize the turn-on/sourcing current and

turn-off/sinking current paths in order to minimize stray

inductance. Otherwise high di/dt established in these loops

with stray inductance can induce significant voltage spikes

on the output of the driver and MOSFET Gate terminal.

Keep power loops as short as possible by paralleling the

source and return traces (flux cancellation).

Keep low level signal lines away from high level power

lines with a lot of switching noise.

Place a ground plane for better noise shielding. Beside

noise shielding, ground plane is also useful for heat

dissipation.

NCP81071 DFN and MSOP package have thermal pad

for: 1) quiet GND for all the driver circuits; 2) heat sink for

the driver . This pad must be connected to a ground plane and

no switching currents from the driven MOSFET should pass

through the ground plane under the driver. To maximize the

heatsinking capability, it is recommended several ground

layers are added to connect to the ground plane and thermal

pad. A via array within the area of package can conduct the

heat from the package to the ground layers and the whole

PCB board. The number of vias and the size of ground plane

are determined by the power dissipation of NCP81071

(VDD voltage, switching frequency and load condition), t he

air flow condition and its maximum junction temperature.

ORDERING INFORMATION

Part Number Output Configuration Temperature Range (5C) Package Type Shipping†

NCP81071ADR2G dual inverting

−40 to +140

SOIC−8

(Pb−Free) 2500 / Tape & Reel

NCP81071BDR2G dual non inverting

NCP81071CDR2G One inverting

one non inverting

NCP81071AZR2G dual inverting

MSOP8 EP

(Pb−Free) 3000 / Tape & Reel

NCP81071BZR2G dual non inverting

NCP81071CZR2G One inverting

one non inverting

NCP81071AMNTXG dual inverting

WDFN8

(Pb−Free) 3000 / Tape & Reel

NCP81071BMNTXG dual non inverting

NCP81071CMNTXG One inverting

one non inverting

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

NCP81071

www.onsemi.com

PACKAGE DIMENSIONS

SOIC−8 NB

CASE 751−07

ISSUE AK

SEATING

PLANE

X 45_

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW

STANDARD IS 751−07.

0.10 (0.004)

DIM

AMIN MAX MIN MAX

INCHES

4.80 5.00 0.189 0.197

MILLIMETERS

B3.80 4.00 0.150 0.157

C1.35 1.75 0.053 0.069

D0.33 0.51 0.013 0.020

G1.27 BSC 0.050 BSC

H0.10 0.25 0.004 0.010

J0.19 0.25 0.007 0.010

K0.40 1.27 0.016 0.050

M0 8 0 8

N0.25 0.50 0.010 0.020

S5.80 6.20 0.228 0.244

−X−

−Y−

0.25 (0.010)

−Z−

0.25 (0.010) ZSXS

____

1.52

0.060

7.0

0.275

0.6

0.024 1.270

0.050

4.0

0.155

ǒmm

inchesǓ

SCALE 6:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

NCP81071

www.onsemi.com

PACKAGE DIMENSIONS

MSOP8 EP, 3x3

CASE 846AM

ISSUE O

NOTES:

1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSIONS: MILLIMETERS.

3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.

ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.10 MM IN

EXCESS OF MAXIMUM MATERIAL CONDITION.

4. DIMENSION D DOES NOT INCLUDE MOLD FLASH,

PROTRUSIONS, OR GATE BURRS. MOLD FLASH,

PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15

MM PER SIDE. DIMENSION E DOES NOT INCLUDE INTER-

LEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR

PROTRUSION SHALL NOT EXCEED 0.25 MM PER SIDE.

DIMENSIONS D AND E ARE DETERMINED AT DATUM F.

5. DATUMS A AND B TO BE DETERMINED AT DATUM F.

6. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE

SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE

BODY.

DIM MIN MAX

MILLIMETERS

A−−− 1.10

A1 0.05 0.15

b0.25 0.40

c0.13 0.23

D2.90 3.10

D2 1.78 REF

E2 1.42 REF

e0.65 BSC

L0.40 0.70

L2 0.254 BSC

E4.75 5.05

E1 2.90 3.10

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

RECOMMENDED

ÉÉ

PIN ONE

SEATING

PLANE

TOP VIEW

SIDE VIEW

BOTTOM VIEW

DETAIL A

END VIEW

8X b

INDICATOR

0.08 BC S S

C0.10

DET AIL A

0.85

5.35

0.65

PITCH

8X 0.42

DIMENSIONS: MILLIMETERS

NCP81071

www.onsemi.com

PACKAGE DIMENSIONS

WDFN8 3x3, 0.65P

CASE 511CD

ISSUE O

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.15 AND 0.30 MM FROM TERMINAL TIP.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

ÇÇÇÇ

C0.10

PIN ONE

REFERENCE

TOP VIEW

SIDE VIEW

BOTTOM VIEW

C0.10

C0.05

A1 SEATING

PLANE

NOTE 3

0.10 C

0.05 C

ABB

DIM MIN MAX

MILLIMETERS

A0.70 0.80

A1 0.00 0.05

b0.25 0.35

D3.00 BSC

D2 2.05 2.25

E3.00 BSC

E2 1.10 1.30

e0.65 BSC

L0.30 0.50

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

0.65

PITCH

1.36 3.30

DIMENSIONS: MILLIMETERS

0.63

NOTE 4

0.40

DET AIL A

A3 0.20 REF

DETAIL B

DETAIL A

ALTERNATE

CONSTRUCTIONS

ÉÉÉ

ÇÇÇ

ÉÉÉ

DETAIL B

MOLD CMPDEXPOSED Cu

ALTERNATE

CONSTRUCTIONS L1 0.00 0.15

OUTLINE

PACKAGE

RECOMMENDED

2.31

e/2

0.20 −−−

ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.

SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed

at www.onsemi.com/site/pdf/Patent− Marking. pdf. S CILLC reserves the r ight to make changes w ithout furt her not ice to a ny products herein. S CILLC makes n o warranty, representation

or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and

specifically disclaims any and all l iabilit y, including without limitation special, c onsequent ial o r i ncident al d amages. “Typical” parameters w hich m ay b e p r ovided i n SCILLC data sheets

and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each

customer application b y c ust omer’s technical e xperts. SCILLC does not c onvey a ny license under its p atent rights nor t he r ights o f o thers. SCILLC products ar e n ot d esigned, i ntended,

or authorized for use as c omponent s i n s yst ems i nt ended f or s urgic al i m plant i nt o the body , or other applications intended to support or s ust ain life, or for any other application in which

the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or

unauthorized application, Buyer shall indemnify and hold SCILLC an d it s officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and

expenses, and r easonable a ttorney f ees a rising o ut of, directly o r i ndirectly, any c laim o f p ersonal i njury o r d eath a ssociated w ith s uch u nintended o r unauthorized use, e ven if such c laim

alleges that SCILLC was negligent regarding the d esign or manufacture of the p art. SCILLC is a n E qual O pportunity/Af firmative Act ion Employer. T his literature is subject to all a pplicable

UBLICATION ORDERING INFORMATION

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5817−1050

NCP81071/D

LITERATURE FULFILLMENT:

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

For additional information, please contact your loc

Sales Representative