STANDARD
MICROCIRCUIT DRAWING
SIZE
A
8003
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
F SHEET 26
DSCC FORM 2234
APR 97
6.7 Pin descriptions - Continued.
Name Description
BUSRQ Input, active Low. This line must be driven Low to request the bus from the CPU. It is
(Bus Request) sampled for being active at the beginning of each machine cycle. When it is released, it
is synchronized with the next rising clock edge.
DS Output, active Low, three-state. This line times the data in and out of the CPU.
(Data Strobe)
MREQ Output, active Low, three-state. A low on this line indicates that the address/data bus
(Memory Request) holds a memory address.
MI, MO Input and output, active Low. These two lines form a resource-request daisy chain that
(Multi-Micro In, allows one CPU in a multi-microprocessor system to access a shared resource. MI is
Multi-Micro Out) sampled on the rising edge of T3 of the last machine cycle of any instruction and
Internally latched.
NMI Edge triggered, input, active Low. A high-to-low transition on NMI request a
(Non-Maskable Interrupt) non-maskable interrupt. The NMI interrupt has the highest priority of the three types of
interrupts. The internal NMI latch is sampled on the rising edge of T3 of the last machine
cycle of any instruction.
NVI Input, active Low. A low on this line requests a non-vectored interrupt. It is sampled on
(Non-Vectored Interrupt) the rising edge of T3 of the last machine cycle of any instruction.
CLK Input. CLK is a 5 V single-phase time-base input.
(System Clock)
RESET Input, active Low. A low on this line resets the CPU. RESET must be active for at least
(Reset) five clock cycles.
R/W Output, Low = Write, three-state. R/W indicates that the CPU is reading from or writing
(Read/Write) to memory or I/O.
ST0 – ST3 Outputs, active High, three-state. These lines specify the CPU status.
(Status)
STOP Input, active Low. This input can be used to single-step instruction execution. It is
(Stop) sampled on the last falling clock edge preceding any first instruction fetch cycle.
VI Input, active Low. A low on this line requests a vectored interrupt. It is sampled on the
(Vectored Interrupt) rising edge of T3 of the last machine cycle of any instruction.
WAIT Input, active Low. This line indicates to the CPU that the memory or I/O device is not ready
(Wait) for data transfer. It is sampled on the falling edge of T2 and any subsequent WAIT states.
B/W Output, Low = word, three-state. This signal defines the type of memory reference on the
(Byte/Word) 16-bit address/data bus.
N/S Output, Low = system mode, three-state. N/S indicates the CPU is in the normal or
(Normal/System Mode) system mode.
SN0 – SN6 Outputs, active High, three-state. These lines provide the 7-bit segment number used to
(Segment Number) address one of 128 segments by the memory management unit. Outputs by the 01, 03,
and 04 parts only. SN6 = MSB.
SEGT Input, active Low. The memory management unit interrupts the CPU with a low on this
(Segment Trap) line when the MMU detects a segmentation trap. Input on the 01, 03, and 04 parts only.
It is sampled on the rising edge of T3 of the last machine cycle of any instruction.