REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Pages 1, 2, 3, 4, 14, 15, 16, editorial changes. Pages 5, 6, 7, 8, symbol corrections. Page 18, added vendor. 81-12-09 M. A. Frye B Add device type 03. Type 02 inactive for new design: Use MIL-M-38510/52002 for case Q. Type 01 and new type 03 are still active. 83-04-06 M. A. Frye C Add device types 04 and 05. 84-10-31 M. A. Frye D Case temperature to +125C. Add LCC package, electrical test improvements. 85-11-12 M. A. Frye E Change to military drawing format. Add device type 06, changes to 1.4, add vendor CAGE number 66958, delete vendor CAGE number 34335, changes to table I, changes to figures 1, 2, and 3. Editorial changes throughout. Change Code Ident. No. to 67268. 87-12-17 M. A. Frye F Update boilerplate to MIL-PRF-38535 requirements. Correct drawing title to indicate device function. - CFS 03-06-11 Thomas M. Hess G Correct marking requirements in 3.5. Update boilerplate in accordance with MIL-PRF-38535 requirements. - PHN. 05-03-23 Thomas M. Hess THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED. REV SHEET REV F F F F F F F F F F F F SHEET 15 16 17 18 19 20 21 22 23 24 25 26 REV STATUS REV G F G G F F F F F F F F F F OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Ray Monnin STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http://www.dscc.dla.mil CHECKED BY Charles Reusing APPROVED BY THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE Michael. A. Frye DRAWING APPROVAL DATE MICROCIRCUIT, DIGITAL, 6-BIT N-CHANNEL SINGLE-CHIP MICROPROCESSOR, MONOLITHIC SILICON 80-07-21 AMSC N/A REVISION LEVEL G DSCC FORM 2233 APR 97 SIZE CAGE CODE A 67268 SHEET 1 OF 80003 26 5962-E240-05 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 80003 01 X X Drawing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Frequency Z8001 Z8002 Z8001A Z8001B Z8002B Z8002A 4.0 MHz 4.0 MHz 6.0 MHz 10.0 MHz 10.0 MHz 6.0 MHz 01 02 03 04 05 06 Circuit function 16-Bit N-channel single-chip microprocessor 16-Bit N-channel single-chip microprocessor 16-Bit N-channel single-chip microprocessor 16-Bit N-channel single-chip microprocessor 16-Bit N-channel single-chip microprocessor 16-Bit N-channel single-chip microprocessor 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Q U X Y Z Descriptive designator GDIP1-T40 or CDIP2-T40 CQCC1-N52 See figure 1 CQCC1-N44 CQCC1-N68 Terminals Package style 40 52 48 44 68 Dual-in-line Square leadless chip carrier Dual-in-line Square leadless chip carrier Square leadless chip carrier 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Supply voltage range with respect to ground (VCC) .................................................... -0.3 V dc to +7.0 V dc Storage temperature range ........................................................................................ -65C to +150C Maximum power dissipation (PD) (per device) ............................................................ 2.2 W Lead temperature (soldering, 5 seconds)................................................................... +270C Maximum junction temperature (TJ)............................................................................ +150C Thermal resistance, junction-to-case (JC): Case X .................................................................................................................... 14C/W Cases Q, U, Y, Z ..................................................................................................... See MIL-STD-1835 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 8003 A REVISION LEVEL F SHEET 2 1.4 Recommended operating conditions. Supply voltage range (VCC)......................................................................................... +4.5 V dc to +5.5 V dc Minimum high level input voltage (VIH): Logic inputs............................................................................................................. +2.2 V dc to VCC + 0.3 V dc Clock input .............................................................................................................. VCC - 0.4 V dc to VCC + 0.3 V dc RESET (NMI) .......................................................................................................... 2.4 V dc to VCC + 0.3 V dc Maximum low level input voltage (VIL): Logic inputs............................................................................................................. -0.3 V dc to +0.8 V dc Clock input .............................................................................................................. -0.3 V dc to +0.45 V dc Frequency of operation: 01, 02 ...................................................................................................................... 0.5 MHz to 4.0 MHz 03, 06 ...................................................................................................................... 0.5 MHz to 6.0 MHz 04, 05 ...................................................................................................................... 0.5 MHz to 10.0 MHz Case operating temperature range (TC) ..................................................................... -55C to +125C Clock rise time (tr): 01, 02 ...................................................................................................................... 20 ns maximum 03, 06 ...................................................................................................................... 15 ns maximum 04, 05 ...................................................................................................................... 10 ns maximum Clock fall time (tf): 01, 02 ...................................................................................................................... 20 ns maximum 03, 06 ...................................................................................................................... 10 ns maximum 04, 05 ...................................................................................................................... 15 ns maximum 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 MIL-STD-1835 - Test Method Standard Microcircuits. Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 MIL-HDBK-780 - List of Standard Microcircuit Drawings. Standard Microcircuit Drawings. (Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or http://assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 8003 A REVISION LEVEL G SHEET 3 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for nonJAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MILPRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A "Q" or "QML" certification mark in accordance with MILPRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein and on figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Logic functions. The logic functions shall be as specified on figure 3. 3.2.4 Timing waveforms. The timing waveforms shall be as specified on figure 4. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked. 3.5.1 Certification/compliance mark. A compliance indicator "C" shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator "C" shall be replaced with a "Q" or "QML" certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturer's product meets the requirements of MIL-PRF38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCC's agent, and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 8003 A REVISION LEVEL G SHEET 4 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC +125C +4.5 V VCC +5.5 V unless otherwise specified Group A subgroups Device type Driven by external clock generator. 1, 2, 3 Limits Unit Min Max All -0.3 1/ 0.45 V Clock input low voltage VIL1 Clock input high voltage VIH1 1, 2, 3 All VCC - 0.4 VCC + 0.3 1/ V Input low voltage VIL2 1, 2, 3 All -0.3 1/ 0.8 V Input high voltage VIH2 1, 2, 3 All 2.4 VCC + 0.3 1/ V Reset input high voltage (NMI) VIH3 1, 2, 3 All 2.4 VCC + 0.3 1/ V High level output voltage all outputs VOH IOH = -250 A VCC = 4.5 V 1, 2, 3 All 2.4 Low level output voltage all outputs VOL IOL = +2.0 mA VCC = 4.5 V 1, 2, 3 All High-impedance (off-state) output current (High) (In Float) IZH VIN = 2.4 V VCC = 5.5 V 1, 2, 3 All High-impedance (off-state) output current (Low) (In Float) IZL VIN = 0.4 V VCC = 5.5 V 1, 2, 3 High level input current (input and bi-directional) IIH VIN = 2.4 V VCC = 5.5 V Low level input current (input and bi-directional) IIL Low level input current (SEGT) IILS Supply current ICC V 0.4 V -10 +10 A All -10 +10 A 1, 2, 3 All -10 +10 A VIN = 0.4 V VCC = 5.5 V 1, 2, 3 All -10 +10 A 0.4 V VIN 2.4 V 1, 2, 3 01, 03, 04 +200 A VCC = 5.5 V 1, 2, 3 All 400 mA See 4.3.1c 7, 8 All 4.5 V VCC 5.5 V Functional tests See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 8003 A REVISION LEVEL F SHEET 5 TABLE I. Electrical performance characteristics - Continued. Test Symbol Clock pulse tcyc Conditions -55C TC +125C +4.5 V VCC +5.5 V unless otherwise specified See figure 4. See Reference No. 1 Group A subgroups 9, 10, 11 2/ CL = 50 pF to 100 pF 10%, all outputs Clock pulse width (Low) tPWL1 See figure 4. See Reference No. 2 9, 10, 11 2/ CL = 50 pF to 100 pF 10%, all outputs Clock pulse width (High) tPWH1 Clock to segment number valid TdC(SNv) 3/ 4/ See figure 4. See Reference No. 3 9, 10, 11 2/ CL = 50 pF to 100 pF 10%, all outputs See figure 4. See Reference No. 6 9, 10, 11 2/ CL = 50 pF to 100 pF 10%, all outputs Clock to segment number not valid TdC(SNn) See figure 4. 4/ See Reference No. 7 Clock to bus float TdC(Bz) 1/ 9, 10, 11 2/ CL = 50 pF to 100 pF 10%, all outputs See figure 4. See Reference No. 8 9, 10, 11 2/ CL = 50 pF to 100 pF 10%, all outputs Clock to address valid TdC(A) Clock to address float TdC(Az) 1/ See figure 4. See Reference No. 9 9, 10, 11 2/ CL = 50 pF to 100 pF 10%, all outputs See figure 4. See Reference No. 10 9, 10, 11 2/ CL = 50 pF to 100 pF 10%, all outputs Address valid to data in required valid TdA(DR) Data to CLK setup time TsDR(C) See figure 4. See Reference No. 11 9, 10, 11 5/ 2/ CL = 50 pF to 100 pF 10%, all outputs See figure 4. See Reference No. 12 2/ Unit Min Max 01, 02 250 2000 03, 06 165 2000 04, 05 100 2000 01, 02 105 03, 06 70 04, 05 40 01, 02 105 03, 06 70 04, 05 40 ns 130 03 110 04 90 01 20 03 10 04 0 01, 02 ns ns 65 ns 03, 06 55 04, 05 50 01, 02 100 03, 06 75 04, 05 65 01, 02 65 ns ns 03, 06 55 04, 05 50 01, 02 475 03, 06 305 01, 02 ns ns 01 04, 05 9, 10, 11 CL = 50 pF to 100 pF 10%, all outputs Limits Device type ns 180 30 03, 06 20 04, 05 10 ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 8003 A REVISION LEVEL F SHEET 6 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TC +125C +4.5 V VCC +5.5 V unless otherwise specified Group A subgroups Device type 9, 10, 11 5/ 01, 02 Limits Min DS to address active TdDS(A) See figure 4. See Reference No. 13 2/ CL = 50 pF to 100 pF 10%, all outputs Clock to data out valid TdC(DW) See figure 4. See Reference No. 14 9, 10, 11 2/ CL = 50 pF to 100 pF 10%, all outputs Data in to DS hold time ThDR(DS) See figure 4. See Reference No. 15 2/ CL = 50 pF to 100 pF 10%, all outputs Data out valid to DS delay TdDW(DS) See figure 4. See Reference No. 16 9, 10, 11 5/ 2/ CL = 50 pF to 100 pF 10%, all outputs Address valid to TdA(MR) MREQ delay See figure 4. See Reference No. 17 9, 10, 11 5/ 2/ CL = 50 pF to 100 pF 10%, all outputs Clock to MREQ delay TdC(MR) MREQ width (High) TwMRh See figure 4. See Reference No. 18 9, 10, 11 2/ CL = 50 pF to 100 pF 10%, all outputs See figure 4. See Reference No. 19 2/ CL = 50 pF to 100 pF 10%, all outputs MREQ to address not active TdMR(A) 1/ See figure 4. See Reference No. 20 9, 10, 11 5/ 2/ CL = 50 pF to 100 pF 10%, all outputs Data out valid to TdDW DS (Write Delay) (DSW) See figure 4. See Reference No. 21 9, 10, 11 5/ 2/ CL = 50 pF to 100 pF 10%, all outputs MREQ to data in required valid TdMR(DR) See figure 4. See Reference No. 22 9, 10, 11 5/ 2/ CL = 50 pF to 100 pF 10%, all outputs 03, 06 45 04, 05 20 ns 01, 02 100 03, 06 75 ns 60 01, 02 0 03, 06 0 04, 05 0 01, 02 295 03, 06 195 04, 05 110 01, 02 55 03, 06 35 04, 05 20 ns ns ns 01, 02 80 03, 06 70 04, 05 9, 10, 11 5/ Max 80 04, 05 9, 10, 11 Unit ns 50 01, 02 210 03, 06 135 04, 05 80 01, 02 70 03, 06 35 04, 05 15 01, 02 55 03, 06 35 04, 05 15 ns ns ns 01, 02 370 03, 06 230 04, 05 140 ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 8003 A REVISION LEVEL F SHEET 7 TABLE I. Electrical performance characteristics - Continued. Test Symbol Clock to MREQ delay TdC(MR) Conditions -55C TC +125C +4.5 V VCC +5.5 V unless otherwise specified Group A subgroups Device type 9, 10, 11 01, 02 Limits Min See figure 4. See Reference No. 23 2/ CL = 50 pF to 100 pF 10%, all outputs Clock to AS delay TdC(ASf) See figure 4. See Reference No. 24 9, 10, 11 2/ CL = 50 pF to 100 pF 10%, all outputs Address valid to TdA(AS) AS delay See figure 4. See Reference No. 25 2/ CL = 50 pF to 100 pF 10%, all outputs Clock to AS delay TdC(ASr) AS to data in required valid TdAS(DR) See figure 4. See Reference No. 27 See figure 4. See Reference No. 26 9, 10, 11 2/ CL = 50 pF to 100 pF 10%, all outputs 9, 10, 11 5/ 2/ CL = 50 pF to 100 pF 10%, all outputs DS to AS delay TdDS(AS) AS width (Low) TwAS See figure 4. See Reference No. 28 9, 10, 11 5/ 2/ CL = 50 pF to 100 pF 10%, all outputs See figure 4. See Reference No. 29 9, 10, 11 5/ 2/ CL = 50 pF to 100 pF 10%, all outputs AS to address not active delay TdAS(A) 1/ See figure 4. See Reference No. 30 9, 10, 11 5/ 2/ CL = 50 pF to 100 pF 10%, all outputs Address float to DS TdAz(DSR) See figure 4. 1/ See Reference No. 31 (Read) delay 9, 10, 11 2/ CL = 50 pF to 100 pF 10%, all outputs AS to DS (Read) delay TdAS(DSR) See figure 4. See Reference No. 32 9, 10, 11 5/ 2/ CL = 50 pF to 100 pF 10%, all outputs Max 80 03, 06 60 04, 05 50 01, 02 80 03, 06 60 04, 05 9, 10, 11 5/ Unit 01, 02 ns ns 45 55 03, 06 35 04, 05 20 ns 01, 02 90 03, 06 80 ns 04, 05 45 01, 02 360 03, 06 220 04, 05 140 01, 02 70 03, 06 35 04, 05 15 01, 02 85 03, 06 55 04, 05 30 01, 02 70 03, 06 45 04, 05 15 01, 02 0 03, 06 0 04, 05 0 01, 02 80 03, 06 55 04, 05 30 ns ns ns ns ns ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 8003 A REVISION LEVEL F SHEET 8 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TC +125C +4.5 V VCC +5.5 V unless otherwise specified Group A subgroups Device type 9, 10, 11 5/ 01, 02 205 Limits Min DS (Read) to data in required valid Clock to DS delay TdDSR(DR) See figure 4. See Reference No. 33 2/ CL = 50 pF to 100 pF 10%, all outputs TdC(DSr) See figure 4. See Reference No. 34 9, 10, 11 2/ CL = 50 pF to 100 pF 10%, all outputs DS to data out not valid TdDS(DW) See figure 4. 1/ See Reference No. 35 2/ CL = 50 pF to 100 pF 10%, all outputs Address valid to DS (Read) delay Clock to DS (Read) delay TdA(DSR) See figure 4. See Reference No. 36 9, 10, 11 5/ 2/ CL = 50 pF to 100 pF 10%, all outputs TdC(DSR) See figure 4. See Reference No. 37 9, 10, 11 2/ CL = 50 pF to 100 pF 10%, all outputs DS (Read) width (Low) TwDSR See figure 4. See Reference No. 38 Clock to DS TdC(DSW) See figure 4. See Reference No. 39 9, 10, 11 5/ 2/ CL = 50 pF to 100 pF 10%, all outputs (Write) delay 9, 10, 11 2/ CL = 50 pF to 100 pF 10%, all outputs DS (Write) width (Low) TwDSW DS (Input) to data in required valid TdDSI(DR) See figure 4. See Reference No. 40 9, 10, 11 5/ 2/ CL = 50 pF to 100 pF 10%, all outputs Clock to DS See figure 4. See Reference No. 41 9, 10, 11 5/ 2/ CL = 50 pF to 100 pF 10%, all outputs TdC(DSf) (IO) delay See figure 4. See Reference No. 42 9, 10, 11 2/ CL = 50 pF to 100 pF 10%, all outputs Max 03, 06 130 04, 05 70 01, 02 70 03, 06 65 04, 05 9, 10, 11 5/ Unit 01, 02 ns 50 75 03, 06 45 04, 05 25 01, 02 180 03, 06 110 04, 05 65 01, 02 ns ns 120 03, 06 85 04, 05 65 01, 02 275 03, 06 185 04, 05 110 01, 02 ns ns 95 03, 06 80 04, 05 65 01, 02 185 03, 06 110 04, 05 75 01, 02 ns ns ns 330 03, 06 210 04, 05 120 01, 02 120 03, 06 90 04, 05 70 ns ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 8003 A REVISION LEVEL F SHEET 9 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TC +125C +4.5 V VCC +5.5 V unless otherwise specified Group A subgroups Device type 9, 10, 11 5/ 01, 02 Limits Min DS (I/O) width (Low) TwDS See figure 4. See Reference No. 43 2/ CL = 50 pF to 100 pF 10%, all outputs AS to DS (Acknowledge) delay Clock to DS (Acknowledge) delay TdAS(DSA) See figure 4. See Reference No. 44 9, 10, 11 5/ 2/ CL = 50 pF to 100 pF 10%, all outputs TdC(DSA) See figure 4. See Reference No. 45 9, 10, 11 2/ CL = 50 pF to 100 pF 10%, all outputs DS (Acknowledge) TdDSA(DR) See figure 4. See Reference No. 46 2/ to data in required delay CL = 50 pF to 100 pF 10%, all outputs 9, 10, 11 5/ Clock to status valid delay 9, 10, 11 TdC(S) See figure 4. See Reference No. 47 2/ CL = 50 pF to 100 pF 10%, all outputs Status valid to TdS(AS) AS delay See figure 4. See Reference No. 48 9, 10, 11 5/ 2/ CL = 50 pF to 100 pF 10%, all outputs RESET to clock set-up time TsR(C) See figure 4. See Reference No. 49 9, 10, 11 2/ CL = 50 pF to 100 pF 10%, all outputs RESET to clock hold time ThR(C) NMI width (Low) TwNMI See figure 4. See Reference No. 50 9, 10, 11 2/ CL = 50 pF to 100 pF 10%, all outputs See figure 4. See Reference No. 51 9, 10, 11 2/ CL = 50 pF to 100 pF 10%, all outputs NMI to clock set-up time TsNMI(C) See figure 4. See Reference No. 52 9, 10, 11 2/ CL = 50 pF to 100 pF 10%, all outputs Unit Max ns 410 03, 06 255 04, 05 160 01, 02 1065 03, 06 690 04, 05 410 01, 02 ns 120 03, 06 85 04, 05 70 01, 02 455 03, 06 295 04, 05 165 01, 02 110 03, 06 85 04, 05 65 01, 02 50 03, 06 30 04, 05 10 01, 02 180 03, 06 70 04, 05 50 01, 02 0 03, 06 0 04, 05 0 01, 02 100 03, 06 70 04, 05 50 01, 02 140 03, 06 70 04, 05 50 ns ns ns ns ns ns ns ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 8003 A REVISION LEVEL F SHEET 10 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TC +125C +4.5 V VCC +5.5 V unless otherwise specified Group A subgroups Device type 9, 10, 11 01, 02 Limits Min VI, NVI to clock set-up time TsVI(C) See figure 4. See Reference No. 53 2/ CL = 50 pF to 100 pF 10%, all outputs VI, NVI to clock hold time ThVI(C) See figure 4. See Reference No. 54 9, 10, 11 2/ CL = 50 pF to 100 pF 10%, all outputs SEGT to clock set-up time TsSGT(C) 4/ See figure 4. See Reference No. 55 9, 10, 11 2/ CL = 50 pF to 100 pF 10%, all outputs SEGT to clock hold time ThSGT(C) 4/ MI to clock set-up time TsMI(C) See figure 4. See Reference No. 56 9, 10, 11 2/ CL = 50 pF to 100 pF 10%, all outputs See figure 4. See Reference No. 57 9, 10, 11 2/ CL = 50 pF to 100 pF 10%, all outputs MI to clock hold time ThMI(C) Clock to MO delay time TdC(MO) See figure 4. See Reference No. 58 9, 10, 11 2/ CL = 50 pF to 100 pF 10%, all outputs See figure 4. See Reference No. 59 9, 10, 11 2/ CL = 50 pF to 100 pF 10%, all outputs STOP to clock set-up time TsSTP(C) STOP to clock hold time ThSTP(C) See figure 4. See Reference No. 60 9, 10, 11 2/ CL = 50 pF to 100 pF 10%, all outputs See figure 4. See Reference No. 61 9, 10, 11 2/ CL = 50 pF to 100 pF 10%, all outputs Unit Max 110 03, 06 50 04, 05 40 01, 02 20 03, 06 20 04, 05 10 01 70 03 55 04 40 01 0 03 0 04 0 01, 02 180 03, 06 140 04, 05 80 01, 02 0 03, 06 0 04, 05 0 01, 02 ns ns ns ns ns ns 120 03, 06 85 04, 05 80 01, 02 140 03, 06 100 04, 05 50 01, 02 0 03, 06 0 04, 05 0 ns ns ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 8003 A REVISION LEVEL F SHEET 11 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TC +125C +4.5 V VCC +5.5 V unless otherwise specified Group A subgroups Device type 9, 10, 11 01, 02 Limits Min WAIT to clock set-up time TsW(C) See figure 4. See Reference No. 62 2/ CL = 50 pF to 100 pF 10%, all outputs WAIT to clock hold time ThW(C) See figure 4. See Reference No. 63 9, 10, 11 2/ CL = 50 pF to 100 pF 10%, all outputs BUSRQ to clock set-up time TsBRQ(C) See figure 4. See Reference No. 64 9, 10, 11 2/ CL = 50 pF to 100 pF 10%, all outputs BUSRQ to clock hold time ThBRQ(C) See figure 4. See Reference No. 65 Clock to TdC(BAKr) See figure 4. See Reference No. 66 9, 10, 11 2/ CL = 50 pF to 100 pF 10%, all outputs BUSAK delay 9, 10, 11 2/ CL = 50 pF to 100 pF 10%, all outputs Clock to BUSAK delay TdC(BAKf) See figure 4. See Reference No. 67 9, 10, 11 2/ CL = 50 pF to 100 pF 10%, all outputs Address valid width TwA See figure 4. See Reference No. 68 2/ CL = 50 pF to 100 pF 10%, all outputs DS to status not valid TdDS(s) 1/ See figure 4. See Reference No. 69 9, 10, 11 5/ 2/ CL = 50 pF to 100 pF 10%, all outputs Max 50 03, 06 30 04, 05 20 01, 02 10 03, 06 10 04, 05 5 01, 02 90 03, 06 80 04, 05 60 01, 02 10 03, 06 10 04, 05 5 01, 02 ns ns ns ns 100 03, 06 75 04, 05 65 01, 02 100 03, 06 75 04, 05 9, 10, 11 5/ Unit 01, 02 ns ns 65 150 03, 06 95 04, 05 50 01, 02 80 03, 06 55 04, 05 30 ns ns See footnotes on next sheet. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 8003 A REVISION LEVEL F SHEET 12 TABLE I. Electrical performance characteristics - Continued. 1/ 2/ 3/ 4/ 5/ Guaranteed, if not tested. The waveform reference number refers to the position where the parameter appears on figure 4. For waveform reference number 6, CL = 50 pF 10%. These parameters are for 01, 03, and 04 devices only. These waveform reference number parameters are clock dependent. The limits provided are at FMAX. To determine the limits at other frequencies use the following equations: Waveform reference number Device types 01 and 02 Device types 04 and 05 11 2 tcyc + tPWH1 - 130 ns 2 tcyc + tPWH1 - 95 ns 2 tcyc + tPWH1 - 60 ns 13 tPWL1 - 25 ns tPWL1 - 25 ns tPWL1 - 20 ns 16 tcyc + tPWH1 - 60 ns tcyc + tPWH1 - 40 ns tcyc + tPWH1 - 30 ns 17 tPWH1 - 50 ns tPWH1 - 35 ns tPWH1 - 20 ns 19 tcyc - 40 ns tcyc - 30 ns tcyc - 20 ns 20 tPWL1 - 35 ns tPWL1 - 35 ns tPWL1 - 20 ns 21 tPWH1 - 50 ns tPWH1 - 35 ns tPWH1 - 25 ns 22 2 tcyc - 130 ns 2 tcyc - 100 ns 2 tcyc - 60 ns 25 tPWH1 - 50 ns tPWH1 - 35 ns tPWH1 - 20 ns 27 2 tcyc - 140 ns 2 tcyc - 110 ns 2 tcyc - 60 ns 28 tPWL1 - 35 ns tPWL1 - 35 ns tPWL1 - 25 ns 29 tPWH1 - 20 ns tPWH1 - 15 ns tPWH1 - 10 ns 30 tPWL1 - 35 ns tPWL1 - 25 ns tPWL1 - 20 ns 32 tPWL1 - 25 ns tPWL1 - 15 ns tPWL1 - 10 ns 33 tcyc + tPWH1 - 150 ns tcyc + tPWH1 - 105 ns tcyc + tPWH1 - 70 ns 35 tPWL1 - 30 ns tPWL1 - 25 ns tPWL1 - 15 ns 36 tcyc - 70 ns tcyc - 55 ns tcyc - 35 ns 38 tcyc + tPWH1 - 80 ns tcyc + tPWH1 - 50 ns tcyc + tPWH1 - 30 ns 40 tcyc - 65 ns tcyc - 55 ns tcyc - 25 ns 41 2 tcyc - 170 ns 2 tcyc - 120 ns 2 tcyc - 80 ns 43 2 tcyc - 90 ns 2 tcyc - 75 ns 2 tcyc - 40 ns 44 4 tcyc + tPWL1 - 40 ns 4 tcyc + tPWL1 - 40 ns 4 tcyc + tPWL1 - 30 ns 46 2 tcyc + tPWH1 - 150 ns 2 tcyc + tPWH1 - 105 ns 2 tcyc + tPWH1 - 75 ns 48 tPWH1 - 55 ns tPWH1 - 40 ns tPWH1 - 30 ns 68 tcyc - 90 ns tcyc - 70 ns tcyc - 50 ns 69 tPWL1 - 25 ns tPWL1 - 15 ns tPWL1 - 10 ns STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 Device types 03 and 06 SIZE 8003 A REVISION LEVEL F SHEET 13 Case Outline X Device types 01, 03, and 04. FIGURE 1. Case outlines. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 8003 A REVISION LEVEL F SHEET 14 Case Outline X Device types 01, 03, and 04. Inches Symbol Min Max Min Max A --- .225 --- 5.72 b .014 .023 0.36 0.58 7 b1 .030 .070 0.76 1.78 2, 7 c .008 .015 0.20 0.38 7 D --- 2.480 --- 62.99 E .510 .620 12.95 15.75 E1 .520 .620 13.21 15.75 e Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. Millimeters .100 BSC 2.54 BSC Notes 6 4, 8 L .120 .200 3.05 5.08 L1 .150 --- 3.81 --- Q .020 .060 0.51 1.52 3 S --- .098 --- 2.40 5 S1 .005 --- 0.13 --- 5 S2 .005 --- 0.13 --- 9 Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. The minimum limit for dimension b1 may be .020 (0.51 mm) for leads number 1, 24, 25, and 48 only. Dimension Q shall be measured from the seating plane to the base plane. The basic pin spacing is .100 (2.54 mm) between centerlines. Each pin centerline shall be located within .010 (0.25 mm) of its exact longitudinal position relative to pins 1 and 48. Applies to all four corners (leads number 1, 24, 25, and 48) (see MIL-STD-1835). Lead center when is 0. E1 shall be measured at the centerline of the leads. All leads - increase maximum limit by .003 (0.08 mm) measured at the center of the flat, when lead finish A is applied. Forty-six spaces. The top of the lead shall not exceed above the brazed pad top surface. FIGURE 1. Case outlines - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 8003 A REVISION LEVEL F SHEET 15 Case outlines X and Q Device types: 01, 03, and 04 Terminal number Terminal symbol Terminal number Terminal symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 AD0 AD9 AD10 AD11 AD12 AD13 STOP MI AD15 AD14 VCC VI NVI SEGT NMI RESET MO MREQ DS ST3 ST2 ST1 ST0 SN3 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 SN1 SN0 BUSRQ WAIT BUSAK R/W N/S B/W NC AS CLOCK GND SN2 AD1 AD2 AD3 AD5 SN4 AD4 AD6 AD7 SN5 SN6 AD8 Device types: 02 and 05 Terminal number Terminal symbol Terminal number Terminal symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 AD9 AD10 AD11 AD12 AD13 STOP MI AD15 AD14 VCC VI NVI NMI RESET MO MREQ DS ST3 ST2 ST1 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ST0 BUSRQ WAIT BUSAK R/W N/S B/W NC AS CLOCK GND AD1 AD2 AD3 AD5 AD4 AD6 AD7 AD8 AD0 NC = No connection. FIGURE 2. Terminal connections. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 8003 A REVISION LEVEL F SHEET 16 Case outline U Device types: 01, 03, and 04 Terminal number Terminal symbol Terminal number Terminal symbol 1 AD0 27 SN1 2 AD9 28 SN0 3 AD10 29 BUSRQ 4 AD11 30 WAIT 5 AD12 31 BUSAK 6 AD13 32 NC 7 NC 33 NC 8 STOP 34 R/W 9 MI 35 N/S 10 AD15 36 B/W 11 AD14 37 RESERVED 12 VCC 38 AS 13 NC 39 CLK 14 VI 40 GND 15 NVI 41 SN2 16 SEGT 42 AD1 17 NMI 43 AD2 18 RESET 44 AD3 19 MO 45 AD5 20 MREQ 46 SN4 21 DS 47 AD4 22 ST3 48 AD6 23 ST2 49 AD7 24 ST1 50 SN5 25 ST0 51 SN6 26 SN3 52 AD8 NC = No connection. FIGURE 2. Terminal connections - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 8003 A REVISION LEVEL F SHEET 17 Case outline Z Device types: 01, 03, and 04 Terminal number Terminal symbol Terminal number Terminal symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 GND +5V AD0 AD9 AD10 AD11 AD12 AD13 NC NC STOP MI AD15 AD14 +5V +5V GND GND VI NVI SEGT NMI RESET MO MREQ NC NC NC DS ST3 ST2 ST1 ST0 SN3 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 SN1 SN0 BUSRQ WAIT BUSAK NC NC NC NC NC R/W N/S B/W RESERVED AS GND CLK +5V GND SN2 AD1 AD2 AD3 AD5 SN4 NC NC NC AD4 AD6 AD7 SN5 SN6 AD8 NC = No connection. FIGURE 2. Terminal connections - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 8003 A REVISION LEVEL F SHEET 18 Case outline Y Device types: 02, 05, and 06 Terminal number Terminal symbol Terminal number Terminal symbol 1 AD9 23 ST0 2 AD10 24 NC 3 AD11 25 NC 4 AD12 26 BUSRQ 5 AD13 27 WAIT 6 NC 28 BUSAK 7 STOP 29 R/W 8 MI 30 N/S 9 AD15 31 B/W 10 AD14 32 RESERVED 11 VCC 33 AS 12 NC 34 CLK 13 VI 35 GND 14 NVI 36 AD1 15 NMI 37 AD2 16 RESET 38 AD3 17 MO 39 AD5 18 MREQ 40 AD4 19 DS 41 AD6 20 ST3 42 AD7 21 ST2 43 AD8 22 ST1 44 AD0 NC = No connection. FIGURE 2. Terminal connections - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 8003 A REVISION LEVEL F SHEET 19 Device types 01, 03, and 04 FIGURE 3. Logic functions. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 8003 A REVISION LEVEL F SHEET 20 Device types 02, 05, and 06 FIGURE 3. Logic functions - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 8003 A REVISION LEVEL F SHEET 21 FIGURE 4. Timing waveforms. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 8003 A REVISION LEVEL F SHEET 22 FIGURE 4. Timing waveforms - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 8003 A REVISION LEVEL F SHEET 23 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA = +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. TABLE II. Electrical test requirements. MIL-STD-883 test requirements Interim electrical parameters (method 5004) Final electrical test parameters (method 5004) Group A test requirements (method 5005) Groups C and D end-point electrical parameters (method 5005) Subgroups (in accordance with MIL-STD-883, method 5005, table I) --1*, 2, 3, 7, 8, 9 1, 2, 3, 7, 8, 9, 10, 11** 1, 2, 3 * PDA applies to subgroup 1. ** Subgroups 10 and 11, if not tested, shall be guaranteed to the specified limits in table I. 4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 of MIL-STD883 including groups A, B, C, and D inspections. The following additional criteria shall apply. 4.3.1 Group A inspection. a. Tests shall be as specified in table II herein. b. Subgroups 4, 5, and 6 in table I, method 5005 of MIL-STD-883 shall be omitted. c. Subgroup 4 (CIN measurement) shall be measured only for the initial test and after process or design changes which may affect input capacitance. d. Subgroups 7 and 8 shall include verification of the functionality of the device. It forms a part of the vendor's test tape and shall be maintained and available from the approved sources of supply. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 8003 A REVISION LEVEL F SHEET 24 4.3.2 Groups C and D inspections. a. End-point electrical parameters shall be as specified in table II herein. b. Steady-state life test conditions, method 1005 of MIL-STD-883. (1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-STD-883. (2) TA = +125C, minimum. (3) Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883. 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535, appendix A. 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. 6.2 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractorprepared specification or drawing. 6.3 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal. 6.4 Record of users. Military and industrial users shall inform Defense Supply Center Columbus (DSCC) when a system application requires configuration control and the applicable SMD. DSCC will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronics devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544. 6.5 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43218-3990, or telephone (614) 692-0547. 6.6 Approved sources of supply. Approved sources of supply are listed in MIL-HDBK-103. The vendors listed in MILHDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted to and accepted by DSCC-VA. 6.7 Pin descriptions. Name Description AD0 - AD15 (Address/Data Bus) Inputs/outputs, active High, three-state. These multiplexed address and data lines are used for both I/O and to address memory. AD15 = MSB. AS (Address Strobe) Output, active Low, three-state. The rising edge of AS indicates addresses are valid. BUSAK (Bus Acknowledge) Output, active Low. A low on this line indicates the CPU has relinquished control of the bus. This occurs after completion of the current machine cycle. BUSAK goes inactive one clock cycle after the synchronization of BUSRQ being released. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 8003 A REVISION LEVEL F SHEET 25 6.7 Pin descriptions - Continued. Name Description BUSRQ (Bus Request) Input, active Low. This line must be driven Low to request the bus from the CPU. It is sampled for being active at the beginning of each machine cycle. When it is released, it is synchronized with the next rising clock edge. DS (Data Strobe) Output, active Low, three-state. This line times the data in and out of the CPU. MREQ (Memory Request) Output, active Low, three-state. A low on this line indicates that the address/data bus holds a memory address. MI, MO (Multi-Micro In, Multi-Micro Out) Input and output, active Low. These two lines form a resource-request daisy chain that allows one CPU in a multi-microprocessor system to access a shared resource. MI is sampled on the rising edge of T3 of the last machine cycle of any instruction and Internally latched. NMI (Non-Maskable Interrupt) Edge triggered, input, active Low. A high-to-low transition on NMI request a non-maskable interrupt. The NMI interrupt has the highest priority of the three types of interrupts. The internal NMI latch is sampled on the rising edge of T3 of the last machine cycle of any instruction. NVI (Non-Vectored Interrupt) Input, active Low. A low on this line requests a non-vectored interrupt. It is sampled on the rising edge of T3 of the last machine cycle of any instruction. CLK (System Clock) Input. CLK is a 5 V single-phase time-base input. RESET (Reset) Input, active Low. A low on this line resets the CPU. RESET must be active for at least five clock cycles. R/W (Read/Write) Output, Low = Write, three-state. R/W indicates that the CPU is reading from or writing to memory or I/O. ST0 - ST3 (Status) Outputs, active High, three-state. These lines specify the CPU status. STOP (Stop) Input, active Low. This input can be used to single-step instruction execution. It is sampled on the last falling clock edge preceding any first instruction fetch cycle. VI (Vectored Interrupt) Input, active Low. A low on this line requests a vectored interrupt. It is sampled on the rising edge of T3 of the last machine cycle of any instruction. WAIT (Wait) Input, active Low. This line indicates to the CPU that the memory or I/O device is not ready for data transfer. It is sampled on the falling edge of T2 and any subsequent WAIT states. B/W (Byte/Word) Output, Low = word, three-state. This signal defines the type of memory reference on the 16-bit address/data bus. N/S (Normal/System Mode) Output, Low = system mode, three-state. N/S indicates the CPU is in the normal or system mode. SN0 - SN6 (Segment Number) Outputs, active High, three-state. These lines provide the 7-bit segment number used to address one of 128 segments by the memory management unit. Outputs by the 01, 03, and 04 parts only. SN6 = MSB. SEGT (Segment Trap) Input, active Low. The memory management unit interrupts the CPU with a low on this line when the MMU detects a segmentation trap. Input on the 01, 03, and 04 parts only. It is sampled on the rising edge of T3 of the last machine cycle of any instruction. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 8003 A REVISION LEVEL F SHEET 26 STANDARD MICROCIRCUIT DRAWING BULLETIN DATE: 05-03-23 Approved sources of supply for SMD 80003 are listed below for immediate acquisition information only and shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepted by DSCC-VA. This information bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current sources of supply at http://www.dscc.dla.mil/Programs/Smcr/. Vendor CAGE number Vendor similar PIN 2/ 8000301UA 0C7V7 Z0800104LMB 8000301XA 0C7V7 Z0800104CMB 8000301ZA 3/ 8000302QA 0C7V7 Z0800204CMB 8000302YA 0C7V7 Z0800204LMB 8000303UA 0C7V7 Z0800106LMB 8000303XA 0C7V7 Z0800106CMB 8000303ZA 3/ Z8001AK2/883 8000304UA 0C7V7 Z0800110LMB 8000304XA 0C7V7 Z0800110CMB 8000304ZA 3/ Z8001BK2/883 8000305QA 0C7V7 Z0800210CMB 8000305YA 0C7V7 Z0800210LMB 8000306QA 0C7V7 Z0800206CMB 8000306YA 0C7V7 Z0800206LMB Standard microcircuit drawing PIN 1/ 1/ 2/ 3/ Z8001K2/883 The lead finish shown for each PIN representing a hermetic package is the most readily available from the manufacturer listed for that part. If the desired lead finish is not listed contact the vendor to determine its availability. Caution. Do not use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. Not available from an approved source of supply. Vendor CAGE number 0C7V7 Vendor name and address QP Semiconductor 2945 Oakmead Village Court Santa Clara, CA 95051 The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in the information bulletin.