REVISIONS
LTR DESCRIPTION DATE (YR-MO-DA) APPROVED
A Pages 1, 2, 3, 4, 14, 15, 16, editorial changes. Pages 5, 6, 7, 8, symbol
corrections. Page 18, added vendor. 81-12-09 M. A. Frye
B Add device type 03. Type 02 inactive for new design: Use MIL-M-38510/52002
for case Q. Type 01 and new type 03 are still active. 83-04-06 M. A. Frye
C Add device types 04 and 05. 84-10-31 M. A. Frye
D Case temperature to +125°C. Add LCC package, electrical test improvements. 85-11-12 M. A. Frye
E Change to military drawing format. Add device type 06, changes to 1.4, add
vendor CAGE number 66958, delete vendor CAGE number 34335, changes to
table I, changes to figures 1, 2, and 3. Editorial changes throughout. Change
Code Ident. No. to 67268.
87-12-17 M. A. Frye
F Update boilerplate to MIL-PRF-38535 requirements. Correct drawing title to
indicate device function. - CFS 03-06-11 Thomas M. Hess
G Correct marking requirements in 3.5. Update boilerplate in accordance with
MIL-PRF-38535 requirements. - PHN. 05-03-23 Thomas M. Hess
THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED.
REV
SHEET
REV F F F F F F F F F F F F
SHEET 15 16 17 18 19 20 21 22 23 24 25 26
REV STATUS REV G F G G F F F F F F F F F F
OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14
PMIC N/A PREPARED BY
Ray Monnin
STANDARD
MICROCIRCUIT
DRAWING
CHECKED BY
Charles Reusing
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
http://www.dscc.dla.mil
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
APPROVED BY
Michael. A. Frye
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
DRAWING APPROVAL DATE
80-07-21
MICROCIRCUIT, DIGITAL, 6-BIT N-CHANNEL
SINGLE-CHIP MICROPROCESSOR, MONOLITHIC
SILICON
SIZE
A CAGE CODE
67268
80003
AMSC N/A
REVISION LEVEL
G SHEET
1 OF
26
DSCC FORM 2233
APR 97 5962-E240-05
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
8003
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
F SHEET 2
DSCC FORM 2234
APR 97
1. SCOPE
1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in
accordance with MIL-PRF-38535, appendix A.
1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example:
80003 01 X X
Drawing number
Device type
(see 1.2.1) Case outline
(see 1.2.2) Lead finish
(see 1.2.3)
1.2.1 Device type(s). The device type(s) identify the circuit function as follows:
Device type Generic number Frequency Circuit function
01 Z8001 4.0 MHz 16-Bit N-channel single-chip microprocessor
02 Z8002 4.0 MHz 16-Bit N-channel single-chip microprocessor
03 Z8001A 6.0 MHz 16-Bit N-channel single-chip microprocessor
04 Z8001B 10.0 MHz 16-Bit N-channel single-chip microprocessor
05 Z8002B 10.0 MHz 16-Bit N-channel single-chip microprocessor
06 Z8002A 6.0 MHz 16-Bit N-channel single-chip microprocessor
1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter Descriptive designator Terminals Package style
Q GDIP1-T40 or CDIP2-T40 40 Dual-in-line
U CQCC1-N52 52 Square leadless chip carrier
X See figure 1 48 Dual-in-line
Y CQCC1-N44 44 Square leadless chip carrier
Z CQCC1-N68 68 Square leadless chip carrier
1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A.
1.3 Absolute maximum ratings.
Supply voltage range with respect to ground (VCC).................................................... -0.3 V dc to +7.0 V dc
Storage temperature range ........................................................................................ -65°C to +150°C
Maximum power dissipation (PD) (per device)............................................................ 2.2 W
Lead temperature (soldering, 5 seconds)................................................................... +270°C
Maximum junction temperature (TJ)............................................................................ +150°C
Thermal resistance, junction-to-case (θJC):
Case X .................................................................................................................... 14°C/W
Cases Q, U, Y, Z..................................................................................................... See MIL-STD-1835
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
8003
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
G SHEET 3
DSCC FORM 2234
APR 97
1.4 Recommended operating conditions.
Supply voltage range (VCC)......................................................................................... +4.5 V dc to +5.5 V dc
Minimum high level input voltage (VIH):
Logic inputs............................................................................................................. +2.2 V dc to VCC + 0.3 V dc
Clock input.............................................................................................................. VCC – 0.4 V dc to VCC + 0.3 V dc
RESET (NMI) .......................................................................................................... 2.4 V dc to VCC + 0.3 V dc
Maximum low level input voltage (VIL):
Logic inputs............................................................................................................. -0.3 V dc to +0.8 V dc
Clock input.............................................................................................................. -0.3 V dc to +0.45 V dc
Frequency of operation:
01, 02...................................................................................................................... 0.5 MHz to 4.0 MHz
03, 06...................................................................................................................... 0.5 MHz to 6.0 MHz
04, 05...................................................................................................................... 0.5 MHz to 10.0 MHz
Case operating temperature range (TC)..................................................................... -55°C to +125°C
Clock rise time (tr):
01, 02...................................................................................................................... 20 ns maximum
03, 06...................................................................................................................... 15 ns maximum
04, 05...................................................................................................................... 10 ns maximum
Clock fall time (tf):
01, 02...................................................................................................................... 20 ns maximum
03, 06...................................................................................................................... 10 ns maximum
04, 05...................................................................................................................... 15 ns maximum
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a
part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in
the solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883 - Test Method Standard Microcircuits.
MIL-STD-1835 - Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 - List of Standard Microcircuit Drawings.
MIL-HDBK-780 - Standard Microcircuit Drawings.
(Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or http://assist.daps.dla.mil
or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
8003
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
G SHEET 4
DSCC FORM 2234
APR 97
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-
JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer
Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-
PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying
activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan
may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device.
These modifications shall not affect the PIN as described herein. A "Q" or "QML" certification mark in accordance with MIL-
PRF-38535 is required to identify when the QML flow option is used.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as
specified in MIL-PRF-38535, appendix A and herein.
3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein and on figure 1.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2.
3.2.3 Logic functions. The logic functions shall be as specified on figure 3.
3.2.4 Timing waveforms. The timing waveforms shall be as specified on figure 4.
3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are
as specified in table I and shall apply over the full case operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical
tests for each subgroup are described in table I.
3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN
listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked.
3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance
to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a "Q" or "QML" certification mark in
accordance with MIL-PRF-38535 to identify when the QML flow option is used.
3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an
approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to
listing as an approved source of supply shall affirm that the manufacturer's product meets the requirements of MIL-PRF-
38535, appendix A and the requirements herein.
3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided
with each lot of microcircuits delivered to this drawing.
3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing.
3.9 Verification and review. DSCC, DSCC's agent, and the acquiring activity retain the option to review the manufacturer's
facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the
reviewer.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
8003
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
F SHEET 5
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics.
Limits
Test
Symbol
Conditions
-55°C ≤ TC ≤ +125°C
+4.5 V ≤ VCC ≤ +5.5 V
unless otherwise specified
Group A
subgroups
Device
type Min Max
Unit
Clock input low
voltage VIL1 1, 2, 3 All -0.3
1/ 0.45 V
Clock input high
voltage VIH1
Driven by external clock generator.
1, 2, 3 All VCC – 0.4 VCC + 0.3
1/ V
Input low voltage VIL2 1, 2, 3 All -0.3
1/ 0.8 V
Input high voltage VIH2 1, 2, 3 All 2.4 VCC + 0.3
1/ V
Reset input high
voltage (NMI) VIH3 1, 2, 3 All 2.4 VCC + 0.3
1/ V
High level output
voltage all outputs VOH IOH = -250 µA
VCC = 4.5 V 1, 2, 3 All 2.4 V
Low level output
voltage all outputs VOL IOL = +2.0 mA
VCC = 4.5 V 1, 2, 3 All 0.4 V
High-impedance
(off-state) output
current (High)
(In Float)
IZH VIN = 2.4 V
VCC = 5.5 V 1, 2, 3 All –10 +10 µA
High-impedance
(off-state) output
current (Low)
(In Float)
IZL VIN = 0.4 V
VCC = 5.5 V 1, 2, 3 All –10 +10 µA
High level input
current (input and
bi-directional)
IIH VIN = 2.4 V
VCC = 5.5 V 1, 2, 3 All -10 +10 µA
Low level input
current (input and
bi-directional)
IIL VIN = 0.4 V
VCC = 5.5 V 1, 2, 3 All -10 +10 µA
Low level input
current (SEGT) IILS 0.4 V ≤ VIN ≤ 2.4 V
4.5 V ≤ VCC ≤ 5.5 V 1, 2, 3
01, 03, 04
+200 µA
Supply current ICC VCC = 5.5 V 1, 2, 3 All 400 mA
Functional tests See 4.3.1c 7, 8 All
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
8003
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
F SHEET 6
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Limits
Conditions
-55°C ≤ TC ≤ +125°C
+4.5 V ≤ VCC ≤ +5.5 V
unless otherwise specified
Group A
subgroups
Device
type Min Max
Unit
01, 02 250 2000
03, 06 165 2000
Clock pulse tcyc See figure 4.
See Reference No. 1 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
04, 05 100 2000
ns
01, 02 105
03, 06 70
Clock pulse width
(Low) tPWL1 See figure 4.
See Reference No. 2 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
04, 05 40
ns
01, 02 105
03, 06 70
Clock pulse width
(High) tPWH1 See figure 4.
See Reference No. 3 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
04, 05 40
ns
01 130
03 110
Clock ↑ to segment
number valid TdC(SNv)
3/ 4/ See figure 4.
See Reference No. 6 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
04 90
ns
01 20
03 10
Clock ↑ to segment
number not valid TdC(SNn)
4/ See figure 4.
See Reference No. 7 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
04 0
ns
01, 02 65
03, 06 55
Clock ↑ to bus float TdC(Bz)
1/ See figure 4.
See Reference No. 8 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
04, 05 50
ns
01, 02 100
03, 06 75
Clock ↑ to address
valid TdC(A) See figure 4.
See Reference No. 9 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
04, 05 65
ns
01, 02 65
03, 06 55
Clock ↑ to address
float TdC(Az)
1/ See figure 4.
See Reference No. 10 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
04, 05 50
ns
01, 02 475
03, 06 305
Address valid to
data in required
valid
TdA(DR) See figure 4.
See Reference No. 11 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
5/ 04, 05 180
ns
01, 02 30
03, 06 20
Data to CLK ↓
setup time TsDR(C) See figure 4.
See Reference No. 12 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
04, 05 10
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
8003
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
F SHEET 7
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions
-55°C ≤ TC ≤ +125°C
+4.5 V ≤ VCC ≤ +5.5 V
unless otherwise specified
Group A
subgroups
Device
type
Limits Unit
Min Max
01, 02 80
03, 06 45
DS ↑ to address
active TdDS(A) See figure 4.
See Reference No. 13 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
5/ 04, 05 20
ns
01, 02 100
03, 06 75
Clock ↑ to data out
valid TdC(DW) See figure 4.
See Reference No. 14 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
04, 05 60
ns
01, 02 0
03, 06 0
Data in to DS ↑
hold time ThDR(DS)
See figure 4.
See Reference No. 15 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
04, 05 0
ns
01, 02 295
03, 06 195
Data out valid to
DS ↑ delay TdDW(DS)
See figure 4.
See Reference No. 16 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
5/ 04, 05 110
ns
01, 02 55
03, 06 35
Address valid to
MREQ ↓ delay TdA(MR) See figure 4.
See Reference No. 17 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
5/ 04, 05 20
ns
01, 02 80
03, 06 70
Clock ↓ to MREQ ↓
delay TdC(MR) See figure 4.
See Reference No. 18 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
04, 05 50
ns
01, 02 210
03, 06 135
MREQ width (High) TwMRh See figure 4.
See Reference No. 19 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
5/ 04, 05 80
ns
01, 02 70
03, 06 35
MREQ ↓ to
address not active TdMR(A)
1/ See figure 4.
See Reference No. 20 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
5/ 04, 05 15
ns
01, 02 55
03, 06 35
Data out valid to
DS ↓ (Write Delay)
TdDW
(DSW) See figure 4.
See Reference No. 21 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
5/ 04, 05 15
ns
01, 02 370
03, 06 230
MREQ ↓ to data in
required valid TdMR(DR)
See figure 4.
See Reference No. 22 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
5/ 04, 05 140
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
8003
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
F SHEET 8
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions
-55°C ≤ TC ≤ +125°C
+4.5 V ≤ VCC ≤ +5.5 V
unless otherwise specified
Group A
subgroups
Device
type
Limits Unit
Min Max
01, 02 80
03, 06 60
Clock ↓ to MREQ ↑
delay TdC(MR) See figure 4.
See Reference No. 23 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
04, 05 50
ns
01, 02 80
03, 06 60
Clock ↑ to AS ↓
delay TdC(ASf) See figure 4.
See Reference No. 24 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
04, 05 45
ns
01, 02 55
03, 06 35
Address valid to
AS ↑ delay TdA(AS) See figure 4.
See Reference No. 25 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
5/ 04, 05 20
ns
01, 02 90
03, 06 80
Clock ↓ to AS ↑
delay TdC(ASr) See figure 4.
See Reference No. 26 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
04, 05 45
ns
01, 02 360
03, 06 220
AS ↑ to data in
required valid TdAS(DR)
See figure 4.
See Reference No. 27 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
5/ 04, 05 140
ns
01, 02 70
03, 06 35
DS ↑ to AS ↓
delay TdDS(AS)
See figure 4.
See Reference No. 28 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
5/ 04, 05 15
ns
01, 02 85
03, 06 55
AS width (Low) TwAS See figure 4.
See Reference No. 29 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
5/ 04, 05 30
ns
01, 02 70
03, 06 45
AS ↑ to address
not active delay TdAS(A)
1/ See figure 4.
See Reference No. 30 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
5/ 04, 05 15
ns
01, 02 0
03, 06 0
Address float to DS
(Read) ↓ delay
TdAz(DSR)
1/ See figure 4.
See Reference No. 31 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
04, 05 0
ns
01, 02 80
03, 06 55
AS ↑ to DS ↓
(Read) delay
TdAS(DSR)
See figure 4.
See Reference No. 32 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
5/ 04, 05 30
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
8003
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
F SHEET 9
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions
-55°C ≤ TC ≤ +125°C
+4.5 V ≤ VCC ≤ +5.5 V
unless otherwise specified
Group A
subgroups
Device
type
Limits Unit
Min Max
01, 02 205
03, 06 130
DS (Read) ↓ to
data in required
valid
TdDSR(DR)
See figure 4.
See Reference No. 33 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
5/ 04, 05 70
ns
01, 02 70
03, 06 65
Clock ↓ to DS ↑
delay TdC(DSr) See figure 4.
See Reference No. 34 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
04, 05 50
ns
01, 02 75
03, 06 45
DS ↑ to data out
not valid TdDS(DW)
1/ See figure 4.
See Reference No. 35 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
5/ 04, 05 25
ns
01, 02 180
03, 06 110
Address valid to
DS (Read) ↓
delay
TdA(DSR)
See figure 4.
See Reference No. 36 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
5/ 04, 05 65
ns
01, 02 120
03, 06 85
Clock ↑ to DS
(Read) ↓ delay TdC(DSR)
See figure 4.
See Reference No. 37 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
04, 05 65
ns
01, 02 275
03, 06 185
DS (Read) width
(Low) TwDSR See figure 4.
See Reference No. 38 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
5/ 04, 05 110
ns
01, 02 95
03, 06 80
Clock ↓ to DS
(Write) ↓ delay TdC(DSW)
See figure 4.
See Reference No. 39 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
04, 05 65
ns
01, 02 185
03, 06 110
DS (Write) width
(Low) TwDSW See figure 4.
See Reference No. 40 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
5/ 04, 05 75
ns
01, 02 330
03, 06 210
DS (Input) ↓ to
data in required
valid
TdDSI
(DR)
See figure 4.
See Reference No. 41 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
5/ 04, 05 120
ns
01, 02 120
03, 06 90
Clock ↓ to DS
(IO) ↓ delay TdC(DSf) See figure 4.
See Reference No. 42 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
04, 05 70
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
8003
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
F SHEET 10
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions
-55°C ≤ TC ≤ +125°C
+4.5 V ≤ VCC ≤ +5.5 V
unless otherwise specified
Group A
subgroups
Device
type
Limits Unit
Min Max
01, 02 410
03, 06 255
DS (I/O) width
(Low) TwDS See figure 4.
See Reference No. 43 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
5/ 04, 05 160
ns
01, 02 1065
03, 06 690
AS ↑ to DS
(Acknowledge) ↓
delay
TdAS(DSA)
See figure 4.
See Reference No. 44 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
5/ 04, 05 410
ns
01, 02 120
03, 06 85
Clock ↑ to DS
(Acknowledge) ↓
delay
TdC(DSA)
See figure 4.
See Reference No. 45 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
04, 05 70
ns
01, 02 455
03, 06 295
DS (Acknowledge) ↓
to data in required
delay
TdDSA(DR)
See figure 4.
See Reference No. 46 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
5/ 04, 05 165
ns
01, 02 110
03, 06 85
Clock ↑ to status
valid delay TdC(S) See figure 4.
See Reference No. 47 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
04, 05 65
ns
01, 02 50
03, 06 30
Status valid to
AS ↑ delay TdS(AS) See figure 4.
See Reference No. 48 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
5/ 04, 05 10
ns
01, 02 180
03, 06 70
RESET to clock ↑
set-up time TsR(C) See figure 4.
See Reference No. 49 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
04, 05 50
ns
01, 02 0
03, 06 0
RESET to clock ↑
hold time ThR(C) See figure 4.
See Reference No. 50 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
04, 05 0
ns
01, 02 100
03, 06 70
NMI width (Low) TwNMI See figure 4.
See Reference No. 51 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
04, 05 50
ns
01, 02 140
03, 06 70
NMI to clock ↑
set-up time TsNMI(C) See figure 4.
See Reference No. 52 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
04, 05 50
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
8003
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
F SHEET 11
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions
-55°C ≤ TC ≤ +125°C
+4.5 V ≤ VCC ≤ +5.5 V
unless otherwise specified
Group A
subgroups
Device
type
Limits Unit
Min Max
01, 02 110
03, 06 50
VI, NVI to clock ↑
set-up time TsVI(C) See figure 4.
See Reference No. 53 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
04, 05 40
ns
01, 02 20
03, 06 20
VI, NVI to clock ↑
hold time ThVI(C) See figure 4.
See Reference No. 54 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
04, 05 10
ns
01 70
03 55
SEGT to clock ↑
set-up time TsSGT(C)
4/ See figure 4.
See Reference No. 55 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
04 40
ns
01 0
03 0
SEGT to clock ↑
hold time ThSGT(C)
4/ See figure 4.
See Reference No. 56 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
04 0
ns
01, 02 180
03, 06 140
MI to clock ↑
set-up time TsMI(C) See figure 4.
See Reference No. 57 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
04, 05 80
ns
01, 02 0
03, 06 0
MI to clock ↑
hold time ThMI(C) See figure 4.
See Reference No. 58 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
04, 05 0
ns
01, 02 120
03, 06 85
Clock ↑ to MO
delay time TdC(MO) See figure 4.
See Reference No. 59 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
04, 05 80
ns
01, 02 140
03, 06 100
STOP to clock ↓
set-up time TsSTP(C)
See figure 4.
See Reference No. 60 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
04, 05 50
ns
01, 02 0
03, 06 0
STOP to clock ↓
hold time ThSTP(C)
See figure 4.
See Reference No. 61 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
04, 05 0
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
8003
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
F SHEET 12
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions
-55°C ≤ TC ≤ +125°C
+4.5 V ≤ VCC ≤ +5.5 V
unless otherwise specified
Group A
subgroups
Device
type
Limits Unit
Min Max
01, 02 50
03, 06 30
WAIT to clock ↓
set-up time TsW(C) See figure 4.
See Reference No. 62 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
04, 05 20
ns
01, 02 10
03, 06 10
WAIT to clock ↓
hold time ThW(C) See figure 4.
See Reference No. 63 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
04, 05 5
ns
01, 02 90
03, 06 80
BUSRQ to clock ↑
set-up time TsBRQ(C)
See figure 4.
See Reference No. 64 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
04, 05 60
ns
01, 02 10
03, 06 10
BUSRQ to clock ↑
hold time ThBRQ(C)
See figure 4.
See Reference No. 65 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
04, 05 5
ns
01, 02 100
03, 06 75
Clock ↑ to
BUSAK ↑ delay TdC(BAKr)
See figure 4.
See Reference No. 66 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
04, 05 65
ns
01, 02 100
03, 06 75
Clock ↑ to
BUSAK ↓ delay TdC(BAKf)
See figure 4.
See Reference No. 67 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
04, 05 65
ns
01, 02 150
03, 06 95
Address valid width TwA See figure 4.
See Reference No. 68 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
5/ 04, 05 50
ns
01, 02 80
03, 06 55
DS ↑ to status not
valid TdDS(s)
1/ See figure 4.
See Reference No. 69 2/
CL = 50 pF to 100 pF ±10%, all outputs
9, 10, 11
5/ 04, 05 30
ns
See footnotes on next sheet.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
8003
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
F SHEET 13
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics - Continued.
1/ Guaranteed, if not tested.
2/ The waveform reference number refers to the position where the parameter appears on figure 4.
3/ For waveform reference number 6, CL = 50 pF ±10%.
4/ These parameters are for 01, 03, and 04 devices only.
5/ These waveform reference number parameters are clock dependent. The limits provided are at FMAX. To determine the
limits at other frequencies use the following equations:
Waveform
reference
number
Device types 01 and 02 Device types 03 and 06 Device types 04 and 05
11
13
16
17
19
20
21
22
25
27
28
29
30
32
33
35
36
38
40
41
43
44
46
48
68
69
2 tcyc + tPWH1 – 130 ns
tPWL1 – 25 ns
tcyc + tPWH1 – 60 ns
tPWH1 – 50 ns
tcyc – 40 ns
tPWL1 – 35 ns
tPWH1 – 50 ns
2 tcyc – 130 ns
tPWH1 – 50 ns
2 tcyc – 140 ns
tPWL1 – 35 ns
tPWH1 – 20 ns
tPWL1 – 35 ns
tPWL1 – 25 ns
tcyc + tPWH1 – 150 ns
tPWL1 – 30 ns
tcyc – 70 ns
tcyc + tPWH1 – 80 ns
tcyc – 65 ns
2 tcyc – 170 ns
2 tcyc – 90 ns
4 tcyc + tPWL1 – 40 ns
2 tcyc + tPWH1 – 150 ns
tPWH1 – 55 ns
tcyc – 90 ns
tPWL1 – 25 ns
2 tcyc + tPWH1 – 95 ns
tPWL1 – 25 ns
tcyc + tPWH1 – 40 ns
tPWH1 – 35 ns
tcyc – 30 ns
tPWL1 – 35 ns
tPWH1 – 35 ns
2 tcyc – 100 ns
tPWH1 – 35 ns
2 tcyc – 110 ns
tPWL1 – 35 ns
tPWH1 – 15 ns
tPWL1 – 25 ns
tPWL1 – 15 ns
tcyc + tPWH1 – 105 ns
tPWL1 – 25 ns
tcyc – 55 ns
tcyc + tPWH1 – 50 ns
tcyc – 55 ns
2 tcyc – 120 ns
2 tcyc – 75 ns
4 tcyc + tPWL1 – 40 ns
2 tcyc + tPWH1 – 105 ns
tPWH1 – 40 ns
tcyc – 70 ns
tPWL1 – 15 ns
2 tcyc + tPWH1 – 60 ns
tPWL1 – 20 ns
tcyc + tPWH1 – 30 ns
tPWH1 – 20 ns
tcyc – 20 ns
tPWL1 – 20 ns
tPWH1 – 25 ns
2 tcyc – 60 ns
tPWH1 – 20 ns
2 tcyc – 60 ns
tPWL1 – 25 ns
tPWH1 – 10 ns
tPWL1 – 20 ns
tPWL1 – 10 ns
tcyc + tPWH1 – 70 ns
tPWL1 – 15 ns
tcyc – 35 ns
tcyc + tPWH1 – 30 ns
tcyc – 25 ns
2 tcyc – 80 ns
2 tcyc – 40 ns
4 tcyc + tPWL1 – 30 ns
2 tcyc + tPWH1 – 75 ns
tPWH1 – 30 ns
tcyc – 50 ns
tPWL1 – 10 ns
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
8003
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
F SHEET 14
DSCC FORM 2234
APR 97
Case Outline X
Device types 01, 03, and 04.
FIGURE 1. Case outlines.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
8003
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
F SHEET 15
DSCC FORM 2234
APR 97
Case Outline X
Device types 01, 03, and 04.
Inches Millimeters
Symbol Min Max Min Max
Notes
A --- .225 --- 5.72
b .014 .023 0.36 0.58 7
b1 .030 .070 0.76 1.78 2, 7
c .008 .015 0.20 0.38 7
D --- 2.480 --- 62.99
E .510 .620 12.95 15.75
E1 .520 .620 13.21 15.75 6
e .100 BSC 2.54 BSC 4, 8
L .120 .200 3.05 5.08
L1 .150 --- 3.81 ---
Q .020 .060 0.51 1.52 3
S --- .098 --- 2.40 5
S1 .005 --- 0.13 --- 5
S2 .005 --- 0.13 --- 9
Notes:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be
located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one
identification mark.
2. The minimum limit for dimension b1 may be .020 (0.51 mm) for leads number 1, 24, 25, and 48 only.
3. Dimension Q shall be measured from the seating plane to the base plane.
4. The basic pin spacing is .100 (2.54 mm) between centerlines. Each pin centerline shall be located
within ±.010 (0.25 mm) of its exact longitudinal position relative to pins 1 and 48.
5. Applies to all four corners (leads number 1, 24, 25, and 48) (see MIL-STD-1835).
6. Lead center when α is 0°. E1 shall be measured at the centerline of the leads.
7. All leads – increase maximum limit by .003 (0.08 mm) measured at the center of the flat, when lead
finish A is applied.
8. Forty-six spaces.
9. The top of the lead shall not exceed above the brazed pad top surface.
FIGURE 1. Case outlines - Continued.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
8003
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
F SHEET 16
DSCC FORM 2234
APR 97
Case outlines X and Q
Device types: 01, 03, and 04
Terminal
number Terminal
symbol Terminal
number Terminal
symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
AD0
AD9
AD10
AD11
AD12
AD13
STOP
MI
AD15
AD14
VCC
VI
NVI
SEGT
NMI
RESET
MO
MREQ
DS
ST3
ST2
ST1
ST0
SN3
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
SN1
SN0
BUSRQ
WAIT
BUSAK
R/W
N/S
B/W
NC
AS
CLOCK
GND
SN2
AD1
AD2
AD3
AD5
SN4
AD4
AD6
AD7
SN5
SN6
AD8
Device types: 02 and 05
Terminal
number Terminal
symbol Terminal
number Terminal
symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
AD9
AD10
AD11
AD12
AD13
STOP
MI
AD15
AD14
VCC
VI
NVI
NMI
RESET
MO
MREQ
DS
ST3
ST2
ST1
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
ST0
BUSRQ
WAIT
BUSAK
R/W
N/S
B/W
NC
AS
CLOCK
GND
AD1
AD2
AD3
AD5
AD4
AD6
AD7
AD8
AD0
NC = No connection. FIGURE 2. Terminal connections.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
8003
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
F SHEET 17
DSCC FORM 2234
APR 97
Case outline U
Device types: 01, 03, and 04
Terminal
number Terminal
symbol Terminal
number Terminal
symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
AD0
AD9
AD10
AD11
AD12
AD13
NC
STOP
MI
AD15
AD14
VCC
NC
VI
NVI
SEGT
NMI
RESET
MO
MREQ
DS
ST3
ST2
ST1
ST0
SN3
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
SN1
SN0
BUSRQ
WAIT
BUSAK
NC
NC
R/W
N/S
B/W
RESERVED
AS
CLK
GND
SN2
AD1
AD2
AD3
AD5
SN4
AD4
AD6
AD7
SN5
SN6
AD8
NC = No connection.
FIGURE 2. Terminal connections - Continued.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
8003
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
F SHEET 18
DSCC FORM 2234
APR 97
Case outline Z
Device types: 01, 03, and 04
Terminal
number Terminal
symbol Terminal
number Terminal
symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
GND
+5V
AD0
AD9
AD10
AD11
AD12
AD13
NC
NC
STOP
MI
AD15
AD14
+5V
+5V
GND
GND
VI
NVI
SEGT
NMI
RESET
MO
MREQ
NC
NC
NC
DS
ST3
ST2
ST1
ST0
SN3
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
SN1
SN0
BUSRQ
WAIT
BUSAK
NC
NC
NC
NC
NC
R/W
N/S
B/W
RESERVED
AS
GND
CLK
+5V
GND
SN2
AD1
AD2
AD3
AD5
SN4
NC
NC
NC
AD4
AD6
AD7
SN5
SN6
AD8
NC = No connection.
FIGURE 2. Terminal connections - Continued.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
8003
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
F SHEET 19
DSCC FORM 2234
APR 97
Case outline Y
Device types: 02, 05, and 06
Terminal
number Terminal
symbol Terminal
number Terminal
symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
AD9
AD10
AD11
AD12
AD13
NC
STOP
MI
AD15
AD14
VCC
NC
VI
NVI
NMI
RESET
MO
MREQ
DS
ST3
ST2
ST1
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
ST0
NC
NC
BUSRQ
WAIT
BUSAK
R/W
N/S
B/W
RESERVED
AS
CLK
GND
AD1
AD2
AD3
AD5
AD4
AD6
AD7
AD8
AD0
NC = No connection.
FIGURE 2. Terminal connections - Continued.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
8003
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
F SHEET 20
DSCC FORM 2234
APR 97
Device types 01, 03, and 04
FIGURE 3. Logic functions.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
8003
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
F SHEET 21
DSCC FORM 2234
APR 97
Device types 02, 05, and 06
FIGURE 3. Logic functions - Continued.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
8003
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
F SHEET 22
DSCC FORM 2234
APR 97
FIGURE 4. Timing waveforms.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
8003
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
F SHEET 23
DSCC FORM 2234
APR 97
FIGURE 4. Timing waveforms - Continued.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
8003
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
F SHEET 24
DSCC FORM 2234
APR 97
4. VERIFICATION
4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535,
appendix A.
4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices
prior to quality conformance inspection. The following additional criteria shall apply:
a. Burn-in test, method 1015 of MIL-STD-883.
(1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision
level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015 of MIL-STD-883.
(2) TA = +125°C, minimum.
b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter
tests prior to burn-in are optional at the discretion of the manufacturer.
TABLE II. Electrical test requirements.
MIL-STD-883 test requirements Subgroups (in accordance with
MIL-STD-883, method 5005, table I)
Interim electrical parameters
(method 5004) ---
Final electrical test parameters
(method 5004) 1*, 2, 3,
7, 8, 9
Group A test requirements
(method 5005) 1, 2, 3, 7, 8,
9, 10, 11**
Groups C and D end-point
electrical parameters (method 5005) 1, 2, 3
* PDA applies to subgroup 1.
** Subgroups 10 and 11, if not tested, shall be guaranteed to the specified limits in table I.
4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 of MIL-STD-
883 including groups A, B, C, and D inspections. The following additional criteria shall apply.
4.3.1 Group A inspection.
a. Tests shall be as specified in table II herein.
b. Subgroups 4, 5, and 6 in table I, method 5005 of MIL-STD-883 shall be omitted.
c. Subgroup 4 (CIN measurement) shall be measured only for the initial test and after process or design changes which
may affect input capacitance.
d. Subgroups 7 and 8 shall include verification of the functionality of the device. It forms a part of the vendor’s test tape
and shall be maintained and available from the approved sources of supply.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
8003
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
F SHEET 25
DSCC FORM 2234
APR 97
4.3.2 Groups C and D inspections.
a. End-point electrical parameters shall be as specified in table II herein.
b. Steady-state life test conditions, method 1005 of MIL-STD-883.
(1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision
level control and shall be made available to the preparing or acquiring activity upon request. The test circuit
shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent
specified in method 1005 of MIL-STD-883.
(2) TA = +125°C, minimum.
(3) Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535, appendix A.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.2 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor-
prepared specification or drawing.
6.3 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.4 Record of users. Military and industrial users shall inform Defense Supply Center Columbus (DSCC) when a system
application requires configuration control and the applicable SMD. DSCC will maintain a record of users and this list will be
used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronics devices (FSC
5962) should contact DSCC-VA, telephone (614) 692-0544.
6.5 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43218-3990, or telephone
(614) 692-0547.
6.6 Approved sources of supply. Approved sources of supply are listed in MIL-HDBK-103. The vendors listed in MIL-
HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted to and accepted
by DSCC-VA.
6.7 Pin descriptions.
Name Description
AD0 – AD15 Inputs/outputs, active High, three-state. These multiplexed address and data lines are
(Address/Data Bus) used for both I/O and to address memory. AD15 = MSB.
AS Output, active Low, three-state. The rising edge of AS indicates addresses are valid.
(Address Strobe)
BUSAK Output, active Low. A low on this line indicates the CPU has relinquished control of the
(Bus Acknowledge) bus. This occurs after completion of the current machine cycle. BUSAK goes inactive
one clock cycle after the synchronization of BUSRQ being released.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
8003
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
F SHEET 26
DSCC FORM 2234
APR 97
6.7 Pin descriptions - Continued.
Name Description
BUSRQ Input, active Low. This line must be driven Low to request the bus from the CPU. It is
(Bus Request) sampled for being active at the beginning of each machine cycle. When it is released, it
is synchronized with the next rising clock edge.
DS Output, active Low, three-state. This line times the data in and out of the CPU.
(Data Strobe)
MREQ Output, active Low, three-state. A low on this line indicates that the address/data bus
(Memory Request) holds a memory address.
MI, MO Input and output, active Low. These two lines form a resource-request daisy chain that
(Multi-Micro In, allows one CPU in a multi-microprocessor system to access a shared resource. MI is
Multi-Micro Out) sampled on the rising edge of T3 of the last machine cycle of any instruction and
Internally latched.
NMI Edge triggered, input, active Low. A high-to-low transition on NMI request a
(Non-Maskable Interrupt) non-maskable interrupt. The NMI interrupt has the highest priority of the three types of
interrupts. The internal NMI latch is sampled on the rising edge of T3 of the last machine
cycle of any instruction.
NVI Input, active Low. A low on this line requests a non-vectored interrupt. It is sampled on
(Non-Vectored Interrupt) the rising edge of T3 of the last machine cycle of any instruction.
CLK Input. CLK is a 5 V single-phase time-base input.
(System Clock)
RESET Input, active Low. A low on this line resets the CPU. RESET must be active for at least
(Reset) five clock cycles.
R/W Output, Low = Write, three-state. R/W indicates that the CPU is reading from or writing
(Read/Write) to memory or I/O.
ST0 – ST3 Outputs, active High, three-state. These lines specify the CPU status.
(Status)
STOP Input, active Low. This input can be used to single-step instruction execution. It is
(Stop) sampled on the last falling clock edge preceding any first instruction fetch cycle.
VI Input, active Low. A low on this line requests a vectored interrupt. It is sampled on the
(Vectored Interrupt) rising edge of T3 of the last machine cycle of any instruction.
WAIT Input, active Low. This line indicates to the CPU that the memory or I/O device is not ready
(Wait) for data transfer. It is sampled on the falling edge of T2 and any subsequent WAIT states.
B/W Output, Low = word, three-state. This signal defines the type of memory reference on the
(Byte/Word) 16-bit address/data bus.
N/S Output, Low = system mode, three-state. N/S indicates the CPU is in the normal or
(Normal/System Mode) system mode.
SN0 – SN6 Outputs, active High, three-state. These lines provide the 7-bit segment number used to
(Segment Number) address one of 128 segments by the memory management unit. Outputs by the 01, 03,
and 04 parts only. SN6 = MSB.
SEGT Input, active Low. The memory management unit interrupts the CPU with a low on this
(Segment Trap) line when the MMU detects a segmentation trap. Input on the 01, 03, and 04 parts only.
It is sampled on the rising edge of T3 of the last machine cycle of any instruction.
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 05-03-23
Approved sources of supply for SMD 80003 are listed below for immediate acquisition information only and shall be
added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to
include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of
compliance has been submitted to and accepted by DSCC-VA. This information bulletin is superseded by the next
dated revision of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current sources of
supply at http://www.dscc.dla.mil/Programs/Smcr/.
Standard microcircuit
drawing PIN 1/ Vendor CAGE
number Vendor similar
PIN 2/
8000301UA 0C7V7 Z0800104LMB
8000301XA 0C7V7 Z0800104CMB
8000301ZA 3/ Z8001K2/883
8000302QA 0C7V7 Z0800204CMB
8000302YA 0C7V7 Z0800204LMB
8000303UA 0C7V7 Z0800106LMB
8000303XA 0C7V7 Z0800106CMB
8000303ZA 3/ Z8001AK2/883
8000304UA 0C7V7 Z0800110LMB
8000304XA 0C7V7 Z0800110CMB
8000304ZA 3/ Z8001BK2/883
8000305QA 0C7V7 Z0800210CMB
8000305YA 0C7V7 Z0800210LMB
8000306QA 0C7V7 Z0800206CMB
8000306YA 0C7V7 Z0800206LMB
1/ The lead finish shown for each PIN representing a hermetic
package is the most readily available from the manufacturer listed
for that part. If the desired lead finish is not listed contact the
vendor to determine its availability.
2/ Caution. Do not use this number for item acquisition. Items
acquired to this number may not satisfy the performance
requirements of this drawing.
3/ Not available from an approved source of supply.
Vendor CAGE Vendor name
number and address
0C7V7 QP Semiconductor
2945 Oakmead Village Court
Santa Clara, CA 95051
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.
