1. General description
The 74LVC2G53 is a low-power, low-voltage, high-speed, Si-gate CMOS device.
The 74LVC2G53 provides one analog multiplexer/demultiplexer with a digital select
input (S), two independent input s /output s (Y0 an d Y1 ), a com mon inp ut/outpu t (Z) and an
active LOW enable input (E). When pin E is HIGH, the switch is turned off.
Schmitt-trigger action at the select and enable inputs makes the circuit tolerant of slower
input rise and fall times across the entire VCC range from 1.65 V to 5.5 V.
2. Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
Very low ON resistance:
7.5 Ω (typical) at VCC =2.7V
6.5 Ω (typical) at VCC =3.3V
6Ω (typical) at VCC =5V
Switch current capability of 32 mA
High noise immunity
CMOS low-power consumption
TTL interface compatibility at 3.3 V
Latch-up performance meets requirements of JESD 78 Class I
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exce ed s 200 V
CDM JESD22-C101E exceeds 1000 V
Control inputs accepts voltages up to 5 V
Multiple package options
Specified from −40 °C to +85 °C and from −40 °C to +125 °C
74LVC2G53
2-channel analog multiplexer/demultiplexer
Rev. 6 — 27 September 2010 Product data sheet
74LVC2G53 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 6 — 27 September 2010 2 of 28
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
3. Ordering information
4. Marking
[1] The pin 1 indicator is located on the lo wer left corner of the device, below the marking code.
5. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74LVC2G53DP −40 °Cto+125°C TSSOP8 plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm SOT505-2
74LVC2G53DC −40 °Cto+125°C VSSOP8 plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm SOT765-1
74LVC2G53GT −40 °Cto+125°C XSON8 plastic extremely thin small outline package; no leads;
8 terminals; body 1 × 1.95 × 0.5 mm SOT833-1
74LVC2G53GF −40 °C to +125 °C XSON8 extremely thin small outline package; no leads;
8 terminals; body 1.35 ×1×0.5 mm SOT1089
74LVC2G53GD −40 °Cto+125°C XSON8U plastic extremely thin small outline package; no leads;
8 terminals; UTLP based; body 3 × 2 × 0.5 mm SOT996-2
74LVC2G53GM −40 °C to +125 °C XQFN8U plastic extremely thin quad flat package; no leads;
8 terminals; UTLP based; body 1.6 ×1.6 ×0.5 mm SOT902-1
74LVC2G53GN −40 °C to +125 °C XSON8 extremely thin small outline package; no leads;
8 terminals; body 1.2 ×1.0 ×0.35 mm SOT1116
74LVC2G53GS −40 °C to +125 °C XSON8 extremely thin small outline package; no leads;
8 terminals; body 1.35 ×1.0 ×0.35 mm SOT1203
Table 2. Marking codes
Type number Marking code[1]
74LVC2G53DC V53
74LVC2G53DP V53
74LVC2G53GT V53
74LVC2G53GF V3
74LVC2G53GD V53
74LVC2G53GM V53
74LVC2G53GN V3
74LVC2G53GS V3
Fig 1. Logic symbol
001aah7
95
S
Z
E
Y0
Y1
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Product data sheet Rev. 6 — 27 September 2010 3 of 28
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
6. Pinning information
6.1 Pinning
Fig 2. Logic diag ra m
001aad3
87
Z
Y0
S
Y1
E
Fig 3. Pin configuration SOT505-2 and SOT765-1 Fig 4. Pin configu ration SOT833-1, SOT1089,
SOT1116 and SOT1203
74LVC2G53
ZV
CC
EY0
GND Y1
GND S
001aae798
1
2
3
4
6
5
8
7
74LVC2G53
Y1
Y0
VCC
S
GND
E
Z
GND
001aae800
36
27
18
45
Transparent top view
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Product data sheet Rev. 6 — 27 September 2010 4 of 28
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
6.2 Pin description
7. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
Fig 5. Pin configuration SOT996-2 Fig 6. Pin co nfiguration SOT902-1
001aai274
74LVC2G53
Transparent top view
8
7
6
5
1
2
3
4
Z
E
GND
GND
VCC
Y0
Y1
S
001aag72
4
EY1
Z
V
CC
GND
Y0
GND
S
Transparent top view
3
6
4
1
5
8
7
2
terminal 1
index area
74LVC2G53
Table 3. Pin description
Symbol Pin Description
SOT505-2, SOT765-1, SOT833-1, SOT1089,
SOT996-2, SOT1116 and SOT1203 SOT902-1
Z 1 7 common output or input
E2 6 enable input (active LOW)
GND 3 5 ground (0 V)
GND 4 4 ground (0 V)
S 5 3 select input
Y1 6 2 independent input or output
Y0 7 1 independent input or output
VCC 8 8 supply voltage
Table 4. Function table[1]
Input Channel on
S E
L L Y0 to Z or Z to Y0
H L Y1 to Z or Z to Y1
X H Z (switch off)
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Product data sheet Rev. 6 — 27 September 2010 5 of 28
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
8. Limiting values
[1] The minimum input voltage rating may be exceeded if the input current rating is observed.
[2] The minimum and maximum switch voltage ratings may be exceeded if the switch clamping current rating is observed.
[3] For TSSOP8 packages: above 55 °C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 packages: above 110 °C the value of Ptot derates linearly with 8.0 mW/K.
For XSON8, XSON8U and XQFN8U packages: above 118 °C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
[1] To avoid sinking GND current from terminal Z when switch current flows in terminal Yn, the voltage drop across the bidirectional switch
must not exceed 0.4 V. If the switch current flows into terminal Z, no GND current will flow from terminal Yn. In this case, there is no limit
for the voltage drop across the switch.
[2] Applies to control signal levels.
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage −0.5 +6.5 V
VIinput voltage [1] −0.5 +6.5 V
IIK input clamping current VI<−0.5 V or VI>V
CC + 0.5 V −50 - mA
ISK switch clamping current VI<−0.5 V or VI>V
CC + 0.5 V - ±50 mA
VSW switch voltage enable and disable mode [2] −0.5 VCC + 0.5 V
ISW switch current VSW >−0.5 V or VSW < VCC + 0.5 V - ±50 mA
ICC supply current - 100 mA
IGND ground current −100 - mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation Tamb =−40 °Cto+125°C[3] - 250 mW
Table 6. Operating conditions
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 1.65 5.5 V
VIinput voltage 0 5.5 V
VSW switch voltage enable and disable mode [1] 0V
CC V
Tamb ambient temperature −40 +125 °C
Δt/ΔV input transition rise and fall rate VCC =1.65Vto2.7V [2] - 20 ns/V
VCC = 2.7 V to 5.5 V [2] - 10 ns/V
74LVC2G53 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 6 — 27 September 2010 6 of 28
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
10. Static characteristics
[1] Typical values are measured at Tamb = 25 °C.
[2] These typical values are measured at VCC =3.3V.
Table 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground 0 V).
Symbol Parameter Conditions Tamb =−40 °C to +85 °C Tamb =−40 °C to +125 °CUnit
Min Typ[1] Max Min Max
VIH HIGH-level
input voltage VCC = 1.65 V to 1.95 V 0.65 × VCC - - 0.65 × VCC -V
VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V
VCC = 3 V to 3.6 V 2.0 - - 2.0 - V
VCC = 4.5 V to 5.5 V 0.7 × VCC --0.7 × VCC -V
VIL LOW-level
input voltage VCC = 1.65 V to 1.95 V - - 0.35 × VCC - 0.35 × VCC V
VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V
VCC = 3 V to 3.6 V - - 0.8 - 0.8 V
VCC = 4.5 V to 5.5 V - - 0.3 × VCC 0.3 × VCC V
IIinput leakage
current pin S and pin E;
VI=5.5VorGND;
VCC =0Vto5.5V
[2] -±0.1 ±2-±10 μA
IS(OFF) OFF-state
leakage
current
VCC =5.5V;
see Figure 7 [2] -±0.1 ±5-±20 μA
IS(ON) ON-state
leakage
current
VCC =5.5V;
see Figure 8 [2] -±0.1 ±5-±20 μA
ICC supply current VI= 5.5 V or GND;
VSW =GNDorV
CC;
VCC =1.65Vto5.5V
[2] -0.110 - 40μA
ΔICC additional
supply current pin S and pin E;
VI=V
CC −0.6 V;
VSW =GNDorV
CC;
VCC =5.5V
[2] -5500 - 5000μA
CIinput
capacitance -2.5- - -pF
CS(OFF) OFF-state
capacitance -6.0- - -pF
CS(ON) ON-state
capacitance -18- - -pF
74LVC2G53 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 6 — 27 September 2010 7 of 28
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
10.1 Test circuits
10.2 ON resistance
VI=V
CC or GND; VO= GND or VCC.
Fig 7. Test circuit for measuring OFF-state leakage current
VO
I
S
001aad390
S
Z
E
Y0
Y1
V
CC
GND
switch
switch
1
12
2
V
IH
V
IL
S
V
IH
V
IH
E
VI
V
IL
or V
IH
V
IH
VI=V
CC or GND and VO= open circuit.
Fig 8. Test circuit for measuring ON-state leakage current
I
S
001aad39
1
S
Z
E
Y0
Y1
V
CC
GND
VI
V
IL
or V
IH
V
IL
switch
1
2V
IH
V
IL
S
V
IL
V
IL
E
VO
switch
1
2
Table 8. ON resistance
At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Figure 10 to Figure 15.
Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °CUnit
Min Typ[1] Max Min Max
RON(peak) ON resistance (peak) VI=GNDtoV
CC; see Figure 9
ISW =4mA;
VCC = 1.65 V to 1.95 V - 34.0 130 - 195 Ω
ISW =8mA; V
CC = 2.3 V to 2.7 V - 12.0 30 - 45 Ω
ISW =12mA; V
CC = 2.7 V - 10.4 25 - 38 Ω
ISW =24mA; V
CC =3Vto3.6V - 7.8 20 - 30 Ω
ISW =32mA; V
CC = 4.5 V to 5.5 V - 6.2 15 - 23 Ω
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Product data sheet Rev. 6 — 27 September 2010 8 of 28
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
[1] Typical values are measured at Tamb = 25 °C and nominal VCC.
[2] Flatness is defined as the difference between the maximum and minimum value of ON resistance measured at identical VCC and
temperature.
10.3 ON resistance test circuit and graphs
RON(rail) ON resistance (rail) VI= GND; see Figure 9
ISW =4mA;
VCC = 1.65 V to 1.95 V -8.218 - 27Ω
ISW =8mA; V
CC = 2.3 V to 2.7 V - 7.1 16 - 24 Ω
ISW =12mA; V
CC =2.7V - 6.9 14 - 21 Ω
ISW =24mA; V
CC =3Vto3.6V - 6.5 12 - 18 Ω
ISW =32mA; V
CC = 4.5 V to 5.5 V - 5.8 10 - 15 Ω
VI=V
CC; see Figure 9
ISW =4mA;
VCC = 1.65 V to 1.95 V - 10.4 30 - 45 Ω
ISW =8mA; V
CC = 2.3 V to 2.7 V - 7.6 20 - 30 Ω
ISW =12mA; V
CC =2.7V - 7.0 18 - 27 Ω
ISW =24mA; V
CC =3Vto3.6V - 6.1 15 - 23 Ω
ISW =32mA; V
CC = 4.5 V to 5.5 V - 4.9 10 - 15 Ω
RON(flat) ON resistance
(flatness) VI=GNDtoV
CC [2]
ISW =4mA;
VCC = 1.65 V to 1.95 V -26.0- - - Ω
ISW =8mA; V
CC = 2.3 V to 2.7 V - 5.0 - - - Ω
ISW =12mA; V
CC =2.7V - 3.5 - - - Ω
ISW =24mA; V
CC =3Vto3.6V - 2.0 - - - Ω
ISW =32mA; V
CC = 4.5 V to 5.5 V - 1.5 - - - Ω
Table 8. ON resistance …continued
At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Figure 10 to Figure 15.
Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °CUnit
Min Typ[1] Max Min Max
RON = VSW / ISW.
Fig 9. Test circuit for measuring ON resist ance
ISW
VSW
001aad39
2
S
Z
E
Y0
Y1
VCC
GND
switch
switch
1
1
2
2
VIH
VIL
S
VIL
VIL
E
VI
VIL or VIH
VIL
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Product data sheet Rev. 6 — 27 September 2010 9 of 28
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
(1) VCC = 1.8 V.
(2) VCC = 2.5 V.
(3) VCC = 2.7 V.
(4) VCC = 3.3 V.
(5) VCC = 5.0 V.
Fig 10. Typical ON resistance as a function of input voltage; Tamb = 25 °C
VI (V)
054231
mna673
20
10
30
40
RON
(Ω)
0
(1)
(2)
(3)
(4) (5)
(1) Tamb = 125 °C.
(2) Tamb =85°C.
(3) Tamb =25°C.
(4) Tamb =−40 °C.
(1) Tamb = 125 °C.
(2) Tamb =85°C.
(3) Tamb =25°C.
(4) Tamb =−40 °C.
Fig 11. ON resistance as a function of input voltage;
VCC =1.8V Fig 12. ON resistance as a function of input voltage;
VCC =2.5V
VI (V)
0 2.01.60.8 1.20.4
001aaa712
25
35
15
45
55
RON
(Ω)
5
(4)
(3)
(2)
(1)
VI (V)
0 2.52.01.0 1.50.5
001aaa708
9
11
7
13
15
RON
(Ω)
5
(1)
(2)
(3)
(4)
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Product data sheet Rev. 6 — 27 September 2010 10 of 28
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
(1) Tamb = 125 °C.
(2) Tamb =85°C.
(3) Tamb =25°C.
(4) Tamb =−40 °C.
(1) Tamb = 125 °C.
(2) Tamb =85°C.
(3) Tamb =25°C.
(4) Tamb =−40 °C.
Fig 13. ON resistance as a function of input voltage;
VCC =2.7V Fig 14. ON resistance as a function of input voltage;
VCC =3.3V
001aaa709
VI (V)
0 3.02.01.0 2.51.50.5
9
7
11
13
RON
(Ω)
5
(1)
(2)
(3)
(4)
VI (V)
04312
001aaa710
6
8
10
RON
(Ω)
4
(1)
(2)
(3)
(4)
(1) Tamb = 125 °C.
(2) Tamb =85°C.
(3) Tamb =25°C.
(4) Tamb =−40 °C.
Fig 15. ON resistance as a function of input voltage; VCC =5.0V
VI (V)
054231
001aaa711
5
4
6
7
RON
(Ω)
3
(2)
(4)
(1)
(3)
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Product data sheet Rev. 6 — 27 September 2010 11 of 28
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
11. Dynamic characteristics
[1] Typical values are measured at Tamb =25°C and nominal VCC.
[2] tpd is the same as tPLH and tPHL.
[3] Propagation delay is the calculated RC time constant of the typical ON resistance of the switch and the specified capacitance when
driven by an ideal voltage source (zero output impedance).
[4] ten is the same as tPZH and tPZL.
[5] tdis is the same as tPLZ and tPHZ.
Table 9. Dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Figure 18.
Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °CUnit
Min Typ[1] Max Min Max
tpd propagation delay Z to Yn or Yn to Z; see Figure 16 [2][3]
VCC = 1.65 V to 1.95 V - - 2 - 2.5 ns
VCC = 2.3 V to 2.7 V - - 1.2 - 1.5 ns
VCC = 2.7 V - - 1.0 - 1.25 ns
VCC = 3.0 V to 3.6 V - - 0.8 - 1.0 ns
VCC = 4.5 V to 5.5 V - - 0.6 - 0.8 ns
ten enable time S to Z or Yn; see Figure 17 [4]
VCC = 1.65 V to 1.95 V 2.6 6.7 10.3 2.6 12.9 ns
VCC = 2.3 V to 2.7 V 1.9 4.1 6.4 1.9 8.0 ns
VCC = 2.7 V 1.9 4.0 5.5 1.8 7.0 ns
VCC = 3.0 V to 3.6 V 1.8 3.4 5.0 1.8 6.3 ns
VCC = 4.5 V to 5.5 V 1.3 2.6 3.8 1.3 4.8 ns
Eto Z or Yn; see Figure 17 [4]
VCC = 1.65 V to 1.95 V 1.9 4.0 7.3 1.9 9.2 ns
VCC = 2.3 V to 2.7 V 1.4 2.5 4.4 1.4 5.5 ns
VCC = 2.7 V 1.1 2.6 3.9 1.1 4.9 ns
VCC = 3.0 V to 3.6 V 1.2 2.2 3.8 1.2 4.8 ns
VCC = 4.5 V to 5.5 V 1.0 1.7 2.6 1.0 3.3 ns
tdis disable time S to Z or Yn; see Figure 17 [5]
VCC = 1.65 V to 1.95 V 2.1 6.8 10.0 2.1 12.5 ns
VCC = 2.3 V to 2.7 V 1.4 3.7 6.1 1.4 7.7 ns
VCC = 2.7 V 1.4 4.9 6.2 1.4 7.8 ns
VCC = 3.0 V to 3.6 V 1.1 4.0 5.4 1.1 6.8 ns
VCC = 4.5 V to 5.5 V 1.0 2.9 3.8 1.0 4.8 ns
Eto Z or Yn; see Figure 17 [5]
VCC = 1.65 V to 1.95 V 2.3 5.6 8.6 2.3 11.0 ns
VCC = 2.3 V to 2.7 V 1.2 3.2 4.8 1.2 6.0 ns
VCC = 2.7 V 1.4 4.0 5.2 1.4 6.5 ns
VCC = 3.0 V to 3.6 V 2.0 3.7 5.0 2.0 6.3 ns
VCC = 4.5 V to 5.5 V 1.3 2.9 3.8 1.3 4.8 ns
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Product data sheet Rev. 6 — 27 September 2010 12 of 28
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
11.1 Waveforms and test circuits
Measurement points are given in Table 10.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 16. Inpu t (Yn or Z) to ou tpu t (Z or Yn) propagation delays
tPLH tPHL
VM
VM
VM
VM
GND
VI
VOH
VOL
Yn or Z
input
Z or Yn
output
001aac36
1
Measurement points are given in Table 10.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 17. Enable an d disable times
VM
VI
GND
VCC
VOL
VOH
GND
S, E input
output
LOW to OFF
OFF to LOW
output
HIGH to OFF
OFF to HIGH
VM
001aad39
VM
tPZL
tPHZ tPZH
VX
VY
switch
disabled
switch
enabled
switch
enabled
Z, Yn
Z, Yn
tPLZ
Table 10. Measurement points
Supply voltage Input Output
VCC VMVMVXVY
1.65 V to 2.7 V 0.5VCC 0.5VCC VOL +0.15V V
OH −0.15 V
2.7 V to 5.5 V 0.5VCC 0.5VCC VOL +0.3V V
OH −0.3 V
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Product data sheet Rev. 6 — 27 September 2010 13 of 28
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
Test data is given in Table 11.
Definitions for test circuit:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = Test voltage for switching times.
Fig 18. Test circuit for measuring switching times
VEXT
VCC
VIVO
001aae23
5
DUT
CL
RT
RL
RL
PULSE
GENERATOR
VMVM
tW
tW
10 %
90 %
0 V
VI
VI
negative
pulse
positive
pulse
0 V
VMVM
90 %
10 %
tf
tr
tr
tf
Table 11. Test data
Supply voltage Input Load VEXT
VCC VItr, tfCLRLtPLH, tPHL tPZH, tPHZ tPZL, tPLZ
1.65 V to 1.95 V VCC ≤2.0ns 30pF 1kΩopen GND 2VCC
2.3 V to 2.7 V VCC ≤2.0ns 30pF 500Ωopen GND 2VCC
2.7 V VCC ≤2.5ns 50pF 500Ωopen GND 2VCC
3 V to 3.6 V VCC ≤2.5ns 50pF 500Ωopen GND 2VCC
4.5 V to 5.5 V VCC ≤2.5ns 50pF 500Ωopen GND 2VCC
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Product data sheet Rev. 6 — 27 September 2010 14 of 28
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
11.2 Additional dynamic characteristics
11.3 Test circuits
Table 12. Additional dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb =25
°
C.
Symbol Parameter Conditions Min Typ Max Unit
THD total harmonic distortion fi= 600 Hz to 20 kHz; RL= 600 Ω;
CL=50pF; V
I= 0.5 V (p-p); see Figure 19
VCC = 1.65 V - 0.260 - %
VCC = 2.3 V - 0.078 - %
VCC = 3.0 V - 0.078 - %
VCC = 4.5 V - 0.078 - %
f(−3dB) −3 dB frequency response RL=50Ω; CL= 5 pF; see Figure 20
VCC =1.65V - 200 - MHz
VCC =2.3V - 300 - MHz
VCC =3.0V - 300 - MHz
VCC =4.5V - 300 - MHz
αiso isolation (OFF-state) RL=50Ω; CL=5pF; f
i=10MHz;
see Figure 21
VCC =1.65V - −42 - dB
VCC =2.3V - −42 - dB
VCC =3.0V - −40 - dB
VCC =4.5V - −40 - dB
Qinj charge injection CL= 0.1 nF; Vgen =0V; R
gen =0Ω;
fi= 1 MHz; RL=1MΩ; see Figure 22
VCC =1.8V - 3.3 - pC
VCC =2.5V - 4.1 - pC
VCC =3.3V - 5.0 - pC
VCC =4.5V - 6.4 - pC
VCC =5.5V - 7.5 - pC
Fig 19. Test circuit for measuring total harmonic distortion
D
001aad394
600 Ω
10 μF
0.1 μF
S
Z
Y0
Y1
V
CC
0.5V
CC
GND
CL
RL
switch
switch
1
12
2
V
IH
V
IL
S
V
IL
V
IL
E
fi
V
IL
or V
IH
E
V
IL
74LVC2G53 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 6 — 27 September 2010 15 of 28
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
Adjust fi voltage to obtain 0 dBm level at output. Increase fi frequency until dB meter reads −3dB.
Fig 20. Test circuit for measuring the frequency response when switch is in ON-state
dB
001aad395
50 Ω
0.1 μF
S
Z
E
Y0
Y1
VCC 0.5VCC
GND
CL
RL
switch
switch
1
12
2
VIH
VIL
S
VIL
VIL
E
fi
VIL or VIH
VIL
Adjust fi voltage to obtain 0 dBm level at input.
Fig 21. Test circuit for measuring isolati on (OFF -state)
dB
001aad396
50 Ω
RL
0.1 μF
S
Z
E
Y0
Y1
VCC
0.5VCC
0.5VCC
GND
CL
RL
switch
switch
1
12
2
VIL
VIH
S
VIH
VIH
E
fi
VIL or VIH
VIH
74LVC2G53 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 6 — 27 September 2010 16 of 28
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
a. Test circuit
b. Input and output pulse definitions
Qinj =ΔVO ×CL.
ΔVO = output voltage variation.
Rgen = generator resistance.
Vgen = generator voltage.
Fig 22. Test circuit for measuring charge injection
001aad39
8
S
Z
Y0
Y1
RLCL
VCC
GND
Rgen
Vgen
switch
1
2
VIVO
E
VIL
G
001aac47
8
ΔVO
offonoff
logic
input
VO
(S)
74LVC2G53 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 6 — 27 September 2010 17 of 28
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
12. Package outline
Fig 23. Package outline SOT505-2 (TSSOP8)
UNIT A1
A
max. A2A3bpLHELpwyv
ceD(1) E(1) Z(1) θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.00
0.95
0.75
0.38
0.22
0.18
0.08
3.1
2.9
3.1
2.9 0.65 4.1
3.9
0.70
0.35
8°
0°
0.13 0.10.20.5
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
0.47
0.33
SOT505-2 - - - 02-01-16
wM
bp
D
Z
e
0.25
14
85
θ
A2
A1
Lp
(A3)
detail X
A
L
HE
E
c
vMA
X
A
y
2.5 5 mm0
scale
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-
2
1.1
pin 1 index
74LVC2G53 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 6 — 27 September 2010 18 of 28
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
Fig 24. Package outline SOT765-1 (VSSOP8)
UNIT A1
A
max. A2A3bpLHELpwyv
ceD(1) E(2) Z(1) θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.00
0.85
0.60
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2 0.5 3.2
3.0
0.4
0.1
8°
0°
0.13 0.10.20.4
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
0.40
0.15
Q
0.21
0.19
SOT765-1 MO-187 02-06-07
wM
bp
D
Z
e
0.12
14
85
θ
A2
A1
Q
Lp
(A3)
detail X
A
L
HE
E
c
vMA
X
A
y
2.5 5 mm0
scale
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-
1
1
pin 1 index
74LVC2G53 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 6 — 27 September 2010 19 of 28
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
Fig 25. Package outline SOT833-1 (XSON8)
terminal 1
index area
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT833-1 - - -
MO-252
- - -
SOT833-
1
07-11-14
07-12-07
DIMENSIONS (mm are the original dimensions)
XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm
D
E
e1
e
A1
b
L
L1
e1e1
0 1 2 mm
scale
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
UNIT
mm 0.25
0.17
2.0
1.9
0.35
0.27
A1
max b E
1.05
0.95
Dee
1L
0.40
0.32
L1
0.50.6
A(1)
max
0.5 0.04
1
8
2
7
3
6
4
5
8×
(2)
4×
(2)
A
74LVC2G53 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 6 — 27 September 2010 20 of 28
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
Fig 26. Package outline SOT1089 (XSON8)
References
Outline
version
European
projection Issue date
IEC JEDEC JEITA
SOT1089 MO-252
sot1089_po
10-04-09
10-04-12
Unit
mm
max
nom
min
0.5 0.04 1.40
1.35
1.30
1.05
1.00
0.95
0.55 0.35
0.35
0.30
0.27
A(1)
Dimensions
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
X
SON8: extremely thin small outline package; no leads;
8
terminals; body 1.35 x 1 x 0.5 mm SOT108
9
A1bL
1
0.40
0.35
0.32
0.20
0.15
0.12
DEee
1L
0 0.5 1 mm
scale
terminal 1
index area
E
D
detail X
A
A1
L
L1
b
e1
e
terminal 1
index area
1
4
8
5
(4×)(2)
(8×)(2)
X
74LVC2G53 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 6 — 27 September 2010 21 of 28
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
Fig 27. Package outline SOT996-2 (XSON8U)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT996-2 - - -- - -
SOT996-
2
07-12-18
07-12-21
UNIT A
max
mm 0.5 0.05
0.00
0.35
0.15
3.1
2.9 0.5 1.5 0.5
0.3
0.6
0.4 0.1 0.05
A1
DIMENSIONS (mm are the original dimensions)
X
SON8U: plastic extremely thin small outline package; no leads;
8
terminals; UTLP based; body 3 x 2 x 0.5 mm
0 1 2 mm
scale
b D
2.1
1.9
E e e1L L1
0.15
0.05
L2v w
0.05
y y1
0.1
C
y
C
y1
X
b
14
85
e1
eAC B
vM
Cw M
L2
L1
L
terminal 1
index area
B A
D
E
detail X
AA1
74LVC2G53 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 6 — 27 September 2010 22 of 28
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
Fig 28. Package outline SOT902-1 (XQFN8U)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT902-1 MO-255- - - - - -
SOT902-
1
05-11-25
07-11-14
UNIT A
max
mm 0.5
A1
0.25
0.15
0.05
0.00
1.65
1.55
0.35
0.25
0.15
0.05
DIMENSIONS (mm are the original dimensions)
X
QFN8U: plastic extremely thin quad flat package; no leads;
8
terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm
bDLe1
1.65
1.55
eE L1v
0.10.55 0.5
w
0.05
y
0.05 0.05
y1
0 1 2 mm
scale
X
C
y
C
y1
terminal 1
index area
terminal 1
index area
B A
D
E
detail X
A
A1
b
8
7
6
5
e1
e1
e
e
AC B
∅ vM
C∅ wM
4
1
2
3
L
L1
metal area
not for soldering
74LVC2G53 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 6 — 27 September 2010 23 of 28
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
Fig 29. Package outline SOT1116 (XSON8)
References
Outline
version
European
projection Issue date
IEC JEDEC JEITA
SOT1116
sot1116_po
10-04-02
10-04-07
Unit
mm
max
nom
min
0.35 0.04 1.25
1.20
1.15
1.05
1.00
0.95
0.55 0.3
0.40
0.35
0.32
A(1)
Dimensions
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
X
SON8: extremely thin small outline package; no leads;
8
terminals; body 1.2 x 1.0 x 0.35 mm SOT111
6
A1b
0.20
0.15
0.12
DEee
1L
0.35
0.30
0.27
L1
0 0.5 1 mm
scale
terminal 1
index area
E
D
(4×)(2)
(8×)(2)
A1A
e1e1e1
e
L
L1
b
4321
5678
74LVC2G53 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 6 — 27 September 2010 24 of 28
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
Fig 30. Package outline SOT1203 (XSON8)
References
Outline
version
European
projection Issue date
IEC JEDEC JEITA
SOT1203
sot1203_po
10-04-02
10-04-06
Unit
mm
max
nom
min
0.35 0.04 1.40
1.35
1.30
1.05
1.00
0.95
0.55 0.35
0.40
0.35
0.32
A(1)
Dimensions
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
X
SON8: extremely thin small outline package; no leads;
8
terminals; body 1.35 x 1.0 x 0.35 mm SOT120
3
A1b
0.20
0.15
0.12
DEee
1L
0.35
0.30
0.27
L1
0 0.5 1 mm
scale
terminal 1
index area
E
D
(4×)(2)
(8×)(2)
A
A1
e
L
L1
b
e1e1e1
1
8
2
7
3
6
4
5
74LVC2G53 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 6 — 27 September 2010 25 of 28
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
13. Abbreviations
14. Revision history
Table 13. Abbreviations
Acronym Description
CMOS Complementary Metal-Oxide Semiconductor
TTL Transistor-Transistor Logic
HBM Human Body Model
ESD ElectroStatic Discharge
MM Machine Model
CDM Charged Device Model
DUT Device Under Test
Table 14. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74LVC2G53 v. 6 20100927 Product data sheet - 74LVC2G53 v. 5
Modifications: •Added type number 74LVC2G53GF (SOT1089/XSON8 package).
•Added type number 74LVC2G53GN (SOT1116/XSON8 package).
•Added type number 74LVC2G53GS (SOT1203/XSON8 package).
74LVC2G53 v. 5 20080618 Product data sheet - 74LVC2G53 v. 4
74LVC2G53 v. 4 20080228 Product data sheet - 74LVC2G53 v. 3
74LVC2G53 v. 3 20070828 Product data sheet - 74LVC2G53 v. 2
74LVC2G53 v. 2 20060331 Product data sheet - 74LVC2G53 v. 1
74LVC2G53 v. 1 20060110 Product data sheet - -
74LVC2G53 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 6 — 27 September 2010 26 of 28
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not b e relied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semicond uctors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre va il.
Product specificatio n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warrant ies, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liabil ity towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descripti ons, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use in automotive applicat ions — This NXP
Semiconductors product has been qualified fo r use i n automotive
applications. The product is not designed, authorized or warranted to be
suitable for use in medica l, military, aircraft, space or life support equipment,
nor in applications where failure or malf unction of an NXP Semiconductors
product can reasonably be expected to result in personal injury, death or
severe property or environmental damage. NXP Semiconductors accepts no
liability for inclusion and/or use of NXP Semiconductors products in such
equipment or applications and therefore such inclusion and/or use is at the
customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Custo mers should provide appropriate
design and operating safeguards to minimize the risks associate d with t heir
applications and products.
NXP Semiconductors does not accept any liabil i ty related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the appl ication or use by customer’s
third party custo m er(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms an d conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter m s and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or the gr ant,
conveyance or implication of any license under any copyrights, patents or
other industrial or inte llectual property right s.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains dat a from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
74LVC2G53 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 6 — 27 September 2010 27 of 28
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
15.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respective ow ners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74LVC2G53
2-channel analog multiplexer/demultiplexer
© NXP B.V. 2010. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 27 September 2010
Document identifier: 74LVC2G53
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7 Functional description . . . . . . . . . . . . . . . . . . . 4
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
9 Recommended operating conditions. . . . . . . . 5
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
10.1 Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
10.2 ON resistance. . . . . . . . . . . . . . . . . . . . . . . . . . 7
10.3 ON resistance test circuit and graphs. . . . . . . . 8
11 Dynamic characteristics . . . . . . . . . . . . . . . . . 11
11.1 Waveforms and test circuits . . . . . . . . . . . . . . 12
11.2 Additional dynamic characteristics . . . . . . . . . 14
11.3 Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 25
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 25
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 26
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 26
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 26
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 27
16 Contact information. . . . . . . . . . . . . . . . . . . . . 27
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28