Am27C400 4 Megabit (524,288 x 8-Bit/262,144 x 16-Bit) ROM Compatible CMOS EPROM DISTINCTIVE CHARACTERISTICS @ Fast access time 100 ns @ Low power consumption 100 HA maximum CMOS standby current @ Industry standard pinout: ROM compatible 44-pin LCC, and PLCC packages provide easy upgrade to 8 Mbits, DIP upgrades require a 40- to 42-pin conversion GENERAL DESCRIPTION The Am27C400 is a 4 Mbit ultraviolet erasable program- mable read-only memory that is functionally and pinout compatible with 4 Mbit masked ROMs. Under control of the BYTE input, the memory canbe configured as either a512K by 8-bit memory or a 256K by 16-bit memory. It operates from a single +5 V supply, has a static standby mode, and features fast single address location pro- gramming. Products are available in windowed ceramic packages as well as plastic one time programmable (OTP) packages for both through hole and surface mount applications. Typically, any byte can be accessed in less than 100 ns, allowing operation with high-performance microproces- sors without any WAIT states. The Am27C400 offers al Advanced Micro Devices @ Single +5 V power supply mM +10% power supply tolerance standard on most speeds @ 100% Flashrite programming Typical programming time of 32 seconds @ Latch-up protected to 100 mA from 1 V to Vec+1V B High noise immunity separate Output Enable (OE) and Chip Enable (CE) controls, thus eliminating bus contention in a multiple bus microprocessor system. AMD's CMOS process technology provides high speed, low power, and high noise immunity. Typical power con- sumption is only 150 mW in active mode, and 100 wW in standby mode. All signals are TTL levels, including programming sig- nals. Bit locations may be programmed singly, in blocks, or at random. The Am27C400 supports AMDs Flash- rite programming algorithm (100 us pulses) resulting in typical programming times of 32 seconds. Oo Voc OE Output Enable _ Chip Enable BYTE and CE/PGM ic AB Y Decoder A0-A17 Address Inputs X Decoder Data Outputs DQo0-DQ15 Orhan aaa) Output Buffers 4,194,304-Bit Cell Matrix 15573B-1 Publication# 15573 Rev.B Amendment/0 Issue Date: July 1993 2-121al AMD PRODUCT SELECTOR GUIDE Family Part No. Am27C400 Ordering Part No: Vec 5% -105 -125 -255 Veco + 10% -100 ~120 -150 -200 -250 Max Access Time (ns) 100 120 150 200 250 CE (E) Access Time (ns) 100 120 150 200 250 OE (G) Access Time (ns) 50 50 65 75 100 CONNECTION DIAGRAM Top View DIP PLCC/LCC A71 * aofJa8 hm on A7 (2 39[_] ag Z2LEEgSSSeezg As (-]3 38[] Ato Bee SS AS ((]4 377] A114 a4 [7 e 39 []A12 A4 C5 36[_] A12 a3 Ts 3af] A13 A3 ([J6 35, A13 A2[]o 37 L a14 A2 (_]7 34f_] A14 Ai [10 36] ] A15 A1 [18 33[_] A15 Ao (11 35[] A16 Ao [C]o 32[__] A16 Pom (PCE (E) [12 34[] BYTE/Vee PGM(P)/CEE) [J 10 31|{_] BYTE/pp Ves [13 33[] Vss Vss [411 30[_] Vss OE () [14 32[] Da15/AB OE(G) [_]12 29[_] DQ15/AB pao [15 31{] 07 pao [7113 28f_] DQ7 bas []16 30[] Da14 bas [_}14 27] Da14 oat [417 29f] Das pat (C415 26f_] Das \__18 19 20 21 22 23 24 25 26 27 28 / ss73p-3 pag] 16 25{_] 0a13 BSfGRESBSEESE pa2 (417 24{__] Das aesogog 79858 paio[~]18 23[-_] Dat2 bas [~] 19 22 [__] Da4 pa11C_]20 21] Vcc 15573B-2 Notes: 1. Inner ring of numbers correspond to the package pins 2. JEDEC nomenciature is in parenthesis PIN DESIGNATIONS _ LOGIC SYMBOL AB = Address Input (BYTE Mode) A0-A17 = Address Inputs TAB BYTE = Byte/Word Switch PD Ao-A17 CE (E)/PGM (P) = Chip Enable and Program Enable Inputs 16 DQ0-DQ15 = Data Inputs/Outputs PA0-Dats cr NC = No Internal Connection *] PGM (P)/CE (E) or8 OE (G) = Output Enable Input SEG) Vcc = Vcc Supply Voltage Vpp = Program Supply Voltage " BYTE Vss = Ground 15573B-4 2-122 Am27C400AMD ol ORDERING INFORMATION EPROM Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM27C400 -100 D Cc B Lt OPTIONAL PROCESSING Blank = Standard processing B = Burn-in TEMPERATURE RANGE C = Commercial (0C to +70C) | Industrial (40C to +85C) E = Extended Commercial (~55C to +125C) PACKAGE TYPE D = 40-Pin Ceramic DIP (CDV040) L = 44-Pin Leadless Chip Carrier (CLV044) SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER/DESCRIPTION Am27C400 4 Megabit (524,288 x 8-Bit/262,144 x 16-Bit) CMOS EPROM Valid Combinations Valid Combinations AM27C400-100 | DC. DCB. DI. DIB Valid Combinations list configurations planned to be LC. LCB ul LIB , supported in volume for this device. Consult the lo- AM27C400-105 _ cal AMD sales office to confirm availability of specific AM27C400-120 valid combinations and to check on newly released AM27C400-125 DC, DCB, DI, DIB, combinations. AM27C400-150_| LC, LCB, LI, LIB AM27C400-200_| DE. DEB, LE, LEB AM27C400-255 Am27C400 2-123&1 amo ORDERING INFORMATION OTP Products AMD standard products are available in several formed by a combination of: AM27C400 -120 {70 packages and operating ranges. The order number (Valid Combination) is Lo OPTIONAL PROCESSING Blank = Standard processing TEMPERATURE RANGE C = Commercial (0C to +70C) 1 = Industrial (-40C to +80C) PACKAGE TYPE P = 40-Pin Plastic DIP (PD 040) J = 44-Pin Rectangular Plastic Leaded Chip Carrier (PL 044) Am27C400 SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER/DESCRIPTION 4 Megabit (524,288 x 8-Bit/262,144 x 16-Bit) CMOS OTP EPROM Valid Combinations AM27C400-120 AM27C400-125 AM27C400-150 PC, JC, PI, Ji AM27C400-200 AM27C 400-255 Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Group A Tests Group A tests consist of Subgroups 1, 2, 3, 7, 8, 9, 10, 11. 2-124 Am27C400ORDERING INFORMATION Military APL Products AMD al AMD products for Aerospace and Defense applications are available in several packages and operating ranges. APL (Approved Products List) products are fully compliant with MIL-STD-883 requirements. The order number (Valid Combination) is formed by a combination of: AM27C400 -150 /B X A | LEAD FINISH A = Hot Solder Dip PACKAGE TYPE X = 40-Pin Ceramic DIP (CDV040) U = 44-Pin Leadless Chip Carrier (CLV040) DEVICE CLASS /B = ClassB SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER Am27C400 4 Megabit (524,288 x 8/262,144 x 16) CMOS UV EPROM Valid Combinations Valid Combinations AM27C400-120 AM27C400-150 AM27C400-200 AM27C400-250 Valid Combinations list configurations planned to be supported in volume for this device. Consult /BUA, /BXA the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Group A Tests Group A tests consist of Subgroups 1, 2, 3, 7, 8, 9, 10, 11. Am27C400 2-125cl AMD FUNCTIONAL DESCRIPTION Erasing the Am27C400 In order to clear all locations of their programmed con- tents, it is necessary to expose the Am27C400 to an ultraviolet light source. A dosage of 15 W seconds/cm2 is required to completely erase an Am27C400. This dos- age can be obtained by exposure to an ultraviolet lamp wavelength of 2,537 Awith intensity of 12,000 pW/ cm? for 15 to 20 minutes. The Am27C400 should be di- rectly under and about one inch from the source and all filters should be removed from the UV light source prior to erasure. it is important to note that the Am27C400 and similar devices will erase with light sources having wavelengths shorter than 4000 A. Although erasure times will be much longer than with UV sources at 2,537A, exposure to fluorescent light and sunlight will eventually erase the Am27C400 and exposure to them should be prevented to realize maximum system reliability. f used in such an environment, the package window should be covered by an opaque label or substance. Programming the Am27C400 Upon delivery or after each erasure the Am27C400 has all 4,194,304 bits in the ONE or HIGH state. ZEROs are loaded into the Am27C400 through the procedure of programming. The programming mode is entered when 12.75 + 0.25 V is applied to the Vpp pin, CE/PGM is at Vi_,and OE is at Vin . For programming, the data to be programmed is applied 16 bits in parallel to the data output pins. The Flashrite algorithm reduces programming time by using 100 ys programming pulses and by giving each addresss only as many pulses as is necessary in order to reliably program the data. After each pulse is applied to a given address, the data in that address is verified. If the data does not verify, additional pulses are given until it verifies or the maximum is reached. This process is re- peated while sequencing through each address of the Am27C400. This part of the algorithm is done at Vcc = 6.25 V to assure that each EPROM bit is programmed to a sufficiently high threshold voltage. After the final ad- dress is completed, the entire EPROM memory is veri- fied at Voc = Vep = 5.25 V. Please refer to Section 6.0 for programming and flow chart characteristics. Program Inhibit Programming of multiple Am27C400s in parallel with different data is also easily accomplished. Except for CE/PGM, all like inputs of the parallel AmM27C400 may be common. A TTL low-level program pulse applied to an Am27C400 CE/PGM input with Vpp = 12.75 V+ 0.25 V, and OE HIGH will program that Am27C400. A high- level CE/PGM input inhibits the other Am27C400 de- vices from being programmed. Program Verify A verify should be performed on the programmed bits to determine that they were correctly programmed. The verify should be performed with OE at Vi_, CE/PGM at Vin and Vpp between 12.5 V and 13.0 V. Auto Select Mode The auto select mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25C + 5C ambient temperature range that is required when programming the Am27C400. To activate this mode, the programming equipment must force 12.0 V + 0.5 V on address line AQ of the Am27C400. Two identifier bytes may then be se- quenced from the device outputs by toggling address line AO from Vit to Vin. All other address lines must be heid at Vi. during auto select mode. Byte 0 (A0 = Vi) represents the manufacturer code, and Byte 1 (AO = Vin), the device identifier code. For the Am27C400, these two identifier bytes are given in the Mode Select table. All identifiers for manufacturer and device codes will possess odd parity, with the MSB (DQ7) defined as the parity bit. Read Mode The Am27C400 has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip Enable (CE/PGM) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (tacc ) is equal to the delay from CE/PGM to output (tce). Data is available at the outputs toe after the falling edge of OE, assuming that CE/PGM has been LOW and addresses have been stable for at least tacctoe. Byte Mode The user has the option of reading data in either 16-bit words or 8-bit bytes under control of the BYTE input. With the BYTE input HIGH, inputs AOA17 will address 256K words of 16-bit data. When the BYTE input is LOW, AB functions as the least significant address input and 512K bytes of data can be accessed. The 8 bits of data will appear on DQO0-DQ7. 2-126 Am27C400Standby Mode The Am27C400 has a CMOS standby mode which re- duces the maximum Vcc current to 100 A. it is placed in CMOS-standby when CE/PGM is at Voc + 0.3 V. The Am27C400 also has a TTL-standby mode which re- duces the maximum Vcc current to 1.0 mA. itis placed in TTL-standby when CE/PGM is at Vin, When in standby mode, the outputs are in a high-impedance state, inde- pendent of the OE input. Output OR-Tieing To accommodate multiple memory connections, a two- line control function is provided to allow for: m Low memory power dissipation m@ Assurance that output bus contention will not occur It is recommended that CE/PGM be decoded and used as the primary device-selecting function, while OE be made a common connection to all devices in the array and connected to the READ line fromthe system control AMD cl bus. This assures that all deselected memory devices are in their low-power standby mode and that the output pins are only active when data is desired from a particu- lar memory device. System Applications During the switch between active and standby condi- tions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the out- put capacitance loading of the device. Ata minimum, a 0.1 WF ceramic capacitor (high frequency, low inherent inductance) should be used on each device between Vec and Vss to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive ef- fects of the printed circuit board traces on EPROM ar- rays, a 4.7 uF bulk electrolytic capacitor should be used between Vcc and Vss for each eight devices. The loca- tion of the capacitor should be close to where the power supply is connected to the array. MODE SELECT TABLE Mode Pins CE/PGM OE AO AQ Vpp Outputs Read . ViL VIL X X X Dout Output Disable Vit VIH X X X Hi-Z Standby (TTL) VIH X X X X Hi-Z Standby (CMOS) Veco +0.3V X X X X Hi-Z Program Vit VIH X X Vpp DIN Program Verify VIH VIL X X Vpp Dout Program Inhibit VIH VIH X X Vpp Hi-Z Auto Select | Manufacturer Code VIL VIL Vit Vy X O1H (Note 3) Device Code VIL VIL Vid Vu X 9DH Notes: 1. Va=120VL05V 2. X = Either Vw or Vi. 3. A1-A8 = AO-A17 = Vi, Am27C400 2-127cl AMD ABSOLUTE MAXIMUM RATINGS Storage Temperature OTP Products ............... 65C to +125C All Other Products ............ -65C to +150C Ambient Temperature with Power Applied ............. 55C to +125C Voltage with Respect To Vss All pins except A9,Vpp,Vcc . -0.6 Vto Vcc + 0.6 V AQand Vpp_ .............05. -0.6 V to +13.5V Voo oo. ee eee eee 0.6 V to +7.0 V Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During transitions, the inputs may overshoot Vss to -2.0 V for pe- riods of up to 20 ns. Maximum DC voltage on input and I/O pins is Vcc + 0.5 V which may overshoot to Vcc + 2.0 V for periods up to 20ns. 2. For AQ and Vpp the minimum DC input is -0.5 V. During transitions, AQ and Vep may overshoot Vss to 2.0 V for periods of up to 20 ns. A9 and Vpp must not exceed 13.5 V for any period of time. Stresses above those listed under Absolute Maximum Rat- ings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. Exposure of the device to absolute maximum rating conditions for ex- tended periods may affect device reliability. OPERATING RANGES Commercial (C) Devices Case Temperature (Tc).......... 0C to +70C Industrial (1) Devices Case Temperature (Tc) ........ 40C to +85C Extended Commercial (E) Devices Case Temperature (Tc)....... 55C to +125C Military (M) Devices Case Temperature (Tc)....... 55C to +125C Supply Read Voltages Vcc for Am27C400-XX5 ..... +4.75 V to +5.25 V Vcc for AmM27C400-XX0 ..... +4.50 V to +5.50 V Operating ranges define those limits between which the func- tionality of the device is guaranteed. 2-128 Am27C400AMD al DC CHARACTERISTICS over operating range unless otherwise specified. (Notes 1, 2, 3 and 4) (for APL Products, Group A, Subgroups 1, 2, 3, 6 and 7 are tested unless otherwise noted) Parameter Symbol Parameter Description Test Conditions Min Max Unit VoH Output HIGH Voltage loH = 400 pA 2.4 Vv VoL Output LOW Voltage lo. = 2.1 mA 0.45 Vv ViH Input HIGH Voltage 2.0 Vec + 0.5 Vv Vit Input LOW Voltage -0.5 +0.8 Vv tu Input Load Current VIN = 0 V to +Vcc 1.0 pA ILo Output Leakage Current VouT = 0 V to +Vcc 5.0 pA icc Vec Active Current CE = Vit, f = 5 MHz, C/l Devices 40 mA (Note 3) louT =O mA E/M Devices 60 Icc2 Vec TTL Standby Current | CE = Vin 1.0 mA Iocs Vcc CMOS Standby Current | CE = Vcc + 0.3 V 100 pA IPP Vpp Current During Read CE = OE = Vit, Ver = Voc 100 pA Notes: 1. Vec must be applied simultaneously or before Vpp, and removed simultaneously or after Vpp. Icc1 is tested with OE/Vpp = Vin to simulate open outputs. 2. Caution: The Am27C400 must not be removed from (or inserted into) a socket when Vcc or Vpp is applied. 3. 4 - Minimum DC Input Voltage is -0.5 V. During transitions, the inputs may overshoot to -2.0 V for periods less than 20 ns. Maximum DC Voltage on output pins is Vcc + 0.5 V, which may overshoot to Vcc + 2.0 V for periods less than 20 ns. 35 30 30 28 IN. 5 7 5 N Ee 24 Se DN o E 25 > o E 26 x e* LA] as DN a 20 a 24 NX 15 22 1 2 3 4 5 6 7 8 9 10 ~75 -50 -25 0 25 50 75 100 125 150 Frequency in MHz Temperature in C Figure 1. Typical Supply Current Figure 2. Typical Supply Current vs. Frequency vs. Temperature Vcc = 5.5 V, T = 25C Vcc = 5.5 V, f = 5 MHz 15573B-5 15573B-6 Am27C400 2-1291 amo CAPACITANCE Parameter Test CDV040 CLV044 PD 040 PL 044 Symbol Parameter Description | Conditions Typ | Max | Typ | Max / Typ | Max | Typ | Max | Unit CIN Input Capacitance VIN =0 9 12 9 11 6 8 9 11 pF Cout Output Capacitance VouT =0 12 15 13 15 9 11 13 15 pF Notes: 1. This parameter is only sampled and not 100% tested. 2. Ta = +25C, f = 1 MHz. SWITCHING CHARACTERISTICS over operating ranges unless otherwise specified (Notes 1, 3 and 4) (for APL Products, Group A, Subgroups 9, 10 and 11 are tested unless otherwise noted) Parameter Am27C400 Symbols Parameter Test -105 | -125 | -155 JEDEC | Standard | Description Conditions -100 | -120 | -150 | -200 | -255 | Unit tavav tacc Address to CE = OE = Min = = - = = Output Delay Vit Max | 100 | 120 {| 150 200 | 250 ns tELav tce Chip Enable to OE = VIL Min = = - = = Output Delay Max } 100 | 120 {| 150 | 200 | 250 ns teLav tOE Output Enable to CE = VIL Min = = = = = Output Delay Max | 50 50 55 60 75 ns tEHaQZ, tDF Chip Enable HIGH or Min | = = = = 1GHQZ (Note 2) | Output Enable HIGH, Max | 30 30 30 40 60 ns whichever comes first, to Output Float taxQx tOH Output Hold from Min 0 0 0 0 0 Addresses, CE, Max - - ~ ~ ~ ns or OE, whichever occurred first Notes: 1. Vcc must be applied simultaneously or before Vep, and removed simultaneously or after Vpp. This parameter is only sampled and not 100% tested. 2 3. Caution: The Am27C400 must not be removed from (or inserted into) a socket or board when Vpp or Vec is applied. 4. Output Load: 1 TTL gate and Cy = 100 pF Input Rise and Fall Times: 20 ns Input Pulse Levels: 0.45 V to 2.4 V Timing Measurement Reference Level: 0.8 V and 2 V for inputs and outputs. 2-130 Am27C400AMD al SWITCHING TEST CIRCUIT Device 2.7 kQ Under Test Diodes = IN3064 or Equivalent 15573B-7 CL = 100 pF including jig capacitance SWITCHING TEST WAVEFORM 2.4V 2.0V 2.0V Test Points . 0.8 V 0.8V 0.45 V Input Output 15573B-8 AC Testing: Inputs are driven at 2.4 V for a logic 1 and 0.45 for a logic 0. Input pulse rise and fall times are < 20 ns. Am27C400 2-131al AMD KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must Be Will Be Steady Steady May Will Be Change Changing from H to L from H to L May Will Be Change Changing from L to H from L to H Dont Care, Changing, Any Change State Permitted Unknown Does Not Center Apply Line is High Impedance Off State ; KS0000 10 SWITCHING WAVEFORMS 2 | | Addresses i 2.0 Addresses Valid 20K 0.45 +_0.8 0.85 _________ _~_ CE/PGM \i +__ tte - - OE \ F f = a _ {DF tace toe as | (Note 2) (Note 1) _ tOH em] High Z High Z output (i ))) Notes: 15573B-9 1. OE may be delayed up to tacc toe after the falling edge of the addresses without impact on tacc. 2. tor is specified from OE or CE, whichever occurs first. 2-132 Am27C400