17-8741-226 - 3M - Datasheet.Live

Products and specifications discussed herein are subject to change by Micron without notice.

512MB (SR), 1GB (DR): (x64) 168-Pin SDRAM UDIMM

Features

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Synchronous DRAM Module

MT8LSDT6464A – 512MB

MT16LSDT12864A – 1GB

For the latest data sheet, refer to Micron’s Web site: www.micron.com/products/modules.

Features

• PC100- and PC133-compliant

• 168-pin, dual in-line memory module (DIMM)

• Utilizes 125 MHz and 133 MHz SDRAM

components

• Unbuffered

• 512MB (64 Meg x 64), 1GB (128 Meg x 64)

• Si n gle +3.3V po wer supply

• Fully synchr onous; all signals registere d on positive

edge of system clock

• Internal pipelined operation; column addres s can

be changed every clock cycle

• Internal SDRAM banks for hiding row access/

precharge

• Programmable burst lengths: 1, 2, 4, 8, or full page

• Auto precharge, including concurrent auto

precharge, and auto refresh modes

• 64ms, 8,192 cycle auto refresh cycle

• Self refresh mode

• LVTTL-compatible inputs and outputs

• Seri a l presence-detect (SP D)

• Gold edge contacts

Table 1: Timing Parameters

Module

Marking Clock

Frequency

Access Time Setup

Time Hold

TimeCL = 2 CL = 3

-13E 133 MHz 5.4ns – 1.5 0.8

-133 133 MHz – 5.4ns 1.5 0.8

Figure 1: 168-Pin DIMM (MO–161)

Notes: 1. Contact Micron for product availability.

Options Marking

•Package

168-pin DIMM (standard) G

168-pin DIMM (lead-free) Y1

• Memory Clock/CAS Latency

(133 MHz)/CL = 2 -13E

(133 MHz)/CL = 3 -133

•PCB

St andard 1.375in. (34.93mm) See note 1 on

page 2

Low-Profile 1.125in. (28.58mm) See note 1 on

page 2

Standard 1.375in. (34.925mm)

Low Profile 1.125in. (28.575mm)

Table 2: Address Table

Parameter 512MB 1GB

Refresh Count 8K 8K

Device Banks 4 (BA0, BA1) 4 (BA0, BA1)

Device Co nfiguration 512Mb (64 Meg x 8) 512Mb (64 Meg x 8)

Row Addressing 8K (A0–A12) 8K (A0–A12)

Column Addressing 2K (A0–A9, A11) 2K (A0–A9, A11)

Module Ranks 1 (S0#,S2#) 2 (S0#, S2#; S1#, S3#)

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512MB (SR), 1GB (DR): (x64) 168-Pin SDRAM UDIMM

Features

Notes: 1. The designators for component and PCB re vision are the last two characters of each part

number. Consult fac tory for current revis ion c odes. Example: MT8LSDT6464AG-133B1.

Table 3: Part Numbers

Part Numbers Module Density Configuration System

Bus Speed

MT8LSDT6464AG-13E_ 512MB 64 Meg x 64 133 MHz

MT8LSDT6464AY-13E_ 512MB 64 Meg x 64 133 MHz

MT8LSDT6464AG-133_ 512MB 64 Meg x 64 133 MHz

MT8LSDT6464AY-133_ 512MB 64 Meg x 64 133 MHz

MT16LSDT12864AG-13E_ 1GB 128 Meg x 64 133 MHz

MT16LSDT12864AY-13E_ 1GB 128 Meg x 64 133 MHz

MT16LSDT12864AG-133_ 1GB 128 Meg x 64 133 MHz

MT16LSDT12864AY-133_ 1GB 128 Meg x 64 133 MHz

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512MB (SR), 1GB (DR): (x64) 168-Pin SDRAM UDIMM

Pin Assignments and Descriptions

Figure 2: Pin Locations (168-Pin DIMM)

Table 4: Pin Assignment

168-Pin DIMM Front 168-Pin DIMM Back

Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol

SS 22 NC 43 VSS 64 VSS 85 VSS 106 NC 127 VSS 148 VSS

2DQ023 VSS 44 NC 65 DQ21 86 DQ32 107 VSS 128 CKE0 149 DQ53

3DQ124 NC 45 S2# 66 DQ22 87 DQ33 108 NC 129 S3# 150 DQ54

4DQ225 NC 46 DQMB2 67 DQ23 88 DQ34 109 NC 130 DQMB6 151 DQ55

5DQ326 VDD 47 DQMB3 68 VSS 89 DQ35 110 VDD 131 DQMB7 152 VSS

6VDD 27 WE# 48 NC 69 DQ24 90 VDD 111CAS#132 NC 153 DQ56

7DQ428 DQMB0 49 VDD 70 DQ25 91 DQ36 112 DQMB4 133 VDD 154 DQ57

8DQ529 DQMB1 50 NC 71 DQ26 92 DQ37 113 DQMB5 134 NC 155 DQ58

9DQ630 S0# 51 NC 72 DQ27 93 DQ38 114 S1# 135 NC 156 DQ59

10 DQ7 31 NC 52 NC 73 VDD 94 DQ39 115RAS#136 NC 157 VDD

11 DQ8 32 VSS 53 NC 74 DQ28 95 DQ40 116 VSS 137 NC 158 DQ60

12 VSS 33 A0 54 VSS 75 DQ29 96 VSS 117A1138VSS 159 DQ61

13 DQ9 34 A2 55 DQ16 76 DQ30 97 DQ41 118 A3 139 DQ48 160 DQ62

14 DQ10 35 A4 56 DQ17 77 DQ31 98 DQ42 119 A5 140 DQ49 161 DQ63

15 DQ11 36 A6 57 DQ18 78 VSS 99 DQ43 120 A7 141 DQ50 162 VSS

16 DQ12 37 A8 58 DQ19 79 CK2 100 DQ44 121 A9 142 DQ51 163 CK3

17 DQ13 38 A10 59 VDD 80 NC 101 DQ45 122 BA0 143 VDD 164 NC

18 VDD 39 BA1 60 DQ20 81 NC 102 VDD 123 A11 144 DQ52 165 SA0

19 DQ14 40 VDD 61 NC 82 SDA 103 DQ46 124 VDD 145 NC 166 SA1

20 DQ15 41 VDD 62 NC 83 SCL 104 DQ47 125 CK1 146 NC 167 SA2

21 NC 42 CK0 63 CKE1 84 VDD 105 NC 126 A12 147 NC 168 VDD

Front View

Back View (Populated only for 1GB module)

Indicates a V

PIN 1 PIN 41 PIN 84

PIN 85

PIN125

PIN 168

U1 U2 U3 U4 U6 U7 U8 U9

U10

U11 U12 U13 U14 U16 U17 U18 U19

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512MB (SR), 1GB (DR): (x64) 168-Pin SDRAM UDIMM

Pin Assignments and Descriptions

Table 5: Pin Descriptions

Pin numbers may not correlate with symbols. Refer to Table 4 on page 3 for pin number and symbol

information.

Pin Numbers Symbol Type Description

27, 111, 115 RAS#, CAS#,

WE# Input C ommand inputs: RAS# , CAS#, and WE# (along with S#) define the

command being entered.

42, 79, 125, 163 CK0–CK3 Input Clock: CK is driven by the system clock. All SDRAM input signals are

sampled on the positive edge of CK. CK also increments the internal

burst counter and controls the output registers.

63, 128 CKE0, CKE1 Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the CK

signal. Deactivating the clock provides PRECHARGE POWER-DOWN

and SELF REFRESH operation (all device banks idle) or CLOCK

SUSPEND OPERATION (burst access in progress). CKE is synchronous

except after the device enters power- down and self refresh modes,

where CKE becomes asynchronous until after exiting the same

mode. The inp ut buffers, including CK, are disabled during power-

down and self refresh modes, providing low standby power.

30, 45,114, 129 S0#–S3# Input Chip select: S# enables (registered LOW) and disables (registered

HIGH) the command decoder. A ll commands are masked when S# is

registered HIGH. S# is considered part of the command code.

28, 29, 46, 47, 112, 113,

130, 131 DQMB0–

DQMB7 Input Input/Outp ut mask: DQMB is an input mask signal for write accesses

and an output enable signal for read accesses. Input data is masked

when DQMB is sampled HIGH during a WRITE cycle. The output

buffers are placed in a High-Z state (two-clock latency) when DQMB

is sampled HIGH during a READ cycle.

39, 122 BA0, BA1 Input Bank address: BA0 and BA1 define to which device bank the

ACTIVE, READ, WRITE, or PRECHARGE command is being applied.

33–38, 117–121, 123, 126 A0–A12 Input Address inputs: Provide the row address for ACTIVE commands, and

the column address and auto precharge bit (A10 ) for READ/WRITE

commands, to select one location out of the memory array in the

respective device bank. A10 sampled during a PRECHARGE

command determines whether the PRECHARGE applies to one

device bank (A10 LOW, device bank selected by BA0, BA1) or all

device banks (A10 HIGH). The address inputs also provide the op-

code during a MODE REGISTER SET command.

83 SCL Input Serial clock for presence-detect: SCL is used to synchronize the

presence-detect data transfer to and from the module.

165–167 SA0–SA2 Input Presence-Detect address Inputs: These pins are used to configure the

presence-detect device.

2–5, 7–11, 13–17, 19–20,

55–58, 60, 65–67, 69–72,

74–77, 86–89, 91–95,

97–101, 103–104, 139–142,

144, 149–151,

153–156,158–161

DQ0–DQ63 Input/

Output Data I/O: Data bus.

82 SDA Input/

Output Serial presence-detect data: SDA is a bidirect ional pin used to

transfer addresses and data into and out of the presence-det ect

portion of the module.

6, 18, 26, 40, 41, 49, 59, 73,

84, 90, 102, 110, 124, 133,

143, 157, 168

VDD Supply Power supply: +3.3V ±0.3V.

1, 12, 23, 32, 43, 54, 64, 68,

78, 85, 96, 107, 116, 127,

138, 148,. 152, 162

VSS Supply Ground.

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512MB (SR), 1GB (DR): (x64) 168-Pin SDRAM UDIMM

Functional Block Diagrams

All resistor values are 10Ω unless otherwise spec ifi e d.

Per industry standard, Micron modules use various component speed grades as refer-

enced in the modu le part numberi n g gui de at: www.micron.com/numberguide.

Standard modules use the following SDRAM devices: MT48LC64M8A2TG. Lead-free

modules use the following SDRAM devices: MT48LC64M8A2P.

Figure 3: Single Rank

21–22, 24–25, 31, 44, 48,

50–53, 61–62, 80, 81,

105–106, 108–109, 132,

134–137, 145–147, 164

NC – Not connected: These pins are not connected on these modules.

Table 5: Pin Descriptions (continued)

Pin numbers may not correlate with symbols. Refer to Table 4 on page 3 for pin number and symbol

information.

Pin Numbers Symbol Type Description

DQM CS#

SA0

SPD

SDA

SA1

SA2

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQMB7

DQM CS#

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQMB6

DQM CS#

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQMB5

DQM CS#

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQMB4

DQM CS#

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQMB3

DQM CS#

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQMB2

DQM CS#

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQMB1

DQM CS#

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQMB0

S2#

S0#

RAS#

CAS#

CKE0

WE#

RAS#: SDRAMs

CAS#: SDRAMs

CKE0: SDRAMs

WE#: SDRAMs

A0-A12: SDRAMs

BA0: SDRAMs

BA1: SDRAMs

A0-A12

BA0

BA1

VDD

VSS

SDRAMs

10pF

CK1,

CK3

CK0

CK2

3.3pF

SCL

WP U10

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512MB (SR), 1GB (DR): (x64) 168-Pin SDRAM UDIMM

Functional Block Diagrams

Figure 4: Dual Rank

DQM CS#

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQMB7

DQM CS#

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQMB6

DQM CS#

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQMB5

DQM CS#

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQMB4

DQM CS#

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQMB3

DQM CS#

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQMB2

DQM CS#

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQMB1

DQM CS#

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQMB0

S2#

S0#

DQM CS#

U12

DQM CS#

U14

DQM CS#

U16

DQM CS#

U18

S1#

DQM CS#

U11

DQM CS#

U13

DQM CS#

U17

DQM CS#

U19

S3#

SA0

SPD

SDA

SA1

SA2

CKE1

CKE0

CAS#

RAS#

WE#

CKE: SDRAMs U11-U19

CKE: SDRAMs U1-U9

CAS#: SDRAMs

RAS#: SDRAMs

WE#: SDRAMs

A0-A12: SDRAMs

BA0: SDRAMs

BA1: SDRAMs

A0-A12

BA0

BA1

SDRAMs

10K Ω

SCL

WP U10

CK0

CK2

3.3pF

U11

U12

U13

U14

CK3

3.3pF

U15

U16

U17

U18

U19

CK1

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512MB (SR), 1GB (DR): (x64) 168-Pin SDRAM UDIMM

General Description

The MT8LSDT6464A and MT16LSDT12864A are high-speed CMOS, dynamic random-

access, 512MB and 1GB memory modules organized in a x64 configuration. These mod-

ules use internally configured quad-bank SDRAMs with a synchronous interface (all sig-

nals are registe red on the positive ed ge of the clock signals CK).

Read and write accesses to SDRAM modules are burst oriented; accesses start at a

selected location and continue for a pr ogramme d number of locations in a progr ammed

sequence. Accesses beg in with the registration of an ACTIVE command, which is then

followed by a READ or WRITE command. The address bits registered coincident with the

ACTIVE command are used to select the de vice bank and row to be accessed (BA0, BA1

select the device bank, A0–A11 select the device row). The address bits registered coinci-

dent with the READ or WRITE command are used to select the starting column location

for the burst access.

The modules provide for programmable READ or WRITE burst lengths of 1, 2, 4, or 8

locations, or the full page, with a burst terminate option. An AUTO PRECHARGE func-

tion may be enabled to provide a self-timed row precharge that is initiated at the end of

the burst seque nce.

SDRAM modules use an internal pipelined architecture to achieve high-speed opera-

tion. This architecture is compatible with the 2n rule of prefetch architectures, but it also

allows the column address to be changed on every clock cycle to achieve a high-speed,

fully random acce ss . P recharg ing one devi ce bank while acc essing one of the other three

device banks will hide the precharge cycles and provide seamless, high-speed, random-

access operation.

SDRAM modules are designed to operate in 3.3V, low-power memory systems. An auto

refresh mode is provided, along with a power-s aving, power-down mode . All inp uts a nd

outputs are LV TTL-compatible.

SDRAM modules offer substanti al adva nces in DRAM oper ating performance , inc luding

the ability to synchronously burst data at a high data rate with automatic column-

address generation, the ability to interleave between internal banks in order to hide pre-

charge time and the capability to randomly change column addresses on each clock

cycle during a burst access. For more information regarding SDRAM operation, refer to

the 512Mb SDRAM component data sheets.

Serial Presence-Detect Op eration

SDRAM modules incorpor ate serial pr esence-detec t (SPD). The SPD function is imple-

mented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes.

The first 128 bytes can be programmed by Micron to identify the module type and vari-

ous SDRAM organizations and timing parameters. The remaining 128 bytes of storage

are available for use b y the customer. System READ/WRITE oper ations between the

master (system logic) and the slave EEPROM device (DIMM) occur via a standard I2C

bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which

pro vide eight unique DIMM/EEPR OM addresses . Write protect (WP) is tied to ground on

the module, permanently disabling hardware write protect.

Initialization SDRAMs must be powered up and initialized in a predefined manner. Operational pr o-

cedures other than those specified may result in undefined operation. Once power is

applied to VDD and VDDQ (simultaneously) and the clock is stable (stable clock is

defined as a signal cycling within timing constraints specified for the clock pin), the

SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND

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512MB (SR), 1GB (DR): (x64) 168-Pin SDRAM UDIMM

Mode Register Definition

INHIBIT or NOP. St arting at some point during this 100µs period and continuing at least

through the end of this pe riod, C O MMAND INHIBIT or NOP commands should be

applied.

Once the 100µs delay has been satisfied wi th at least one COMMAND INHIBIT or NOP

command having been applied, a PRECHARGE command should be applied. All devic e

banks must then be pr echarged, thereby placing the device in the all banks idle state.

Once in the idle state, two AUTO refresh cycles must be perf ormed. After the AUTO

refresh cycles are complete, the SDRAM is ready for mode register programming.

Because the mode re gister will power up in an unknown state, it should be loaded prior

to applying any operational command.

Mode Register Definition

The mode register is used to define the specific mode of operation of the SDRAM. This

definition includes the selection of a burst length, a burst type, a CAS latency, an operat-

ing mode and a write burst mode, as shown in the Mode Register Definition Diagram.

The mode register is programmed via the LOAD MODE REGISTER command and will

retain the stored information until it is programmed again or the device loses power.

Mode r egister bits M0–M2 specify the burst length, M3 specifies the type of burst

(sequential or interleaved), M4–M6 specify the CAS latency, M7 and M8 specify the oper-

ating mode, M9 specifies the write burst mode, and M10 and M11 are r eserved for future

use.

The mode regi ster must be loaded when all device banks ar e idle, and the contro ller

must wait the specified time before initiating the subsequent operation. Violating either

of these requi rements will resul t in unspecified operation.

Burst Length Read and write accesses to the SDRAM are burst oriented, with the burst le ng th being

programmable, as shown in Mode Register Definition Diagram. The burst length deter-

mines the maximum number of column locations that can be accessed for a given READ

or WRITE command. Burst lengths of 1, 2, 4, or 8 locations are available for both the

sequential and the interleaved burst types, and a full-page burst is available for the

sequential type. The full-page burst is used in conjunction with the BURST TERMINATE

command to generate arbitrary burst lengths.

Reserved states should not be used, as unknown operation or incompatibility with

future versions may result.

When a READ or WRITE comm and is issu ed , a block of col u m n s eq ual to the bu rst

length is effectivel y selected. All accesses for that burst take place within this block,

meaning that the burst will wrap within the block if a boundary is reached, as sho wn in

Table 6 on page 10. The block is uniquely selected by A1–A9 when BL = 2; by A2–A9 when

BL = 4; and by A3–A9 when BL = 8. The remaining (least significant) address bit(s) is (ar e)

used to select the starting location within the block. Full-page bursts wrap within the

page if the boundary is reached, as shown in Table 6 on page 10.

Burst Type A ccesses within a gi ven burst may be pr ogrammed to be either sequenti al or interleav ed;

this is referred to as the burst type and is selected via bit M3.

The ordering of accesse s within a burst is determi ned by the burst leng th, the burst type

and the starting column address, as show n in Table 6 on page 10.

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512MB (SR), 1GB (DR): (x64) 168-Pin SDRAM UDIMM

Mode Register Definition

Figure 5: Mode Register Definition Diagram

Reserved

M3 = 0

Reserved

Full Page

M3 = 1

Reserved

Operating Mode

Standard Operation

All Other States Reserved

Defined

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

Burst Length

Burst LengthCAS LatencyBT

A9 A7 A6A5 A4 A3

A8 A2 A1 A0

Mode Register (Mx)

Address Bus

976543

8210

M6–M0

M8 M7

Op Mode

A10

A11

A12

Write Burst Mode

Programmed Burst Length

Single Location Access

Program

M12, M11, M10 = “0, 0, 0”

to ensure compatibility

with future devices.

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512MB (SR), 1GB (DR): (x64) 168-Pin SDRAM UDIMM

Mode Register Definition

Notes: 1. For full-page accesses: y = 2,048.

2. For BL = 2, A1–A9, A11 select the block of two burst ; A0 sel ect s th e sta rti ng co lu mn wi th in

the block.

3. For BL = 4, A2–A9, A11 select the block of four burst; A0–A1 select the starting column

within the block.

4. For BL = 8, A3–A9, A11 select the block of eight burst; A0–A2 select the starting column

within the block.

5. For a full-page burst, the full row is selected and A0–A9, A11 select the starting column.

6. Whenever a boundary of the block is reached within a given sequence above, the follow-

ing access wraps within the block.

7. For BL = 1, A0–A9, A11 select the unique column to be accessed, and mode register bit M3

is ignored.

Table 6: Burst Definition Table

Burst

Length Starting Column

Address

Order of Accesses Within a Burst

Type = Sequential Type = Interle aved

2A0

00-1 0-1

11-0 1-0

A1 A0

0 0 0-1-2-3 0-1-2-3

0 1 1-2-3-0 1-0-3-2

1 0 2-3-0-1 2-3-0-1

1 1 3-0-1-2 3-2-1-0

A2 A1 A0

0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7

0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6

0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5

0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4

1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3

1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2

1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1

1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

Full Page

(y) n = A0–A9, A11

(location 0-y) Cn, Cn+1, Cn+2 Cn+3,

Cn+4...

...Cn-1, Cn... Not Supported

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512MB (SR), 1GB (DR): (x64) 168-Pin SDRAM UDIMM

Mode Register Definition

Figure 6: CAS Latency Diagram

Burst Type A ccesses within a gi ven burst may be pr ogrammed to be either sequenti al or interleav ed;

this is referred to as the burst type and is selected via bit M3.

The ordering of the accesses within a burst is determined by the burst length, the burst

type, and the starting column address, as shown in Table 6 on page 10.

CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ com-

mand and the availability of the first piece of output data. The l atency can be set to two

or three clocks.

If a READ command is registered at clock edge n, and the latency is m clocks, the data

will be available by clock edge n + m. The DQ will start drivin g as a result of the clock

edge one cycle earlier (n + m - 1), and provided that the relevant access times are met,

the data will be valid by clock edge n + m. For example, assuming that the clock cycle

time is such that all relevant access times ar e met, if a READ command is r egister ed at T0

and the latency is programmed to two clocks, the DQ will start driving after T1 and the

data will be valid by T2, as shown in Fi gure 6. Table 7 on page 12, indicates the operating

frequencies at which each CAS latency set ting can b e use d.

Reserved states should not be used as unkno wn operation or incompatibility with future

versions may result.

CLK

T2T1 T3T0

CAS Latency = 3

DOUT

tOH

COMMAND NOPREAD

tAC

NOP

DON’T CARE

UNDEFINED

CLK

T2T1 T3T0

CAS Latency = 2

DOUT

tOH

COMMAND NOPREAD

tAC

NOP

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512MB (SR), 1GB (DR): (x64) 168-Pin SDRAM UDIMM

Mode Register Definition

Operating Mode The normal operating mode is selected by set ting M7 and M8 to zero; the other comb i-

nations of values for M7 and M8 are reserved for future use and/or test modes. The pro-

grammed burst length applies to both READ and WRITE bursts.

Test modes and reserved states should not be used because unknown operation or

incompatibility with future versions may result.

Write Burst Mode When M9 = 0, the burst length programmed via M0–M2 applies to both READ and

WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but

write accesses are single-location (non burst) accesses.

Table 7: CAS Latency Table

Speed

Allowable Operating Clock Frequency (MHz)

CAS Latency = 2 CAS Latency = 3

-13E ≤ 133 ≤ 143

-133 ≤ 100 ≤ 133

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512MB (SR), 1GB (DR): (x64) 168-Pin SDRAM UDIMM

Commands

Commands Table 8 provides a quick reference of available commands. This is followed by a written

description of each command. For a more detailed description of commands and oper-

ations, refer to the 512Mb SDRAM component data sheet.

Notes: 1. A0–A12 provide row address; BA0–BA1 determine which de vice bank is made active.

2. A0–A9, A11 provide column address; A10 HIGH enables the auto-precharge feature (non-

persistent), while A10 LOW disables the auto-precharge feature; BA0–BA1 determine

which device bank is being re a d fr om or writte n to .

3. A10 LOW: BA0–BA1 determine which device bank is being precharged. A10 HIGH: all

device banks are precharged and BA0, BA1 are “Don’t Care.”

4. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.

5. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care”

except for CKE.

6. A0–A11 define the op-code written to the mode register and A12 should be driven LOW.

7. Activates or deactivates the DQ during WRITEs (zero-clock delay) and READs (two-clock

delay).

Table 8: Truth Table – SDRAM Commands and DQMB Operation

CKE is HIGH for all commands shown except SELF REFRESH; notes appear following the Truth Table

Name (Function) CS# RAS# CAS# WE# DQMB ADDR DQ Notes

COMMAND INHIBIT (NOP) HXXX X X X

NO OPERATION (NOP) LHHH X X X

ACTIVE (Select bank and act iva t e ro w) L L H H X Bank/Row X 1

READ (Select bank and column, and start READ burst) LHLHL/HBank/ColX 2

WRITE (Select bank and column, and start WRITE burst) L H L L L/H Bank/Col Valid 2

BURST TERMINATE LHHL X XActive

PRECHARGE (Deactivate row in bank or banks) LLHL X Code X 3

AUTO REFRESH or SELF REFRESH (Enter self refresh

mode) LLLHX X X4, 5

LOAD MODE REGISTER LLLL XOp-codeX 6

Write Enable/Output Enable –––– L –Active7

Write Inhibit/Output High-Z –––– H –High-Z7

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512MB (SR), 1GB (DR): (x64) 168-Pin SDRAM UDIMM

Absolute Maximum Ratings

S tresses gr eater than those listed may cause permanent damage to the device . This is a

stress r ating only, and functional operation of the device at these or any other conditions

above those indicate d in the operational sections of this spe c ification is not implie d.

Exposure to absolute maximum rating conditions for extended periods may affect

reliability.

DC Operating Specifications

Table 9: Absolute Maximum DC Ratings

Parameter Min Max Unit

Voltage on VDD, VDDQ supply relative to V SS -1 +4.6 V

Voltage on inputs NC or I/O pins relative to VSS -1 +4.6 V

Operating temperature TOPR (commercial - ambient) . 0 +65 °C

Storage temperature (plastic) -55 +150 °C

Table 10: DC Electrical Characteristics and Operating Conditions – 512MB

Notes:1, 5, 6; notes appear on page 18; VDD = VDDQ = +3.3V ±0.3V

Parameter/Condition Symbol Min Max Units Notes

Supply voltage VDD, VDDQ3 3.6 V

Input high voltage: Logic 1; All inputs VIH 2VDD + 0.3 V 22

Input low voltage: Logic 0; All inputs VIL -0.3 0.8 V 22

Input leakage current:

Any input 0V ≤ VIN ≤ VDD

(All other pins not under test = 0V)

Command and

address Inputs, CKE II-40 40 µA

CK, S# -20 20 µA

DQMB -5 5 µA

Output leakage current: DQ pins are

disabled; 0V ≤ VOUT ≤ VDDQDQ IOZ -5 5 µA 33

Output levels:

Output high voltage (IOUT = -4mA)

Output low voltage (IOUT = 4mA)

VOH 2.4 – V

VOL –0.4V

Table 11: DC Electrical Characteristics and Operating Conditions – 1GB

Notes: 1, 5, 6; notes appear on page 18; VDD = VDDQ = +3.3V ±0.3V

Parameter/Condition Symbol Min Max Units Notes

Supply voltage VDD, VDDQ3 3.6 V

Input high voltage: Logic 1; All inputs VIH 2VDD + 0.3 V 22

Input low voltage: Logic 0; All inputs VIL -0.3 0.8 V 22

Input leakage current:

Any input 0V ≤ VIN ≤ VDD

(All other pins not under test = 0V)

Command and

address Inputs, CKE II

-80 80 µA

CK, S# -20 20 µA

DQMB -10 10 µA

Output leakage current: DQ pins are

disabled; 0V ≤ VOUT ≤ VDDQDQ IOZ -10 10 µA 33

Output levels:

Output high voltage (IOUT = -4mA)

Output low voltage (IOUT = 4mA)

VOH 2.4 – V

VOL –0.4V

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512MB (SR), 1GB (DR): (x64) 168-Pin SDRAM UDIMM

Specifications and Conditions

IDD Specifications and Conditions

Note: a - Value calculated as one module rank in this condition, and all other module ranks in

power- down mode (IDD2).

b - Value calculated reflects all module ranks in this condition.

Table 12: IDD Specifications and Conditions – 512MB

Notes: 1, 5, 6, 11, 13; notes appear on page 18; VDD, VDDQ = +3.3V ±0.3V; SDRAM component values only

Parameter/Condition Symbol

Max

Units Notes-13E -133

Operating current: Active mode; Burst = 2; READ or WRITE; tRC =

tRC (MIN) IDD1960 880 mA 3, 18,19,

Standby current: Power-Down mode; All device banks idle; CKE =

LOW IDD228 28 mA 30

Standby current: Active mode; CKE = HIGH; CS# = HIGH; All device

banks active after tRCD met; No accesses in progress IDD3360 360 mA 3, 12, 19,

Operating current: Burst Mode; Continuous burst; READ or WRITE;

All device banks active IDD41,000 1,000 mA 3, 18, 19,

Auto refresh current tRFC = tRFC (MIN) IDD51,960 1,960 mA 3, 12

CKE = HIGH; CS# = HIGH tRFC = 7.8125µs IDD648 48 mA 18, 19 ,

30, 31

Self refresh current: CKE ≤ 0.2V IDD748 48 mA 4

Table 13: IDD Specifications and Conditions – 1GB

Notes: 1, 6, 11, 13; notes appear on page 18; VDD, VDDQ = +3.3V ±0.3V; SDRAM component values only

Parameter/Condition Symbol

Max

Units Notes-13E -133

Operating current: Active mode; Burst = 2; READ or WRITE;

tRC = tRC (MIN) IDD1a1,112 1,008 mA 3, 18,19,

Standby current: Power-Down mode; All device banks idle;

CKE = LOW IDD2b63 63 mA 30

Standby current: Active mode; CKE = HIGH; CS# = HIGH; All device

banks active after tRCD met; No accesses in progress IDD3a437 437 mA 3, 12, 19,

Operating current: Burst Mode; Continuous burst; READ or WRITE;

All device banks active IDD4a1,157 1,157 mA 3, 18, 19,

Auto refresh current tRFC = tRFC (MIN) IDD5b4,410 4,410 mA 3, 12

CKE = HIGH; CS# = HIGH tRFC = 7.8125µs IDD6b108 108 mA 18, 19,

30, 31

Self refresh current: CKE ≤ 0.2V IDD7b108 108 mA 4

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512MB (SR), 1GB (DR): (x64) 168-Pin SDRAM UDIMM

Capacitance

AC Operating Specifications

Table 14: Capacitance – 512MB

Note 2; notes appear on page 18

Parameter Symbol Min Max Units

Input capacitance: Address and command CI120 30.4 pF

Input capacitance: CK CI213.3 17.3 pF

Input capacitance: S# CI310 15.2 pF

Input capacitance: CKE CI420 30.4 pF

Input capacitance: DQMB CI52.5 3.8 pF

Input/Output capacitance: DQ CIO246pF

Table 15: Capacitance – 1GB

Note 2; notes appear on page 18

Parameter Symbol Min Max Units

Input capacitance: Address and command CI140 60.8 pF

Input capacitance: CK CI213.3 17.3 pF

Input capacitance: S# CI310 15.2 pF

Input capacitance: CKE CI420 30.4 pF

Input capacitance: DQMB CI557.6pF

Input/Output capacitance: DQ CIO2812pF

Table 16: Electrical Characteristics and Recommended AC Operating Conditions

Notes: 5, 6, 8, 9, 11, 31; notes appear on page 18

Module AC timing parameters comply with PC100 and PC133 Design Specs, based on component parameters

AC Characteristics

Symbol

-13E -133

Units NotesParameter Min Max Min Max

Access time from CLK (positive edge) CL = 3 tAC(3) 5.4 5.4 ns 27

CL = 2 tAC(2) 5.4 6 ns

Address hold time tAH 0.8 0.8 ns

Address setup time tAS 1.5 1.5 ns

CLK high-level width tCH 2.5 2.5 ns

CLK low-level width tCL 2.5 2.5 ns

Clock cycle time CL = 3 tCK(3) 7 7.5 ns 23

CL = 2 tCK(2) 7.5 10 ns 23

CKE hold time tCKH 0.8 0.8 ns

CKE setup time tCKS 1.5 1.5 ns

CS#, RAS#, CAS#, WE#, DQM hold time tCMH 0.8 0.8 ns

CS#, RAS#, CAS#, WE#, DQM setup time tCMS 1.5 1.5 ns

Data-in hold time tDH 0.8 0.8 ns

Data-in setup time tDS 1.5 1.5 ns

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512MB (SR), 1GB (DR): (x64) 168-Pin SDRAM UDIMM

AC Operating Specifications

Data-out High-Z time CL = 3 tHZ(3) 5.4 5.4 ns 10

CL = 2 tHZ(2) 5.4 6 ns 10

Data-out Low-Z time tLZ 1 1 ns

Data-out hold time (load) tOH 2.7 2.7 ns

Data-out hold time (no load) tOHN1.8 1.8 ns 28

ACTIVE-to-PRECHARGE command tRAS 37 120,000 44 120,000 ns 32

ACTIVE-to-ACTIVE command period tRC 60 66 ns

ACTIVE-to-READ or WRITE delay tRCD 15 20 ns

Refresh period (8,192 rows) tREF 64 64 ms

Auto refresh period tRFC 66 66 ns

PRECHARGE command period tRP 15 20 ns

ACTIVE bank a to ACTIVE bank b command tRRD 14 15 ns

Transition time tT 0.3 1.2 0.3 1.2 ns 7

WRITE recovery time tWR 1 CLK

+ 7ns 1 CLK

+ 7ns ns 24

14 15 ns 25

Exit SELF REFRESH-to-ACTIVE command tXSR 67 75 ns 20

Table 17: AC Functional Characteristics

Notes: 5, 6, 7, 8, 9, 11, 31; notes appear on page 18

Parameter Symbol -13E -133 Units Notes

READ/WRITE command to READ/WRITE command tCCD 1 1 tCK 17

CKE to clock disable or power-down entry mode tCKED 1 1 tCK 14

CKE to clock enable or power-down exit setup mode tPED 1 1 tCK 14

DQM to input data delay tDQD 0 0 tCK 17

DQM to data mask during WRITEs tDQM 0 0 tCK 17

DQM to data High-Z during READs tDQZ 2 2 tCK 17

WRITE command to input data delay tDWD 0 0 tCK 17

Data-into ACTIVE command tDAL 4 5 tCK 15, 21

Data-into PRECHARGE command tDPL 2 2 tCK 16, 21

Last data-in to burst STOP command tBDL 1 1 tCK 17

Last data-in to new READ/WRITE command tCDL 1 1 tCK 17

Last data-into PRECHARGE command tRDL 2 2 tCK 16, 21

LOADMODEREGISTER command to ACTIVE or REFRESH command tMRD 2 2 tCK 26

Data-out to High-Z from PRECHARGE command CL = 3 tROH(3) 3 3 tCK 17

CL = 2 tROH(2) 2 2 tCK 17

Table 16: Electrical Characteristics and Recommended AC Operating Conditions (continued)

Notes: 5, 6, 8, 9, 11, 31; notes appear on page 18

Module AC timing parameters comply with PC100 and PC133 Design Specs, based on component parameters

AC Characteristics

Symbol

-13E -133

Units NotesParameter Min Max Min Max

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512MB (SR), 1GB (DR): (x64) 168-Pin SDRAM UDIMM

Notes

Notes 1. All voltages referenced to VSS.

2. This parameter is sampled . VDD, VDDQ = +3.3V; TA= 25°C; pin under test biased at

1.4V; f = 1 MHz.

3. IDD is dependent on output loading and cy cle rates. Specified value s are obtained

with minimum cycle time and the outputs open.

4. Enables on-chip refresh and address counters.

5. The minimum specifications are used only to indicate cycle time at which proper

operation over the full temperature range is ensured.

6. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH

commands, before prope r devi ce operation is ensured. (VDD and VDDQ must be pow-

ered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO

REFRESH command wake-ups should be repeated any time the tREF re fresh require-

ment is exceeded.

7. AC characteristics assume tT = 1ns.

8. In addition to meeting the transition rate specification, the clock and CKE must tran-

sit between VIH and VIL (or between VIL and VIH) in a monotonic manner.

9. Outputs measured at 1.5V with equivalent load:

10. tHZ defines the time at which the output achieves the open circuit condition; it is not

a reference to VOH or VOL. The last valid data elemen t will meet tOH before going

High-Z.

11. AC timing and IDD tests have VIL = 0V and VIH = 3.0V with timing referenced to 1.5V

crossover point. If the input transition time is longer than 1ns, then the timing is ref-

erenced at VIL (MAX) and VIH (MIN) and no longer at the 1.5V crossover point.

12. Other input signals are allowed to transition no more than once every two clocks and

are otherwise at valid VIH or VIL levels.

13. IDD specifications are tested after the device is properly initialized.

14. Timing actually specified by tCKS; clock(s) specified as a ref erence only at minimum

cycle rate.

15. Timing actually specified by tWR plus tRP; clock(s) specified as a referen ce on ly a t

minimum cycle rate.

16. Timing actually specified by tWR.

17. Required clocks are specified by JEDEC functionality and are not dependent on any

timing parameter.

18. The IDD current will increase or decrease proportionally according to the amount of

frequency alteration for the test condition.

19. Address transitions average one transition every two clocks.

20. CLK must be toggled a minimum of two times during this period.

21. Based on tCK = 7.5ns for -133 and -13E.

22. VIH overshoot: VIH (MA X) = VDDQ + 2V for a pulse width ≤ 3ns, and the pulse width

cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for

a pulse width ≤ 3ns for all inputs except A12. VIH ove r shoot for pin A12 is limited to

VDDQ + 1V for a pulse width ≤ 3ns, and the pulse width cannot be greater than one

third of the cycle rate.

Q50pF

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512MB (SR), 1GB (DR): (x64) 168-Pin SDRAM UDIMM

Notes

23. The clock frequency must remain constant (stable clock is defined as a signal cycling

within timing constraints specified for the clock pin) during access or precharge

states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be

used to reduce the data rate.

24. Auto precharge mode only. The precharge timing budget (tRP) begins 7ns for -13E,

and 7.5ns for -133 after the first clock delay, after the last WRITE is executed. May not

exceed limit set for precharge mode.

25. Precharge mode only.

26. JEDEC and PC100 specify three clocks.

27. tAC for -133/-13E at CL = 3 with no load is 4.6ns and is guaranteed by design.

28. Parameter guaranteed by design.

29. For -13E, CL = 2 and tCK = 7.5ns; and for -133, CL = 3 and tCK = 7.5ns.

30. CKE is HIGH durin g refresh command period tRFC (MIN) else CKE is LOW. The IDD6

limit is actually a nomina l value and does not result in a fail value.

31. Refer to device data sheet for timing waveforms.

32. The value of tRAS used in -13E speed grade modules is calculated from tRC - tRP.

33. Leakage number reflects the worst case l eakage poss ible thr ough the module pin, not

what each memory device contributes.

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512MB (SR), 1GB (DR): (x64) 168-Pin SDRAM UDIMM

Serial Presence Detect

SPD Clock and Data Conventions

Data states on the SDA line can change only during SCL LOW. SDA state changes during

SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure7,

and Figure 8 on page 21).

SPD Start Condition

All commands are preceded by the start condition, which is a HIGH-to-LOW transition

of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL

lines for the start condition and will not respond to any command until this condition

has been met.

SPD Stop ConditionAll communications are terminated by a stop condition, which is a LOW-to-HIGH tran-

sition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device

into standby power mode.

SPD Acknowledge Acknowledge is a software convention used to indicate succ essful data transfers. The

transmitting device, either master or slave, will release the bus after transmitting eight

bits. During the ninth clock cy cle, the receiv er will pull the SDA line LO W to ackno wledge

that it received the eight bits of data (as shown in Figure9 on page 21).

The SPD device will always respond with an acknowledge after recognition of a start

condition and its slave address. If both the device and a WRITE operation have been

selected, the SPD device will respond with an acknowledge after the receipt of each sub-

sequent eight bit word. In the read mode the SPD device will transmit eight bits of data,

release the SDA line and monitor the line for an acknowledge. If an acknowledge is

detected and no stop condition is generated by the master, the slave will continue to

transmit data. If an acknowledge is not detected, the slave will terminate further data

transmissions and await the stop condition to return to standby power mode.

Figure 7: Data Validity

SCL

SDA

Data stable Data stableData

change

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512MB (SR), 1GB (DR): (x64) 168-Pin SDRAM UDIMM

Serial Presence Detect

Figure 8: Definition of Start and Stop

Figure 9: Acknowledge Response From Receiver

Table 18: EEPROM Device Select Code

The most significant bit (b7) is sent first

Device Type Identifier Chip Enable RW

b7 b6 b5 b4 b3 b2 b1 b0

Memory area select code (two arrays) 1 0 1 0 SA2 SA1 SA0 RW

Protecti on register se le ct code 0 1 1 0 SA2 SA1 SA0 RW

Table 19: EEPROM Operating Modes

Mode RW Bit WC Bytes Initial Sequence

Current address read 1V

IH or VIL 1Start, device select, RW = 1

Random address read 0V

IH or VIL 1Start, device select, RW= 0, Address

IH or VIL Restart, device select, RW= 1

Sequential read 1V

IH or VIL ≥ 1Similar to current or random address read

Byte write 0V

IL 1Start, device select, RW = 0

Page write 0V

IL ≤ 16 Start, device select, RW = 0

SCL

SDA

Start

bit Stop

bit

SCL from Master

Data Output

from Transmitter

Data Output

from Receiver

Acknowledge

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512MB (SR), 1GB (DR): (x64) 168-Pin SDRAM UDIMM

Serial Presence Detect

Figure 10: SPD EEPROM Timing Diagram

Table 20: SERIAL Presence-Detect EEPROM DC Operating Conditions

All voltages referen ce d to VSS; VDDSPD = +2.3V to +3.6V

Parameter/Condition Symbol Min Max Units

Supply voltage VDD 33.6V

Input high voltage: Logic 1; All inputs VIH VDD × 0.7 VDD + 0.5 V

Input low voltage: Logic 0; All inputs VIL -1 VDD × 0.3 V

Output low voltage: IOUT = 3mA VOL –0.4V

Input leakage current: VIN = GND to VDD ILI –10µA

Output leakage current: VOUT = GND to VDD ILO –10µA

Standby current: SCL = SDA = VDD - 0.3V; All other inputs = GND or

3.3V ±10% ICCS –30µA

Power supply current:

SCL Clock frequency = 100 KHz ICC Write

ICC Read –

–3

1mA

Table 21: Serial Presence-Detect EEPROM AC Operating Conditions

All voltages referen ce d to VSS; VDDSPD = +2.3V to +3.6V

Parameter/Condition Symbol Min Max Units Notes

SCL LOW to SDA data-out valid tAA 0.2 0.9 µs 1

Time the bus must be free before a new transition can start tBUF 1.3 µs

Data-out hold time tDH 200 ns

SDA and SCL fall time tF300ns2

Data-in hold time tHD:DAT 0 µs

Start condition hold time tHD:STA 0.6 µs

Clock HIGH period tHIGH 0.6 µs

Noise suppression time constant at SCL, SDA inputs tI50ns

Clock LOW period tLOW 1.3 µs

SDA and SCL rise time tR0.3µs2

SCL clock frequency fSCL 400 KHz

SCL

SDA IN

SDA OUT

tLOW

tSU:STA tHD:STA

tFtHIGH tR

tBUF

tDH

tAA

tSU:STO

tSU:DAT

tHD:DAT

UNDEFINED

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512MB (SR), 1GB (DR): (x64) 168-Pin SDRAM UDIMM

Serial Presence Detect

Notes: 1. To avoid spurious start and stop con ditions, a minimum delay is placed between SCL = 1

and the falling or rising edge of SDA.

2. This parameter is sampled.

3. For a restart condition, or following a WRITE cycle.

4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a

write sequence to the end of the EEPROM internal erase/program cycle. During the WRITE

cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resis-

tor, and the EEPROM does not respond to its slave address.

Data-in setup time tSU:DAT 100 ns

Start condition setup time tSU:STA 0.6 µs 3

Stop condition setup time tSU:STO 0.6 µs

WRITE cycle time tWRC 10 ms 4

Table 21: Serial Presence-Detect EEPROM AC Operating Conditions (continued)

All voltages referen ce d to VSS; VDDSPD = +2.3V to +3.6V

Parameter/Condition Symbol Min Max Units Notes

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512MB (SR), 1GB (DR): (x64) 168-Pin SDRAM UDIMM

Serial Presence Detect

Table 22: Serial Presence-Detect Matrix

VDD = +3.3V ±0.3V; “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”

Byte Description Entry (Version) MT8LSDT6464A MT16LSDT12864A

0Number of bytes used by Micron 128 80 80

1Total number of SPD memory bytes 256 08 08

2Memory type SDRAM 04 04

3Number of row addresses 13 0D 0D

4Number of column addresses 11 0B 0B

5Number of module ranks 1 or 2 01 02

6Module data width 64 40 40

7Module data width (continued) 000 00

8Module voltage interface levels LVTTL 01 01

9SDRAM cycle time, tCK

(CAS latency = 3) 7ns (-13E)

7.5ns (-133) 70

75 70

10 SDRAM access from Clock, tAC

(CAS latency = 3) 5.4ns (-13E/-133) 54 54

11 Module configuration type NON-ECC 00 00

12 Refresh rate/type 7.8125µs/SELF 82 82

13 SDRAM width (primary SDRAM) 808 08

14 Error-checking SDRAM data width NONE 00 00

15 Minimum clock delay from back-to-back random

column addresses, tCCD 101 01

16 Burst lengths supported 1, 2, 4, 8, PAGE 8F 8F

17 Number of banks on SDRAM device 404 04

18 CAS latencies supported 2, 3 06 06

19 CS latency 001 01

20 WE latency 001 01

21 SDRAM module attributes UNBUFFERED 00 00

22 SDRAM device attributes: general 0E 0E 0E

23 SDRAM cycle time, tCK

(CAS latency = 2) 7.5ns (13E)

10ns (-133) 75

A0 75

24 SDRAM access from clock, tAC

(CAS latency = 2) 5.4ns (-13E)

6ns (-133) 54

60 54

25 SDRAM cycle time, tCK, (CAS latency = 1) 00 00

26 SDRAM access from clock, tAC, (CAS latency = 1) 00 00

27 Minimum row precharge time, tRP 15ns (-13E)

20ns (-133) 0F

14 0F

28 Minimum row active to row active, tRRD 14ns (-1 3E )

15ns (-133) 0E

0F 0E

29 Minimum RAS# to CAS# delay, tRCD 15ns (-13E)

20ns (-133) 0F

14 0F

30 Minimum RAS# pu lse wid t h, tRAS (see note 1) 45ns (-13E)

44ns (133) 2D

2C 2D

31 Module rank density 512MB 80 80

32 Command and address setup time, tAS, tCMS 1.5ns (-13E/-133) 15 15

33 Command and address hold time, tAH, tCMH 0.8ns (-13E/-133) 08 08

34 Data signal input setup time, tDS 1.5ns (-13E/-133) 15 15

35 Data signal input hold time, tDH 0.8ns (-13E/-133) 08 08

36-40 Reserved 00 00

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512MB (SR), 1GB (DR): (x64) 168-Pin SDRAM UDIMM

Serial Presence Detect

Notes: 1. The value of tRAS used for -13E modules is calculated from tRC - tRP. Actual device spe c.

value is 37ns.

41 Device minimum active/auto-refresh time, tRC 60ns (-13E)

66ns (-133) 3C

42 3C

42-61 Reserved 00 00

62 SPD revision REV. 2.0 02 02

63 Checksum for bytes 0–62 (-13E)

(-133) F8

44 F9

64 Manufacturer’s JEDEC ID code MICRON 2C 2C

65-71 Manufacturer’s JEDEC ID code (continued) FF FF

72 Manufacturing location 01 - 06 01 - 06

73-90 Module part number (ASCII) Variable Data Variable Data

91 PCB identification code 01-04 01-04

92 Identification code (continued) 000 00

93 Year of manufacture in BCD Variable Data Variable Data

94 Week of manufacture in BCD Variable Data Variable Data

95-98 Module serial number Variable Data Variable Data

99-125 Manufacturer-specific data (RSVD)

126 System frequency 100 MHz

(-13E/-133) 64 64

127 SDRAM component and clock detail AF FF

Table 22: Serial Presence-Detect Matrix (continued)

VDD = +3.3V ±0.3V; “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”

Byte Description Entry (Version) MT8LSDT6464A MT16LSDT12864A

PDF: 09005aef8088b2e3/Source: 09005aef8088077a Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

512MB (SR), 1GB (DR): (x64) 168-Pin SDRAM UDIMM

Module Dimensions

Figure 11: 168-Pin DIMM Dimensions – 512MB

Note: All dimensions in inches (millimeters); or typical where noted.

0.125 (3.18)

MAX

0.054 (1.37)

0.046 (1.17)

PIN 1 (PIN 85 ON BACKSIDE)

0.700 (17.78)

TYP

0.118 (3.00)

(2X)

0.118 (3.00) TYP

4.550 (115.57)

0.050 (1.27)

TYP

.118 (3.00)

TYP 0.039 (1.00)

TYP

0.079 (2.00) R

(2X)

0.039 (1.00)R

(2X)

FRONT VIEW

0.128 (3.25)

0.118 (3.00)

PIN 84 (PIN 168 ON BACKSIDE)

(2X)

0.250 (6.35) TYP

1.661 (42.18)

2.625 (66.68)

1.380 (35.05)

1.370 (34.80)

5.256 (133.50)

5.244 (133.20)

U1 U2 U3 U4 U6 U7 U8 U9

U10

STANDARD PCB

0.125 (3.18)

MAX

0.054 (1.37)

0.046 (1.17)

PIN 1 (PIN 85 ON BACKSIDE)

0.700 (17.78)

TYP

0.118 (3.00)

(2X)

0.118 (3.00) TYP

4.550 (115.57)

0.050 (1.27)

TYP

0.118 (3.00)

TYP 0.039 (1.00)

TYP

0.079 (2.00) R

(2X)

0.039 (1.00)R

(2X)

FRONT VIEW

0.128 (3.25)

0.118 (3.00)

PIN 84 (PIN 168 ON BACKSIDE)

(2X)

0.250 (6.35) TYP

1.661 (42.18)

2.625 (66.68)

1.131 (28.73)

1.119 (28.42)

5.256 (133.50)

5.244 (133.20)

U1 U2 U3 U4 U6 U7 U8 U9

U10

LOW PROFILE PCB

MAX

MIN

PDF: 09005aef8088b2e3/Source: 09005aef8088077a Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

512MB (SR), 1GB (DR): (x64) 168-Pin SDRAM UDIMM

Module Dimensions

Figure 12: 168-Pin DIMM Dimensions – 1GB

Note: All dimensions in inches (millimeters); or typical where noted.

0.157 (3.99)

MAX

0.054 (1.37)

0.046 (1.17)

PIN 1

0.700 (17.78)

TYP

0.118 (3.00)

0(2X)

.118 (3.00) TYP

4.550 (115.57)

0.050 (1.27)

TYP

0.118 (3.00)

TYP 0.039 (1.00)

TYP

0.079 (2.00) R

(2X)

0.039 (1.00)R

(2X)

FRONT VIEW

0.128 (3.25)

0.118 (3.00)

PIN 84

(2X)

0.250 (6.35) TYP

1.661 (42.18)

2.625 (66.68)

1.131 (28.73)

1.119 (28.42)

5.256 (133.50)

5.244 (133.20)

U1 U2 U3 U4 U6 U7 U8 U9

U10

LOW PROFILE PCB

U11 U12 U13 U14 U16 U17 U18 U19

PIN 85

PIN 168

BACK VIEW

0.157 (3.99)

MAX

0.054 (1.37)

0.046 (1.17)

PIN 1

0.700 (17.78)

TYP

0.118 (3.00)

(2X)

0.118 (3.00) TYP

4.550 (115.57)

0.050 (1.27)

TYP

0.118 (3.00)

TYP 0.039 (1.00)

TYP

0.079 (2.00) R

(2X)

0.039 (1.00)R

(2X)

FRONT VIEW

0.128 (3.25)

0.118 (3.00)

PIN 84

(2X)

0.250 (6.35) TYP

1.661 (42.18)

2.625 (66.68)

1.380 (35.05)

1.370 (34.80)

5.256 (133.50)

5.244 (133.20)

U1 U2 U3 U4 U6 U7 U8 U9

U10

STADARD PCB

U11 U12 U13 U14 U16 U17 U18 U19

PIN 85

PIN 168

BACK VIEW

MAX

MIN

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

prodmktg@micron.com www.micron.com Customer Comment Line: 800-932- 4992

Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range

for production devices. Although considered final, these specifications are subject to change, as further product

development and data characterization sometimes occur.

PDF: 09005aef8088b2e3/Source: 09005aef8088077a Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

512MB (SR), 1GB (DR): (x64) 168-Pin SDRAM UDIMM

Module Dimensions