Contents
Arria® 10 Device Overview..................................................................................................3
Key Advantages of Arria 10 Devices................................................................................4
Summary of Arria 10 Features....................................................................................... 4
Arria 10 Device Variants and Packages............................................................................7
Arria 10 GX........................................................................................................7
Arria 10 GT...................................................................................................... 11
Arria 10 SX...................................................................................................... 14
I/O Vertical Migration for Arria 10 Devices..................................................................... 17
Adaptive Logic Module................................................................................................ 17
Variable-Precision DSP Block........................................................................................18
Embedded Memory Blocks........................................................................................... 21
Types of Embedded Memory............................................................................... 21
Embedded Memory Capacity in Arria 10 Devices....................................................21
Embedded Memory Configurations for Single-port Mode......................................... 22
Clock Networks and PLL Clock Sources.......................................................................... 22
Clock Networks.................................................................................................22
Fractional Synthesis and I/O PLLs........................................................................22
FPGA General Purpose I/O...........................................................................................23
External Memory Interface.......................................................................................... 24
Memory Standards Supported by Arria 10 Devices.................................................24
PCIe Gen1, Gen2, and Gen3 Hard IP.............................................................................26
Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet............................................. 26
Interlaken Support............................................................................................ 26
10 Gbps Ethernet Support.................................................................................. 26
Low Power Serial Transceivers......................................................................................27
Transceiver Channels......................................................................................... 28
PMA Features................................................................................................... 29
PCS Features....................................................................................................30
SoC with Hard Processor System.................................................................................. 32
Key Advantages of 20-nm HPS............................................................................33
Features of the HPS...........................................................................................35
FPGA Configuration and HPS Booting................................................................... 37
Hardware and Software Development.................................................................. 37
Dynamic and Partial Reconfiguration............................................................................. 37
Dynamic Reconfiguration....................................................................................37
Partial Reconfiguration....................................................................................... 38
Enhanced Configuration and Configuration via Protocol....................................................38
SEU Error Detection and Correction.............................................................................. 39
Power Management.................................................................................................... 39
Incremental Compilation............................................................................................. 40
Document Revision History.......................................................................................... 40
Contents
Intel® Arria® 10 Device Overview
2
Arria® 10 Device Overview
The Intel® Arria® 10 device family consists of high-performance and power-efficient
20 nm mid-range FPGAs and SoCs.
Arria 10 device family delivers:
• Higher performance than the previous generation of mid-range and high-end
FPGAs.
• Power efficiency attained through a comprehensive set of power-saving
technologies.
The Arria 10 devices are ideal for high performance, power-sensitive, midrange
applications in diverse markets.
Table 1. Sample Markets and Ideal Applications for Arria 10 Devices
Market Applications
Wireless • Channel and switch cards in remote radio heads
• Mobile backhaul
Wireline • 40G/100G muxponders and transponders
• 100G line cards
• Bridging
• Aggregation
Broadcast • Studio switches
• Servers and transport
• Videoconferencing
• Professional audio and video
Computing and Storage • Flash cache
• Cloud computing servers
• Server acceleration
Medical • Diagnostic scanners
• Diagnostic imaging
Military • Missile guidance and control
• Radar
• Electronic warfare
• Secure communications
Related Links
Arria 10 Device Handbook: Known Issues
Lists the planned updates to the Arria 10 Device Handbook chapters.
Arria® 10 Device Overview
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2008
Registered
Key Advantages of Arria 10 Devices
Table 2. Key Advantages of the Arria 10 Device Family
Advantage Supporting Feature
Enhanced core architecture • Built on TSMC's 20 nm process technology
• 60% higher performance than the previous generation of mid-range FPGAs
• 15% higher performance than the fastest previous-generation FPGA
High-bandwidth integrated
transceivers
• Short-reach rates up to 25.8 Gigabits per second (Gbps)
• Backplane capability up to 17.5 Gbps
• Integrated 10GBASE-KR and 40GBASE-KR4 Forward Error Correction (FEC)
Improved logic integration and
hard IP blocks
• 8-input adaptive logic module (ALM)
• Up to 65.6 megabits (Mb) of embedded memory
• Variable-precision digital signal processing (DSP) blocks
• Fractional synthesis phase-locked loops (PLLs)
• Hard PCI Express Gen3 IP blocks
• Hard memory controllers and PHY up to 2,666 Megabits per second (Mbps)
• Hard memory controllers and PHY up to 2,666 Megabits per second (Mbps)
Second generation hard
processor system (HPS) with
integrated ARM* Cortex*-A9*
MPCore* processor
• Tight integration of a dual-core ARM Cortex-A9 MPCore processor, hard IP, and an
FPGA in a single Arria 10 system-on-a-chip (SoC)
• Supports over 128 Gbps peak bandwidth with integrated data coherency between
the processor and the FPGA fabric
Advanced power savings • Comprehensive set of advanced power saving features
• Power-optimized MultiTrack routing and core architecture
• Up to 40% lower power compared to previous generation of mid-range FPGAs
• Up to 60% lower power compared to previous generation of high-end FPGAs
Summary of Arria 10 Features
Table 3. Summary of Features for Arria 10 Devices
Feature Description
Technology • TSMC's 20-nm SoC process technology
• Allows operation at a lower VCC level of 0.83 V instead of the 0.9 V standard VCC core voltage
Packaging • 1.0 mm ball-pitch Fineline BGA packaging
• 0.8 mm ball-pitch Ultra Fineline BGA packaging
• Multiple devices with identical package footprints for seamless migration between different
FPGA densities
• Devices with compatible package footprints allow migration to next generation high-end
Stratix® 10 devices
• RoHS, leaded1, and lead-free (Pb-free) options
High-performance
FPGA fabric
• Enhanced 8-input ALM with four registers
• Improved multi-track routing architecture to reduce congestion and improve compilation time
• Hierarchical core clocking architecture
• Fine-grained partial reconfiguration
Internal memory
blocks
• M20K—20-Kb memory blocks with hard error correction code (ECC)
• Memory logic array block (MLAB)—640-bit memory
continued...
1 Contact Intel for availability.
Arria® 10 Device Overview
Intel® Arria® 10 Device Overview
4
Feature Description
Embedded Hard IP
blocks
Variable-precision DSP • Native support for signal processing precision levels from 18 x 19 to
54 x 54
• Native support for 27 x 27 multiplier mode
• 64-bit accumulator and cascade for systolic finite impulse responses
(FIRs)
• Internal coefficient memory banks
• Preadder/subtractor for improved efficiency
• Additional pipeline register to increase performance and reduce
power
• Supports floating point arithmetic:
— Perform multiplication, addition, subtraction, multiply-add,
multiply-subtract, and complex multiplication.
— Supports multiplication with accumulation capability, cascade
summation, and cascade subtraction capability.
— Dynamic accumulator reset control.
— Support direct vector dot and complex multiplication chaining
multiply floating point DSP blocks.
Memory controller DDR4, DDR3, and DDR3L
PCI Express* PCI Express (PCIe*) Gen3 (x1, x2, x4, or x8), Gen2 (x1, x2, x4, or x8)
and Gen1 (x1, x2, x4, or x8) hard IP with complete protocol stack,
endpoint, and root port
Transceiver I/O • 10GBASE-KR/40GBASE-KR4 Forward Error Correction (FEC)
• PCS hard IPs that support:
— 10-Gbps Ethernet (10GbE)
— PCIe PIPE interface
— Interlaken
— Gbps Ethernet (GbE)
— Common Public Radio Interface (CPRI) with deterministic latency
support
— Gigabit-capable passive optical network (GPON) with fast lock-
time support
• 13.5G JESD204b
• 8B/10B, 64B/66B, 64B/67B encoders and decoders
• Custom mode support for proprietary protocols
Core clock networks • Up to 800 MHz fabric clocking, depending on the application:
— 667 MHz external memory interface clocking with 2,666 Mbps DDR4 interface
— 800 MHz LVDS interface clocking with 1,600 Mbps LVDS interface
• Global, regional, and peripheral clock networks
• Clock networks that are not used can be gated to reduce dynamic power
Phase-locked loops
(PLLs)
• High-resolution fractional synthesis PLLs:
— Precision clock synthesis, clock delay compensation, and zero delay buffering (ZDB)
— Support integer mode and fractional mode
— Fractional mode support with third-order delta-sigma modulation
• Integer PLLs:
— Adjacent to general purpose I/Os
— Support external memory and LVDS interfaces
FPGA General-purpose
I/Os (GPIOs)
• 1.6 Gbps LVDS—every pair can be configured as receiver or transmitter
• On-chip termination (OCT)
• 1.2 V to 3.0 V single-ended LVTTL/LVCMOS interfacing
External Memory
Interface
• Hard memory controller— DDR4, DDR3, and DDR3L support
— DDR4—speeds up to 1,333 MHz/2,666 Mbps
— DDR3—speeds up to 1,067 MHz/2,133 Mbps
• Soft memory controller—provides support for RLDRAM 32, QDR IV2, and QDR II+
continued...
Arria® 10 Device Overview
Intel® Arria® 10 Device Overview
5
Feature Description
Low-power serial
transceivers
• Continuous operating range:
— Arria 10 GX—1 Gbps to 17.4 Gbps
— Arria 10 GT—1 Gbps to 25.8 Gbps
• Backplane support:
— Arria 10 GX—up to 16.0 Gbps
— Arria 10 GT—up to 17.4 Gbps
• Extended range down to 125 Mbps with oversampling
• ATX transmit PLLs with user-configurable fractional synthesis capability
• Electronic Dispersion Compensation (EDC) support for XFP, SFP+, QSFP, and CFP optical
module
• Adaptive linear and decision feedback equalization
• Transmitter pre-emphasis and de-emphasis
• Dynamic partial reconfiguration of individual transceiver channels
• On-chip instrumentation (EyeQ non-intrusive data eye monitoring)
HPS
(Arria 10 SX devices
only)
Processor and system • Dual-core ARM Cortex-A9 MPCore processor—1.2 GHz CPU with
1.5 GHz overdrive capability
• 256 KB on-chip RAM and 64 KB on-chip ROM
• System peripherals—general-purpose timers, watchdog timers, direct
memory access (DMA) controller, FPGA configuration manager, and
clock and reset managers
• Security features—anti-tamper, secure boot, Advanced Encryption
Standard (AES) and authentication (SHA)
• ARM CoreSight* JTAG debug access port, trace port, and on-chip
trace storage
External interfaces • Hard memory interface—Hard memory controller (2,666 Mbps DDR4,
and 2,166 Mbps DDR3), Quad serial peripheral interface (QSPI) flash
controller, NAND flash controller, direct memory access (DMA)
controller, Secure Digital/MultiMediaCard (SD/MMC) controller
• Communication interface— 10/100/1000 Ethernet media access
control (MAC), USB On-The-GO (OTG) controllers, I2C controllers,
UART 16550, serial peripheral interface (SPI), and up to 62
HPS GPIO interfaces (48 direct-share I/Os)
Interconnects to core • High-performance ARM AMBA* AXI bus bridges that support
simultaneous read and write
• HPS–FPGA bridges—include the FPGA-to-HPS, HPS-to-FPGA, and
lightweight HPS-to-FPGA bridges that allow the FPGA fabric to issue
transactions to slaves in the HPS, and vice versa
• Configuration bridge that allows HPS configuration manager to
configure the core logic via dedicated 32-bit configuration port
• FPGA-to-HPS SDRAM controller bridge—provides configuration
interfaces for the multiport front end (MPFE) of the HPS SDRAM
controller
continued...
2 Arria 10 devices support this external memory interface using hard PHY with soft memory
controller.
Arria® 10 Device Overview
Intel® Arria® 10 Device Overview
6
Feature Description
Configuration • Tamper protection—comprehensive design protection to protect your valuable IP investments
• Enhanced 256-bit advanced encryption standard (AES) design security with authentication
• Configuration via protocol (CvP) using PCIe Gen1, Gen2, or Gen3
• Dynamic reconfiguration of the transceivers and PLLs
• Fine-grained partial reconfiguration of the core fabric
• Active Serial x4 Interface
Power management • SmartVID
• Low static power device options
• Programmable Power Technology
• Quartus® Prime integrated PowerPlay power analysis
Software and tools • Quartus Prime design suite
• Transceiver toolkit
• Qsys system integration tool
• DSP Builder for Intel FPGAs
• OpenCL™ support
• Intel SoC FPGA Embedded Design Suite (EDS)
Related Links
Arria 10 Transceiver PHY Overview
Provides details on Arria 10 transceivers.
Arria 10 Device Variants and Packages
Table 4. Device Variants for the Arria 10 Device Family
Variant Description
Arria 10 GX FPGA featuring 17.4 Gbps transceivers for short reach applications with 16.0 Gbps backplane
driving capability.
Arria 10 GT FPGA featuring:
• 17.4 Gbps transceivers for short reach applications with 17.4 Gbps backplane driving
capability.
• 25.8 Gbps transceivers for supporting CAUI-4 and CEI-25G applications with CFP2 and CFP4
modules.
Arria 10 SX SoC integrating ARM-based HPS and FPGA featuring 17.4 Gbps transceivers for short reach
applications with 16.0 Gbps backplane driving capability.
Arria 10 GX
This section provides the available options, maximum resource counts, and package
plan for the Arria 10 GX devices.
The information in this section is correct at the time of publication. For the latest
information and to get more details, refer to the Intel FPGA Product Selector.
Related Links
Intel FPGA Product Selector
Provides the latest information on Intel products.
Arria® 10 Device Overview
Intel® Arria® 10 Device Overview
7
Available Options
Figure 1. Sample Ordering Code and Available Options for Arria 10 GX Devices
Family Signature
Transceiver Count
Transceiver
Speed Grade
Package Type
Package Code
Operating Temperature
FPGA Fabric
Speed Grade
Optional Suffix
Indicates specific device
options or shipment method
X : GX variant
17.4 Gbps transceivers
10A : Arria 10
016 : 160K logic elements
022 : 220K logic elements
027 : 270K logic elements
032 : 320K logic elements
048 : 480K logic elements
057 : 570K logic elements
066 : 660K logic elements
090 : 900K logic elements
115 : 1,150K logic elements
N : 48
R : 66
S : 72
U : 96
C : 6
E : 12
H : 24
K : 36
1 (fastest)
4
2
3
F : FineLine BGA (FBGA), 1.0 mm pitch
U : Ultra FineLine BGA (UBGA), 0.8 mm pitch
FBGA Package Type
27 : 672 pins, 27 mm x 27 mm
29 : 780 pins, 29 mm x 29 mm
34 : 1,152 pins, 35 mm x 35 mm
35 : 1,152 pins, 35 mm x 35 mm
40 : 1,517 pins, 40 mm x 40 mm
45 : 1,932 pins, 45 mm x 45 mm
UBGA Package Type
19 : 484 pins, 19 mm x 19 mm
I : Industrial (TJ = -40° C to 100° C)
E : Extended (TJ = 0° C to 100° C)
M : Military (TJ = -55° C to 125° C)
1 (fastest)
2
3
Power Option
S : Standard
L : Low
RoHS
G : RoHS6
N : RoHS5
P : Leaded
ES : Engineering sample
10A X F
066 K2S35 I 2ESG
Logic Density
Family Variant
}Contact Intel
for availability
V
: SmartVID (Speed Grade -2 and -3 only)
Related Links
Transceiver Performance for Arria 10 GX/SX Devices
Provides more information about the transceiver speed grade.
Arria® 10 Device Overview
Intel® Arria® 10 Device Overview
8
Maximum Resources
Table 5. Maximum Resource Counts for Arria 10 GX Devices (GX 160, GX 220, GX 270,
GX 320, and GX 480)
Resource Product Line
GX 160 GX 220 GX 270 GX 320 GX 480
Logic Elements (LE) (K) 160 220 270 320 480
ALM 61,510 80,330 101,620 119,900 183,590
Register 246,040 321,320 406,480 479,600 734,360
Memory (Kb) M20K 8,800 11,740 15,000 17,820 28,620
MLAB 1,050 1,690 2,452 2,727 4,164
Variable-precision DSP Block 156 192 830 985 1,368
18 x 19 Multiplier 312 384 1,660 1,970 2,736
PLL Fractional
Synthesis
6 6 8 8 12
I/O 6 6 8 8 12
17.4 Gbps Transceiver 12 12 24 24 36
GPIO 3288 288 384 384 492
LVDS Pair 4120 120 168 168 222
PCIe Hard IP Block 1 1 2 2 2
Hard Memory Controller 6 6 8 8 12
3 The number of GPIOs does not include transceiver I/Os. In the Quartus Prime software, the
number of user I/Os includes transceiver I/Os.
4 Each LVDS I/O pair can be used as differential input or output.
Arria® 10 Device Overview
Intel® Arria® 10 Device Overview
9
Table 6. Maximum Resource Counts for Arria 10 GX Devices (GX 570, GX 660, GX 900,
and GX 1150)
Resource Product Line
GX 570 GX 660 GX 900 GX 1150
Logic Elements (LE) (K) 570 660 900 1,150
ALM 217,080 251,680 339,620 427,200
Register 868,320 1,006,720 1,358,480 1,708,800
Memory (Kb) M20K 36,000 42,620 48,460 54,260
MLAB 5,096 5,788 9,386 12,984
Variable-precision DSP Block 1,523 1,687 1,518 1,518
18 x 19 Multiplier 3,046 3,374 3,036 3,036
PLL Fractional
Synthesis
16 16 32 32
I/O 16 16 16 16
17.4 Gbps Transceiver 48 48 96 96
GPIO 3696 696 768 768
LVDS Pair 4324 324 384 384
PCIe Hard IP Block 2 2 4 4
Hard Memory Controller 16 16 16 16
Package Plan
Table 7. Package Plan for Arria 10 GX Devices (U19, F27, and F29)
Refer to I/O and High Speed I/O in Arria 10 Devices chapter for the number of 3 V I/O, LVDS I/O, and LVDS
channels in each device package.
Product Line U19
(19 mm × 19 mm,
484-pin UBGA)
F27
(27 mm × 27 mm,
672-pin FBGA)
F29
(29 mm × 29 mm,
780-pin FBGA)
3 V I/O LVDS
I/O
XCVR 3 V I/O LVDS
I/O
XCVR 3 V I/O LVDS
I/O
XCVR
GX 160 48 192 6 48 192 12 48 240 12
GX 220 48 192 6 48 192 12 48 240 12
GX 270 — — — 48 192 12 48 312 12
GX 320 — — — 48 192 12 48 312 12
GX 480 — — — — — — 48 312 12
Arria® 10 Device Overview
Intel® Arria® 10 Device Overview
10
Table 8. Package Plan for Arria 10 GX Devices (F34, F35, NF40, and KF40)
Refer to I/O and High Speed I/O in Arria 10 Devices chapter for the number of 3 V I/O, LVDS I/O, and LVDS
channels in each device package.
Product Line F34
(35 mm × 35 mm,
1152-pin FBGA)
F35
(35 mm × 35 mm,
1152-pin FBGA)
KF40
(40 mm × 40 mm,
1517-pin FBGA)
NF40
(40 mm × 40 mm,
1517-pin FBGA)
3 V
I/O
LVDS
I/O
XCVR 3 V
I/O
LVDS
I/O
XCVR 3 V
I/O
LVDS
I/O
XCVR 3 V
I/O
LVDS
I/O
XCVR
GX 270 48 336 24 48 336 24 — — — — — —
GX 320 48 336 24 48 336 24 — — — — — —
GX 480 48 444 24 48 348 36 — — — — — —
GX 570 48 444 24 48 348 36 96 600 36 48 540 48
GX 660 48 444 24 48 348 36 96 600 36 48 540 48
GX 900 — 504 24 — — — — — — — 600 48
GX 1150 — 504 24 — — — — — — — 600 48
Table 9. Package Plan for Arria 10 GX Devices (RF40, NF45, SF45, and UF45)
Refer to I/O and High Speed I/O in Arria 10 Devices chapter for the number of 3 V I/O, LVDS I/O, and LVDS
channels in each device package.
Product Line
RF40
(40 mm × 40 mm,
1517-pin FBGA)
NF45
(45 mm × 45 mm)
1932-pin FBGA)
SF45
(45 mm × 45 mm)
1932-pin FBGA)
UF45
(45 mm × 45 mm)
1932-pin FBGA)
3 V
I/O
LVDS
I/O
XCVR 3 V
I/O
LVDS
I/O
XCVR 3 V
I/O
LVDS
I/O
XCVR 3 V
I/O
LVDS
I/O
XCVR
GX 900 — 342 66 — 768 48 — 624 72 — 480 96
GX 1150 — 342 66 — 768 48 — 624 72 — 480 96
Related Links
I/O and High-Speed Differential I/O Interfaces in Arria 10 Devices chapter, Arria 10
Device Handbook
Provides the number of 3 V and LVDS I/Os, and LVDS channels for each Arria 10
device package.
Arria 10 GT
This section provides the available options, maximum resource counts, and package
plan for the Arria 10 GT devices.
The information in this section is correct at the time of publication. For the latest
information and to get more details, refer to the Intel FPGA Product Selector.
Related Links
Intel FPGA Product Selector
Provides the latest information on Intel products.
Arria® 10 Device Overview
Intel® Arria® 10 Device Overview
11
Available Options
Figure 2. Sample Ordering Code and Available Options for Arria 10 GT Devices
Family Signature
Transceiver Count
Transceiver
Speed Grade
Package Type
Package Code
Operating Temperature
FPGA Fabric
Speed Grade
Optional Suffix
Indicates specific device
options or shipment method
T : GT variant
28.3 Gbps transceivers
10A : Arria 10
090 : 900K logic elements
115 : 1,150K logic elements
S : 72
2 (fastest)
3
4
F : FineLine BGA (FBGA), 1.0 mm pitch
40 : 1,517 pins, 40 mm x 40 mm
45 : 1,932 pins, 45 mm x 45 mm
I :
E :
M :
1 (fastest)
2
3
Power Option
S
: Standard
L : Low
RoHS
G : RoHS6
N : RoHS5
P : Leaded
ES : Engineering sample
10A TF
115 S2S
40 I2ESG
Logic Density
Family Variant
}Contact Intel
for availability
Industrial (TJ = -40° C to 100° C)
Extended (TJ = 0° C to 100° C)
Military (TJ = -55° C to 125° C)
V
:
SmartVID (Speed Grade -2 and -3 only)
Arria® 10 Device Overview
Intel® Arria® 10 Device Overview
12
Maximum Resources
Table 10. Maximum Resource Counts for Arria 10 GT Devices
Resource Product Line
GT 900 GT 1150
Logic Elements (LE) (K) 900 1,150
ALM 339,620 427,200
Register 1,358,480 1,708,800
Memory (Kb) M20K 48,460 54,260
MLAB 9,386 12,984
Variable-precision DSP Block 1,518 1,518
18 x 19 Multiplier 3,036 3,036
PLL Fractional Synthesis 32 32
I/O 16 16
Transceiver 17.4 Gbps 72 572 5
25.8 Gbps 6 6
GPIO6624 624
LVDS Pair7312 312
PCIe Hard IP Block 4 4
Hard Memory Controller 16 16
Related Links
Arria 10 GT Channel Usage
Configuring GT/GX channels in Arria 10 GT devices.
Package Plan
Table 11. Package Plan for Arria 10 GT Devices
Refer to I/O and High Speed I/O in Arria 10 Devices chapter for the number of 3 V I/O, LVDS I/O, and LVDS
channels in each device package.
Product Line
SF45
(45 mm × 45 mm, 1932-pin FBGA)
3 V I/O LVDS I/O XCVR
GT 900 — 624 72
GT 1150 — 624 72
5 If all 6 GT channels are in use, 12 of the GX channels are not usable.
6 The number of GPIOs does not include transceiver I/Os. In the Quartus Prime software, the
number of user I/Os includes transceiver I/Os.
7 Each LVDS I/O pair can be used as differential input or output.
Arria® 10 Device Overview
Intel® Arria® 10 Device Overview
13
Related Links
I/O and High-Speed Differential I/O Interfaces in Arria 10 Devices chapter, Arria 10
Device Handbook
Provides the number of 3 V and LVDS I/Os, and LVDS channels for each Arria 10
device package.
Arria 10 SX
This section provides the available options, maximum resource counts, and package
plan for the Arria 10 SX devices.
The information in this section is correct at the time of publication. For the latest
information and to get more details, refer to the Intel FPGA Product Selector.
Related Links
Intel FPGA Product Selector
Provides the latest information on Intel products.
Available Options
Figure 3. Sample Ordering Code and Available Options for Arria 10 SX Devices
Family Signature
Transceiver Count
Transceiver
Speed Grade
Package Type
Package Code
Operating Temperature
FPGA Fabric
Speed Grade
Optional Suffix
Indicates specific device
options or shipment method
S : SX variant
(SoC with 17.4 Gbps transceivers)
10A : Arria 10
016 : 160K logic elements
022 : 220K logic elements
027 : 270K logic elements
032 : 320K logic elements
048 : 480K logic elements
057 : 570K logic elements
066 : 660K logic elements
K : 36
N : 48
C : 6
E : 12
H : 24
1 (fastest)
2
3
4
F : FineLine BGA (FBGA), 1.0 mm pitch
U : Ultra FineLine BGA (UBGA), 0.8 mm pitch
FBGA Package Type
27 : 672 pins, 27 mm x 27 mm
29 : 780 pins, 29 mm x 29 mm
34 : 1,152 pins, 35 mm x 35 mm
35 : 1,152 pins, 35 mm x 35 mm
40 : 1,517 pins, 40 mm x 40 mm
UBGA Package Type
19 : 484 pins, 19 mm x 19 mm
I :
E :
M :
1 (fastest)
2
3
Power Option
S : Standard
L : Low
RoHS
G : RoHS6
N : RoHS5
P : Leaded
ES : Engineering sample
10A S F
066 K2S35 I 2ESG
Logic Density
Family Variant
}Contact Intel
for availability
Industrial (TJ = -40° C to 100° C)
Extended (TJ = 0° C to 100° C)
Military (TJ = -55° C to 125° C)
V
:
SmartVID (Speed Grade -2 and -3 only)
Related Links
Transceiver Performance for Arria 10 GX/SX Devices
Provides more information about the transceiver speed grade.
Arria® 10 Device Overview
Intel® Arria® 10 Device Overview
14
Maximum Resources
Table 12. Maximum Resource Counts for Arria 10 SX Devices
Resource Product Line
SX 160 SX 220 SX 270 SX 320 SX 480 SX 570 SX 660
Logic Elements (LE) (K) 160 220 270 320 480 570 660
ALM 61,510 80,330 101,620 119,900 183,590 217,080 251,680
Register 246,040 321,320 406,480 479,600 734,360 868,320 1,006,720
Memory (Kb) M20K 8,800 11,740 15,000 17,820 28,620 36,000 42,620
MLAB 1,050 1,690 2,452 2,727 4,164 5,096 5,788
Variable-precision DSP Block 156 192 830 985 1,368 1,523 1,687
18 x 19 Multiplier 312 384 1,660 1,970 2,736 3,046 3,374
PLL Fractional
Synthesis
6 6 8 8 12 16 16
I/O 6 6 8 8 12 16 16
17.4 Gbps Transceiver 12 12 24 24 36 48 48
GPIO 8288 288 384 384 492 696 696
LVDS Pair 9120 120 168 168 174 324 324
PCIe Hard IP Block 1 1 2 2 2 2 2
Hard Memory Controller 6 6 8 8 12 16 16
ARM Cortex-A9 MPCore
Processor
Yes Yes Yes Yes Yes Yes Yes
Package Plan
Table 13. Package Plan for Arria 10 SX Devices (U19, F27, F29, and F34)
Refer to I/O and High Speed I/O in Arria 10 Devices chapter for the number of 3 V I/O, LVDS I/O, and LVDS
channels in each device package.
Product Line U19
(19 mm × 19 mm,
484-pin UBGA)
F27
(27 mm × 27 mm,
672-pin FBGA)
F29
(29 mm × 29 mm,
780-pin FBGA)
F34
(35 mm × 35 mm,
1152-pin FBGA)
3 V
I/O
LVDS
I/O
XCVR 3 V
I/O
LVDS
I/O
XCVR 3 V
I/O
LVDS
I/O
XCVR 3 V
I/O
LVDS
I/O
XCVR
SX 160 48 144 6 48 192 12 48 240 12 — — —
SX 220 48 144 6 48 192 12 48 240 12 — — —
SX 270 — — — 48 192 12 48 312 12 48 336 24
SX 320 — — — 48 192 12 48 312 12 48 336 24
continued...
8 The number of GPIOs does not include transceiver I/Os. In the Quartus Prime software, the
number of user I/Os includes transceiver I/Os.
9 Each LVDS I/O pair can be used as differential input or output.
Arria® 10 Device Overview
Intel® Arria® 10 Device Overview
15
Product Line U19
(19 mm × 19 mm,
484-pin UBGA)
F27
(27 mm × 27 mm,
672-pin FBGA)
F29
(29 mm × 29 mm,
780-pin FBGA)
F34
(35 mm × 35 mm,
1152-pin FBGA)
3 V
I/O
LVDS
I/O
XCVR 3 V
I/O
LVDS
I/O
XCVR 3 V
I/O
LVDS
I/O
XCVR 3 V
I/O
LVDS
I/O
XCVR
SX 480 — — — — — — 48 312 12 48 444 24
SX 570 — — — — — — — — — 48 444 24
SX 660 — — — — — — — — — 48 444 24
Table 14. Package Plan for Arria 10 SX Devices (F35, KF40, and NF40)
Refer to I/O and High Speed I/O in Arria 10 Devices chapter for the number of 3 V I/O, LVDS I/O, and LVDS
channels in each device package.
Product Line F35
(35 mm × 35 mm,
1152-pin FBGA)
KF40
(40 mm × 40 mm,
1517-pin FBGA)
NF40
(40 mm × 40 mm,
1517-pin FBGA)
3 V I/O LVDS
I/O
XCVR 3 V I/O LVDS
I/O
XCVR 3 V I/O LVDS
I/O
XCVR
SX 270 48 336 24 — — — — — —
SX 320 48 336 24 — — — — — —
SX 480 48 348 36 — — — — — —
SX 570 48 348 36 96 600 36 48 540 48
SX 660 48 348 36 96 600 36 48 540 48
Related Links
I/O and High-Speed Differential I/O Interfaces in Arria 10 Devices chapter, Arria 10
Device Handbook
Provides the number of 3 V and LVDS I/Os, and LVDS channels for each Arria 10
device package.
Arria® 10 Device Overview
Intel® Arria® 10 Device Overview
16
I/O Vertical Migration for Arria 10 Devices
Figure 4. Migration Capability Across Arria 10 Product Lines
• The arrows indicate the migration paths. The devices included in each vertical
migration path are shaded. Devices with fewer resources in the same path have
lighter shades.
• To achieve the full I/O migration across product lines in the same migration path,
restrict I/Os and transceivers usage to match the product line with the lowest I/O
and transceiver counts.
• An LVDS I/O bank in the source device may be mapped to a 3 V I/O bank in the
target device. To use memory interface clock frequency higher than 533 MHz,
assign external memory interface pins only to banks that are LVDS I/O in both
devices.
• There may be nominal 0.15 mm package height difference between some product
lines in the same package type.
• Some migration paths are not shown in the Quartus Prime software Pin Migration
View.
Variant Product
Line
Package
U19 F27 F29 F34 F35 KF40 NF40 RF40 NF45 SF45 UF45
Arria 10 GX
GX 160
GX 220
GX 270
GX 320
GX 480
GX 570
GX 660
GX 900
GX 1150
Arria 10 GT GT 900
GT 1150
Arria 10 SX
SX 160
SX 220
SX 270
SX 320
SX 480
SX 570
SX 660
Note: To verify the pin migration compatibility, use the Pin Migration View window in the
Quartus Prime software Pin Planner.
Adaptive Logic Module
Arria 10 devices use a 20 nm ALM as the basic building block of the logic fabric.
The ALM architecture is the same as the previous generation FPGAs, allowing for
efficient implementation of logic functions and easy conversion of IP between the
device generations.
Arria® 10 Device Overview
Intel® Arria® 10 Device Overview
17
The ALM, as shown in following figure, uses an 8-input fracturable look-up table (LUT)
with four dedicated registers to help improve timing closure in register-rich designs
and achieve an even higher design packing capability than the traditional two-register
per LUT architecture.
Figure 5. ALM for Arria 10 Devices
FPGA Device
1
2
3
4
5
6
7
8
Adaptive
LUT
Full
Adder
Reg
Reg
Full
Adder
Reg
Reg
The Quartus Prime software optimizes your design according to the ALM logic
structure and automatically maps legacy designs into the Arria 10 ALM architecture.
Variable-Precision DSP Block
The Arria 10 variable precision DSP blocks support fixed-point arithmetic and floating-
point arithmetic.
Features for fixed-point arithmetic:
• High-performance, power-optimized, and fully registered multiplication operations
• 18-bit and 27-bit word lengths
• Two 18 x 19 multipliers or one 27 x 27 multiplier per DSP block
• Built-in addition, subtraction, and 64-bit double accumulation register to combine
multiplication results
• Cascading 19-bit or 27-bit when pre-adder is disabled and cascading 18-bit when
pre-adder is used to form the tap-delay line for filtering applications
• Cascading 64-bit output bus to propagate output results from one block to the
next block without external logic support
• Hard pre-adder supported in 19-bit and 27-bit modes for symmetric filters
Arria® 10 Device Overview
Intel® Arria® 10 Device Overview
18
• Internal coefficient register bank in both 18-bit and 27-bit modes for filter
implementation
• 18-bit and 27-bit systolic finite impulse response (FIR) filters with distributed
output adder
• Biased rounding support
Features for floating-point arithmetic:
• A completely hardened architecture that supports multiplication, addition,
subtraction, multiply-add, and multiply-subtract
• Multiplication with accumulation capability and a dynamic accumulator reset
control
• Multiplication with cascade summation capability
• Multiplication with cascade subtraction capability
• Complex multiplication
• Direct vector dot product
• Systolic FIR filter
Table 15. Variable-Precision DSP Block Configurations for Arria 10 Devices
Usage Example Multiplier Size (Bit) DSP Block Resources
Medium precision fixed point Two 18 x 19 1
High precision fixed or Single precision
floating point
One 27 x 27 1
Fixed point FFTs One 19 x 36 with external adder 1
Very high precision fixed point One 36 x 36 with external adder 2
Double precision floating point One 54 x 54 with external adder 4
Table 16. Resources for Fixed-Point Arithmetic in Arria 10 Devices
The table lists the variable-precision DSP resources by bit precision for each Arria 10 device.
Variant Product Line Variable-
precision
DSP Block
Independent Input and Output
Multiplications Operator
18 x 19
Multiplier
Adder Sum
Mode
18 x 18
Multiplier
Adder
Summed
with 36 bit
Input
18 x 19
Multiplier
27 x 27
Multiplier
Arria 10 GX GX 160 156 312 156 156 156
GX 220 192 384 192 192 192
GX 270 830 1,660 830 830 830
GX 320 984 1,968 984 984 984
GX 480 1,368 2,736 1,368 1,368 1,368
GX 570 1,523 3,046 1,523 1,523 1,523
GX 660 1,687 3,374 1,687 1,687 1,687
GX 900 1,518 3,036 1,518 1,518 1,518
GX 1150 1,518 3,036 1,518 1,518 1,518
continued...
Arria® 10 Device Overview
Intel® Arria® 10 Device Overview
19
Variant Product Line Variable-
precision
DSP Block
Independent Input and Output
Multiplications Operator
18 x 19
Multiplier
Adder Sum
Mode
18 x 18
Multiplier
Adder
Summed
with 36 bit
Input
18 x 19
Multiplier
27 x 27
Multiplier
Arria 10 GT GT 900 1,518 3,036 1,518 1,518 1,518
GT 1150 1,518 3,036 1,518 1,518 1,518
Arria 10 SX SX 160 156 312 156 156 156
SX 220 192 384 192 192 192
SX 270 830 1,660 830 830 830
SX 320 984 1,968 984 984 984
SX 480 1,368 2,736 1,368 1,368 1,368
SX 570 1,523 3,046 1,523 1,523 1,523
SX 660 1,687 3,374 1,687 1,687 1,687
Table 17. Resources for Floating-Point Arithmetic in Arria 10 Devices
The table lists the variable-precision DSP resources by bit precision for each Arria 10 device.
Variant Product Line Variable-
precision
DSP Block
Single
Precision
Floating-
Point
Multiplicatio
n Mode
Single-Precision
Floating-Point
Adder Mode
Single-
Precision
Floating-
Point
Multiply
Accumulate
Mode
Peak
Giga
Floating-
Point
Operations
per Second
(GFLOPs)
Arria 10 GX GX 160 156 156 156 156 140
GX 220 192 192 192 192 173
GX 270 830 830 830 830 747
GX 320 984 984 984 984 886
GX 480 1,369 1,368 1,368 1,368 1,231
GX 570 1,523 1,523 1,523 1,523 1,371
GX 660 1,687 1,687 1,687 1,687 1,518
GX 900 1,518 1,518 1,518 1,518 1,366
GX 1150 1,518 1,518 1,518 1,518 1,366
Arria 10 GT GT 900 1,518 1,518 1,518 1,518 1,366
GT 1150 1,518 1,518 1,518 1,518 1,366
Arria 10 SX SX 160 156 156 156 156 140
SX 220 192 192 192 192 173
SX 270 830 830 830 830 747
SX 320 984 984 984 984 886
SX 480 1,369 1,368 1,368 1,368 1,231
SX 570 1,523 1,523 1,523 1,523 1,371
SX 660 1,687 1,687 1,687 1,687 1,518
Arria® 10 Device Overview
Intel® Arria® 10 Device Overview
20
Embedded Memory Blocks
The embedded memory blocks in the devices are flexible and designed to provide an
optimal amount of small- and large-sized memory arrays to fit your design
requirements.
Types of Embedded Memory
The Arria 10 devices contain two types of memory blocks:
• 20 Kb M20K blocks—blocks of dedicated memory resources. The M20K blocks are
ideal for larger memory arrays while still providing a large number of independent
ports.
• 640 bit memory logic array blocks (MLABs)—enhanced memory blocks that are
configured from dual-purpose logic array blocks (LABs). The MLABs are ideal for
wide and shallow memory arrays. The MLABs are optimized for implementation of
shift registers for digital signal processing (DSP) applications, wide and shallow
FIFO buffers, and filter delay lines. Each MLAB is made up of ten adaptive logic
modules (ALMs). In the Arria 10 devices, you can configure these ALMs as ten
32 x 2 blocks, giving you one 32 x 20 simple dual-port SRAM block per MLAB.
Embedded Memory Capacity in Arria 10 Devices
Table 18. Embedded Memory Capacity and Distribution in Arria 10 Devices
Variant
Product
Line
M20K MLAB
Total RAM Bit
(Kb)Block RAM Bit (Kb) Block RAM Bit (Kb)
Arria 10 GX GX 160 440 8,800 1,680 1,050 9,850
GX 220 587 11,740 2,703 1,690 13,430
GX 270 750 15,000 3,922 2,452 17,452
GX 320 891 17,820 4,363 2,727 20,547
GX 480 1,431 28,620 6,662 4,164 32,784
GX 570 1,800 36,000 8,153 5,096 41,096
GX 660 2,131 42,620 9,260 5,788 48,408
GX 900 2,423 48,460 15,017 9,386 57,846
GX 1150 2,713 54,260 20,774 12,984 67,244
Arria 10 GT GT 900 2,423 48,460 15,017 9,386 57,846
GT 1150 2,713 54,260 20,774 12,984 67,244
Arria 10 SX SX 160 440 8,800 1,680 1,050 9,850
SX 220 587 11,740 2,703 1,690 13,430
SX 270 750 15,000 3,922 2,452 17,452
SX 320 891 17,820 4,363 2,727 20,547
SX 480 1,431 28,620 6,662 4,164 32,784
SX 570 1,800 36,000 8,153 5,096 41,096
SX 660 2,131 42,620 9,260 5,788 48,408
Arria® 10 Device Overview
Intel® Arria® 10 Device Overview
21
Embedded Memory Configurations for Single-port Mode
Table 19. Single-port Embedded Memory Configurations for Arria 10 Devices
This table lists the maximum configurations supported for single-port RAM and ROM modes.
Memory Block Depth (bits) Programmable Width
MLAB 32 x16, x18, or x20
64 10 x8, x9, x10
M20K 512 x40, x32
1K x20, x16
2K x10, x8
4K x5, x4
8K x2
16K x1
Clock Networks and PLL Clock Sources
The clock network architecture is based on Intel's global, regional, and peripheral
clock structure. This clock structure is supported by dedicated clock input pins,
fractional clock synthesis PLLs, and integer I/O PLLs.
Clock Networks
The Arria 10 core clock networks are capable of up to 800 MHz fabric operation across
the full industrial temperature range. For the external memory interface, the clock
network supports the hard memory controller with speeds up to 2,666 Mbps in a
quarter-rate transfer.
To reduce power consumption, the Quartus Prime software identifies all unused
sections of the clock network and powers them down.
Fractional Synthesis and I/O PLLs
Arria 10 devices contain up to 32 fractional synthesis PLLs and up to 16 I/O PLLs that
are available for both specific and general purpose uses in the core:
• Fractional synthesis PLLs—located in the column adjacent to the transceiver blocks
• I/O PLLs—located in each bank of the 48 I/Os
Fractional Synthesis PLLs
You can use the fractional synthesis PLLs to:
• Reduce the number of oscillators that are required on your board
• Reduce the number of clock pins that are used in the device by synthesizing
multiple clock frequencies from a single reference clock source
10 Supported through software emulation and consumes additional MLAB blocks.
Arria® 10 Device Overview
Intel® Arria® 10 Device Overview
22
The fractional synthesis PLLs support the following features:
• Reference clock frequency synthesis for transceiver CMU and Advanced Transmit
(ATX) PLLs
• Clock network delay compensation
• Zero-delay buffering
• Direct transmit clocking for transceivers
• Independently configurable into two modes:
— Conventional integer mode equivalent to the general purpose PLL
— Enhanced fractional mode with third order delta-sigma modulation
• PLL cascading
I/O PLLs
The integer mode I/O PLLs are located in each bank of 48 I/Os. You can use the I/O
PLLs to simplify the design of external memory and high-speed LVDS interfaces.
In each I/O bank, the I/O PLLs are adjacent to the hard memory controllers and LVDS
SERDES. Because these PLLs are tightly coupled with the I/Os that need to use them,
it makes it easier to close timing.
You can use the I/O PLLs for general purpose applications in the core such as clock
network delay compensation and zero-delay buffering.
Arria 10 devices support PLL-to-PLL cascading.
FPGA General Purpose I/O
Arria 10 devices offer highly configurable GPIOs. Each I/O bank contains 48 general
purpose I/Os and a high-efficiency hard memory controller.
The following list describes the features of the GPIOs:
• Consist of 3 V I/Os for high-voltage application and LVDS I/Os for differential
signaling
— Up to two 3 V I/O banks, available in some devices, that support up to 3 V I/O
standards
— LVDS I/O banks that support up to 1.8 V I/O standards
• Support a wide range of single-ended and differential I/O interfaces
• LVDS speeds up to 1.6 Gbps
• Each LVDS pair of pins has differential input and output buffers, allowing you to
configure the LVDS direction for each pair.
• Programmable bus hold and weak pull-up
• Programmable differential output voltage (VOD) and programmable pre-emphasis
Arria® 10 Device Overview
Intel® Arria® 10 Device Overview
23
• Series (RS) and parallel (RT) on-chip termination (OCT) for all I/O banks with OCT
calibration to limit the termination impedance variation
• On-chip dynamic termination that has the ability to swap between series and
parallel termination, depending on whether there is read or write on a common
bus for signal integrity
• Easy timing closure support using the hard read FIFO in the input register path,
and delay-locked loop (DLL) delay chain with fine and coarse architecture
External Memory Interface
Arria 10 devices offer massive external memory bandwidth, with up to seven 32-bit
DDR4 memory interfaces running at up to 2,666 Mbps. This bandwidth provides
additional ease of design, lower power, and resource efficiencies of hardened high-
performance memory controllers.
The memory interface within Arria 10 FPGAs and SoCs delivers the highest
performance and ease of use. You can configure up to a maximum width of 144 bits
when using the hard or soft memory controllers. If required, you can bypass the hard
memory controller and use a soft controller implemented in the user logic.
Each I/O contains a hardened DDR read/write path (PHY) capable of performing key
memory interface functionality such as read/write leveling, FIFO buffering to lower
latency and improve margin, timing calibration, and on-chip termination.
The timing calibration is aided by the inclusion of hard microcontrollers based on
Intel's Nios® II technology, specifically tailored to control the calibration of multiple
memory interfaces. This calibration allows the Arria 10 device to compensate for any
changes in process, voltage, or temperature either within the Arria 10 device itself, or
within the external memory device. The advanced calibration algorithms ensure
maximum bandwidth and robust timing margin across all operating conditions.
In addition to parallel memory interfaces, Arria 10 devices support serial memory
technologies such as the Hybrid Memory Cube (HMC). The HMC is supported by the
Arria 10 high-speed serial transceivers which connect up to four HMC links, with each
link running at data rates up to 15 Gbps.
Related Links
External Memory Interface Spec Estimator
Provides a parametric tool that allows you to find and compare the performance of
the supported external memory interfaces in IntelFPGAs.
Memory Standards Supported by Arria 10 Devices
The I/Os are designed to provide high performance support for existing and emerging
external memory standards.
Arria® 10 Device Overview
Intel® Arria® 10 Device Overview
24