CY7C1212H-133AXI - Cypress Semiconductor Corp.

1-Mbit (64K x 18) Pipelined Sync SRAM

CY7C1212H

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document #: 38-05668 Rev. *B Revised July 6, 2006

Features

• Registered inp uts and outputs for pipelined op eration

• 64K × 18 common I/O architecture

• 3.3V core power supply (VDD)

• 2.5V/3.3V I/O power supply (VDDQ)

• Fast clock-to-output times

— 3.5 ns (for 166-MHz device)

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel®

Pentium® interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed write

• Asynchr onous output ena bl e

• Available in JEDEC-standard lead-free 100-Pin TQFP

package

• “ZZ” Sleep Mode Option

Functional Description[1]

The CY7C1212H SRAM integrates 64K x 18 SRAM cells with

advanced synchronous peripheral circuitry and a two-bit

counter for internal burst operation. All synchronous inputs are

gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, address-pipelining Chip Enable

(CE1), depth-expansion Chip Enables (CE2 and CE3), Burst

Control inputs (ADSC, ADSP, and ADV), Write Enables

(BW[A:B], and BWE), and Global Write (GW). Asynchronous

inputs include the Output Enable (OE) and the ZZ pin.

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to two bytes wide as

controlled by the Byte Write control inputs. GW when active

LOW causes all bytes to be written.

The CY7C1212H operates from a +3.3V core power supply

while all outputs may operate either with a +2.5V or +3.3V

supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

0, A1, A ADDRESS

ADV

CLK BURST

COUNTER

AND

LOGIC

CLR

ADSC

BWB

BWA

CE1

DQB,DQPB

WRITE REGISTER

DQA,DQPA

WRITE REGISTER

ENABLE

SENSE

AMPS

MEMORY

ARRAY

ADSP

MODE

CE2

CE3

BWE

PIPELINED

ENABLE

DQs

DQP

OUTPUT

REGISTERS

INPUT

REGISTERS

DQP

WRITE DRIVER

OUTPUT

BUFFERS

DQP

WRITE DRIVER

A[1:0]

Logic Block Diagram

CY7C1212H

Document #: 38-05668 Rev. *B Page 2 of 15

Pin Configuration

Selection Guide

166 MHz 133 MHz Unit

Maximum Access T i me 3.5 4.0 ns

Maximum Operating Current 240 225 mA

Maximum CMOS Standby Current 40 40 mA

NC/72M

NC/36M

VSS

VDD

NC/18M

NC/9M

NC/2M

NC/4M

VDDQ

VSS

DQPA

DQA

VSS

VDDQ

DQA

VSS

VDD

DQA

VDDQ

VSS

DQA

VSS

VDDQ

DDQ

DQP

DDQ

CE1

CE2

BWB

BWA

CE3

VDD

VSS

CLK

BWE

ADSC

ADSP

ADV

100

MODE

BYTE A

BYTE B

CY7C1212H

100-Pin TQFP

Top View

CY7C1212H

Document #: 38-05668 Rev. *B Page 3 of 15

Pin Definitions

Name I/O Description

A0, A1, A I nput-

Synchronous Address Inputs used to select one of the 64K address locations. Sampled at the rising edge

of the CLK if ADSP or ADSC is active LO W, and CE1, CE2, and CE3 are sampled active. A1, A0

feed the 2-bit counter.

BWA,BWBInput-

Synchronous Byte Write Select Input s, active LOW. Qualified with BWE to conduct Byte Writes to the SRAM.

Sampled on the rising edge of CLK.

GW Input-

Synchronous Global Write Enable Input, active LOW . When asserted LOW on the rising edge of CLK, a global

Write is conducted (ALL bytes are written, regardless of the values on BW[A:B] and BWE).

BWE Input-

Synchronous Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be

asserted LOW to conduct a Byte Write.

CLK Input-

Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the

burst counter when ADV is asserted LOW , during a burst operation.

CE1Input-

Synchronous Chip Enable 1 Input, active LOW . Sampled on the rising edge of CLK. Used in conjunction with

CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only

when a new external address is loaded.

CE2Input-

Synchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with

CE1 and CE3 to select/deselect the device. CE2 is sampled only when a new external address is

loaded.

CE3Input-

Synchronous Chip Enable 3 Input, active LOW . Sampled on the rising edge of CLK. Used in conjunction with

CE1 and CE2 to select/deselect the device. Not connected for BGA. Where referenced, CE3 is

assumed active throughout this document for BGA. CE3 is sampled only when a new external

address is loaded.

OE Input-

Asynchronous Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When

LOW , the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as

input data pins. OE is masked during the first clock of a Read cycle when emerging from a

deselected state.

ADV Input-

Synchronous Advance Input signal, sa mpled on the rising edge of CLK, active LOW. When asserted, it

automatically increments the address in a burst cycle.

ADSP Input-

Synchronous Address Strobe from Processor, sampled on the rising edge of CL K, active LOW. When

asserted LOW, A is captured in the address registers. A1, A0 are also loaded into the burst counter.

When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1

is deasserted HIGH.

ADSC Input-

Synchronous Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When

asserted LOW, A is captured in the address registers. A1, A0 are also loaded into the burst

counter. When ADSP and ADSC are both asserted, only ADSP is recognized.

ZZ Input-

Asynchronous ZZ “Sleep” Input, active HIGH. This input, when HIGH places the device in a non-time-critical

“sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or

left floating. ZZ pin has an internal pull-down.

DQs

DQPA,

DQPB

I/O-

Synchronous Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered

by the rising edge of CLK. As outputs, they deliver the data contained in the memory location

specified by “A” during the previous clock rise of the Read cycle. The direction of the pins is

controlled by OE. When OE is asserted LOW , the pins behave as outputs. When HIGH, DQs and

DQP[A:B] are placed in a tri-state condition.

VDD Power Supply Power supply inputs to the core of the device.

VSS Ground Ground for the device.

VDDQ I/O Power

Supply Power supply for the I/O circuitry.

MODE Input-

Static Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left

floating selects interleaved burst sequence. This is a strap pin and should remain static during

device operation. Mode pin has an internal pull-up.

NC No Connects. Not internally connected to the die. 2M, 4M, 9M,18M, 72M, 144M, 288M, 576M

and 1G are address expansion pins and are not internally connected to the die.

CY7C1212H

Document #: 38-05668 Rev. *B Page 4 of 15

Functional Overview

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock.

The CY7C1212H supports secondary cache in systems

utilizing either a linear or interleaved burst sequence. The

interleaved burst order supports Pentium and i486™

processors. The linear burst sequence is suited for processors

that utilize a linear burst sequence. The burst order is user

selectable, and is determined by sampling the MODE input.

Accesses can be initiated with either the Processor Address

Strobe (ADSP) or the Controller Address Strobe (ADSC).

Address advancement through the burst sequence is

controlled by the ADV input. A two-bit on-chip wraparound

burst counter captures the first address in a burst sequence

and automatically increments the address for the rest of the

burst access.

Byte Write operations are qualified with the Byte Write Enable

(BWE) and Byte Write Select (BW[A:B]) inputs. A Global Write

Enable (GW) overrides all Byte Write inputs and writes data to

all four bytes. All Writes are simplified with on-chip

synchronous self-timed Write circuitry.

Three synchronous Chip Selects (CE1, CE2, CE3) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. ADSP is ignored if CE1

is HIGH.

Single Read Accesses

This access is initiated when the following conditions are

satisfied at clock rise: (1) ADSP or ADSC is asserted LOW , (2)

CE1, CE2, CE3 are all asserted active, and (3) the Write

signals (GW , BWE) are all deserted HIGH. ADSP is ignored if

CE1 is HIGH. The address presented to the address inputs (A)

is stored into the address advancement logic and the address

sponding data is allowed to propagate to the input of the output

registers. At the rising edge of the next clock the data is

allowed to propagate through the output register and onto the

data bus within tCO if OE is active LOW. The only exception

occurs when the SRAM is emerging from a deselected state

to a selected state, it s outputs are always tri-stated during the

first cycle of the access. After the first cycle of the access, the

outputs are controlled by the OE signal. Consecutive single

Read cycles are supported. Once the SRAM is deselected at

clock rise by the chip select and either ADSP or ADSC signals,

its output will tri-state immediately.

Single Write Accesses Initiated by ADSP

This access is initiated when both of the following conditions

are satisfied at clock rise: (1) ADSP is asserted LOW, and

(2) CE1, CE2, CE3 are all asserted active. The address

presented to A is loaded into the address register and the

address advancement logic while being delivered to the

memory array . The W rite signals (GW , BWE, and BW[A:B]) and

ADV inputs are ignored during this first cycle.

ADSP-triggered Write accesses require two clock cycles to

complete. If GW is asserted LOW on the second clock rise, the

data presented to the DQ inputs is written into the corre-

sponding address location in the memory array. If GW is HIGH,

then the Write operation is controlled by BWE and BW[A:B]

signals. The CY7C1212H provides Byte Write capability that

is described in the Write Cycle Descriptions table. Asserting

the Byte Write Enable input (BWE) with the selected Byte

Wri te (BW [A:B]) input, will selectively write to only the desired

bytes. Bytes not selected during a Byte Write operation will

remain unaltered. A synchronous self-timed Write mechanism

has been provided to simplify the Write operations.

Because the CY7C1212H is a common I/O device, the Output

Enable (OE) must be deasserted HIGH before presenting data

to the DQ inputs. Doing so will tri-state the output drivers. As

a safety precaution, DQ are automatically tri-stated whenever

a Write cycle is detected, regardless of the state of OE.

Single Write Accesses Initiated by ADSC

ADSC Write accesses are initiated when the following condi-

tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is

deserted HIGH, (3) CE1, CE2, CE3 are all asserted active, and

(4) the appropriate combination of the Write inputs (GW , BWE,

and BW[A:B]) are asserted active to conduct a Write to the

desired byte(s). ADSC-triggered Write accesses require a

single clock cycle to complete. The address presented to A is

loaded into the address register and the address

advancemen t logic while being delivered to the memory array.

The ADV input is ignored during this cycle. If a global Write is

conducted, the data presented to DQs is written into the corre-

sponding address location in the memory core. If a Byte Write

is conducted, only the selected bytes are written. Bytes not

selected during a Byte Write operation will remain unalte red.

A synchronous self-timed Write mechanism has been

provided to simplify the Write operations.

Because the CY7C1212H is a common I/O device, the Output

Enable (OE) must be deasserted HIGH before presenting data

to the DQ inputs. Doing so will tri-state the output drivers. As

a safety precaution, DQs are automatically tri-stated whenever

a Write cycle is detected, regardless of the state of OE.

Burst Sequences

The CY7C1212H provides a two-bit wraparound counter, fed

by A1, A0, that implements either an interleaved or linear burst

sequence. The interleaved burst sequence is designed specif-

ically to support Intel Pentium applications. The linear burst

sequence is designed to support processors that follow a

linear burst se quence. T he burst seq uence is user se lectable

through the MODE input.

Asserting ADV LOW at clock rise will automatically increment

the burst counter to the next address in the burst sequence.

Both Read and Write burst operations are supported.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ

places the SRAM in a power conservation “sleep” mode. Two

clock cycles are required to enter into or exit from this “sleep”

mode. While in this mode, data integrity is guaranteed.

Accesses pending when entering the “sleep” mode are not

considered valid nor is the completion of the operation

guaranteed. The device must be deselected p rior to entering

the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must

remain inactive for the duration of tZZREC after the ZZ input

returns LOW.

CY7C1212H

Document #: 38-05668 Rev. *B Page 5 of 15

Interleaved Burst Address Table

(MODE = Floating or VDD)

First

Address

A1, A0

Second

Address

A1, A0

Third

Address

A1, A0

Fourth

Address

A1, A0

00 01 10 11

01 00 11 10

10 11 00 01

11 10 01 00

Linear Burst Address Table (MODE = GND)

First

Address

A1, A0

Second

Address

A1, A0

Third

Address

A1, A0

Fourth

Address

A1, A0

00 01 10 11

01 10 11 00

10 11 00 01

11 00 01 10

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min. Max. Unit

IDDZZ Sleep mode standby current ZZ > VDD – 0.2V 40 mA

tZZS Device operation to ZZ ZZ > VDD – 0.2V 2tCYC ns

tZZREC ZZ recovery time ZZ < 0.2V 2tCYC ns

tZZI ZZ Active to sleep current This parameter is sampled 2tCYC ns

tRZZI ZZ Inactive to exit sleep current This parameter is sampled 0 ns

Truth Table[2, 3, 4, 5, 6, 7]

Next Cycle Add. Used CE1CE2CE3ZZ ADSP ADSC ADV OE DQ Write

Unselected None H X X L X L X X Tri-State X

Unselected None L X H L L X X X Tri-State X

Unselected None L L X L L X X X Tri-State X

Unselected None L X H L H L X X Tri-State X

Unselected None L L X L H L X X Tri-State X

Begin Read External L H L L L X X X Tri-State X

Begin Read External L H L L H L X X Tri-State Read

Continue Read Next X X X L H H L H Tri-State Read

Continue Read Next X X X L H H L L DQ Read

Continue Read Next H X X L X H L H Tri-State Read

Continue Read Next H X X L X H L L DQ Read

Suspend Read Current X X X L H H H H Tri-State Read

Suspend Read Current X X X L H H H L DQ Read

Suspend Read Current H X X L X H H H Tri-State Read

Suspend Read Current H X X L X H H L DQ Read

Begin Write Current X X X L H H H X Tri-State Write

Notes:

2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.

3. WRITE = L when any one or more Byte Write Enable signals (BW A,BWB) and BWE = L o r GW = L. WRITE = H whe n a ll B yte wr ite en able signal s (BWA,BWB),

BWE, GW = H.

4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

5. CE1, CE2, and CE3 are available only in the TQFP package.

6. The SRAM always initiates a Read cycle when ADSP is asse rted, regardle ss of the st ate of G W , BWE, or B W[A:B]. W rites may occur only on subsequ ent clocks

after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to tri-state. OE is a

don't care for the remain der of the Write cycle.

7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are Tri-State when OE

is inactive or when the device is deselecte d, and all data bits behave as output when OE is active (LOW).

CY7C1212H

Document #: 38-05668 Rev. *B Page 6 of 15

Begin Write Current H X X L X H H X Tri-State Write

Begin Write External L H L L H H X X Tri-State Write

Continue Write Next X X X L H H H X Tri-State Write

Continue Write Next H X X L X H H X Tri-State Write

Suspend Write Current X X X L H H H X Tri-State Write

Suspend Write Current H X X L X H H X Tri-State Write

ZZ “Sleep” None X X X H X X X X Tri-State X

Truth Table for Read/Write[2, 3]

Function GW BWE BWBBWA

Read H H X X

Read H L H H

Write Byte A – (DQA and DQPA)HLHL

Write Byte B – (DQB and DQPB)HLLH

Write All Bytes H L L L

Write All Bytes L X X X

Truth Table[2, 3, 4, 5, 6, 7] (continued)

Next Cycle Add. Used CE1CE2CE3ZZ ADSP ADSC ADV OE DQ Write

CY7C1212H

Document #: 38-05668 Rev. *B Page 7 of 15

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature ............. ... ... ... ..........–65°C to + 150°C

Ambient Temperature with

Power Applied.............. ... ... .............. ... .......–55°C to + 125°C

Supply Voltage on VDD Relative to GND.......–0.5V to + 4.6V

Supply Voltage on VDDQ Relative to GND.....–0.5V to + VDD

DC Voltage Applied to Outputs

in Tri-State....................... .............. ... ...–0.5V to VDDQ + 0.5V

DC Input Voltage ....................... ... .........–0.5V to VDD + 0.5V

Current into Outputs (LOW).........................................20 mA

Static Discharge Voltage........................................... >2001V

(per MIL-STD-883, Method 3015)

Latch-up Current..................................................... >200 mA

Operating Range

Range Ambient

Temperature VDD VDDQ

Commercial 0°C to +70°C 3.3V

–5%/+10% 2.5V –5% to

VDD

Industrial –40°C to +85°C

Electrical Characteristics Over the Operating Range[8, 9]

Parameter Description Test Conditions Min. Max. Unit

VDD Power Supply Voltage 3.135 3.6 V

VDDQ I/O Supply Voltage for 3.3V I/O 3.135 VDD V

for 2.5V I/O 2.375 2.625 V

VOH Output HIGH Voltage for 3.3V I/O, IOH = –4.0 mA 2.4 V

for 2.5V I/O, IOH = –1.0 mA 2.0 V

VOL Output LOW Voltage for 3.3V I/O, IOL = 8.0 mA 0.4 V

for 2.5V I/O, IOL = 1.0 mA 0.4 V

VIH Input HIGH Voltage[8] for 3.3V I/O 2.0 VDD + 0.3V V

for 2.5V I/O 1.7 VDD + 0.3V V

VIL Input LOW Voltage[8] for 3.3V I/O –0.3 0.8 V

for 2.5V I/O –0.3 0.7 V

IXInput Leakage Current

except ZZ and MODE GND ≤ VI ≤ VDDQ –5 5µA

Input Curre n t of MODE Input = VSS –30 µA

Input = VDD 5µA

Input Curre n t of ZZ Input = VSS –5 µA

Input = VDD 30 µA

IOZ Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled –5 5µA

IDD VDD Operating Supply

Current VDD = Max., IOUT = 0 mA,

f = fMAX = 1/t CYC 6-ns cycle,166 MHz 240 mA

7.5-ns cycle,133 MHz 225 mA

ISB1 Automatic CS

Power-down

Current—TTL Inputs

VDD = Max, Device Deselected,

VIN ≥ VIH or VIN ≤ VIL

f = fMAX = 1/t CYC

6-ns cycle,166 MHz 100 mA

7.5-ns cycle,133 MHz 90

ISB2 Automatic CS

Power-down

Current—CMOS Inputs

VDD = Max, Device Deselected,

VIN ≤ 0.3V or VIN > VDDQ – 0.3V,

f = 0

All speeds 40 mA

ISB3 Automatic CS

Power-down

Current—CMOS Inputs

VDD = Max, Device Deselected, or

VIN ≤ 0.3V or VIN > VDDQ – 0.3V

f = fMAX = 1/t CYC

6-ns cycle,166 MHz 85 mA

7.5-ns cycle,133 MHz 75 mA

ISB4 Automatic CS

Power-down

Current—TTL Inputs

VDD = Max, Device Deselected,

VIN ≥ VIH or VIN ≤ VIL, f = 0 All speeds 45 mA

Notes:

8. Overshoot: VIH(AC) < VDD+1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2).

9. TPower-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.

CY7C1212H

Document #: 38-05668 Rev. *B Page 8 of 15

Capacitance[10]

Parameter Description Test Conditions 100 TQFP

Max. Unit

CIN Input Capacitance TA = 25°C, f = 1 MHz,

VDD = 3.3V.

VDDQ = 2.5V

5pF

CCLK Clock Input Capacitance 5 pF

CI/O Input/Output Capacitance 5 pF

Thermal Resistance[10]

Parameter Description Test Conditions 100 TQFP

Package Unit

ΘJA Thermal Resistance

(Junction to Ambient) Test cond itions follow standard test methods and

procedures for measuring thermal impedance, per

EIA/JESD51

30.32 °C/W

ΘJC Thermal Resistance

(Junction to Case) 6.85 °C/W

AC Test Loads and W ave forms

Note:

10.Tested initially and after any design or process change that may affect these parameters.

OUTPUT

R = 317Ω

R = 351Ω

5pF

INCLUDING

JIG AND

SCOPE

(a) (b)

OUTPUT

RL= 50Ω

Z0= 50Ω

= 1.5V

3.3V ALL INPUT PULSES

VDDQ

GND

90%

10% 90%

10%

≤1 ns ≤1 ns

(c)

OUTPUT

R = 1667Ω

R =1538Ω

5pF

INCLUDING

JIG AND

SCOPE

(a) (b)

OUTPUT

RL= 50Ω

Z0= 50Ω

VT= 1.25V

2.5V ALL INPUT PULSES

VDDQ

GND

90%

10% 90%

10%

≤1 ns ≤

1 ns

(c)

3.3V I/O Test Load

2.5V I/O Test Load

CY7C1212H

Document #: 38-05668 Rev. *B Page 9 of 15

Switching Characteristics Over the Operating Range[11, 12]

Parameter Description

166 MHz 133 MHz

UnitMin. Max. Min. Max.

tPOWER VDD(Typical) to the First Access[13] 11ms

Clock

tCYC Clock Cycle Time 6.0 7.5 ns

tCH Clock HIGH 2.5 3.0 ns

tCL Clock LOW 2.5 3.0 ns

Output Times

tCO Data Output Valid after CLK Rise 3.5 4.0 ns

tDOH Data Output Hold after CLK Rise 1.5 1.5 ns

tCLZ Clock to Low-Z[14, 15, 16] 00ns

tCHZ Clock to High-Z[14, 15, 16] 3.5 4.0 ns

tOEV OE LOW to Output Valid 3.5 4.5 ns

tOELZ OE LOW to Output Low-Z[14, 15, 16] 00ns

tOEHZ OE HIGH to Output High-Z[14, 15, 16 ] 3.5 4.0 ns

Set-up Times

tAS Address Set-up before CLK Rise 1.5 1.5 ns

tADS ADSC, ADSP Set-up before CLK Rise 1.5 1.5 ns

tADVS ADV Set-up before CLK Rise 1.5 1.5 ns

tWES GW, BWE, BW[A:B] Set-up before CLK Rise 1.5 1.5 ns

tDS Data Input Set-up before CLK Rise 1.5 1.5 ns

tCES Chip Enable Set-Up before CLK Rise 1.5 1.5 ns

Hold Times

tAH Address Hold after CLK Rise 0.5 0.5 ns

tADH ADSP, ADSC Hold after CLK Rise 0.5 0.5 ns

tADVH ADV Hold after CLK Rise 0.5 0.5 ns

tWEH GW, BWE, BW[A:B] Hold after CLK Rise 0.5 0.5 ns

tDH Data Input Hold after CLK Rise 0.5 0.5 ns

tCEH Chip Enable Hold after CLK Rise 0.5 0.5 ns

Notes:

11.Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.

12.Test conditions shown in (a) of AC Test Loads unless otherwise tested.

13.This part has a volt age regulator internally; tPOWER is the time that the power nee ds to be supplied above VDD(minimum) initially before a Read or W rite operation

can be initiated.

14.tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in pa rt (b) of AC Test Loads. Transition is measured ± 20 0 mV from steady-state voltage.

15.At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus content ion between SRAMs when sharing the same

data bus. These specifi ca tions do no t i mply a bus con tentio n condi tio n, b ut ref lect p aramet ers gu arantee d over worst case u ser condi tions. Device is d esigned

to achieve High-Z prior to Low-Z under the same system conditions.

16.This parameter is sampled and not 100% tested.

CY7C1212H

Document #: 38-05668 Rev. *B Page 10 of 15

Switching Waveforms

Read Cycle Timing[17]

Note:

17.On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

tCYC

tCL

CLK

ADSP

tADH

tADS

ADDRESS

tCH

ADSC

tAH

tAS

tCEH

tCES

GW, BWE,

[A:B]

ata Out (Q) High-Z

tCLZ tDOH

tCO

ADV

tOEHZ

tCO

Single READ BURST READ

tOEV

tOELZ tCHZ

ADV

suspends

burst.

Burst wraps around

to its initial state

tADVH

tADVS

tWEH

tWES

tADH

tADS

Q(A2) Q(A2 + 1) Q(A2 + 2)

Q(A1) Q(A2) Q(A2 + 1)Q(A2 + 3)

A2 A3

Deselect

cycle

Burst continued with

new base address

DON’T CARE UNDEFINED

CY7C1212H

Document #: 38-05668 Rev. *B Page 11 of 15

Write Cycle Timing[17, 18]

Note:

18.Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:B] LOW.

Switching Waveforms (continued)

tCYC

tCL

CLK

ADSP

tADH

tADS

ADDRESS

tCH

ADSC

tAH

tAS

tCEH

tCES

BWE,

BW[A :D]

ata Out (Q)

High-Z

ADV

BURST READ BURST WRITE

D(A2) D(A2 + 1) D(A2 + 1)

D(A1) D(A3) D(A3 + 1) D(A3 + 2)D(A2 + 3)

A2 A3

Data In (D)

Extended BURST WRITE

D(A2 + 2)

Single WRITE

tADH

tADS

tADH

tADS

tOEHZ

tADVH

tADVS

tWEH

tWES

tDH

tDS

tWEH

tWES

Byte write signals are

ignored for first cycle when

ADSP initiates burst

ADSC extends burst

ADV suspends burst

DON’T CARE UNDEFINED

CY7C1212H

Document #: 38-05668 Rev. *B Page 12 of 15

Read/Write Cycle Timing[17, 19, 20 ]

Notes:

19.The data bus (Q) remains in High-Z following a Write cycle unless an ADSP, ADSC, or ADV cycle is performed.

20.GW is HIGH.

Switching Waveforms (continued)

tCYC

tCL

CLK

ADSP

tADH

tADS

ADDRESS

tCH

ADSC

tAH

tAS

tCEH

tCES

BWE,

[A:B]

ata Out (Q)

High-Z

ADV

Single WRITE

D(A3)

A4 A5 A6

D(A5) D(A6)

Data In (D)

BURST READBack-to-Back READs

High-Z

Q(A2)Q(A1) Q(A4) Q(A4+1) Q(A4+2)

tWEH

tWES

Q(A4+3)

tOEHZ

tDH

tDS

tOELZ

tCLZ

tCO

Back-to-Back

WRITEs

DON’T CARE UNDEFINED

CY7C1212H

Document #: 38-05668 Rev. *B Page 13 of 15

ZZ Mode Timing[21, 22]

Notes:

21.Device must be deselected when entering ZZ mode. See Cycle Descript ions table for all possible signal conditions to deselect the device.

22.DQs are in High-Z when exiting ZZ sleep mode.

Switching Waveforms (continued)

tZZ

SUPPLY

CLK

tZZREC

LL INPUTS

(except ZZ)

DON’T CARE

IDDZZ

tZZI

tRZZI

Outputs (Q)

High-Z

DESELECT or READ Only

CY7C1212H

Document #: 38-05668 Rev. *B Page 14 of 15

© Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is subject to change wi t hou t n oti ce. C ypr ess S em ic onductor Corporation assumes no resp onsibility f or the u se

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypr ess. Furtherm ore, Cypress doe s not authorize i ts

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant inju ry to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

i486 is a trademark, and Intel and Pentium are registered tra demarks, of Intel Corporation. Po werPC is a registered trademark

of IBM Corporation. All product and company names mentioned in this document may be trademarks of their respective holders.

Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered.

Speed

(MHz) Ordering Code Package

Diagram Package Type Operating

Range

100 CY7C1212H-100AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial

CY7C1212H-100AXI Industrial

133 CY7C1212H-133AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial

CY7C1212H-133AXI Industrial

Package Diagrams

NOTE:

1. JEDEC STD REF MS-026

2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH

MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE

3. DIMENSIONS IN MILLIMETERS

BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH

0.30±0.08

0.65

20.00±0.10

22.00±0.20

1.40±0.05

12°±1°

1.60 MAX.

0.05 MIN.

0.60±0.15

0° MIN.

0.25

0°-7°

(8X)

STAND-OFF

R 0.08 MIN.

TYP.

0.20 MAX.

0.15 MAX.

0.20 MAX.

R 0.08 MIN.

0.20 MAX.

14.00±0.10

16.00±0.20

0.10

SEE DETAIL A

DETAIL

100

31 50

GAUGE PLANE

1.00 REF.

0.20 MIN.

SEATING PLANE

100-Pin TQFP (14 x 20 x 1.4 mm) (51-85050)

51-85050-*B

CY7C1212H

Document #: 38-05668 Rev. *B Page 15 of 15

Document History Page

Document Title: CY7C1212H 1-Mbit (64K x 18) Pipelined Sync SRAM

Document Number: 38-05668

REV. ECN NO. Issue Date Orig. of

Change Description of Change

** 343896 See ECN PCI New Data Sheet

*A 430677 See ECN NXR Changed address of Cypress Semiconductor Corporation on Page# 1 from

“3901 North First Street” to “198 Champion Court”

Added 2.5VI/O option

Changed Three-State to Tri-Sta te

Included Maximum Ratings for VDDQ relative to GND

Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the

Electrical Characteristics Table

Modified test condition from VIH < VDD to VIH < VDD

Replaced Package Name column with Package Diagram in the Ordering

Information table

*B 482139 See ECN VKN Converted from Preliminary to Final.

Updated the Ordering Information table.