L6935TR - STMicroelectronics

May 2008 Rev 1 1/20

L6935

High performance 3 A ULDO linear regulator

Features

■Up to 5 V input voltage range

■60 mΩ max RDS(on)

■35 µA shut-down current

■3 A maximum output current

■Split bias and power supplies

■Adjustable output voltage: 0.5 V to 3.0 V

■Excellent load and line regulation: 1 %

accuracy (over temperature)

■MLCC supported

■Programmable soft-start

■Short-circuit protection

■3.5 A overcurrent protection

■Thermal shut-down

■VFQFPN20 4 x 4 x 1.0 mm package

Applications

■Motherboard

■Mobile PC

■Hand-held instruments

■PCMCIA cards

■Processors I/O

■Chipset and RAM supply

Description

L6935 is an ultra low drop output linear regulator

operating up to 5 V input and is able to support

output current up to 3 A. Designed with an

internal low-RDS(on) N-channel MOSFET, it can

be used for on-board DC-DC conversions saving

in real estate, list of components and power

dissipation.

Bias input and power input are split to allow linear

conversion from buses lower than 1.2 V

minimizing power losses.

L6935 provides the application with an adjustable

voltage from 0.5 V to 3.0 V with a voltage

regulation accuracy of 1 %. soft-start is available

to program the output voltage rise-time according

to the external capacitor connected.

Enable and Power Good functions make L6935

suitable for complex systems and programmable

start-up sequencing.

The current limit at 3 A protects the system during

a short circuit. The current is sensed in the power

DMOS in order to limit the power dissipation.

Thermal shut down limits the internal temperature

at 150 °C with a hysteresis of 20 °C.

VFQFPN20

(4.0 x 4.0 x 1.0 mm)

Table 1. Device summary

Order codes Package Packing

L6935 VFQFPN20 Tu b e

L6935TR Tape and reel

www.st.com

Contents L6935

2/20

Contents

1 Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 3

1.1 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Pins description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . 5

2.1 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4 Typical performances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5.1 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5.2 Power Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.3 VIN vs VBIAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.4 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.4.1 Over-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.4.2 Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.1 Components selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.1.1 Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.1.2 Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6.2 VIN, VBIAS and sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

7 Demonstration board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

8 VFQFPN20 mechanical data and package dimensions . . . . . . . . . . . . 18

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Typical application circuit and block diagram L6935

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1 Typical application circuit and block diagram

1.1 Application circuit

Figure 1. Typical application circuit - VIN = VBIAS

Figure 2. Typical application circuit - VIN ≠ VBIAS

L6935 Reference Schematic

OUT

= 0.5V to 3.0V

PGOOD

L6935

VIN

SS GND PGOOD

VOUT

ADJ

VBIAS

PAD

CSS

L6935 Reference Schematic

VIN = 0.75V to VBIAS

CIN

COUT

VOUT > 0.5V (*)

PGOOD

L6935

VIN

SS GND PGOOD

VOUT

ADJ

VBIAS

PAD

VBIAS

(*) Vin may decrease until the minimum drop is reached. Conversely, Vout can rise untile the minimum drop is reached.

Typical application circuit and block diagram L6935

4/20

1.2 Block diagram

Figure 3. Block diagram

REFERENCE

0.500V

CURRENT

LIMIT

THERMAL

SENSOR

ENABLEEN

VIN

ADJ

PGOOD

GND

CHARGE

PUMP

ERROR

AMPLIFIER DRIVER

VREF

0.9 VREF

VBIAS

VOUT

Pins description and connection diagrams L6935

5/20

2 Pins description and connection diagrams

Figure 4. Pins connection (top view)

2.1 Pin descriptions

GND

N.C.

PGOOD

N.C.

L6935

VOUT

ADJ

VIN

10987

16 17 18 19

N.C.

VBIAS

N.C.

Table 2. Pins descriptions

Pin # Name Function

1 N.C. Not internally connected.

2 GND Ground connection. Connect to PCB ground plane.

3, 4 N.C. Not internally connected.

5 PGOOD

Power Good output flag: the pin is open drain and it is forced low if the

output voltage is lower than 90 % of the programmed voltage. If not used, it

can be left floating.

6 VBIAS

Input bias supply. This pin supplies the internal logic to drive the power

N-channel MOSFET that realize the voltage conversion. Connect directly to

VIN or to a different supply ranging from VIN to 5 V.

The voltage connected to this pin MUST always be higher or equal that VIN.

7EN

Enables the device if a voltage higher than 1 V is applied.

When pulled low, the device is in low-power consumption: everything inside

the controller is kept OFF.

See Section 6.2 for details about EN signal and power sequencing.

8 to 10 VIN

Power supply voltage. This pin is connected to the drain of the internal

N-channel MOSFET.

Filter to GND with capacitor larger than the one used for VOUT

11 to15 N.C. Not internally connected.

16 to 18 VOUT

Regulated output voltage. This pin is connected to the source of the

internal N-mos. MLCC capacitor are supported. Filter to GND with

capacitor smaller than the one used for VIN.

Pins description and connection diagrams L6935

6/20

19 ADJ

Feedback for the IC regulation.

Connecting this pin through a voltage divider to VOUT

, it is possible to

program the output voltage between 0.5 V and 3.0 V.

20 SS

Soft-start pin. The soft-start time is programmed connecting an external

capacitor CSS from this pin to GND.

In steady state regulation, the voltage at this pin is 3.3 V.

PA D G N D Ground connection. Connect to PCB GND Plane with enough VIAs to

improve thermal conductivity.

Table 2. Pins descriptions (continued)

Pin # Name Function

Electrical specifications L6935

7/20

3 Electrical specifications

3.1 Absolute maximum ratings

Table 3. Absolute maximum ratings

3.2 Thermal data

Table 4. Thermal data

Symbol Parameter Value Unit

VIN to GND 5.5 V

VBIAS, EN, PGOOD to GND 6 V

SS, VOUT to GND -0.3 to 3.3 V

ADJ to GND -0.3 to 1 V

Maximum withstanding voltage range test condition:

CDF-AEC-Q100-002 “human body model”

acceptance criteria: “normal performance”

±1000 V

Symbol Parameter Value Unit

thJA

Thermal resistance junction to ambient(1)

1. Measured with the component mounted on demonstration board in free air (22 x 28.5 mm - 2 layer 70 µm

copper).

55 °C/W

MAX

Maximum junction temperature 150 °C

STG

Storage temperature range -50 to 150 °C

Junction temperature range -25 to 150 °C

Electrical specifications L6935

8/20

3.3 Electrical characteristics

Table 5. Electrical characteristics

(VIN = 5 V, VBIAS = 5 V; TA = 25 °C unless otherwise specified).

Symbol Parameter Test conditions Min Typ Max Unit

Recommended operating conditions

VIN Operating supply voltage VIN = VBIAS

VBIAS < 5 V

5.0

VBIAS

VBIAS UVLO VBIAS rising 1.275 V

IIN

Quiescent current Iout = 0 A 2.3 3 mA

Shut-down current VIN = VBIAS = 3.3 V

VIN = VBIAS = 5.0 V

40 µA

Voltage regulation

VOUT Output voltage Io = 0.1 A; VIN = 3.3 V; ADJ = OUT 0.496 0.500 0.504 V

ADJ Line regulation Vin = 3.30 V +/- 10 %; Io = 10 mA

Vin = 4.50 V +/- 10 %; Io = 10 mA

2.5

2.5 mV

Load regulation Vin = 3.3 V; Io = 100 mA to 3 A 7 mV

Ripple rejection (1)

1. Parameter guaranteed by design, not tested in production

F = 100...120 Hz; Io = 10 mA

Vin = 3 V; ∆Vin = 2 Vpp; Vout = 1 V 45 dB

RDS(on) Drain-to-source resistance Io = 3 A 30 60 mΩ

Enable, SS and protections

IOCP Current limiting Vo = 1.8 V 3.15 3.50 3.85 A

PGOOD

Power Good threshold VADJ falling, wrt Ref. 77 85 %

Hysteresis 10 %

Voltage low I = -1 mA 0.4 V

EN Enable threshold EN rising 1.05 V

SS Soft start current Vss = 0 V 1.0 µA

OT Thermal shut-down Temperature rising (1) 150 °C

Hysteresis (1) 20 °C

Typical performances L6935

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4 Typical performances

Figure 5. Output voltage and OC threshold vs junction temperature

Figure 6. Quiescent and shutdown current vs junction temperature

Figure 7. Line regulation

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

-40 -20 0 20 40 60 80 100 120 140

T em perat ur e [ ° C]

Out put Voltage [%]

3.0

3.2

3.4

3.6

3.8

4.0

-40 -20 0 20 40 60 80 100 120 140

T emperat ur e [ ° C]

OC Threshold [A

]

3.0

3.2

3.4

3.6

3.8

4.0

-40-200 20406080100120140

T emperat ur e [ °C]

Quiescent Current [mA

]

-40 -20 0 20 40 60 80 100 120 140

T emperat ur e [° C]

Shutdown Current [ uA

3 VIN

5 VIN

-0.2%

-0.1%

0.0%

0.1%

0.2%

1.01.52.02.53.03.54.04.55.0

VIN [V]

Line Regulation [%

]

VBI AS = VIN, VOUT = 0.5V

-0.2%

-0.1%

0.0%

0.1%

0.2%

2.0 2.5 3.0 3.5 4.0 4.5 5.0

VIN [V]

Line Regulation [%

]

VBIAS = 1.4V, VOUT = 2V

Typical performances L6935

10/20

Figure 8. Load regulation

-0.3%

-0.2%

-0.1%

0.0%

0.1%

0.2%

0.3%

0.0 0.5 1.0 1.5 2.0 2.5

Out put Current [A]

Load Regulation [ %

]

VBIAS = 1. 4V, VIN = 2. 6V, VO UT = 2V

-0.3%

-0.2%

-0.1%

0.0%

0.1%

0.2%

0.3%

0.0 0.5 1.0 1.5 2.0 2.5

Output Current [A]

Load Regulation [%

]

VBIAS = VIN = 1.4 V, VOUT = 0.5V

Device description L6935

11/20

5 Device description

5.1 Soft-start

L6935 implements a soft-start feature to smoothly charge the output filter avoiding high in-

rush currents to be required to the input power supply.

The soft-start process begins as soon as VBIAS reaches UVLO and ENABLE is asserted.

A constant current ISS = 1.0 µA is sourced through the SS pin: connecting an external

capacitor (CSS) to this pin a voltage ramp is implemented; the voltage ramp internally

clamps the E.A. reference, resulting in a controlled slope for the output voltage. As the

voltage on CSS reaches the VREF value the internal clamp is released.

In this way, the soft-start process lasts for:

where CSS is the external capacitor [F] and TSS is the soft-start time [sec.].

If the device is disabled (ENABLE low) and the VBIAS is still present, the SS pin is clamped

to GND for a fixed time of about 50 µs. in order to discharge the residual charge present on

CSS: in this way, the device will be ready for a new SS process as ENABLE is asserted

again.

Figure 9 describes a typical soft-start process.

Figure 9. Soft start process diagram (left) and measured (right)

TSS CSS

VREF

ISS

--------------

⋅510

5CSS F[]⋅⋅==

ENABLE

Vbias

ADJ

Vout

0.5V

>0.7V

>1.1V

Programmed Vout

~50µsec

Programmed Tss

Device description L6935

12/20

5.2 Power Good

L6935 presents a PGOOD flag, an open drain output that is grounded during all the soft

start procedure, and is left free when VOUT reaches 90 % of the programmed value.

An hysteresis of 10 % is also provided in order to avoid false triggering due to the noise

generated by the application. Figure 10 shows the PGOOD commutations.

Figure 10. Power good window

5.3 VIN vs VBIAS

L6935 provides the flexibility to supply the internal logic (VBIAS) with a supply different than

the power input (VIN). The aim of this feature is to provide low-drop regulation still having

the supply voltage to correctly drive the internal power mosfet so optimizing the conversion.

VIN drives only the drain of the power DMOS and it can be kept as low as possible

(VIN > VOUT + VDROPmin), while VBIAS drives the control section. VBIAS must be typically

higher than VIN.

5.4 Protections

L6935 is equipped with a set of protections in order to protect both the load and the device

from electrical overstress. Each protection does not latch the device, that returns to work

properly as the perturbation disappear.

5.4.1 Over-current protection

An over current protection is provided: if the current that flows through the power DMOS is

greater than 3.5 A, the device adjust the power DMOS driving voltage in order to keep

constant the delivered current (IOUT). Anyhow the output may drop also causing the

PGOOD to be set low.

Figure 11 show the way the OCP intervention: as the threshold value is reached by IOUT

, the

device forces a lower output current (~3.5 A).

Device description L6935

13/20

Figure 11. Over-current protection

5.4.2 Thermal protection

The device constantly monitors its internal temperature. As the silicon reaches a 150 °C, the

control circuit turns off the power DMOS, and stays off until a safe temperature of

150° - 20° = 130 °C. Figure 12 shows how the over-temperature protection intervention.

Figure 12. Over-temperature protection

Application information L6935

14/20

6 Application information

L6935 is the best choice in smart linear regulator applications, due to its own small size,

high power delivered and high regulation accuracy. Furthermore thermal shut-down and

OCP guarantee the highest reliability for each application.

VIN can be separated by VBIAS: in this way the device can regulate the output voltage even if

VIN < VBIAS, resulting in a better performance. In fact, the power dissipated decreases as

VIN get lower, according to the relationship PDISS = (VIN - VOUT) x IOUT

6.1 Components selection

6.1.1 Input capacitor

The choice of the input capacitor value depends on the several factor such as load transient

requirements, input source (battery or DC/DC converter) and its distance from the input

capacitor. Generally speaking, a capacitor with the lowest ESR possible should be chosen:

a value within the range [10 µF; 100 µF] can be sufficient in many cases.

6.1.2 Output capacitor

The choice of the output capacitor value basically depends on the load transient

requirement. Output capacitor must be sized according to the dynamic requests of the load.

A too small capacitor may exhibit huge voltage drop after a load transient is applied: a value

greater than 10 µF should be used.

In order to guarantee a good reliability, at least X5R type should be used as I/O capacitors.

Different kinds of input/output capacitors can be used: Table 6. shows a few tested

examples.

Table 6. Input/output capacitor selection guide

Manufacturer Type I/O cap. value Rated voltage

Murata - GRM31CR61ExxxK(1)

1. xxx in the part numbers stands for 106 (10 µF), 226 (22 µF)... 105 (100 µF)

MLCC, SMD1206, X5R 10...100 µF 6.3 - 25 V

Panasonic - ECJ3YB1AxxxM MLCC, SMD1206, X5R 10...100 µF 10 - 25 V

Panasonic - EEFFD0HxxxR SPCap - SMD7343

28 mΩ ESR 10...100 µF4 - 8 V

Sanyo - 8TPE100MPC2 POSCAP, SMD6032

25 mΩ ESR 10...100 µF 6.3 - 25 V

TDK - C3216X5R0JxxxMT MLCC, SMD1210, X5R 10...100 µF 6.3 V

Application information L6935

15/20

6.2 VIN, VBIAS and sequencing

Different configurations for VIN and VBIAS are possibleand the power sequencing must

consider the different timings in which the power suppliesbecomes available. In order to

properly drive the device internal logic, it is reccomendedto control the sequence between

EN signal and the VIN / VBIAS application: the device need to result being disabled when

VBIAS crosses the UVLO threshols. Furthermore, in case of VIN <> VBIAS, the EN signal

needs to be driven by the last-coming between the two supplies.

It is reccomended to drive the EN pin with a resistor divider connected as reported into

Figure 13 and Figure 14.

Figure 13. Recommended circuit for VBIAS = VIN

Figure 14. Reccomended circuit for VBIAS ≠ VIN

VIN

CIN COUT

VOUT = 0.5V to 3.0V

PGOOD

L6935

VIN

SS GND ADJ

VOUT

PGOOD

CSS

VBIAS

PAD

REH

REL

RPG

(OpenDrain Toggle **)

** Drive EN with external Open-Drain Signal.

OUT

VOUT = 0.5V to 3.0V

PGOOD

L6935

VIN

SS GND ADJ

VOUT

PGOOD

VBIAS

PAD

(OpenDrain Toggle **)

VBIAS

VIN (< VBIAS)

* EN Divider (REH) needs to be connected to the Last-Coming rail between VCC and VIN.

** Drive EN with external Open-Drain Signal.

Demonstration board description L6935

16/20

7 Demonstration board description

Figure 15 and Figure 16 show the schematic and the layout of the demonstration board

designed for L6935. VIN and VBIAS may be different and, in this case, R4 must not be

mounted. C3 defines the Soft-Start timer, according to the relationship described in the

Section 5.1.

The value of the output divider R1 / R2 have to be designed in order to program the desired

VOUT value, according to the following equation:

Figure 15. Demonstration board schematic

Figure 16. Demonstration board layout

VOUT 0.5=1R1

-------+

⎝⎠

⎛⎞

⋅

OUT

L6935

VIN

SS GND

VOUT

ADJ

VBIAS

PAD

BIAS

PGOOD

ADJ

6 16,17,18

8, 9, 10

GND

Demonstration board description L6935

17/20

Different values for R1 are available in order to program the value of VOUT (R2 = 10 kΩ)

VOUT = 0.50 VDC @ R1 = 0 Ω

VOUT = 0.75 VDC @ R1 = 5 kΩ

VOUT = 1.00 VDC @ R1 = 10 kΩ

VOUT = 1.25 VDC @ R1 = 15 kΩ

VOUT = 1.50 VDC @ R1 = 20 kΩ

VOUT = 3.00 VDC @ R1 = 50 kΩ

Table 7. L6935 demonstration board bill of material

Reference Description

C1, C2, c3 Chip capacitor 100 nF - 6.3 V - X5R

C4 Murata chip capacitor (GRM31CR60J226K) 1206, X5R, 6.3-25V, 22 µF

C5 Murata chip capacitor (GRM31CR61E106K) 1206, X5R, 6.3-25V, 10 µF

C6 Not mounted

R1 Chip resistor 15 kΩ +/-0.1% - 1/16 W

R2 Chip resistor 10 kΩ +/-0.1% - 1/16 W

R3, R5 Chip resistor 10 kΩ +/-5% - 1/16 W

R4 Chip resistor 0 Ω

VFQFPN20 mechanical data and package dimensions L6935

18/20

8 VFQFPN20 mechanical data and package dimensions

In order to meet environmental requirements, ST offers these devices in ECOPACK®

packages. These packages have a lead-free second level interconnect. The category of

second Level Interconnect is marked on the package and on the inner box label, in

compliance with JEDEC Standard JESD97. The maximum ratings related to soldering

conditions are also marked on the inner box label. ECOPACK is an ST trademark.

ECOPACK specifications are available at: www.st.com.

Figure 17. VFQFPN20 mechanical data and package dimensions

PACKAGE AND

PACKING INFORMATION

VFQFPN20 (4x4x1.00mm)

Weight: not available

DIMENSIONS

REF. mm mils

MIN. TYP. MAX. MIN. TYP. MAX.

A 0.80 0.90 1.00 31.496 35.433 39.370

A1 0.02 0.05

A2 0.65

A3 0.25

b 0.18 0.23 0.30

D 4.00

D2 2.70 2.80 2.90

e0.50

L 0.3 0.4 0.5

1.00

4.153.85

4.00 4.153.85

2.70 2.80 2.90

0.45 0.55

ddd 0.08

Very Fine Quad Flat

Package No lead

0.787 1.969

25.591 39.370

9.843

7.087 9.055 11.811

151.57 157.48 163.39

106.30 110.24 114.17

151.57 157.48 163.39

106.30 110.24 114.17

17.717 19.685 21.654

11.811 15.748 19.685

3.150

Revision history L6935

19/20

9 Revision history

Table 8. Document revision history

Date Revision Changes

20-May-2008 1Initial release

L6935

20/20

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