TOSHIBA Original CMOS 32-Bit Microcontroller TLCS-900/H2 Series TMP94C251A Semiconductor Company Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, "Points of Note and Restrictions". Especially, take care below cautions. **CAUTION** How to release the HALT mode Usually, interrupts can release all halts status. However, the interrupts = ( NMI , INT0), which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 3 clocks of X1) with IDLE or STOP mode (RUN is not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficultly. The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt. TMP94C251A CMOS 32-Bit Microcontroller TMP94C251AF 1. Outline and Device Characteristics TMP94C251A is high-speed advanced 32-bit microcontroller developed for controlling equipment which processes mass data. TMP94C251A is a microcontroller which has a high-performance CPU (900/H2 CPU) and various built-in I/Os. And TMP94C251A is enhanced memory interface functions. TMP94C251AF is housed in an 144-pin mini flat package. Device characteristics are as follows: (1) CPU: 32-bit CPU (900/H2 CPU) * Compatible with TLCS-900, 900/L, 900/L1, 900/H's instruction code * 16 Mbytes of linear address space * General-purpose registers and register banks * Micro DMA: 8 channels (250 ns/4 bytes at 20 MHz) (2) Minimum instruction execution time: 50 ns (at 20 MHz) (3) Internal memory * Internal RAM: 2 Kbytes (can use for code section) * Internal ROM: None (4) External memory expansion * Expandable up to 16 Mbytes (shared program/data area) * Can simultaneously support 8-/16-bit width external data bus (5) Memory controller * Chip select output: 6 channels (6) DRAM Controller: 2 channels * Direct interface (supported 8-/16-bit external data bus) 030619EBP1 * The information contained herein is subject to change without notice. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunctionor failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. * For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 94C251A-1 2005-05-10 TMP94C251A (7) 8-bit timer: 4 channels (8) 16-bit timer: 4 channels (9) Serial interface: 2 channels (10) 10-bit AD converter: 8 channels (with sample hold circuit) (11) 8-bit DA converter: 2 channels (with CMOS-AMP) (12) Watchdog timer (13) Interrupt controller * 18 internal interrupts * 10 external interrupts (14) I/O port: 64 pins (15) Package: 144-pin QFP (P-QFP144-2020-0.50) 94C251A-2 2005-05-10 TMP94C251A Figure 1.1 TMP94C251A Block Diagram 94C251A-3 2005-05-10 TMP94C251A 2. 2.1 Pin Assignment and Functions Pin Assignment (Top view) Figure 2.1.1 Pin Assignment 94C251A-4 2005-05-10 TMP94C251A 2.2 Pin Names and Functions The names of input/output pins and their functions are described below. Table 2.2.1 Pin Names and Functions (1/6) Pin Name P00 to P07 D0 to D7 Number of Pins I/O 8 I/O Port 0: I/O port (TTL) I/O Data: 0 to 7 for data bus Functions TMP94C251A is external ROM type, these pins are initialized to this function. When TMP94C251A doesn't access external memories, these pins are put in the high-impedance state. P10 to P17 8 I/O Port 1: I/O port D8 to D15 (TTL) I/O Data: 8 to15 for data bus If TMP94C251A is external ROM type and is start with 16-bit data bus, these pins are initialized to this function. When TMP94C251A doesn't access external memories, these pins are put in the high-impedance state. P40 to P47 8 A0 to A7 I/O Output Port 4: I/O port Address: 0 to 7 for address bus TMP94C251A is external ROM type, these pins are initialized to this function. When TMP94C251A doesn't access external memories, these pins don't change. P50 to P57 8 A8 to A15 I/O Output Port 5: I/O port Address: 8 to 15 for address bus TMP94C251A is external ROM type, these pins are initialized to this function. When TMP94C251A doesn't access external memories, these pins don't change. P60 to P67 8 A16 to A23 I/O Output Port 6: I/O port Address: 16 to 23 for address bus TMP94C251A is external ROM type, these pins are initialized to this function. When TMP94C251A doesn't access external memories, these pins don't change. P70 1 RD Output Port 70: Output port (output "high" when initialized) Output Read: Strobe signal for reading external memory When TMP94C251A doesn't access external memory, doesn't output strobe. TMP94C251A is external ROM type, these pins are initialized to this function. P71 1 WRL Output Port 71: Output port (output "high" when initialized) Output Write LL: Strobe signal for writing data on pins D0 to D7 When TMP94C251A doesn't access external memory, doesn't output strobe. P72 1 WRH Output Port 72: Output port (output "high" when initialized) Output Write LH: Strobe signal for writing data on pins D8 to D15 When TMP94C251A doesn't access external memory, doesn't output strobe. P73 1 Output Port 73: Output port (output "high" when initialized) P74 1 Output Port 74: Output port (output "high" when initialized) 94C251A-5 2005-05-10 TMP94C251A Table 2.2.2 Pin Names and Functions (2/6) Pin Name P75 Number of Pins 1 I/O I/O Input BUSRQ Functions Port 75: I/O port Bus request: Signal used to request high impedance for memory interface signals. If these signals are used as port, there are not change. The memory interface signals are follows: A0 to A23, D0 to D15, RD , WRLL , WRLH The output signals of memory controller. Output Port 76: Output port (output "high" when initialized) Output Bus acknowledge: Signal indicating that request of BUSRQ signal is accepted. Output Port 80: Output port (output "high" when initialized) Output Chip select 0: Outputs "low" if address is within specified address area. Output Port 81: Output port (output "high" when initialized) CS1 Output Chip select 1: Outputs "low" if address is within specified address area. RAS0 Output Row address strobe 0: Outputs RAS strobe for DRAM if address is within specified address area. Output Port 82: Output port (output "high" when initialized) Output Chip select 2: Outputs "low" if address is within specified address area. P76 1 BUSAK P80 1 CS0 P81 P82 1 1 CS2 Output Port 83: Output port (output "high" when initialized) CS3 Output Chip select 3: Outputs "low" if address is within specified address area. RAS1 Output Row address strobe 1: Outputs RAS strobe for DRAM if address is within specified address area. Output Port 84: Output port (output "high" when initialized) Output Chip select 4: Outputs "low" if address is within specified address area. Output Port 85: Output port (output "high" when initialized) Output Chip select 5: Outputs "low" if address is within specified address area. P83 P84 1 1 CS4 P85 1 CS5 P86 WAIT 1 I/O Input Port 86: I/O port Wait: Signal used to request CPU bus wait. 94C251A-6 2005-05-10 TMP94C251A Table 2.2.3 Pin Names and Functions (3/6) Pin Name PA0 Number of Pins I/O 1 Functions Output Port A0: Output port (output "high" when initialized) CAS0 Output Column address strobe 0: Outputs CAS strobe for DRAM if address is within specified address area. LCAS0 Output Lower column address strobe 0: Outputs lower CAS strobe for DRAM if address is within specified address area. Output Port A1: Output port (output "high" when initialized) Output Upper Column address strobe 0: Outputs upper CAS strobe for DRAM if address is within specified address area. Output Port A2: Output port (output "high" when initialized) PA1 1 UCAS0 PA2 1 Output Output enable 0: Outputs read enable signal for DRAM. 1 Output Port A3: Output port (output "high" when initialized) Output Output enable 1: Outputs read enable signal for DRAM. 1 Output Port A4: Output port (output "high" when initialized) Output Write enable 0: Outputs write enable signal for DRAM. OE0 PA3 OE1 PA4 WE0 PB0 Output Port B0: Output port (output "high" when initialized) CAS1 Output Column address strobe 1: Outputs CAS strobe for DRAM if address is within specified address area. LCAS1 Output Lower column address strobe 1: Outputs lower CAS strobe for DRAM if address is within specified address area. Output Port B1: Output port (output "high" when initialized) Output Upper Column address strobe 1: Outputs upper CAS strobe for DRAM if address is within specified address area. Port B2: Output port (output "high" when initialized) PB1 1 1 UCAS1 PB2 1 Output PB3 1 Output Port B3: Output port (output "high" when initialized) PB4 1 Output Port B4: Output port (output "high" when initialized) Output Write enable 1: Outputs write enable signal for DRAM. WE1 94C251A-7 2005-05-10 TMP94C251A Table 2.2.4 Pin Names and Functions (4/6) Pin Name PC0 Number of Pins 1 I/O I/O Functions Port C0: I/O port TO1 Output Timer output 1: 8-bit timer 0 or 1 output TO7 Output Timer output 7: 16-bit timer 7 output PC1 1 I/O Port C1: I/O port TO3 Output Timer output 3: 8-bit timer 2 or 3 output TOB Output Timer output B: 16-bit timer B output PD0 1 TO4 PD1 I/O Output 1 I/O Port D0: I/O port Timer output 4: 16-bit timer 4 output Port D1: I/O port TI4 Input Timer input 4: 16-bit timer 4 input INT4 Input Interrupt request pin 4: Interrupt request pin with programmable rising/falling edge PD2 1 I/O Port D2: I/O port TI5 Input Timer input 5: 16-bit timer 4 input INT5 Input Interrupt request pin 5: Interrupt request pin with rising edge PD4 1 TO6 PD5 I/O Output 1 I/O Port D4: I/O port Timer output 6: 16-bit timer 6 output Port D5: I/O port TI6 Input Timer input 6: 16-bit timer 6 input INT6 Input Interrupt request pin 6: Interrupt request pin with programmable rising/falling edge PD6 1 I/O Port D6: I/O port TI7 Input Timer input 7: 16-bit timer 6 input INT7 Input Interrupt request pin 7: Interrupt request pin with rising edge PE0 1 TO8 PE1 I/O Output 1 I/O Port E0: I/O port Timer output 8: 16-bit timer 8 output Port E1: I/O port TI8 Input Timer input 8: 16-bit timer 8 input INT8 Input Interrupt request pin 8: Interrupt request pin with programmable rising/falling edge PE2 1 I/O Port E2: I/O port TI9 Input Timer input 9: 16-bit timer 8 input INT9 Input Interrupt request pin 9: Interrupt request pin with rising edge PE4 1 TOA PE5 I/O Output 1 I/O Port E4: I/O port Timer output A: 16-bit timer A output Port E5: I/O port TIA Input Timer input A: 16-bit timer A input INTA Input Interrupt request pin A: Interrupt request pin with programmable rising/falling edge PE6 1 I/O Port E6: I/O port TIB Input Timer input B: 16-bit timer A input INTB Input Interrupt request pin B: Interrupt request pin with rising edge 94C251A-8 2005-05-10 TMP94C251A Table 2.2.5 Pin Names and Functions (5/6) Pin Name PF0 Number of Pins 1 TXD0 PF1 I/O Output 1 RXD0 PF2 I/O I/O Input 1 I/O Functions Port F0: I/O port Serial send data 0 Port F1: I/O port Serial receive data 0 Port F2: I/O port CTS0 Input SCLK0 I/O Serial clock I/O 0 I/O Port F4: I/O port PF4 1 TXD1 PF5 Output 1 RXD1 PF6 I/O Input 1 I/O Serial data receive enable 0 Serial send data 1 Port F5: I/O port Serial receive data 1 Port F6: I/O port CTS1 Input SCLK1 I/O Serial clock I/O 1 8 Input Port G: Input port Input Analog input: Input to 10-bit AD converter DAOUT0 1 Output DAOUT1 1 Output PH0 1 I/O PG0 to PG7 AN0 to AN7 TC0 PH1 Output 1 TC1 PH2 1 TC2 PH3 I/O Output 1 TC3 PH4 I/O Output I/O Output 1 INT0 I/O Input PZ0 to PZ7 8 I/O NMI 1 Input Serial data receive enable 1 DA output 0: Output from 8-bit DA converter 0 DA output 1: Output from 8-bit DA converter 1 Port H0: I/O port Terminal count 0: Outputs "high" strobe when counter value of micro-DMA channel 0 is "0". Port H1: I/O port Terminal count 1: Outputs "high" strobe when counter value of micro-DMA channel 1 is "0". Port H2: I/O port Terminal count 2: Outputs "high" strobe when counter value of micro-DMA channel 2 is "0". Port H3: I/O port Terminal count 3: Outputs "high" strobe when counter value of micro-DMA channel 3 is "0". Port H4: I/O port (schmitt input) Interrupt request pin 0: Interrupt request pin with programmable level/rising edge. (schmitt input) Port Z: I/O port Non-maskable interrupt request pin: Interrupt request pin with falling edge. Can also be operated at rising edge by program. (schmitt input) WDTOUT 1 Output Watchdog timer output pin 94C251A-9 2005-05-10 TMP94C251A Table 2.2.6 Pin Names and Functions (6/6) Pin Name AM0, 1 Number of Pins I/O 2 Input Functions Address mode: Selects external data bus width. AM1 = "low" AM0 = "low": Start with 8-bit external data bus AM1 = "low" AM0 = "high": Start with 16-bit external data bus AM1 = "high" AM0 = "low": Don't use this setting AM1 = "high" AM0 = "high": Don't use this setting TEST0, 1 2 Input Test: Input "low" when using CLK 1 Output X1/X2 2 I/O RESET 1 Input Reset: Initializes LSI (with pull-up resistor) (schmitt input) Clock output: Outputs system clock Oscillator connecting pin VREFH 1 Input Pin for reference voltage input to AD converter ("high" level) VREFL 1 Input Pin for reference voltage input to AD converter ("low" level) DAREFH 1 Input Pin for reference voltage input to DA converter ("high" level) DAREFL 1 Input ADVCC 1 - Power supply pin for 10-bit AD converter ADVSS 1 - GND pin for 10-bit AD converter (0 V) DAVCC 1 - Power supply pin for 8-bit DA converter DAVSS 1 - GND pin for 8-bit DA converter (0 V) CLVCC 1 - Power supply pin for clock doubler CLVSS 1 - GND pin for clock doubler DVCC 8 - Power supply pin (+5 V) (Connect all DVCC pins to +5V) DVSS 8 - GND pin (0 V) (Connect all DVSS pins to GND(0V).) Pin for reference voltage input to DA converter ("low" level) 94C251A-10 2005-05-10 TMP94C251A 3. Operation The following is a block-by-block description of the functions and basic operation of TMP94C251A. 3.1 CPU TMP94C251A contains an advanced, high-speed 32-bit CPU (900/H2 CPU). 3.1.1 CPU Outline 900/H2 CPU is high-speed and high-performance CPU based on 900/H CPU. 900/H2 CPU has expanded 32-bit internal data bus to process instructions more quickly. Functional differences between 900/H2 CPU and 900/H CPU are as follows: 94C251A-11 2005-05-10 TMP94C251A 3.1.2 Reset Operation When resetting the TMP94C251A microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then set the RESET input to low level at least for 10 system clocks (2 s at 10 MHz). When the reset is accepted, the CPU: * Set the program counter (PC) to the reset vector stored at addresses FFFF00H to FFFF02H. PC (7:0) PC (15:8) PC (23:16) Value at address FFFF00H Value at address FFFF01H Value at address FFFF02H * Sets the stack pointer (XSP) to 00000000H * Sets bits IFF2 to IFF0 of the status register (SR) to 111 (This sets the interrupt level mask register to level 7). * Clears bits RFP1 to RFP0 of the status register (SR) to 00 (This sets the register banks to 0). After reset is released, the CPU begins execution from the instruction at the location specified in the PC. Other than the changes described above, reset does not alter any internal CPU registers. When reset is accepted, processing of the internal I/O, port, and other pins are as follows: * Initializes the internal I/O registers as table of "Special Function Register" in section 5. * Set ports pins to general-purpose input port mode. * Sets the WDTOUT pin to "Low". (However, when reset is released, sets to "High".) When external reset is released, built-in clock doubler begins operation and after the stable time (1.6384 ms at 20 MHz) elapse of the circuit, internal reset is released. The operation of memory controller and DRAM controller cannot be insured until power supply becomes stable after power-on reset. The external RAM data provided before turning on the TMP94C251A may be spoiled because the control signals are unstable until power supply becomes stable after power on reset. 94C251A-12 2005-05-10 TMP94C251A 3.1.3 Data Bus Size after Reset Release The start data bus size is determined depending on the state of a AM1/AM0 pins just after reset release. Then the external memory is accessed as follows. For the details, refer to chapter 3.6 "Memory Controller". 3.1.4 Setting of TEST0, TEST1 Connect TEST0, TEST1 pin to "GND" to use. 94C251A-13 2005-05-10 TMP94C251A 3.2 Memory Map Figure 3.2.1 is a memory map of the TMP94C251A. Note 1: Emulator control area is for emulator, it is mapped F00000H to F10000H address. Don't use this area. This area is reserved. On emulator WR signal and RD signal are asserted, when this area is accessed. Be careful to use external memory. Note 2: Don't use the last 16-byte area (FFFFF0H to FFFFFFH). This area is reserved. Figure 3.2.1 Memory Map 94C251A-14 2005-05-10 TMP94C251A 3.3 Interrupts TLCS-900/H2 interrupts are controlled by the CPU interrupt mask flip-flops <IFF2:0> and the internal interrupt controller. Interrupts can come from a total of 38 sources: * Interrupts from CPU itself: 2 (Software interrupt and illegal instructions) * Interrupts from external pins ( NMI , INT0, INT4 to INTB): 10 * Interrupts from internal I/O: 18 * Interrupts from micro DMA: 8 Individual interrupt vector numbers (Fixed) are allocated to each interrupt source. Six levels of priority (Variable) can be allocated to maskable interrupts. The priority of non-maskable interrupts is fixed at "7" (The highest priority). When an interrupt is generated, the interrupt controller sends the priority value of that interrupt to the CPU. If more than one interrupt is generated simultaneously, the interrupt with the highest priority (7 non-maskable interrupts is the highest) is sent to the CPU. The CPU compares the priority value with the value of the CPU interrupt mask register <IFF2:0>, and accepts the interrupt if the priority is higher or equal to the value in the CPU interrupt mask register. The value of the interrupt mask register <IFF2:0> can be modified using the EI instruction (EI num sets <IFF2:0> to num). For example, executing "EI3" enables acceptance of non-maskable interrupts and maskable interrupts with a priority of 3 or higher set in the interrupt controller. The DI instruction (Sets <IFF2:0> to "7") is operationally the same as specifying "EI7". As maskable interrupts have priorities in the range of 0 to 6, the DI instruction disables acceptance of maskable interrupts. The EI instruction is valid immediately after its execution. In addition to the general-purpose interrupt processing mode described above, there is also a micro DMA processing mode. The micro DMA is a mode used by the CPU to automatically transfer 1/2/4 byte. It enables the CPU to transfer to the internal or external memories and the built-in I/O at high speed. Furthermore, TMP94C251A has a software start function to request by software except that micro DMA is requested by interrupt sources. Figure 3.3.1 is a flowchart showing overall interrupt processing. 94C251A-15 2005-05-10 TMP94C251A Micro DMA Software Start Request Figure 3.3.1 Interrupt Processing Flowchart 94C251A-16 2005-05-10 TMP94C251A 3.3.1 General-purpose Interrupt Processing When accepting an interrupt the CPU operates as follows, which is the same as it is in TLCS-900/L and TLCS-900/H. (1) The CPU reads the interrupt vector from the interrupt controller. When more than one interrupt with the same level is generated simultaneously, the interrupt vectors in accordance with the default priority (which is fixed as follows: the smaller the vector value, the higher the priority), then clears the interrupt request. (2) The CPU pushes the program counter (PC) and the status register (SR) to the system stack area (Area indicated by the XSP). (3) The CPU sets a value in the CPU interrupt mask register <IFF2:0> that is higher by 1 than the value of the accepted interrupt level. However, if the value is 7, 7 is set without an increment. (4) The CPU sets the interrupt nesting counter (INTNEST) to +1. (5) The CPU jumps to address FFFF00H + interrupt vector, then starts the interrupt processing routine. All the above processing is completed in 10 states (Internal operation with 500 ns at 20 MHz) in the most approximate processing (The external memory is 32-bit data bus 0 wait, the stack area is the built-in RAM and the stack pointer value is an integer multiple of 4). To return to the main routine after completion of the interrupt processing, the RETI instruction is usually used. Executing this instruction restores the contents of the program counter and the status registers, and decrements the interrupt nesting counter (INTNEST). Though acceptance of non-maskable interrupts cannot be disabled by program, acceptance of maskable interrupts can. A priority can be set for each source of maskable interrupts. The CPU accepts an interrupt request with a priority higher than the value in the CPU mask register <IFF2:0>. The CPU mask register <IFF2:0> is set to a value higher by 1 than the priority of the accepted interrupt. Thus, if an interrupt with a level higher than the interrupt being processed is generated, the CPU accepts the interrupt with the higher level, causing interrupt processing to nest. If an interrupt generated while the CPU is performing processes (1) to (5) for an earlier interrupt, the new interrupt is sampled immediately after the start instruction of the interrupt processing routine is executed. Setting DI as the start instruction disables maskable interrupt nesting. Resetting initializes the CPU mask register <IFF2:0> to 7; therefore, maskable interrupts are disabled. The addresses FFFF00H to FFFFFFH (256 bytes) of TMP94C251A are assigned for interrupt vector area. The interrupt vector area is depended on the derivative products. 94C251A-17 2005-05-10 TMP94C251A Table 3.3.1 TMP94C251A Interrupt Table 94C251A-18 2005-05-10 TMP94C251A 3.3.2 Micro DMA TMP94C251A supports the micro DMA function. For interrupt requests set for micro DMA, micro DMA processing is performed at the highest priority for maskable interrupts, regardless of the set interrupt level. Since the micro DMA has eight channels, it can transfer continuously by the burst specification which is described later. (1) Micro DMA operation When an interrupt request occurs for an interrupt specified by the micro DMA start vector register, micro DMA sends data to the CPU with the highest priority for maskable interrupts, regardless of the interrupt level set for the interrupt. If IFF = 7, micro DMA request is not accept. The micro DMA function has eight channels. This allows micro DMA to be set for up to eight interrupts at the same time. When micro DMA is accepted, the interrupt request F/F for the micro DMA channel is cleared, data are transferred (1/2/4 byte) once from the transfer source address to the transfer destination address (The addresses are set in the control register), and the transfer counter is decremented. If the decremented result is 0, the CPU informs a micro DMA transfer end to the interrupt controller. The interrupt controller generates a micro DMA transfer end interrupt (INTTCn). The CPU clears the micro DMA start vector register (DMAnV) 0, disables the next micro DMA startup, and terminates the micro DMA processing. If the decremented result is other than zero, micro DMA processing is terminated without the burst specification which is described later. In this case, the transfer end interrupt (INTTCN) is not generated. When the interrupt source is used only to start micro DMA, the interrupt level must be set to "0". When the interrupt request generates until the interrupt sources are set to the micro DMA start vector, the CPU performs the general-purpose interrupt processing at the interrupt level of 1 to 6. When simultaneously using the same interrupt resource for both the micro DMA and general-purpose interrupts as described above, set the level of the interrupt source used to start micro DMA lower than the levels of all other interrupt sources. Like other maskable interrupts, the priority of the micro DMA transfer end interrupt is determined by the interrupt level and default priority. If multiple-channel micro DMA requests occur at the same time, the priority is determined by the channel numbers, not the interrupt levels. The lower the channel number, the higher the priority. (CH0 (High) to CH2 (Low)) The transfer source and transfer destination addresses are set in 32-bit control registers. However, as only 24-bit addresses are output, the address space available to micro DMA is 16 Mbytes. 94C251A-19 2005-05-10 TMP94C251A Three transfer modes are supported: 1-byte transfer, 2-byte transfer and 4-byte transfer. For each transfer mode, it is possible to specify whether to increment, decrement, or fix source and destination addresses after transfer. These modes facilitate data transfer from I/O to memory, from memory to I/O, and from I/O to I/O. For transfer mode details, see "Transfer Mode Register Details" later in this manual. As a 16-bit transfer counter is used, micro DMA can perform a maximum of 65536 transfers (Initializing the counter to 0000H specifies the maximum number of transfers) and the software start (Total 35 interrupt sources) can be used to start micro DMA processing. Figure 3.3.2 shows the micro DMA cycle for transfer destination address INC mode (the same apart from counter mode). (Condition: 0-wait built-in RAM in the transfer address area) Figure 3.3.2 Micro DMA Cycle Timing States 1, 2: Instruction fetch cycle (Prefetches the next instruction code) State 3: Micro DMA read cycle State 4: Micro DMA write cycle State 5: (The same as in state 1, 2) 94C251A-20 2005-05-10 TMP94C251A (2) Software start function In addition to starting the micro DMA function by interrupts, TMP94C251A includes a micro DMA software start function that starts micro DMA on the generation of the write cycle to the DMAR register. Writing "1" to each bit of DMAR register causes micro DMA once. At the end of transfer, the bits of the DMAR register which support the end channel are automatically cleared to "0". Writing again to the DMAB register triggers another software start, provided the micro DMA trance counter is set to other than "0". When the burst is specified by DMAB register, data is continuously transferred until the value in the micro DMA transfer counter is "0" after startup of the micro DMA. (3) Transfer control register The transfer source address and the transfer destination address are set by the following registers. These registers set data using "LDC cr,r" instruction. 94C251A-21 2005-05-10 TMP94C251A (4) DMA mode register details Note: The execution time is measured at 1 state = 50 ns (operation at internal 20 MHz). 94C251A-22 2005-05-10 TMP94C251A 3.3.3 Interrupt Controller Operation Figure 3.3.3 is a block diagram of the interrupt circuit. The left-hand side of the diagram shows the interrupt controller circuit. The right-hand side shows the CPU interrupt request signal circuit and the halt release circuit. For each interrupt channel (36 channels in total), an interrupt request flag (Flip-flop), an interrupt priority setting register, and a micro DMA start vector register. The interrupt request flag latches interrupt request from the peripherals. The flag is cleared to zero in the following cases: When reset occurs, when the CPU reads the channel vector of an interrupt it has received, when the CPU receives a micro DMA request (when micro DMA is set), when the micro DMA burst transfer is terminated, and when an instruction that clears the interrupt for that channel is executed (by writing "0" to the clear bit in the interrupt priority setting register). The interrupt priority can be set independently for each interrupt source by writing the priority to the interrupt priority setting register (e.g., INTE0AD, INTE12). Six interrupt priorities from 1 to 6 are provided. Setting "0" (or "7") disables the interrupt request. The priority of non-maskable interrupts (NMI pin, watchdog timer) is fixed at 7. If interrupt requests with the same level are generated at the same time, the default priority (The interrupt with the lowest priority or, in other words, the interrupt with the lowest vector value) is used to determine which interrupt request to accept first. Reading the 3rd bit and the 7th bit in the interrupt priority setting register sees the state of the interrupt request flag and whether there are the interrupt request of each channel. The interrupt controller sends the interrupt request with the highest priority among the simultaneous interrupts and its vector address to the CPU. The CPU compares the priority value <IFF2:0> set in the status register by the interrupt request signal with the priority value set; if the latter is higher, the interrupt is accepted. Then the CPU sets a value higher than the priority value by 1 in the CPU SR <IFF2:0>. Interrupt request where the priority value equals or is higher than the set value are accepted simultaneously during the previous interrupt routine. When interrupt processing is completed (after execution of the RETI instruction), the CPU restores the priority value saved in the stack before the interrupt was generated to the CPU SR<IFF2:0>. The interrupt controller also has eight registers used to store the micro DMA start vector. Writing the start vector of the interrupt source for the micro DMA processing (See Table 3.3.1), enables the corresponding interrupt to be processed by micro DMA processing. The values must be set in the micro DMA parameter register (e.g., DMAS and DMAD) prior to the micro DMA processing. 94C251A-23 2005-05-10 TMP94C251A Figure 3.3.3 Block Diagram of Interrupt Controller 94C251A-24 2005-05-10 TMP94C251A (1) Interrupt priority setting register 94C251A-25 2005-05-10 TMP94C251A 94C251A-26 2005-05-10 TMP94C251A (2) External interrupt control Note 1: Disable INT0 request before changing INT0 pin mode from level-sense to edge-sense. Setting example: DI LD (IIMC), xxxxxx0xB ; Switches from level to edge. LD (INTCLR), 0AH ; Clears interrupt request flag. EI Note 2: See electrical characteristics in section 4 for external interrupt input pulse width. 94C251A-27 2005-05-10 TMP94C251A Setting of External Interrupt Pin Function (3) Interrupt request flag clear register The interrupt request flag is cleared by writing the micro DMA start vector, which is listed in Table 3.3.1, to the INTCLR register. For example, to clear the INT0 interrupt flag, operate the following register after execution of DI instruction. Clears INT0 interrupt request flag INTCLR0AH (4) Micro DMA start vector register This register assigns micro DMA processing to an interrupt source. The interrupt source with a micro DMA start vector that matches the vector set in this register is assigned as the micro DMA start source. 94C251A-28 2005-05-10 TMP94C251A When the micro DMA transfer counter value reaches 0, the micro DMA transfer end interrupt corresponding to the channel is set to the interrupt controller, the micro DMA start vector register is cleared, and the micro DMA start source of the channel is cleared. Therefore, to continue micro DMA processing, set the micro DMA start vector register again during the processing of the micro DMA transfer end interrupt. If the same vector is set in the micro DMA start vector registers of more than one channel, the channel with the lowest number has a higher priority. Accordingly, if the same vector is set in the micro DMA start vector registers of two channels, the interrupt generated in the channel with the lower number is executed until the micro DMA transfer is complete. If the micro DMA start vector of this channel is not set again, the next micro DMA is started for the channel with the higher number (Micro DMA chaining). Symbol Name Address Start Vector 100h Start Vector 101h Start Vector 102h Start Vector Start Vector 103h Start Vector 104h Start Vector 105h Start Vector 0 DMA0V5 DMA0V4 DMA0V3 DMA0V2 DMA0V1 DMA0V0 R/W 0 0 0 0 0 0 - - - - DMA1V5 DMA1V4 DMA1V3 DMA1V2 DMA1V1 DMA1V0 R/W 0 0 0 0 0 0 - - DMA2V5 DMA2V4 DMA2V3 DMA2V2 DMA2V1 DMA2V0 R/W - 0 0 0 0 0 0 - - - - - - - - DMA3V5 DMA3V4 DMA3V3 DMA3V2 DMA3V1 DMA3V0 R/W 0 0 0 0 0 0 DMA4V5 DMA4V4 DMA4V3 DMA4V2 DMA4V1 DMA4V0 R/W 0 0 0 0 0 0 - - - - DMA5V5 DMA5V4 DMA5V3 DMA5V2 DMA5V1 DMA5V0 R/W 0 0 0 0 0 0 DMA6 Start Vector 106h - - DMA6V5 DMA6V4 DMA6V3 DMA6V2 DMA6V1 DMA6V0 R/W - - 0 0 0 0 0 0 DMA7 Start Vector DMA7 DMA7V 1 DMA5 Start Vector DMA6 DMA6V 2 DMA4 Start Vector DMA5 DMA5V - 3 DMA3 Start Vector DMA4 DMA4V - - DMA3 DMA3V - 4 DMA2 Start Vector DMA2 DMA2V - 5 DMA1 Start Vector DMA1 DMA1V 6 DMA0 Start Vector DMA0 DMA0V 7 107h - - - - DMA7V5 DMA7V4 DMA7V3 DMA7V2 DMA7V1 DMA7V0 R/W 94C251A-29 0 0 0 0 0 0 2005-05-10 TMP94C251A (5) Micro DMA burst specification Specifying the micro DMA burst continues the micro DMA transfer until the transfer counter register reaches 0 after micro DMA start. Setting a bit which corresponds to the micro DMA channel of the DMAB registers mentioned below to "1" specifies a burst. 94C251A-30 2005-05-10 TMP94C251A (6) Notes The instruction execution unit and the bus interface unit of this CPU operate independently. Therefore, immediately before an interrupt is generated, if the CPU fetches an instruction that clears the corresponding interrupt request flag, the CPU may execute the instruction that clears the interrupt request flag between accepting and reading the interrupt vector. In this case, the CPU reads the default vector 0004H and reads the interrupt vector at address FFFF04H. To avoid the above problem, place instructions that clear interrupt request flags after a DI instruction. And in the case of setting an interrupt enable again by EI instruction after the execution of clearing instruction, execute EI instruction after clearing and more than 3-instructions (e.g., "NOP" * 3times). If placed EI instruction without waiting NOP instruction after execution of clearing instruction, interrupt will be enable before request flag is cleared. In the case of changing the value of the interrupt mask register <IFF2:0> by execution of POP SR instruction, disable an interrupt by DI instruction before execution of POP SR instruction. In addition, take care as the following 2 circuits are exceptional and demand special attention. INT0 level mode INT0 in level mode is not an edge-detect interrupt, so the interrupt request flip-flop function is canceled. The peripheral interrupt request bypasses the S input of the flip-flop, and acts as the Q output. Changing modes from edge to level automatically clears the interrupt request flag. If the CPU enters the interrupt response sequence as a result of setting INT0 from 0 to 1, INT0 must be held at 1 until the interrupt response sequence is completed. If the INT0 level mode is used to release a halt, INT0 must be held at 1 from the time INT0 changes from 0 to 1, to the time when the halt is released. (Ensure that INT0 does not go back 0 due to noise before the halt is released.) When switching modes from level to edge, any interrupt request flag set in level mode is not cleared. Accordingly, clear the interrupt request flag using the following sequence. DI LD (IIMC), 00H; Switches from level to edge. LD (INTCLR), 0AH; Clears interrupt request flag. NOP; Wait EI execution NOP NOP EI INTRX The interrupt request flip-flop can only be cleared by reset or by reading the serial channel receive buffer, not by an instruction. Note: The following instructions or pin changes are equivalent to instructions that clear the interrupt request flag. INT0: Instructions that switch to level mode after an interrupt request is generated in edge mode. The pin input changes from high to low after an interrupt request is generated in level mode. ("H" "L") INTRX: Instructions that read the receive buffer. 94C251A-31 2005-05-10 TMP94C251A 3.4 Standby Function [1] HALT mode Executing the HALT instruction sets either RUN, IDLE, or STOP mode depending on the content of WDMOD<HALTM1:0>. (1) RUN: Halts the CPU only. Power dissipation remains almost unchanged. (2) IDLE: Operates only the internal oscillator, while halts all other circuits. (3) STOP: Halts all internal circuits, including the internal oscillator. [2] Release from HALT mode Release from HALT mode can trigger an interrupt request or a reset. A combination of the interrupt mask register <IFF2:0> state and the HALT mode determine the useable halt release source. (For details, see Table 3.4.2.) * Release by interrupt request The operation to release HALT mode by using an interrupt request differs according to the interrupt enable state. If the interrupt request level set prior to the execution of the HALT instruction is higher than the interrupt mask register value, after HALT mode is released, interrupt processing is performed by this source, and processing starts from the next instruction following the HALT instruction. If the interrupt request level is lower than the interrupt mask register value, HALT mode is not released. (At a non-maskable interrupt, interrupt processing is performed after HALT mode release irrespective of the mask register value.) However, in the case of the INT0 interrupt only, HALT mode can be released if the interrupt request level is lower than the interrupt mask register value. In this case the interrupt processing is not performed. Processing always starts from the next instruction following the HALT instruction. (The INT0 interrupt request flag is held at 1.) Note: Usually, interrupts can release all halts status. However, the interrupts = ( NMI and INT0) which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 3 clocks of X1) with IDLE or STOP mode (RUN is not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficultly. The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt. * Release by reset All HALT modes can be released by a reset. However, when releasing STOP mode, allow sufficient reset time (at least 2 s) for the oscillator to stabilize. When releasing HALT mode by a reset, the internal RAM retains the data prevailing immediately prior to entering the HALT mode. However, other settings are initialized. On execution of the HALT instruction, the device enters standby state in RUN mode. Release halt using INT0. 94C251A-32 2005-05-10 TMP94C251A (1) RUN mode Figure 3.4.1 is the timing chart for releasing a halt in RUN mode using an interrupt. In RUN mode, the MCU internal system clock does not stop after the HALT instruction is executed. Only CPU instruction execution stops. Therefore, the CPU performs repeated dummy cycles until the halt state is released. In the halt state, interrupt requests are sample on the cycle of the CLK signal. Figure 3.4.1 Timing Chart for Releasing Halt in RUN Mode Using Interrupt 94C251A-33 2005-05-10 TMP94C251A (2) IDLE mode Figure 3.4.2 is the timing chart for releasing a halt in IDLE mode using an interrupt. In IDLE mode, the MCU internal system clock stops. functions. Only the internal oscillator In the halt state, interrupt requests are sampled synchronously to the system clock. The release from the halt state (Operation restart), however, is synchronized with the clock. In IDLE mode, interrupt requests other than external interrupts (NMI, INT0) are disabled. Figure 3.4.2 Timing Chart for Releasing Halt in IDLE Mode Using Interrupt 94C251A-34 2005-05-10 TMP94C251A (3) STOP mode Figure 3.4.3 is the timing chart for releasing a halt in STOP mode using an interrupt. In STOP mode, all internal circuits stop, including the internal oscillator. Also, in STOP mode, all pins, apart from a few exceptions, are set to high impedance and are disconnected from the internal circuit of the MCU. However, setting WDMOD<DRVE> in the internal I/O register to "1" specifies that pins maintain the states prior to the halt. Reset clears the register to "0". When the CPU receives an interrupt request, the internal oscillation restarts. Then, after the time set by the warm-up counter for the internal oscillation to stabilize, the system clock starts its output. The CLKMOD<WARM> bit sets the warm-up time. Setting this bit to 0 specifies a warm-up time of 215 clock cycles; setting the bit to 1 specifies a warm-up time of 217 clock cycles. Reset clears CLKMOD<WARM> to "0". STOP mode can only be released by an NMI pin or INT0 pin interrupt, or by reset. When STOP mode is released by other than reset, the system clock starts its output after the time set by the warm-up counter for the internal oscillation to stabilize. When using reset to release stop mode, input reset signals long enough for stable oscillation. In systems with an external oscillator, the warm-up counter also operates when STOP mode is released. Therefore, such systems also require a warm-up time between input of release signal and system clock output. Figure 3.4.3 Timing Chart for Releasing Halt in STOP Mode Using Interrupt 94C251A-35 2005-05-10 TMP94C251A Table 3.4.1 Pin states in STOP mode 94C251A-36 2005-05-10 TMP94C251A Table 3.4.2 I/O Operation During Halt and Release Interrupt Mask and Request Level Settings HALT Mode HALT Release Source x *1 *2 : : : : : Interrupt Interrupt Request Level Interrupt Mask <IFF2:0> Interrupt Request Level *2 < Interrupt Mask <IFF2:0> RUN RUN IDLE STOP - - - - - - * IDLE NMI INTWD x STOP *1 x *1 1 INT0 INT4 to 9, A, B x x x x x INTT0 to 3 x x x x x INTTR4 to 9, A, B x x x x x INTRXD0, 1 x x x x x INTTXD0, 1 x x x x x INTAD x x x x x RESET After a halt is released, interrupt processing begins. (Reset initializes the LSI.) After a halt is released, processing begins from the next address following the HALT instruction. Cannot be used to release a halt. Halt is released after the warm-up time has elapsed. Same as a DI instruction. 94C251A-37 2005-05-10 TMP94C251A 3.5 Functions of Ports TMP94C251A has I/O port pins which are shown in Table 3.5.1. In addition to functioning as general-purpose I/O ports, these pins are also used by internal CPU and I/O functions. Table 3.5.1 Port Functions (1/2) 94C251A-38 2005-05-10 TMP94C251A Table 3.5.2 Port Functions (2/2) Port Name Port E Port F Pin Name Number of Pins I/O I/O Setting Pin Name for built-in function PE0 1 I/O Bit TO8 PE1 1 I/O Bit TI8/INT8 PE2 1 I/O Bit TI9/INT9 PE4 1 I/O Bit TOA PE5 1 I/O Bit TIA/INTA PE6 1 I/O Bit TIB/INTB PF0 1 I/O Bit TXD0 PF1 1 I/O Bit RXD0 PF2 1 I/O Bit CTS0 /SCLK0 PF4 1 I/O Bit TXD1 PF5 1 I/O Bit RXD1 PF6 1 I/O Bit CTS1 /SCLK1 Port G PG0 to PG7 8 Input (Fixed) Port H PH0 1 I/O Bit TC0 PH1 1 I/O Bit TC1 PH2 1 I/O Bit TC2 PH3 1 I/O Bit TC3 PH4 1 I/O Bit INT0 PZ0 to PZ7 8 I/O (Fixed) - Port Z 94C251A-39 AN0 to AN7 2005-05-10 TMP94C251A 3.5.1 Port 0 (P00 to P07/D0 to D7) Port 0 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P0CR and function register P0FC. In addition to functioning as a general-purpose I/O port, port 0 can also function as data bus (D0 to D7). Setting the AM1 and AM0 pins as shown below and resetting the device initialize port 0 to the following function pins: Figure 3.5.1 Port 0 Table 3.5.3 Port 0 Registers Note)Read-modify-write is prohibited for P0CR and P0FC. 94C251A-40 2005-05-10 TMP94C251A 3.5.2 Port 1 (P10 to P17/D8 to D15) Port 1 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P1CR and function register P1FC. In addition to functioning as a general-purpose I/O port, port 1 can also function as data bus (D8 to D15). Setting the AM1 and AM0 pins as shown below and resetting the device initialize port 1 to the following function pins: Figure 3.5.2 Port 1 Table 3.5.4 Port 1 Registers Note)Read-modify-write is prohibited for P1CR and P1FC. 94C251A-41 2005-05-10 TMP94C251A 3.5.3 Port 4 (P40 to P47/A0 to A7) Port 4 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P4CR and function register P4FC. In addition to functioning as a general-purpose I/O port, port 4 can also function as data bus (A0 to A7). When accessing internal memory and internal I/O, these pins retain the addresses of the previous bus cycle. Setting the AM1 and AM0 pins as shown below and resetting the device initialize port 4 to the following function pins: Figure 3.5.3 Port 4 Table 3.5.5 Port 4 Registers Note)Read-modify-write is prohibited for P4CR and P4FC. 94C251A-42 2005-05-10 TMP94C251A 3.5.4 Port 5 (P50 to P57/A8 to A15) Port 5 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P5CR and function register P5FC. In addition to functioning as a general-purpose I/O port, port 5 can also function as data bus (A8 to A15). When accessing internal memory and internal I/O, these pins retain the addresses of the previous bus cycle. Setting the AM1 and AM0 pins as shown below and resetting the device initialize port 5 to the following function pins: Figure 3.5.4 Port 5 Table 3.5.6 Port 5 Registers Note)Read-modify-write is prohibited for P5CR and P5FC. 94C251A-43 2005-05-10 TMP94C251A 3.5.5 Port 6 (P60 to P67/A16 to A23) Port 6 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P6CR and function register P6FC. In addition to functioning as a general-purpose I/O port, port 6 can also function as data bus (A16 to A23). When accessing internal memory and internal I/O, these pins retain the addresses of the previous bus cycle. Setting the AM1 and AM0 pins as shown below and resetting the device initialize port 6 to the following function pins: Figure 3.5.5 Port 6 Table 3.5.7 Port 6 Registers Note)Read-modify-write is prohibited for P6CR and P6FC. 94C251A-44 2005-05-10 TMP94C251A 3.5.6 Port 7 (P70 to P76) Port 7 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P7CR and function register P7FC. In addition to functioning as a general-purpose I/O port, port 7 can also function as read/write strobe signals to connect with an external memory and control signals to release bus. A reset initializes P71 to P74 and P76 pins to output port mode, and P75 pin to input port mode. Setting the AM0 and AM1 pins as shown below and resetting the device initialize port 70 to the following function pins: AM1 AM0 Function Setting after reset is released 0 0 RD 0 1 RD 1 0 Don't use this setting 1 1 Don't use this setting Figure 3.5.6 Port 7 (P70 to P74) 94C251A-45 2005-05-10 TMP94C251A Figure 3.5.7 Port 7 (P75, P76) Table 3.5.8 Port 7 Registers Note)Read-modify-write is prohibited for P7CR and P7FC. 94C251A-46 2005-05-10 TMP94C251A 3.5.7 Port 8 (P80 to P86) Port 8 is a 7-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P8CR and function register P8FC. In addition to functioning as a general-purpose I/O port, port 8 can also function as chip selection to connect with an external memory and wait input. A reset initializes P80 to P85 pins to output port mode, and P86 pin to input port mode. Figure 3.5.8 Port 8 94C251A-47 2005-05-10 TMP94C251A Table 3.5.9 Port 8 Registers Note)Read-modify-write is prohibited for P8CR and P8FC. 94C251A-48 2005-05-10 TMP94C251A 3.5.8 Port A (PA0 to PA4) Port A is a 5-bit general-purpose I/O port. In addition to functioning as a general-purpose I/O port, port A can also function as external DRAM (Channel 0) connection. A reset initializes port A to output port mode. Figure 3.5.9 Port A Table 3.5.10 Port A Registers Note)Read-modify-write is prohibited for PAFC. 94C251A-49 2005-05-10 TMP94C251A 3.5.9 Port B (PB0 to PB4) Port B is a 5-bit general-purpose I/O port. In addition to functioning as a general-purpose I/O port, port A can also function as external DRAM (Channel 1) connection. A reset initializes port A to output port mode. Figure 3.5.10 Port B Table 3.5.11 Port B Registers Note)Read-modify-write is prohibited for PBFC. 94C251A-50 2005-05-10 TMP94C251A 3.5.10 Port C (PC0 to PC4) Port C is a 2-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register PCCR and function register PCFC. In addition to functioning as a general-purpose I/O port, port C can also function as 8-bit timer or 16-bit timer output. A reset initializes port C to output port mode. PCCR register PCFC register PC register TO1/TO3 TO7/TOB 0 S 0 S 1 1 PC0 (TO1/TO7) PC1 (TO3/TOB) Selector Selector S Port read data 1 0 Selector Figure 3.5.11 Port C Table 3.5.12 Port C Registers Note)Read-modify-write is prohibited for PCCR and PCFC. 94C251A-51 2005-05-10 TMP94C251A 3.5.11 Port D (PD0 to PD6) Port D is a 6-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register PDCR and function register PDFC. In addition to functioning as a general-purpose I/O port, port D can also function as 16-bit timer I/O and interrupt input. A reset initializes port D to output port mode. PDCR register PDFC register PD register 0 Timer output S 1 Selector S Port read data PD0 (TO4) PD1 (TI4/INT4) PD2 (TI5/INT5) PD4 (TO6) PD5 (TI6/INT6) PD6 (TI7/INT7) 1 0 Selector Timer interrupt request Figure 3.5.12 Port D Table 3.5.13 Port D Registers Note)Read-modify-write is prohibited for PDCR and PDFC. 94C251A-52 2005-05-10 TMP94C251A 3.5.12 Port E (PE0 to PE6) Port E is a 6-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register PECR and function register PEFC. In addition to functioning as a general-purpose I/O port, port E can also function as 8-bit timer or 16-bit timer output and interrupt input. A reset initializes port E to input port mode. PECR register PEFC register PE register 0 Timer output S 1 Selector S Port read data 1 PE0 (TO8) PE1 (TI8/INT8) PE2 (TI9/INT9) PE4 (TOA) PE5 (TIA/INTA) PE6 (TIB/INTB) 0 Selector Timer interrupt request Figure 3.5.13 Port E Table 3.5.14 Port E Registers Note)Read-modify-write is prohibited for PECR and PEFC. 94C251A-53 2005-05-10 TMP94C251A 3.5.13 Port F (PF0 to PF6) Port F is a 6-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register PFCR and function register PFFC. In addition to functioning as a general-purpose I/O port, port F can also function as I/O functions of serial interface. A reset initializes port F to input port mode. PFCR register PFFC register PF register 0 SCLK output S 1 TXD output Selector S Port read data RXD input 1 PF0 (TXD0) PF1 (RXD0) PF2 (SCLK0/ CTS0 ) PF4 (TXD1) PF5 (RXD1) PF6 (SCLK1/ CTS1 ) 0 Selector SCLK input CTS input Figure 3.5.14 Port F Table 3.5.15 Port F Registers Note)Read-modify-write is prohibited for PFCR and PFFC. 94C251A-54 2005-05-10 TMP94C251A 3.5.14 Port G (PG0 to PG7) Port G is an 8-bit general-purpose input-only port. In addition to functioning as a general-purpose I/O port, port G can also function as I/O functions of AD converter. Figure 3.5.15 Port G Table 3.5.16 Port G Register 94C251A-55 2005-05-10 TMP94C251A 3.5.15 Port H (PH0 to PH4) Port H is a 5-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register PHCR and function register PHFC. In addition to functioning as a general-purpose I/O port, port H can also function as terminal count output function of micro DMA and interrupt input function. A reset initializes port H to input port mode. PHCR register PHFC register PH register PH4 (INT0) S Port read data 1 0 Selector Selector 1 INT0 interrupt request S 0 Rising edge detector INT0 level/edge mode select signal Figure 3.5.16 Port H 94C251A-56 2005-05-10 TMP94C251A Table 3.5.17 Port H Registers Note)Read-modify-write is prohibited for PHCR and PHFC. 3.5.16 Port Z (PZ0 to PZ7) Port Z is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register PZCR. A reset initializes port Z to input port mode. Figure 3.5.17 Port Z Table 3.5.18 Port Z Registers Note)Read-modify-write is prohibited for PZCR. 94C251A-57 2005-05-10 TMP94C251A 3.6 Memory Controller 3.6.1 Functions TMP94C251A has a memory controller with a variable 6-block address area that controls as follows. (1) 6-block address area support Specifies a start address and a block size respectively for 6-block address area (block 0 to 5). (2) Connecting memory specification Specifies SRAM, ROM and DRAM as memories to connect with the respective block address areas. DRAM is specified only in block 1 and block 3. When SRAM or ROM is specified, a usual bus cycle is executed. When DRAM is specified, DRAM is effectively accessed with built-in DRAM controller. The page access of ROM is also supported in block 2. For details, see 3.6.4 "ROM Control (Page mode)". (3) Data bus size selection Whether 8 bits, 16 bits is selected as the data bus size of the respective block address areas. (4) Wait control Wait specification bit in the control register and WAIT input pin control the number of waits in the external bus cycle. Read cycle and write cycle can specify the number of waits individually. The number of waits is controlled in three mode mentioned below. 0 waits, 1 wait, 2 waits, 3 waits, N waits (controls with WAIT pin) (5) DRAM control TMP94C251A has DRAM controller to control refresh and DRAM accessing. This document describes in order of the operation after reset release, basic functions and ROM page mode. Each section explains the operation and the register setting method and the signal timing. The register setting method is mentioned as the lists of registers in the final. 94C251A-58 2005-05-10 TMP94C251A 3.6.2 Control Register and Operation after Reset Release This section describes the registers to control the memory controller, the state after reset release and necessary settings. (1) Control register The control registers of the memory controller are as follows. * Control register: BnCSH/BnCSL (n = 0 to 5) Sets the basic functions of the memory controller, that is the connecting memory type, the data bus size, the number of waits to be read and written. * Memory start address register: MSARn (n = 0 to 5) Sets a start address in the respective block address areas. * Memory address mask register: MAMRn (n = 0 to 5) Sets a block size in the respective block address areas. In addition to setting of the above-mentioned registers, it is necessary to set the following registers to control ROM page mode access and DRAM. * Page ROM control register: PMEMCR Sets to executed ROM page mode accessing. * DRAM control register: DRAMnCRL/DRAMnCRH (n = 0 to 1) Sets DRAM access. * DRAM refresh control register: DRAMnREF (n = 0 to 1) Sets DRAM refresh operation. 94C251A-59 2005-05-10 TMP94C251A (2) Operation After Reset Release The start data bus size is determined depending on the state of AM1/AM0 pins just after reset release. Then, the external memory is accessed as follows. AM1/AM0 pins are valid only just after reset release. In the other cases, the data bus width is set to the value set to BnBUS bit of the control register. After reset, only control register (B2CSH/B2CSL) of the block address area 2 is automatically valid. The data bus width which is specified by AM1/AM0 pins is loaded to the bit to specify the bus width of the control register in the block address area 2. The block address area 2 is set to addresses 000000H to FFFFFFH after reset. After reset release, the block address areas are specified by the memory start address register (MSARn) and the memory address mask register (MAMRn). Then the control register (BnCS) is set. Set the enable bit (BnE) of the control register to "1" to enable the setting. Set relevant registers to access ROM page mode and DRAM. 3.6.3 Basic Functions and Register Setting In this section, setting of the block address area, the data bus width, the connecting memory and the number of waits out of the memory controller's functions are described. (1) Block address area specification The block address area is specified by two registers. The memory start address register (MSARn) sets the start address of the block address areas. The memory controller compares between the register value and the address every bus cycles. The address bit which is masked by the memory address mask register (MAMRn) is not compared by the memory controller. The block address area size is determined by setting the memory address mask register. The set value in the register is compared with the block address area on the bus. If the compared result is a match, the memory controller sets the chip select signal (CSn) to "Low". (i) Setting memory start address register The MnS23 to MnS16 bits of the memory start address register respectively correspond with addresses A23 to A16. The lower start address A15 to A0 are always set to address 0000H. Therefore, the start address of the block address area are set to addresses 000000H to FF0000H every 64 Kbytes. 94C251A-60 2005-05-10 TMP94C251A (ii) Setting memory address mask registers The memory address mask register sets whether an address bit is compared or not. Set the register to "0" to compare, or to "1" not to compare. The address bit to be set is depended on the block address area. Block address area 0: A20 to A8 Block address area 1: A21 to A8 Block address area 2 to 5: A22 to A15 The above-mentioned bits are always compared. The block address area size is determined by the compared result. The size to be set depending on the block address areas is as follows. Note: After reset release, only the control register of the block address area 2 is valid. The control register of the block address area 2 has B2M bit. Setting B2M bit to "0" sets the block address area 2 to addresses 000000H to FFFFFFH. Setting B2M bit to "1" specifies the start address and the address area size as it is in the other block address area. (iii) Example of register setting To set the block address area 1 to 512 bytes from address 110000H, set the register as follows. MSAR1 Register M1S23 to M1S16 bits of the memory start address register MSAR1 correspond with addresses A23 to A16. A15 to A0 are set to "0". Therefore, setting MSAR1 to the above-mentioned value specifies the start address of the block address area 1 to address 110000H. The start address is set as it is in the other block address areas. 94C251A-61 2005-05-10 TMP94C251A MAMR1 Register M1V21 to M1V16 and M1V8 bits of the memory address mask register MAMR1 set whether addresses A21 to A16 and A8 are compared or not. Set the register to "0" to compare, or to "1" not to compare. M1V15 to M1V9 bits set whether addresses A15 to A9 are compared or not with 1 bit. A23 and A22 are always compared. Setting the above-mentioned compares A23 to A9 with the values set as the start addresses. Therefore, 512 bytes of addresses 110000H to 1101FFH are set as the block address area 1, and compared with the addresses on the bus. If the compared result is a match, the chip select signal CS1 is set to "Low". The other block address area sizes are specified like this. A23 and A22 are always compared in the block address area 0. Whether A20 to A8 are compared or not is set to the register. Similarly, A23 is always compared in the block address areas 2 to 5. Whether A22 to A15 are compared or not is set to the register. Note: When the set block address area overlaps with the built-in memory area, or both two address areas overlap, the block address areas are processed according to priority as follows. Built-in I/O > Built-in memory > Block address area 0 > 1 > 2 > 3 > 4 > 5 Note also that any accessed areas outside the address spaces set by CS0 to CS5 are processed as the CS2 space. Therefore, settings of CS2 apply for the control of wait cycles, data bus width, etc., and the CS2 signal is output. 94C251A-62 2005-05-10 TMP94C251A (2) Connection memory specification Setting the BnOM1 to BnOM0 bit of the control register (BnCSH) specifies the memory type to be connected with the block address areas. The interface signal is output according to the set memory as follows. BnOM1, BnOM0 Bit (BnCSH register) DRAM is set only in the block address are 1 and 3. When ROM is selected, the page mode is accessed. It is possible to specify only in the block address area 2. (3) Data bus width specification The data bus width is set for every block address areas. The bus size is set by the BnBUS1 and BnBUS0 bits of the control register (BnCSH) as follows. BnBUS Bit (BnCSH register) This way of changing the data bus size depending on the address being accessed is called "dynamic bus sizing". The part where the data is output to is depended on the data size, the bus width and the start address. Note: Since there is a possibility of abnormal writing/reading of the data if two memories with different bus width are put in consecutive address, do not execute a access both memories with one command. 94C251A-63 2005-05-10 TMP94C251A 94C251A-64 2005-05-10 TMP94C251A (4) Wait control The external bus cycle completes a wait of two states at least (100ns at 20 MHz). Setting the BnWW2 to BnWW0 and BnWR2 to BnWR0 of the control register (BnCSL) specifies the number of waits in the read cycle and the write cycle. BnWW is set with the same method as BnWR. BnWW/BnWR Bit (BnCSL register) Note: When DRAM is specified as a connecting memory, setting should be 3 states (1 wait) or more. In the case of DRAM access, the WAIT pin input mode cannot be used. (i) Waits number fixed mode The bus cycle is completed with the set states. The number of states is selected from 2 states (0 waits) to 5 states (3 waits). (ii) WAIT pin input mode This mode samples the WAIT input pins. It continuously samples the WAIT pin state and inserts a wait if the pin is active. The bus cycle is minimum 2 states. The bus cycle is completed when the wait signal is non-active ("High" level) at 2 states. The bus cycle extends if the wait signal is active at 2 states and more. BnREC Bit (BnCSH register) When not inserting a dummy cycle (0 waits) When inserting a dummy cycle (0 waits) Figure 3.6.1 Read Cycle when Dummy Cycle is Inserted 94C251A-65 2005-05-10 TMP94C251A (5) Basic bus timing External read/write bus cycle (0 waits) External read/write bus cycle (1 wait) 94C251A-66 2005-05-10 TMP94C251A External read/write bus cycle (0 waits at WAIT pin input mode) External read/write bus cycle (n waits at WAIT pin input mode) 94C251A-67 2005-05-10 TMP94C251A Example of WAIT input cycle (5 waits) FF0 D CK RES FF2 FF1 Q D Q D FF3 Q CK CK RES RES D FF4 Q CK RES D Q WAIT CK RES CLK CS RD WR 94C251A-68 2005-05-10 TMP94C251A 3.6.4 ROM Control (Page mode) This section describes ROM page mode accessing and how to set the registers. ROM page mode is set by the page ROM control register. (1) Operation and how to set the registers TMP94C251A supports ROM access of the page mode. The ROM access of the page mode is specified only in the block address area 2. ROM page mode is set by the page ROM control register (PMEMCR). Setting OPGE bit of the PMEMCR register to "1" sets the memory access of the block address area 2 to ROM page mode access. The number of read cycles is set by the OPWR1, OPWR0 bit of the PMEMCR register. OPWR1/OPWR0 Bit (PMEMCR register) Note: Set the number of waits "n" to the control register (BnCSL) in each block address area. The page size (The number of bytes) of ROM in the CPU side is set to the PR1 and 0 bits of the PMEMCR register. When data is read out until a border of the set page, the controller completes the page reading operation. The start data of the next page is read in the normal cycle. The following data is set to page read again. PR1/PR0 Bit (PMEMCR register) (2) Signal timing pulse For the signal timing pulse, see ROM read cycle in section 4.3.2. 94C251A-69 2005-05-10 TMP94C251A 3.6.5 List of Registers The memory control registers and the settings are described as follows. addresses of the registers, see "List of Special Function Registers" in section 5. For the (1) Control register The control register is a pair of BnCSL and BnCSH. (n is a number of the block address area.) BnCSL has the same configuration regardless of the block address areas. In BnCSH, only B2CSH which is corresponded to the block address area 2 has a different configuration from the others. Note)Read-modify-write is prohibited. BnWW[2:0] Specifies the number of write waits. 001 = 2 states (0 waits) access 010 = 3 states (1 wait) access 101 = 4 states (2 waits) access 110 = 5 states (3 waits) access 011 = WAIT pin input mode Others = (Reserved) BnWR[2:0] Specifies the number of read waits. 001 = 2 states (0 waits) access 010 = 3 states (1 wait) access 101 = 4 states (2 waits) access 110 = 5 states (3 waits) access 011 = WAIT pin input mode Others = (Reserved) Note: When DRAM is specified as a connecting memory, setting should be 3 states (1 wait) or more. In the case of DRAM access, the WAIT pin input mode cannot be used. Note)Read-modify-write is prohibited. B2E Enable bit 0 = No chip select signal output 1 = Chip select signal output (Default) Note: B2M After reset release, only the enable bit B2E of B2CS register is valid ("1"). Block address area specification 0 = Sets the block address area of CS2 to addresses 000000H to FFFFFFH. (Default) 1 = Sets the block address area of CS2 to programmable. Note: After reset release, the block address area 2 is set to addresses 000000H to FFFFFFH. 94C251A-70 2005-05-10 TMP94C251A B2REC Sets the dummy cycle for data output recovery time. 0 = Not insert a dummy cycle (Default) 1 = Insert a dummy cycle B2OM [1:0] 00 = SRAM or ROM (Default) Others = (Reserved) B2BUS [1:0] Sets the data bus width 00 = 8 bits (Default) 01 = 16 bits 10 = (Reserved) 11 = (Reserved) Note: The value of B2BUS bit is set according to the state of AM[1:0] pin after reset release. Note)Read-modify-write is prohibited. BnE Enable bit 0 = No chip select signal output (Default) 1 = Chip select signal BnREC Sets the dummy cycle for data output recovery time. 0 = Not insert a dummy cycle (Default) 1 = Insert a dummy cycle BnOM [1:0] Sets the connecting device. 00 = SRAM or ROM (Default) 01 = (Reserved) 10 = DRAM 11 = (Reserved) Note: DRAM is set only by B1CS and B3CS. BnBUS [1:0] Sets data bus width. 00 = 8 bits (Default) 01 = 16 bits 10 = (Reserved) 11 = (Reserved) 94C251A-71 2005-05-10 TMP94C251A (2) Block address register A start address and an address area of the block address area are specified by the memory start address register (MSARn) and the memory address mask register (MAMRn). The memory start address register sets all start addresses similarly regardless of the block address areas. The bit to be set by the memory address mask register is depended on the block address area. MnS [23:16] Sets a start address. Sets the start address of the block address areas. The bit are corresponding to the addresses A23 to A16. M0V [20:8] Enables or masks comparison of the addresses. M0V20 to M0V8 are corresponding to addresses A20 to A8. The bit of M0V14 to M0V9 are corresponding to addresses A14 to A9 by 1 bit. If "0" is set, the comparison between the value of the address bus and the start address is enabled. If "1" is set, the comparison is masked. M1V [21:8] Enables or masks comparison of the addresses. M1V20 to M1V8 are corresponding to addresses A21 to A8. The bit of M1V15 to M1V9 are corresponding to addresses A15 to A9 by 1 bit. If "0" is set, the comparison between the value of the address bus and the start address is enabled. If "1" is set, the comparison is masked. 94C251A-72 2005-05-10 TMP94C251A MnV [22:15] Enables or masks comparison of the addresses. MnV22 to MnV15 are corresponding to addresses A22 to A15. If "0" is set, the comparison between the value of the address bus and the start address is enabled. If "1" is set, the comparison is masked. (3) Page ROM control register (PMEMCR) The page ROM control register sets page ROM accessing. ROM page accessing is executed only in the block address area 2. OPGE enable bit 0 = No ROM page mode accessing (Default) 1 = ROM page mode accessing OPWR [1:0] Specifies the number of waits. 00 = 1 state (n-1-1-1 mode) (n 2) (Default) 01 = 2 states (n-2-2-2 mode) (n 3) 10 = 3 states (n-3-3-3 mode) (n 4) 01 = (Reserved) Note: Set the number of waits "n" to the control register (BnCSL) in each block address area. PR [1:0] ROM page size 00 = 64 bytes 01 = 32 bytes 10 = 16 bytes (Default) 11 = 8 bytes 94C251A-73 2005-05-10 TMP94C251A Table 3.6.1 Control Register (1/2) Note)Read-modify-write is prohibited for B0CSL,B0CSH, B1CSL,B1CSH, B2CSL,B2CSH, B3CSL,B3CSH, B4CSL and B4CSH. 94C251A-74 2005-05-10 TMP94C251A Table 3.6.2 Control Register (2/2) Note)Read-modify-write is prohibited for B5CSL and B5CSH. 94C251A-75 2005-05-10 TMP94C251A 3.6.6 Cautions If the parasitic capacitance of the read signal (Output enable signal) is greater than that of the Chip Select signal, it is possible that an unintended read cycle occurs due to a delay in the read signal. Such an unintended read cycle may cause a trouble as in the case of (a) in Figure 3.6.2. Figure 3.6.2 Read Signal Delay Read cycle Example: When using an externally connected flash E2PROM which uses JEDEC standard commands, note that the toggle bit may not be read out correctly. If the Read signal in the cycle immediately preceding the access to the flash E2PROM does not go High in time, as shown in Figure 3.6.3, an unintended Read cycle like the one shown in (b) may occur. Figure 3.6.3 Flash E2PROM Toggle Bit Read cycle When the toggle bit reverses with this unexpected read cycle, TMP94C251A always reads same value of the toggle bit, and cannot read the toggle bit correctly. To avoid this phenomena, the data polling control is recommended. 94C251A-76 2005-05-10 TMP94C251A 3.7 DRAM Controller TMP94C251A has a two-channel DRAM controller. In addition, it controls DRAM access, address multiplexed, refresh, etc. as followings. * Mapping area Block address area 1 ... 256 to 4 Mbytes Block address area 3 ... 32K to 8 Mbytes * Memory access mode 2CAS (16-bit bus), 1CAS (8-bit bus) Supports the page mode. Note) The 32-bit bus mode is supported only in the channel 1. * Memory access address length Selects of 8 to 11 bits. * Refresh mode CAS-before-RAS refresh mode * Refresh interval Programmable (78 to 384 states) * Refresh cycle width Programmable (2 to 9 states) * Self-refresh Sets the self-refresh mode. * Arbitration between refresh and access Refresh is prior to access. Wait is automatically inserted to the access cycle. * Operation during bus release While the bus is released, there is a mode to support only DRAM refresh operation. The data bus width and the number of waits to access DRAM are set according to the set value to the control register (B1CSH, B3CSH) in the block address area 1 and 3. This wait setting should be 3 states (1 wait) or more. In the case of DRAM access, the WAIT pin input mode cannot be used. The DRAM control register (DRAM0CRL/H, DRAM1CRL/H) and the DRAM refresh control register (DRAM0REF, DRAM1REF) set the other values. DRAM accessing and refresh are explained with the setting method of the registers. 94C251A-77 2005-05-10 TMP94C251A (1) DRAM access pin The DRAM accessing is performed by the following pins. The functions of the pins are depended on the connected data bus width. The data bus width is set to the control register (B1CSH, B3CSH) in the block address area 1 and 3. (2) DRAM access control The DRAM control register (DRAM0CRL/H, DRAM1CRL/H) sets the DRAM access mode. The following explains the operations of the modes and the setting of the register. (i) Address multiplexing In TMP94C251A, the internal address multiplexer outputs the row/column address. The multiplexed address lines depend on the bus size: 8-bit or 11-bit. * Setting method The MUXWn1 and MUXWn0 bits of the DRAM control register specify the multiplexed address width. The value set as follows is valid by setting MUXEn bit to "1". MUXWn 94C251A-78 2005-05-10 TMP94C251A The multiplexed access bus size is depended on the data bus width after the multiplexed address width is set. In addition, the following multiplexed method is provided to connect 16 M bit DRAM and 64 M bit DRAM. The following procedure can be used to set the multiplexed method. Select a multiplexed method(16M/64M) to set "DRAMSELn" bit of DRAM control register. "DRAMSELn" setting can be used by setting "ChnEN" bit of DRMEXT register to "1". 94C251A-79 2005-05-10 TMP94C251A DRAMSEL n Bit Note: This mode does not support development tools. (ii) Page mode access The DRAM page mode is accessed by setting the PGEn bit of the DRAM control register to "1". In the usual DRAM accessing, the number of waits is set to the control register (BnCSL) in the block address areas. However in the page mode accessing, it is set to the DRAM control register. * Setting method The number of waits in writing is set to the PnWW1, PnWW0 bits. The number of waits in reading is set to the PnWR1, PnWR0 bits. The setting method is the same as follows. PnWW/PnWR Bit Note: Set the number of waits "n" to the control register (BnCSL) in each block address area. (iii) DRAM access signal timing For details of the signal timing pulse, see DRAM bus cycle in section 4.3.3. 94C251A-80 2005-05-10 TMP94C251A (3) DRAM refresh controller TMP94C251A supports three refresh controls as followings, * CAS-before-RAS interval refresh * CAS-before-RAS self-refresh * Dummy refresh The DRAM refresh control register (DRAM0REF, DRAM1REF) and the SRFC bit of the DRAM control register control the DRAM refresh operation. The followings explain the setting method and the operations. (i) CAS-before-RAS interval refresh In the CAS-before-RAS interval refresh mode, the RAS and CAS signals which are necessary for DRAM refresh are created according to the refresh interval and the refresh cycle width. * Execution procedure Setting the RCn bit of the DRAM refresh control register (DRAM0REF, DRAM1REF) to "1" inserts the refresh cycle. The refresh cycle width is set to RWn2 to RWn0 bit, and the refresh cycle insertion interval is set to RSn2 to RSn0 bit. When using DRAM, set to at least three cycles. The RWn bit is set as follows. RWn 94C251A-81 2005-05-10 TMP94C251A The refresh insertion interval is set in accordance with the setting of the RSn bit. The refresh cycle insertion interval is set in accordance with the frequency of the system clock as follows. RSn * Refresh cycle timing (ii) CAS-before-RAS self-refresh The CAS-before-RAS self-refresh (Hereinafter refered to as self-refresh mode) used when the clock supplied is stopped by a HALT instruction while refreshing using the CAS-before-RAS interval refresh mode (Hereinafter refereed to as interval mode). (To stop clock supplied by a HALT instruction, the standby function is set in the IDLE mode or the STOP mode.) 94C251A-82 2005-05-10 TMP94C251A * Execution procedure Setting the SFRCn bit of the DRAM control register to "0" during refresh in usual interval mode executes self-refresh. In the self-refresh mode, the RAS and CAS signals maintain their low levels after turning to "Low", as it is in the interval mode. When HALT is released and the clock is supplied, "1" is set to the SFRCn bit by HALT release detector. The self-refresh mode is automatically released. But "1" isn't set in "RUN mode". After the self-refresh mode is released, RAS and CAS signals turn to "High". The usual refresh is executed to return to the interval refresh mode. * Self-refresh cycle timing (iii) Dummy refresh The dummy refresh executes CAS-before-RAS interval refresh successively. The refresh cycle width is fixed to 4 states; the interval, to 6 states. 94C251A-83 2005-05-10 TMP94C251A * Execution procedure Setting the DMn bit of the DRAM refresh control register (DRAM0REF, DRAM1REF) to "1" generates the dummy refresh. Dummy refresh is released by writing "0" to the DMn bit, by enabling DAM access control, or setting the RCn bit of the DRAM refresh control register to "1" and setting to the interval refresh mode. When dummy refresh mode is released by enabling DRAM access control or by setting the RCn bit of the DRAM refresh control register, the DMn bit is not cleared to zero. * Cycle timing CLK RAS CAS 4 cycle 6 cycle (4) Priorities As the DRAM refresh cycle is asynchronous to the CPU operating cycle, the refresh cycle may overlap with DRAM read and write cycles. If an overlap occurs, the DRAM controller gives priority to the cycle that started first. If the refresh cycle and DRAM access request are generated at the same time, the refresh cycle is given priority. In this case, the DRAM controller automatically inserts wait states in the memory access cycle until the refresh cycle completes. (5) Refresh in the bus release mode TMP94C251A has a bus release function. DRAM accessing pins ( RAS , CAS ) include two modes; either to release mode (Set to high impedance) in the same way as other pins, or to non-release mode (Output refresh signals). The BRMn bit of DRAM control register sets these modes. BRMn 94C251A-84 2005-05-10 TMP94C251A * DRAM accessing pin release mode When "0" is input to the BRMn bit and the bus release request pin ( BUSRQ ) is set to active, TMP94C251A acknowledges a bus release request. When the current bus cycle completes, TMP94C251A first set the DRAM accessing pins ( RAS , CAS ) to high, then turns the output buffer off to set the pins to high impedance. As the refresh cycle is asynchronous to the access cycle, when a refresh request is generated and has to wait, the refresh cycle is generated and the bus is released. Only one refresh request generated during the bus release is held. The refresh cycle is generated immediately upon return of the bus mastership to TMP94C251A at bus release completion. * DRAM accessing pin non-release mode When "1" is input to the BRMn bit, DRAM accessing pins do not release the bus when a bus release request occurs. The pins continue to operate but support refresh cycles only. In DRAM accessing pin non-release mode, the bus release timing is not affected by refresh requests. (6) List of registers The registers to control DRAM controller and the settings are described as follows. For the addresses of the registers, see List of Special Function Registers in section 5. DRAM can be set to the connecting memory only in the block address area 1 and 3. DRAMEXT, DRAM0CRL, DRAM0CRH and DRAM0REF control DRAM (Channel 0) in the block address area 1. DRAMEXT, DRAM1CRL, DRAM1CRH and DRAM1REF control DRAM (Channel 1) in the block address area 3. 94C251A-85 2005-05-10 TMP94C251A * SFRC0/1 self-refresh control 0 = Self-refresh 1 = No self-refresh * BRM0/1 bus release mode control 0 = Also releases DRAM pin in bus release mode 1 = Does not release DRAM pin in bus release mode. Supports only refresh. * DRAMSEL0/1 multiplex system 0 = 16 Mbits 1 = 64 Mbits * MUXE0/1 address multiplex 0 = Disable 1 = Enable (Make this setting when using DRAM.) * MUXW0/1[1:0] multiplex address length control 00 = 8 bits 01 = 9 bits 10 = 10 bits 11 = 11 bits * MAC0/1 enable bit 0 = No DRAM access control 1 = DRAM access control 94C251A-86 2005-05-10 TMP94C251A * P0/1WW[1:0] specifies the number of DRAM page mode write waits. 00 = (Reserved) 01 = 2 states (n-2-2-2 mode) (n 3) 10 = 3 states (n-3-3-3 mode) (n 4) 11 = (Reserved) Note: Set the number of waits "n" in the corresponding control register (BnCSL). * P0/1WR[1:0] specifies the number of DRAM page mode read waits. 00 = (Reserved) 01 = 2 states (n-2-2-2 mode) (n 3) 10 = 3 states (n-3-3-3 mode) (n 4) 11 = (Reserved) Note: * Set the number of waits "n" to the control register (BnCSL) in each block address area. PGE0/1 page mode access enable 0 = No page mode access 1 = Page mode access Note: Please set the same value to PGE0 and PGE1. Setting the different value may occur malfunction. * DM0/1 dummy refresh cycle control 0 = No dummy refresh cycle 1 = Dummy refresh cycle 94C251A-87 2005-05-10 TMP94C251A * RS0/1[2:0] refresh cycle insertion interval 000 = 78 cycles 001 = 154 cycles 010 = 188 cycles 011 = 226 cycles 100 = 246 cycles 101 = 302 cycles 110 = 308 cycles 111 = 384 cycles * RW0/1[2:0] refresh cycle width 000 = 2 cycles 001 = 3 cycles 010 = 4 cycles 011 = 5 cycles 100 = 6 cycles 101 = 7 cycles 110 = 8 cycles 111 = 9 cycles * RC0/1 enable bit 0 = No refresh cycle 1 = Refresh cycle * CH0EN/CH1EN DRAMSELn bit enable 0 = "DRAMSELn" setting is invalid. 1 = "DRAMSELn" setting is valid. 94C251A-88 2005-05-10 TMP94C251A (7) Register setting examples The following shows an example of setting block address space 1 (CS1) with addresses 100000H to 1FFFFFH (1-Mbyte space), 8-bit data bus width, write 3 states, read 3 states, no dummy cycle for data bus recovery, and 8-bit address multiplex DRAM mode. MSAR1 = 10H MAMR1 = 3FH B1CSL = 22H B1CSH = 88H DRAM0CRL = 8DH The following shows an example of setting block address space 3 (CS3) with addresses 300000H to 3FFFFFH (1-Mbyte space), 16-bit data bus width, write/read 1 wait, page access, and 10-bit address multiplex DRAM mode. MSAR3 = 30H MAMR3 = 1FH B3CSH = 89H DRAM1CRL = 8DH DRAM1CRH = 58H 94C251A-89 2005-05-10 TMP94C251A Table 3.7.1 List of Registers 94C251A-90 2005-05-10 TMP94C251A 3.8 8-Bit Timers TMP94C251A incorporates four 8-bit timers (Timers 0 to 3). Each timer can operate independently or be cascaded to form two 16-bit timers. The 8-bit timers have the following four operating modes. * * 8-bit interval timer mode (4 channels) The above two modes can be combined 16-bit interval timer mode (2 channels) (for example, two 8-bit timers and one 16-bit timers) * 8-bit programmable square wave (PPG: Variable cycle, variable duty) output mode (2 channels) * 8-bit PWM (Pulse width modulation: Variable duty at fixed cycle) output mode (2 channels) Figure 3.8.1 is a block diagram for 8-bit timers (Timers 0, 1). Timers 2 and 3, have the same circuit configuration as timers 0 and 1. Each interval timer consists of an 8-bit up counter, an 8-bit comparator, and an 8-bit timer register. One timer flip-flop each (TFF1, TFF3) is provided for the timer pairs: timers 0 and 1, timers 2 and 3. Of the input clock sources for interval timers, the T1, T4, T16, and T256 internal clocks are obtained from the 9-bit prescaler shown in Figure 3.8.2. The 8-bit timer operating mode and the timer flip-flops are controlled by six control registers (T01MOD, T23MOD, TFFCR, T8RUN, T16RUN, and TRDC) 94C251A-91 2005-05-10 Selector 94C251A-92 TREG-WR PWMTRG PPGTRG TRDC<TR0DE> Select T01MOD<T0CLK1:0> T16 T4 T1 Clear Register buffer TREG0 Comparator 8-bit up counter (UC0) RUN T8RUN<T0RUN> 2 -1 n Internal bus INTT0 Selector T01MOD<T1CLK1:0> T1 T16 T256 TREG1 Comparator 8-bit up counter (UC1) RUN T8RUN<T1RUN> Clear INTT1 Selector T01MOD<T01M1:0> TFFCR <TFF1IS> Selector T01MOD<T01M1:0> Soft trigger *1 Set *2 Clear *3 Invert TO1 TFFCR<TFF1IE> TFF1 *1 *2 *3 F/F control T02FFCR <FF1C1:0> TMP94C251A Figure 3.8.1 8-Bit Timer Block Diagram (Timers 0, 1) 2005-05-10 TMP94C251A [1] Prescaler The input to the 9-bit prescaler is the CPU fundamental clock (fc) divided by four (fc/4). The prescaler generates an input clock for the 8-bit timers, the 16-bit timer/event counters, and baud rate generator, for example. The 8-bit timers can use the following four clock signals: T1, T4, T16, and T256. To set the prescaler to count or stop, use timer control register T16RUN<PRRUN>. Setting T16RUN<PRRUN> to "1" starts the count. Clearing <PRRUN> to "0" clears and stops the prescaler. Resetting clears <PRRUN> to "0", and clears and stops the prescaler. Note: The number in the parenthesis indicates the frequency when TMP94C251A operates is the maximum frequency. Figure 3.8.2 Prescaler 94C251A-93 2005-05-10 TMP94C251A [2] Up counter The up counter is an 8-bit binary counter that counts up using the input clock specified by timer 0 and 1 mode registers T01MOD, T23MOD. The timer 0, 2 input clocks are selected from internal clocks T1, T4, and T16 in accordance with the T01MOD, T23MOD settings. The timer 1, 3 input clocks vary according to the operating mode. When the up-counter is set to 16-bit timer mode, timer 0, 2 overflow output is used as an input clock. When the up-counter is set to other than 16-bit timer mode, two further settings are available: internal clocks T1, T16, or T256 based on the T01MOD, T23MOD settings, and timer 0, 2 comparator output (Match detect). Example: If T01MOD<T01M1:0> is set to "01", the timer 0 overflow output is used as the timer 1 input clock (16-bit timer mode). T01MOD<T01M1:0> is "00" and <T1CLK1:0> is "01", T1 is used as the timer 1 input clock (8-bit timer mode). The T01MOD, T23MOD registers also set the operating mode. A reset sets the up-counter to 8-bit timer mode. To control the count, stop, and clear functions of each up-counter interval timer, use timer control register T8RUN. A reset clears all up-counters and stops the timers. [3] Timer registers The timer registers are 8-bit registers for setting interval times. When the setting of timer registers TREG0 to TREG3 matches the up-counter value, the comparator match detect signal becomes active. If "00H" is set, the match detect signal is activated when the up-counter overflows. Timer registers TREG0, TREG2 have a double-buffer configuration and are paired with a register buffer. TREG0, TREG2 enable or disable the double-buffer using timer register double-buffer control register TRDC<TR0/2DE>. Setting <TR0/2DE> to "0" disables the double-buffer; setting <TR0/2DE> to "1" enables the double-buffer. With the double-buffer enabled, data are transferred from the register buffer to the timer register at a 2n - 1 overflow in pulse width modulation (PWM) mode, or at an interval comparison match in programmable pulse generation (PPG) mode. 94C251A-94 2005-05-10 TMP94C251A A reset initializes <TR0/2DE> to "0", disabling the double-buffer. When using the double-buffer, first write data to the timer register and set <TR0/2DE> to "1", then write the following data to the register buffer. Figure 3.8.3 Timer Register 0/2/4/6 Configuration Note: The timer register and register buffer are allocated to the same address in memory. When <TR0/2DE> is set to "0", the same value is written to both the register buffer and the timer register. When <TR0/2DE> is set to "1", the value is written to the register buffer only. The timer registers are allocated in memory as follows. The timer register TREG0, TREG1, TREG2 and TREG3 are write-only; cannot read data from them. As the initial values are undefined, when using an 8-bit timer, be sure to write values. 94C251A-95 2005-05-10 TMP94C251A Figure 3.8.4 Timer 0/1 Mode Register (T01MOD) 94C251A-96 2005-05-10 TMP94C251A Figure 3.8.5 Timer 2/3 Mode Register (T23MOD) 94C251A-97 2005-05-10 TMP94C251A T T T T T T T T Note)Read-modify-write is prohibited. Figure 3.8.6 8-Bit Timer Flip-Flop Control Register (TFFCR) 94C251A-98 2005-05-10 TMP94C251A Figure 3.8.7 8-Bit Timer Operation Control Register (T8RUN) 94C251A-99 2005-05-10 TMP94C251A Figure 3.8.8 Timer Register Double-Buffer Control Register (TRDC) Figure 3.8.9 16-Bit Timer Operation Control Register (T16RUN) 94C251A-100 2005-05-10 TMP94C251A Note)Read-modify-write is prohibited. Figure 3.8.10 Timer Register [4] Comparator The comparator compares the up-counter value with the timer register value. If the values match, the comparator clears the up counter to 0 and generates an interrupt (INTT0 to INTT3). If the timer flip-flop invert is enabled at this time, the comparator inverts the timer flip-flop value. [5] Timer flip-flops (Timer F/F) Each interval timer match detect signal (Comparator output) inverts the timer flip-flops and outputs the values to timer output pins TO1 (also used as PC0), TO3 (also used as PC1). One timer flip-flop is provided for a timer pair: TFF1 for timer pair 0, 1; TFF3 for pair 2, 3. TFF1 is output to pin TO1, TFF3 to pin TO3. 94C251A-101 2005-05-10 TMP94C251A The following explains the operation of the 8-bit timers. (1) 8-bit timer mode Four interval timers 0 to 3 can be used independently as 8-bit interval timers. As all the timers operate the same, the following describes timer 1 only. [1] Generating a fixed-interval interrupt When using timer 1 to generate a timer 1 interrupt (INTT1) for each fixed interval, first halt timer 1, then set the operating mode, input clock, and interval in T01MOD and TREG1. Next, enable INTT1, and start timer 1 counting. Example: If a timer 1 interrupt is required every 40 s at fc = 20 MHz, set the registers in the following order: Note: X: Don't care -: No change For input clock selection, see the following table. Table 3.8.1 Selecting Interrupt Interval and the Input Clock Using 8-Bit Timer 94C251A-102 2005-05-10 TMP94C251A [2] Generating a square wave with a 50% duty cycle Invert the timer flip-flop at fixed intervals and output the timer flip-flop values to the timer output pin (TO1). Example: To output a square wave from pin TO1 with an interval of 2.4 s at fc = 20 MHz, set the registers in the following order. Use either timer 0 or 1. The example shows the register settings for timer 1. Note: X: Don't care -: No change Figure 3.8.11 Square Wave (50% Duty) Output Timing Chart 94C251A-103 2005-05-10 TMP94C251A [3] Setting timer 1 to count up at timer 0 match output Set 8-bit timer mode and set the timer 1 input clock to timer 0 comparator output. Figure 3.8.12 Timer 1 Count-up due to Matching Output of Timer 0 [4] Output invert by software The timer flip-flop (Timer F/F) value can be inverted independently of timer operation. For example, writing "00" to TFFCR<FF1C1:0> inverts the TFF1 value; writing "00" to TFFCR<FF3C1:0> inverts the TFF3 value. [5] Timer flip-flop (Timer F/F) initialization The timer flip-flop value can be initialized to "0" or "1" independently of timer operation. For example, to set TFF1 to 0, write "10" to TFFCR<FF1C1:0>. To set TFF1 to 1, write "01" to TFFCR<FF3C1:0>. Note: The timer flip-flop or timer register value cannot be read. (2) 16-bit timer mode Timers 0 and 1, 2 and 3 can be paired to configure 16-bit interval timers. As timers 0 and 1, 2 and 3 operate the same, the following describes timers 0 and 1 only. To cascade-connect timers 0 and 1 and configure a 16-bit interval timer, set mode register T01MOD<T01M1:0> to "01". 94C251A-104 2005-05-10 TMP94C251A When setting 16-bit timer mode, the input clock for timer 1 is provided by the overflow output of timer 0, irrespective of the clock control register TCLK setting. Table 3.8.2 Selection of 16-Bit Timer (Interrupt) Interval and Input Clock To set the timer interrupt interval, set the lower eight bits in timer register TREG0 and the upper eight bits in TREG1. Be sure to set TREG0 first (as entering data in TREG0 temporarily disables the compare, while entering data in TREG1 starts the compare). Setting example: To generate interrupt INTT1 every 0.4 s at fc = 20 MHz, set the following values in timer registers TREG0 and TREG1: Using T16 ( = 6.4 s at 20 MHz) as a timer input clock, 0.4 s / 6.4 s = 62500 = F424H Therefore, set TREG1 to F4H, and TREG0 to 24H. A match between up-counter UC0 and TREG0 triggers the timer 0 comparator to generate a match detect signal, but does not clear up-counter UC0. No interrupt INTT0 is generated. A match between up-counter UC1 and TREG1 at comparator timing triggers the timer 1 comparator to generate a match detect signal. When comparator match detect signals for both timer 0 and timer 1 are generated, up-counter 0 and up-counter 1 are cleared to 0 and interrupt INTT1 only is generated. When invert is enabled, the value of timer flip-flop TFF1 is inverted. 94C251A-105 2005-05-10 TMP94C251A (3) 8-bit programmable pulse generation output mode Timers 0, 2 can output variable frequencies and square waves (Pulses) with variable duty. The output pulse can be set to either active low or active high. Timers 1, 3 cannot be used in this mode. Timer 0 outputs from pin TO1 (also used as PC0), timer 2 outputs from pin TO3 (also used as PC1). As timers 0, 2 operate the same, the following describes timer 0 only. 94C251A-106 2005-05-10 TMP94C251A Figure 3.8.13 8-Bit PPG Output Mode Block Diagram Enabling the TREG0 double-buffer in this mode shifts the register buffer value to TREG0 when TREG1 matches UC0. Using the double-buffer facilitates output of waveforms with a low duty ratio (when changing the duty). Register Buffer Operation 94C251A-107 2005-05-10 TMP94C251A Example: Output a 1/4-duty 62.5 kHz pulse (at fc = 20 MHz) * Determine the set value in the timer register. Setting the frequency to 62.5 kHz generates a square wave with a cycle of t = 1/62.5 kHz = 16 s. Using T1 = 0.4 s (at fc = 20 MHz) results in: 16 s / 0.4 s = 40 Accordingly, set timer register 1 (TREG1) to TREG1 = 40 = 28H. Next, set the duty to 1/4 as follows: t x 1/4 = 16 s x 1/4 = 4 s Accordingly, set timer register 0 (TREG0) to TREG0 = 10 = 0AH. Note: X ; Don't care - ; No change 94C251A-108 2005-05-10 TMP94C251A (4) 8-bit pulse width modulation (PWM) output mode Only timers 0, 2 support this mode, which allows up to two pulse width modulation outputs with 8-bit resolution. For timer 0, PWM is output to pin TO1 (also used as PC0). For timer 2 PWM is output to pin TO3 (also used as PC1). Timers 1, 3 can be used as 8-bit timers. As timers 0, 2 operate the same, the following describes timer 0 only. Timer output is inverted when the up-counter UC0 setting and the timer register TREG setting match, or when 2n-1 (T01MOD specifies one of n = 6, n = 7, or n = 8) counter overflow occurs. The up-counter UC0 is cleared by the 2n-1 counter overflow. In 8-bit PWM output mode, the following conditions must be satisfied: (Timer register setting) < (2n - 1 counter overflow setting) (Timer register setting) 0 94C251A-109 2005-05-10 TMP94C251A Figure 3.8.14 8-Bit PWM Output Mode Block Diagram Enabling the TREG0 double-buffer in this mode shifts the register buffer value to TREG0 when 2n - 1 overflow is detected. Using the double-buffer facilitates output of waveforms with a low duty ratio (when changing the duty). Register Buffer Operation 94C251A-110 2005-05-10 TMP94C251A Example: Output the following PWM waveform to pin TO1 using timer 0 for fc = 20 MHz: To realize a PWM interval of 50.8 s using T1 = 0.4 s (at fc = 20 MHz) 50.8 s / 0.4 s = 127 = 2n-1 Accordingly, set n = 7. As the low-level interval is 36.0 s, at T1 = 0.4 s, set 36.0 s / 0.4 s = 90 = 5AH in TREG0 Note: X: Don't care -: No change Table 3.8.3 Setting PWM Interval and 2n-1 Counter 94C251A-111 2005-05-10 TMP94C251A (5) Table 3.8.4 shows the settings for all 8-bit timer modes. Table 3.8.4 Setting Register for All Timer Modes 94C251A-112 2005-05-10 TMP94C251A 3.9 16-Bit Timers TMP94C251A incorporates four multi-function 16-bit timer/event counters (Timers 4, 6, 8, and A). * 16-bit interval timer mode * 16-bit event counter mode * 16-bit programmable pulse generation (PPG) output mode * Frequency measurement mode * Pulse width modulation (PWM) mode * Time differential measurement mode The timer/event counters have a 16-bit up counter, two 16-bit timer registers (One with a double-buffer configuration), two 16-bit capture registers, two comparators, capture input control, and timer flip-flops and accompanying F/F control circuit. The timer/event counter is controlled by four control registers: T4MOD/T6MOD/ T8MOD/TAMOD, T4FFCR/T6FFCR/T8FFCR/TAFFCR, T16RUN and T16CR. Figure 3.9.1, Figure 3.9.2, Figure 3.9.3, and Figure 3.9.4 are block diagrams of a 16-bit timer/event counter (Timer 4, 6, 8, A). 94C251A-113 2005-05-10 TMP94C251A Figure 3.9.1 16-Bit Timer Block Diagram (Timer 4) 94C251A-114 2005-05-10 TMP94C251A Figure 3.9.2 16-Bit Timer Block Diagram (Timer 6) 94C251A-115 2005-05-10 TMP94C251A Figure 3.9.3 16-Bit Timer Block Diagram (Timer 8) 94C251A-116 2005-05-10 TMP94C251A Figure 3.9.4 16-Bit Timer Block Diagram (Timer A) 94C251A-117 2005-05-10 TMP94C251A Note)Read-modify-write is prohibited. Figure 3.9.5 16-Bit Timer Mode Control Register (T4MOD) (1/2) 94C251A-118 2005-05-10 TMP94C251A Note)Read-modify-write is prohibited. Figure 3.9.6 16-Bit Timer Control Register (T4MOD) (2/2) 94C251A-119 2005-05-10 TMP94C251A Note)Read-modify-write is prohibited. Figure 3.9.7 16-Bit Timer 4 F/F Control (T4FFCR) 94C251A-120 2005-05-10 TMP94C251A Note)Read-modify-write is prohibited. Figure 3.9.8 16-Bit Timer Mode Control Register (T6MOD) (1/2) 94C251A-121 2005-05-10 TMP94C251A Note)Read-modify-write is prohibited. Figure 3.9.9 16-Bit Timer Control Register (T6MOD) (2/2) 94C251A-122 2005-05-10 TMP94C251A Note)Read-modify-write is prohibited. Figure 3.9.10 16-Bit Timer 6 F/F Control (T6FFCR) 94C251A-123 2005-05-10 TMP94C251A Note)Read-modify-write is prohibited. Figure 3.9.11 16-Bit Timer Mode Control Register (T8MOD) (1/2) 94C251A-124 2005-05-10 TMP94C251A Note)Read-modify-write is prohibited. Figure 3.9.12 16-Bit Timer Control Register (T8MOD) (2/2) 94C251A-125 2005-05-10 TMP94C251A Note)Read-modify-write is prohibited. Figure 3.9.13 16-Bit Timer 8 F/F Control (T8FFCR) 94C251A-126 2005-05-10 TMP94C251A Note)Read-modify-write is prohibited. Figure 3.9.14 16-Bit Timer Mode Control Register (TAMOD) (1/2) 94C251A-127 2005-05-10 TMP94C251A Note)Read-modify-write is prohibited. Figure 3.9.15 16-Bit Timer Control Register (TAMOD) (2/2) 94C251A-128 2005-05-10 TMP94C251A Note)Read-modify-write is prohibited. Figure 3.9.16 16-Bit Timer A F/F Control (TAFFCR) 94C251A-129 2005-05-10 TMP94C251A Figure 3.9.17 16-Bit Timer Operation Control Register (T16RUN) Figure 3.9.18 16-Bit Timer (4, 6, 8, A) Control Register (T16CR) 94C251A-130 2005-05-10 TMP94C251A Note)Read-modify-write is prohibited. Figure 3.9.19 Timer Register 94C251A-131 2005-05-10 TMP94C251A Figure 3.9.20 Capture Register 94C251A-132 2005-05-10 TMP94C251A [1] Up counter The up counter is a 16-bit binary counter that counts up using the input clock specified by 16-bit timer mode control registers T4MOD<T4CLK1:0>, T6MOD<T6CLK1:0>, T8MOD<T8CLK1:0>, and TAMOD<TACLK1:0>. The input clock is selected from internal clocks T1, T4, and 16 output from the 9-bit prescaler (shared with the 8-bit timers), or the external clocks output from pin TI4 (also used as PD1/INT4), pin TI6 (also used as PD5/INT6), pin TI8 (also used as PE1/INT8), and pin TIA (also used as PE5/INTA). A reset initializes <T4CLK1:0> /<T8CLK1:0>/<T9CLK1:0>/<TACLK1:0> to "00", selecting an external input clock on pin TI4/TI6/TI8/TIA as the input clock. To control the count, stop, and clear functions for the counter, use timer control register T16RUN<T4RUN, T6RUN, T8RUN, TARUN>. If up counter clearing is enabled, up counter UC4/UC6/UC8/UCA are cleared to 0 when up counter UC4/UC6/UC8/UCA matches timer register TREG6/TREG7/TREG9/ TREGB. The clear enable/disable is set with T4MOD<CLE>, T6MOD<CLE>, T8MOD <CLE>, and TAMOD<CLE>. When clear disable is set, the counter operates as a free-running counter. [2] Timer registers Each timer has two internal 16-bit registers for setting counter values. When the value set in the timer register matches the value of the up counter UC4/UC6/UC8/UCA, the comparator match detect signal is activated. Setting data for both H and L registers (TREG4L/H, TREG5L/H, TREG6L/H, TREG7L/H, TREG8L/H, TREG9L/H, TREGAL/H, TREGBL/H) are always needed. For example, either using the 2-byte data load instruction or the 1-byte data load instruction twice; first to write data to the lower 8 bits, then to write data to the upper 8 bits. Timer registers TREG4, TREG6, TREG8, and TREGA have a double-buffer configuration and are paired with a register buffer. Timer registers TREG4/TREG6/ TREG8/TREGA enable/disable the double-buffer function using timer control register T16CR<DB4EN, DB6EN, DB8EN, DBAEN>. Setting <DB4EN, DB6EN, DB8EN, DBAEN> to 0 disables the double buffer; setting <DB4EN, DB6EN, DB8EN, DBAEN> to 1 enables the double buffer. With the double buffer enabled, data are transmitted from the register buffer to the timer register at a match between up counter UC4/UC6/UC8/UCA and timer register TREG5/TREG7/TREG9/TREGB. A reset initializes T16CR<DB4EN, DB6EN, DB8EN, DBAEN> to "0", disabling the double buffer. When using the double buffer, write data to the timer register and set <DB4EN, DB6EN, DB8EN, DBAEN> to "1", then write the next data to the register buffer. TREG4/TREG6/TREG8/TREGA and the register buffer are allocated to the same addresses in memory (000090H, 000091H/0000A0H, 0000A1H/0000B0H, 0000B1H/0000C0H, 0000C1H). When <DB4EN, DB6EN, DB8EN, DBAEN>is set to "0", the same value is written to TREG4/TREG6/TREG8/TREGA and to their respective register buffers. When <DB4EN, DB6EN, DB8EN, DBAEN> is set to "1", the value is written to the register buffers only. Therefore, disable the register buffers before writing the initial values to the timer registers. As the timer registers are undefined after a reset, be sure to write data to the upper and lower registers before using the timers. 94C251A-133 2005-05-10 TMP94C251A [3] Capture register The capture register is a 16-bit register for latching the up counter value. Data in the capture registers should be read all 16 bits(H and L). When reading the capture register, use the 2-byte data load instruction, or the 1-byte data load instruction twice; first to read data from the lower 8 bits, then to read data from the upper 8 bits. [4] Capture input control The capture input control circuit controls the timing to latch the up counter UC4/UC6/UC8/UCA value to capture registers CAP4, CAP5/CAP6, CAP7/CAP8, CAP9/CAPA, CAPB. Set the capture register latch timing using T4MOD<CAP45M1:0>/T6MOD <CAP67M1:0>/T8MOD<CAP89M1:0>/TAMOD<CAPABM1:0>. * When T4MOD<CPA45M1:0>/T6MOD<CAP67M1:0>/T8MOD<CAP89M1:0>/ DAMOD<CAPABM1:0> = "00", the capture function is disabled. Resetting disables the capture function. * When T4MOD<CPA45M1:0>/T6MOD<CAP67M1:0>/T8MOD<CAP89M1:0>/ DAMOD<CAPABM1:0> = "01", On the TI4 (also used as PD1/INT4)/TI6 (also used as PD5/INT6)/TI8 (also used as PE1/INT8)/TIA (also used as PE5/INTA) input rising edge, the up counter value is loaded to capture register CAP4/CAP6/CAP8/CAPA. On the TI5 (also used as PD2/INT5)/TI7 (also used as PD6/INT7)/TI9 (also used as PE2/INT9)/TIB (also used as PE6/INTB) input rising edge, the up counter value is loaded to capture register CAP5/CAP7/CAP9/CAPB (Time differential measurement). * When T4MOD<CPA45M1:0>/T6MOD<CAP67M1:0>/T8MOD<CAP89M1:0>/ DAMOD<CAPABM1:0> = "10", On the TI4/TI6/TI8/TIA input rising edge, the up counter value is loaded to capture register CAP4/CAP6/CAP8/CAPA. On the input falling edge, the up counter value is loaded to capture register CAP5/CAP7/CAP9/CAPB. In this mode only, interrupt INT4/INT6 is generated on a falling edge (Pulse width measurement). * When T4MOD<CPA45M1:0>/T6MOD<CAP67M1:0>/T8MOD<CAP89M1:0>/ DAMOD<CAPABM1:0> = "11", On the timer flip-flop TFF1 rising edge, the up counter value is loaded to capture register CAP4/CAP6/CAP8/CAPA. On the falling edge, the up counter value is loaded to capture register CAP5/CAP7/CAP9/CAPB. The up counter value can also be loaded to a capture register on a software request. When "0" is written to T4MOD<CAP4IN>/T6MOD<CAP6IN>/T8MOD <CAP8IN>/TAMOD <CAPAIN>, the up counter value at that time is loaded to capture register CAP4/CAP6/CAP8 /CAPA. The prescaler must be set to RUN (Set T16RUN<PRRUN> to "1"). 94C251A-134 2005-05-10 TMP94C251A [5] Comparator A 16-bit comparator compares the up counter UC4/UC6/UC8/UCA value with the value set in the timer register (TREG4, TREG5/TREG6, TREG7/TREG8, TREG9/TREGA, TREGB) to detect a match. On detection of a match, the comparator generates interrupt INTTR4/INTTR5, INTTR6/INTTR7, INTTR8/INTTR9, INTTRA/INTTRB. Only a match with TREG5/TREG7/TREG9/TREGB clears up counter UC4/UC6/UC8/UCA. (Setting T4MOD <CLE>/T6MOD<CLE>/T8MOD<CLE>/TAMOD<CLE> to "0" disables UC4/UC6/ UC8/UCA clearing.) [6] Timer flip-flop TFF4/TFF6/TFF8/TFFA This flip-flop is inverted by a match detect signal from the comparator and a latch signal to the capture register. Enable or disable the invert for each interrupt source using T4FFCR<CAP5T4, CAP4T4, EQ5T4, EQ4T4>/T6FFCR<CAP7T6, CAP6T6, EQ7T6, EQ6T6>/T8FFCR <CAP9T8, CAP8T8, EQ9T8, EQ8T8>/TAFFCR<CAPBTA, CAPATA, EQBTA, EQATA>. To invert TFF4/TFF6/TFF8/TFFA write "00" to T4FFCR<TFF4C1:0>/T6FFCR <TFF6C1:0>/T8FFCR<TFF8C1:0>/TAFFCR<TFFAC1:0>. Writing "01" sets TFF4/TFF6/TFF8/TFFA to 1; "10" clears TFF4/TFF6/TFF8/TFFA to 0. The TFF4/TFF6/TFF8/TFFA value can be output to timer output pin TO4 (also used as PD0)/TO6 (also used as PD4)/TO8 (also used as PE0)/TOA (also used as PE4). [7] Timer flip-flop TFF7/TFFB This flip-flop is inverted by a match detect signal between up counter UC6/A and timer register TREG7/B, and a latch signal to capture register CAP7/B. Enable or disable the invert for each interrupt source using T6MOD<CAP7T7, EQ7T7>/TAMOD<CAPBTB, EQBTB>. To invert TFF7/B, write "00" to T6FFCR<TFF7C1:0>/TAFFCR<TFFBC1:0>. Writing "01" sets TFF7/B to 1; "10" clears TFF7/B to 0. The TFF7/B value can be output to timer output pin TO7 (also used as PC3)/TOB (also used as PC1). Note: Only timer 6 and timer A contain this flip-flop (TFF7/TFFB). 94C251A-135 2005-05-10 TMP94C251A (1) 16-bit timer mode Timers 4, 6, 8 and A operate independently. As both timers operate the same, the following describes timer 4 only. Example: Generate fixed-interval interrupts Set an interval time in timer register TREG5 and generate interrupt INTTR5. Note: X ; Don't care - ; No change (2) 16-bit event counter mode Setting external clock TI4/TI6/TI8/TIA as an input clock in 16-bit timer mode results in an event counter. To obtain a counter value, load the counter value into a capture register using "software capture" and read the captured value from the capture register. The counter counts up at the TI4/TI6/TI8/TIA input rising edge. The TI4/TI6/TI8/TIA pin is also used as PD1/INT4, PD5/INT6, PE1/INT8, PE5/INTA. As timers 4, 6, 8 and A operate the same, the following describes timer 4 only. Note: Set the prescaler to RUN when using a 16-bit counter as an event counter. 94C251A-136 2005-05-10 TMP94C251A (3) 16-bit programmable pulse generation (PPG) output mode As timers 4, 6, 8 and A operate the same, the following describes timer 4 only. To enter PPG mode, set the device to invert timer flip-flop TFF4 and output the TFF4 value from the TO4 pin (also used as PD0) at a match between up counter UC4 and the TREG4/TREG5 register value. The following condition must be satisfied: (TREG4 setting) < (TREG5 setting). Note: X: Don't care -: No change Figure 3.9.21 Programmable Pulse Generation (PPG) Output Waveform 94C251A-137 2005-05-10 TMP94C251A Enabling the TREG4 double-buffer in this mode shifts the value of register buffer 4 to TREG4 when TREG5 matches UC4. Using the double-buffer facilitates output of waveforms with a low duty ratio. Figure 3.9.22 Register Buffer Operation The following is a block diagram of this mode. T16RUN<T4RUN> TI4 T1 T4 T16 16-bit up counter UC4 Selector TO4 (PPG output) Clear F/F (TFF4) T4MOD<T4CLK1:0> 16-bit comparator Match 16-bit comparator TREG4 Selector TREG4-WR Register buffer 4 TREG5 T16CR<DB4EN> Internal bus Figure 3.9.23 16-Bit PPG Mode Block Diagram 94C251A-138 2005-05-10 TMP94C251A (4) Capture function application example As timers 4, 6, 8 and A operate the same, the following describes timer 4 only. The following features of the 16-bit timer can be enabled or disabled as required: loading of up counter UC4 value to capture registers CAP4 and CAP5, inversion of timer flip/flop TFF4 on a match detect signal from comparators CP4 and CP5, and outputting of TFF4 to pin TO4. Many functions can be obtained by combining these features with interrupts. For example: [1] One-shot pulse output from the external trigger pulse [2] Frequency measurement [3] Pulse width measurement [4] Time differential measurement [1] One-shot pulse output from external trigger pulse Set up counter UC4 to free-running using internal clock input. Input the external trigger pulse from pin TI4, and load the up counter value to capture register CAP4 on the TI4 input rising edge (Set T4MOD<CAP45M1:0> to "01"). On the TI4 input rising edge, add the value of capture register CAP4 at interrupt INT4 (c) to the delay time (d), and set timer register TREG4 to the sum of these values (c + d). Add the pulse width of the one-shot pulse (p) to TREG4, and set TREG5 to the result (c + d + p). On interrupt INT4, set register T4FFCR <EQ5T4, EQ4T4> to "enable the inversion of timer flip-flop TFF4 only when the up counter matches with TREG4 or TREG5". On interrupt INTTR5, disable the inversion of timer flip-flop TFF8. Figure 3.9.24 One-Shot Pulse Output (With delay) 94C251A-139 2005-05-10 TMP94C251A Setting Example: On pin TI4, output a 2ms one-shot pulse with a 3ms-delay after an external trigger pulse. Note: X: Don't care -: No change If delay time is not required, invert timer flip-flop TFF4 by loading to capture register 4 (CAP4). Set timer register TREG5 to the sum of the one-shot pulse width (p) and the value of CAP4 at interrupt INT4 (c) (c + p). Enable TFF4 invert on match between TREG5 and up counter UC4. On interrupt INTTR5, disable the timer flip-flop TFF4 invert. 94C251A-140 2005-05-10 TMP94C251A Figure 3.9.25 One-Shot Pulse Output (No Delay) [2] Frequency measurement This mode is used to measure the frequency of the external clock. Input the external clock on pin TI4 and measure its frequency with the 8-bit timers (Timers 0, 1) and the 16-bit timer/event counter (Timer 4). Set the TI4 input as the timer 4 input clock, and load the value of up counter UC4 to capture register CAP4 when timer flip/flop TFF4 of the 8-bit timer (Timer 0, 1) rises, and to capture register CAP5 when timer flip/flop TFF4 falls. The frequency is determined from the difference between capture registers CAP4 and CAP5 at the 8-bit timer interrupts (INTT0 or INTT1). Figure 3.9.26 Frequency Measurement For example, if TFF1 is set to "1" for 0.5 s by the 8-bit timers, and the difference between CAP4 and CAP5 is 100, the frequency is 100 / 0.5 [s] = 200 [Hz]. 94C251A-141 2005-05-10 TMP94C251A [3] Pulse width measurement This mode is used for measuring the "high" level width of an external pulse. Input the external pulse through pin TI4 and set the 16-bit timer/event counter to free-running count-up using an internal clock. Load the up counter UC4 value into capture register CAP4 and CAP5 on the rising and falling edge respectively of the external pulse. Interrupt INT4 is generated on the falling edge of pin TI4. The pulse width can now be determined according to the difference between CAP4 and CAP5, and the internal clock interval. For example, if the difference between CAP4 and CAP5 is 100 and the internal clock interval is 0.8 s, the pulse width is 100 x 0.8 s = 80 s. Figure 3.9.27 Pulse Width Measurement Note: Only in pulse width measurement mode where T4MOD<CAP45M1, 0> = "10", external interrupt INT4 is generated at the falling edge of pin TI4. In other modes, external interrupt INT4 is generated at the rising edge. Determine the "low" level width at the second INT4 using the difference between the value of C5 at the first interrupt and the value of C4 at the second interrupt. [4] Time differential measurement This mode measures the time difference between the rising edge of the external pulses input to pins TI4 and TI5. Set the 16-bit timer/event counter (Timer 4) to free-running count-up using an internal clock. When a rising edge is detected in the pulse on pin TI4, the up counter UC4 value is loaded into capture register CAP4 and interrupt INT4 is generated. Similarly, when a rising edge is detected in the pulse on pin TI5, the up counter UC4 value is loaded into capture register CAP5 and interrupt INT5 is generated. When the up counter values are loaded to CAP4 and CAP5, the time difference can be determined from the difference between CAP4 and CAP5. 94C251A-142 2005-05-10 TMP94C251A Figure 3.9.28 Time Differential Measurement (5) Phase output mode Set the up counter UC4/6/8/A to free-running and output a signal with any phase differential. As timers 4, 6, 8 and A operate the same, the following describes timer 6 only. A match between up counter UC6 and TREG6 or TREG7 inverts TFF6 or TFF7 respectively, and outputs the invert values to TO6 and TO7 respectively. Figure 3.9.29 Phase Output The following table shows the interval (Counter overflow time) of the above waveform output. 94C251A-143 2005-05-10 TMP94C251A 3.10 Serial Channel TMP94C251A features two built-in serial input/output channels. The serial channel operating modes are as follows: * I/O interface mode Mode 0: For receiving and transmitting I/O data for I/O extension, and for receiving and transmitting synchronous I/O data signals (SCLK). * Universal asynchronous receiver transmitter (UART) mode Mode 1 : 7-bit transmit/receive data Mode 2: 8-bit transmit/receive data Mode 3: 9-bit transmit/receive data Parity bits can be added in modes 1 and 2. Figure 3.10.1 shows the data formats (for one frame) in each mode. * Mode 0 (I/O interface mode) * Mode 1 (7-bit UART mode) * Mode 2 (8-bit UART mode) * Mode 3 (9-bit UART mode) Figure 3.10.1 Data Formats 94C251A-144 2005-05-10 TMP94C251A Serial channel buffer registers temporarily hold data to be transmitted or received (full-duplex), allowing independent transmission and reception. Note that in I/O interface mode, the serial clock (SCLK) is shared between reception and transmission (half-duplex). The buffer register for reception features a double-buffer configuration to prevent overrun error; an extra frame holds data until the data are read by the CPU. That is, a receive buffer holds the data already received, while the buffer register receives the next frame of data. By using CTS and RTS (as no RTS pin is provided, a pin in any port must be controlled by software), it is possible to halt data transmission until the CPU reads the data received after each frame (handshake function). In UART mode, a check function prevents data receive operations from starting due to erroneous start bits being generated by noise or other interference on the line. The channel starts receiving data only when the start bit is detected as normal in at least two of three samplings. When the transmit buffer is empty, an INTTX interrupt is generated to request the CPU to supply the next data to transmit. When the receive buffer has data to be read by the CPU, an INTRX interrupt is generated. When an overrun error, parity error, or framing error is detected at data reception, the corresponding flag <OERR, PERR, FERR> is set in the control register (SC0CR/SC1CR) of the relevant serial channel. Serial channels 0 and 1 have a dedicated baud rate generator, which can set any baud rate by dividing the frequency of internal input clocks (T0, T2, T8, and T32) from the 9-bit prescaler (shared with 8/16 bit timers) by a value between 1 and 16. In addition to the clock from the internal baud rate generator, an arbitrary baud rate can be obtained from the external clock input (SCLK0/1). Moreover, in I/O interface mode, a sync signal (SCLK0/1) can be input and data transfer performed using this external clock. 3.10.1 Control Registers Each serial channel is controlled by three control registers (SC0CR, SC0MOD, and BR0CR for channel 0). Transmit/receive data are stored in a register in each channel (SC0BUF for channel 0). 94C251A-145 2005-05-10 TMP94C251A SC0MOD (00D2H) bit Symbol 7 6 5 TB8 CTSE RXE Read/Write After reset Function R/W Undefined 0 Transmit data bit 8 Handshake function control 0: CTS disable 1: CTS enable 4 3 2 - SM1 SM0 R/W 0 Receive control 0 Fixed to "0" 1 0 SC1 SC0 0 0 R/W 0 0 Serial transfer mode 00: I/O interface mode Serial transfer clock (UART) 0: receive disable 01: 7-bit UART mode 00: TO2 trigger 01: baud rate generator 1: receive enable 10: 8-bit UART mode 11: 9-bit UART mode 10: internal clock 1 11: external clock (SCLK0) Serial transfer clock (UART) 00 Timer 2 match detect signal 01 Baud rate generator 10 Internal clock 1 11 External clock (SCLK0) Serial transfer mode 00 I/O interface mode 01 10 7-bit UART mode 11 8-bit 9-bit Receive control 0 Receive disable 1 Receive enable Handshake function ( CTS pin) 0 Disable (transmission always enabled) 1 Enable Transmit data bit 8 Note: SC1MOD (D6H) is provided for channel 1. Figure 3.10.2 Serial Mode Control Register (SC0MOD, Channel 0) 94C251A-146 2005-05-10 TMP94C251A Figure 3.10.3 Serial Control Register (SC0CR, Channel 0) 94C251A-147 2005-05-10 TMP94C251A Figure 3.10.4 Baud Rate Generator Control Register (BR0CR, Channel 0) Note)Read-modify-write is prohibited. Figure 3.10.5 Serial Transmit/Receive Register (SC0BUF, Channel 0) 94C251A-148 2005-05-10 TMP94C251A SC1MOD (00D6H) bit Symbol 7 6 5 TB8 CTSE RXE Read/Write After reset Function R/W Undefined 0 Transmit data bit 8 Handshake function control 0: CTS disable 1: CTS enable 4 3 2 - SM1 SM0 R/W 0 Receive control 0 Fixed to "0" 1 0 SC1 SC0 0 0 R/W 0 0 Serial transfer mode 00: I/O interface mode Serial transfer clock (UART) 0: receive disable 01: 7-bit UART mode 00: TO2 trigger 01: baud rate generator 1: receive enable 10: 8-bit UART mode 11: 9-bit UART mode 10: internal clock 1 11: external clock SCLK1 Serial transfer clock (UART) 00 Timer 2 match detect signal 01 Baud rate generator 10 Internal clock 1 11 External clock SCLK1 Serial transfer mode 00 I/O interface mode 01 10 7-bit UART mode 11 8-bit 9-bit Receive control 0 Receive disable 1 Receive enable Handshake function ( CTS pin) 0 Disable (transmission always enabled) 1 Enable Transmit data bit 8 Figure 3.10.6 Serial Mode Control Register (SC1MOD, Channel 1) 94C251A-149 2005-05-10 TMP94C251A Figure 3.10.7 Serial Control Register (SC1CR, Channel 1) 94C251A-150 2005-05-10 TMP94C251A Figure 3.10.8 Baud Rate Generator Control Register (BR1CR, Channel 1) Note)Read-modify-write is prohibited. Figure 3.10.9 Serial Transmit/Receive Buffer Register (SC1BUF, Channel 1) 94C251A-151 2005-05-10 TMP94C251A Figure 3.10.10 Port F Function Register (PFFC) 94C251A-152 2005-05-10 TMP94C251A 3.10.2 Configuration Figure 3.10.11 is a block diagram of serial channel 0. Serial channel 1 has the same circuit configuration. Serial clock generator circuit external clock (SCLK0) TO2TRG (timer 2 comparator output) BR0CR<BR0CK1,0> <BR0S3:0> T0 T2 T8 T32 selector selector divider UART mode selector SC0MOD <SC1:0> baud rate generator 1 (fc/2) /2 SIOCLK SC0MOD <SM1:0> I/O interface mode selector SCLK0 input (also used as PF2)> SC0CR <IOC> SCLK0 output (also used as PF2) INTRX0 INTTX0 receive counter (16 in UART mode only) serial channel interrupt control transmit counter (16 in UART mode only) TXDCLK RXDCLK SC0MOD receive <RXE> transmit control control SC0CR <PE> <EVEN> CTS0 (also used as PF2) SC0MOD<CTSE> parity control RxD0 (also used as PF1) Receive buffer 1 (shift register) RB8 RB8 receive buffer 2 (SC0BUF) error flag TB8 transmit buffer SC0CR <OERR><PERR><FERR> TxD0 (also used as PF0) Internal bus Figure 3.10.11 Serial Channel 0 Block Diagram 94C251A-153 2005-05-10 TMP94C251A [1] Baud rate generator The baud rate generator is a circuit to generate the transmission clock signals that control the serial channel transmission rate. The baud rate generator input clock is one of T0 (4/fc), T2 (16/fc), T8 (64/fc), or T32 (256/fc) from the 9-bit prescaler that the baud rate generator shares with the timers. Bits 5 and 4 <BR0CK1:0>/<BR1CK1:0> of the baud rate generator control register (BR0CR/BR1CR) select the input clock. The baud rate generator features a built-in 4-bit divider. Set the transmission rate by dividing the frequency by 1 to 16 using the divider. Baud rates using the baud rate generator are determined as follows: * UART mode Baud Rate = * Baud rate generator input clock / 16 Baud rate generator divisor I/O interface mode Baud Rate = Baud rate generator input clock /2 Baud rate generator divisor The relationship between the input clock and the source clock (fc) is: T0 = 4/fc T2 = 16/fc T8 = 64/fc T32 = 256/fc Accordingly, with the source clock set to 19.6608 MHz, when T2 (16/fc) is selected as input clock and the divisor is 8, the baud rate in UART mode is: fc/16 / 16 8 = 19.6608 x 106 / 16 / 8 / 16 = 9600 (bps) Baud Rate = Table 3.10.1 shows examples of the baud rates in UART mode. In UART mode, the serial channels use 8-bit timer 2 to obtain the baud rate. Table 3.10.2 shows examples of baud rates using timer 2. Moreover, the external clock input can also be used as the serial clock. The baud rate in this case is determined as follows. Baud rate = External clock input / 16 94C251A-154 2005-05-10 TMP94C251A Table 3.10.1 UART Mode Baud Rate Selection (1) (Using baud rate generator) Table 3.10.2 UART Mode Baud Rate Selection (2) (Using timer 2 input clock T1) Baud rate calculation (using timer 2): Transmission rate: = fc TREG2 x 8 x 16 (Where timer 2 input clock is T1) Input clocks for timer 0 T1 = 8/fc T4 = 32/fc T16 = 128/fc Note: In I/O interface mode, the timer 2 match signal cannot be used as a transmission clock. 94C251A-155 2005-05-10 TMP94C251A [2] Serial clock generator circuit This circuit generates the transmit/receive basic clock. * In I/O interface mode In SCLK output mode where SC0CR/SC1CR<IOC> is set to "0", the basic clock (SIOCLK) is generated by dividing the output of the baud rate generator by 2. In SCLK input mode where SC0CR/SC1CR<IOC> is set to "1" the basic clock is derived from the rising or falling edge of the SCLK input, as determined by the setting of the SC0CR/SC1CR<SCLKS> register. * In universal asynchronous receiver transmitter (UART) mode Basic clock SIOCLK is selected from one of the following depending on the setting of the <SC1:0> bits of the SC0MOD or SC1MOD register: the clock from the baud rate generator, internal clock 1 (500K bps at fc = 16 MHz), a match detect signal from timer 2, or an external clock. [3] Receive counter The receive counter is a 4-bit binary counter that counts by the SIOCLK clock and is used in universal asynchronous receiver transmitter (UART) mode. Sixteen cycles of SIOCLK are used to receive one bit of data. The data are sampled three times: at the 7th, 8th, and 9th clock cycles. The data received are checked by the majority rule applied to the three samples. For example, if the sampled data bits are 1, 0, 1 at the 7th, 8th, and 9th clock cycles respectively, the data are determined as "1". If the samplings are 0, 0, 1, the data received are determined as "0". [4] Receive control section * In I/O interface mode In SCLK output mode where SC0CR/SC1CR<IOC> is set to "0", the RxD0/1 pin is sampled at the rising edge of the shift clock output on the SCLK0/1 pin. In SCLK input mode where SC0CR/SC1CR<IOC> is set to "1", the RxD0/1 pin is sampled at the rising or falling edge of SCLK input as determined by the setting of the SC0CR/SC1CR<SCLKS> register. * In universal asynchronous receiver transmitter (UART) mode The receive control section has a circuit for detecting the start bit by the majority rule. If two or more 0s are detected among three samples, the circuit recognizes the bit as a start bit and begins receiving. Data being received are also checked by the majority rule. 94C251A-156 2005-05-10 TMP94C251A [5] Receive buffer The receive buffer has a double-buffer configuration to prevent overrun error. Receive buffer 1 (a shift register buffer) stores the data received bit by bit. When the receive buffer contains seven or eight bits of data, the data are transferred to receive buffer 2 (SC0BUF/SC1BUF), generating interrupt INTRX0/INTRX1. The CPU reads only receive buffer 2 (SC0BUF/SC1BUF). Data can be stored in receive buffer 1 even before the CPU reads receive buffer 2. However, receive buffer 2 must be read before all bits of the next data unit are received by buffer 1. Otherwise, an overrun error occurs and the contents of receive buffer 1 are lost, although the contents of receive buffer 2 and SC0CR<RB8>/SC1CR<RB8> are preserved. Reading receive buffer 2 (SC0BUF/SC1BUF) clears interrupt request flags INTRX0<IRX0C> and INTRX1<IRX1C>. In 8-bit UART mode with parity added, the parity bit is stored in SC0CR<RB8>/SC1CR <RB8>. In 9-bit UART mode, the MSB is stored in SC0CR<RB8>/SC1CR<RB8>. [6] Transmit counter The transmit counter is a 4-bit binary counter for use in universal asynchronous receiver transmitter (UART) mode. Like the receive counter, the transmit counter counts by the SIOCLK clock, generating transmission clock TxDCLK every 16 clock cycles. Figure 3.10.12 Transmission Clock Generation [7] Transmit control section * In I/O interface mode In SCLK output mode where SC0CR/SC1CR<IOC> is set to "0", the data in the transmit buffer is output bit by bit to the TxD0/1 pin at the rising edge of the shift clock output on the SCLK0/1 pin. In SCLK input mode where SC0CR/SC1CR<IOC> is set to "1", the data in the transmit buffer is output bit by bit to the TxD0/1 pin at the rising or falling edge of SCLK input as determined by the setting of the SC0CR/SC1CR<SCLKS> register. 94C251A-157 2005-05-10 TMP94C251A * In universal asynchronous receiver transmitter (UART) mode When the CPU writes data in the transmit buffer, transmission begins from the next rising edge of the TxDCLK, generating transmission shift clock TxDSFT. Handshake Function The serial channels use the CTS pin to transmit data in units of frames, thus preventing an overrun error. Use SC0MOD/SC1MOD<CTSE> to enable or disable the handshake function. When CTS goes high, data transmission is halted after the completion of the current transmission and is not restarted until CTS returns to low. An INTTX interrupt is generated to request the CPU for the next data to transmit. When the CPU writes the data to the transmit buffer, processing enters standby mode. An RTS pin is not provided, but a handshake function can easily be configured if the receiver sets any port assigned to the RTS function to high (in the receive interrupt routine) after data receive, and requests the transmitter to temporarily halt transmission. Figure 3.10.13 Handshake Function Timing for writing data to transmit buffer CTS Transmission is halted here. 1 13 2 14 15 16 1 2 3 14 15 16 1 2 3 SIOCLK TxDCLK TxD start bit bit 0 Note 1: When the CTS signal rises during transmission, transmission of the next data frame halts after transmission of the current data frame is complete. Note 2: Transmission begins at the first TxDCLK clock falling edge after the CTS signal falls. Figure 3.10.14 CTS (Clear to send) Signal Timing 94C251A-158 2005-05-10 TMP94C251A [8] Transmit buffer Transmit buffer (SC0BUF/SC1BUF) shifts out and transmits the transmit data written by the CPU, beginning with the least significant bit, using the transmission shift clock (TxDSFT) generated by the transmission control section. When all bits are shifted out, the empty transmit buffer generates interrupt INTTX0/INTTX1. [9] Parity control circuit When serial channel control register SC0CR<PE>/SC1CR<PE> is set to "1", data are transmitted and received with parity. However, parity can be added only in 7-bit or 8-bit UART mode. The SC0CR<EVEN>/SC1CR<EVEN> register selects even/odd parity. At transmission, the parity control circuit automatically generates parity according to the data written in the transmit buffer (SC0BUF/SC1BUF). In 7-bit UART mode, the parity bit is stored in SC0BUF<TB7>/SC1BUF<TB7> prior to transmission. In 8-bit UART mode, parity is stored in SC0MOD<TB8>/ SC1MOD<TB8> prior to transmission. Set both <PE> and <EVEN> before writing the transmit data in the transmit buffer. At receiving, data are first shifted into receive buffer 1. The parity control circuit automatically generates parity according to the data transferred to receive buffer 2 (SC0BUF/SC1BUF). In 7-bit UART mode, the generated parity is compared with the received parity in SC0BUF<RB7>/SC1BUF<RB7>. In 8-bit UART mode, the generated parity is compared with the received parity in SC0CR<RB8>/SC1CR<RB8>. If the parities differ, a parity error occurs and the SC0CR<PERR>/SC1CR<PERR> flag is set. [10] Error flags Three error flags improve the reliability of data reception. 1. Overrun error <OERR> When all bits of the next data frame have been received in receive buffer 1 while valid data are stored in receive buffer 2 (SC0BUF/SC1BUF), an overrun error occurs. 2. Parity error <PERR> The parity generated according to the data shifted into receive buffer 2 (SC0BUF/SC1BUF) is compared with the parity bit received from the RxD pin. If the parities are not equal, a parity error occurs. 3. Framing error <FERR> The stop bit of data received is sampled three times around the center. If the majority of the samples are "0", a framing error occurs. 94C251A-159 2005-05-10 TMP94C251A [11] Signal generation timing 1) In UART mode Receive Note: In 9-bit and 8-bit + Parity mode, interrupts coincide with the ninth bit pulse. Thus, when servicing the interrupt, it is necessary to wait for a 1-bit period (to allow the stop bit to be transferred) to allow checking for a framing error. Transmit 2) In I/O interface mode 94C251A-160 2005-05-10 TMP94C251A 3.10.3 Operation (1) Mode 0 (I/O interface mode) This mode is used to increase the number of I/O pins for transmitting or receiving data to an external shift register or other external destinations. This mode consists of SCLK output mode for outputting a synchronous clock (SCLK), and SCLK input mode for inputting a synchronous clock (SCLK) from an external source. Figure 3.10.15 Example of SCLK Output Mode Connection Figure 3.10.16 Example of SCLK Input Mode Connection 94C251A-161 2005-05-10 TMP94C251A [1] Transmission (Example: Ch1) In SCLK output mode, each time the CPU transmits data to the transmit buffer, eight data bits are output from the TxD0/1 pin, and a synchronous clock signal is output from the SCLK0/1 pin. When all data are output, INTES0<ITX0C>/ INTES1<ITX1C> is set, generating interrupt INTTX0/1. Figure 3.10.17 Data Transmission in I/O Interface Mode (SCLK output mode) In SCLK input mode, 8-bit data are output from TxD0/1 pin when SCLK input becomes active while data are written in the transmission buffer by CPU. When all data are output, INTES0<ITX0C>/INTES1<ITX1C> is set, generating interrupt INTTX0/1. Figure 3.10.18 Data Transmission in I/O Interface Mode (SCLK input mode) 94C251A-162 2005-05-10 TMP94C251A [2] Receiving (Example: Ch1) In SCLK output mode, whenever the CPU reads the received data and clears the receive interrupt flag INTES0<IRX0C>/INTES1<IRX1C>, a synchronous clock is output from the SCLK0/1 pin and the next data frame is shifted to receive buffer 1. When an 8-bit data frame has been received, it is transferred to receive buffer 2 (SC0BUF/SC1BUF), and INTES0<IRX0C>/INTES1<IRX1C> is set again, generating interrupt INTRX0/1. Figure 3.10.19 Data Receive in I/O Interface Mode (SCLK output mode) In SCLK input mode, if SCLK is input after the CPU reads the received data and clears the receive interrupt flag INTES0<IRX0C>/INTES1<IRX1C>, the next data frame is shifted into receive buffer 1. When an 8-bit data frame is received, the data are shifted to receive buffer 2 (SC0BUF/SC1BUF) and INTES0<IRX0C>/ INTES1<IRX1C> is set again, generating interrupt INTRX0/1. Figure 3.10.20 Data Receive in I/O Interface Mode (SCLK input mode) Note: To receive data in either SCLK input mode or SCLK output mode, first enable receive (SC0MOD/SC1MOD<RXE> = "1"). 94C251A-163 2005-05-10 TMP94C251A (2) Mode 1 (7-bit UART mode) Setting the serial channel mode register SC0MOD<SM1:0>/SC1MOD<SM1:0> to "01" specifies 7-bit UART mode. A parity bit can be added in this mode. Enable or disable the addition of a parity bit by the serial channel control register SC0CR<PE>/SC1CR<PE> bit. With <PE> set to "1" (Parity enabled), select even or odd parity using SC0CR<EVEN>/SC1CR<EVEN>. Example: When data are transmitted in the following format, the control registers are set as follows. The example shows channel 0. 7 6 5 4 3 2 1 0 PFCR - - - - - - - 1 PFFC - - X - - - X 1 SC0MOD X 0 - 0 0 1 0 1 SC0CR X 1 1 X X X 0 0 Adds even parity. BR0CR 0 X 1 0 1 0 0 0 Sets transmission rate to 2400 bps. T16RUN 1 X - - - - - - Starts prescaler for baud rate generator. INTES0 X 1 0 0 - - - - Enables interrupt INTTX0 and sets interrupt level 4. SC0BUF * * * * * * * * Sets transmit data. Sets PF0 as TxD0 pin. Sets 7-bit UART mode. Note : X; Don't care -; No change (3) Mode 2 (8-bit UART mode) Setting serial channel mode register SC0MOD<SM1:0>/SC1MOD<SM1:0> to "10" selects 8-bit UART mode. A parity bit can be added in this mode. Enable or disable the addition of a parity bit by the serial channel control register SC0CR<PE>/SC1CR<PE> bit. With <PE> set to "1" (parity enabled), select even or odd parity using SC0CR<EVEN>/SC1CR<EVEN>. Example: When data are transmitted in the following format, the control registers are set as follows. The example shows channel 0. 94C251A-164 2005-05-10 TMP94C251A Main routine settings: 7 6 5 4 3 2 1 0 PFCR - - - - - - 0 - SC0MOD - 0 1 0 1 0 0 1 SC0CR X 0 1 X X X 0 0 BR0CR 0 X 0 1 1 0 0 0 Sets transmission rate to 9600 bps. T16RUN 1 X - - - - - - Starts prescaler for baud rate generator. INTES0 - - - - X 1 0 0 Enables interrupt INTRX0 and sets interrupt level 4. Sets PF1 (RxD0) as input pin. Sets 8-bit UART mode and enables reception. Adds odd parity. Interrupt routine processing example: Acc SC0CR AND 00011100 If Acc 0 then ERROR Acc SC0BUF Checks for errors. Reads data received. Note : X; Don't care -; No change (4) Mode 3 (9-bit UART mode) Setting the serial channel mode register SC0MOD<SM1:0>/SC1MOD<SM1:0> to "11" selects 9-bit UART mode. A parity bit cannot be added in this mode. At transmission, the most significant bit (9th bit) is written to <TB8> of the serial channel mode register. At receiving, the most significant bit is saved in <RB8> of the serial channel control register. When data are written to or read from the buffer, the most significant bit is always read or written first, followed by the SC0BUF/SC1BUF register. 94C251A-165 2005-05-10 TMP94C251A 3.11 Analog/Digital Converter TMP94C251A incorporates a high-speed, high-precision 10-bit analog/digital converter (AD converter) with 8-channel analog input. Figure 3.11.1 is a block diagram of the AD converter. The 8-channel analog input pins (AN0 to AN7) are also used as input-only port G pins and can be also used as input ports. Figure 3.11.1 Block Diagram for AD Converter 94C251A-166 2005-05-10 TMP94C251A Figure 3.11.2 AD Control Register 94C251A-167 2005-05-10 TMP94C251A Figure 3.11.3 AD Control Register 94C251A-168 2005-05-10 TMP94C251A Note: The result registers are used both as AN0 and AN4, AN1 and AN5, AN2 and AN6, and AN3 and AN7. They are stored in ADREG04, ADREG15, ADREG26 and ADREG37. Figure 3.11.4 AD Conversion Result Register (ADREG04, ADREG15) 94C251A-169 2005-05-10 TMP94C251A Figure 3.11.5 AD Conversion Result Register (ADREG26, ADREG37) 94C251A-170 2005-05-10 TMP94C251A 3.11.1 Operation (1) Analog reference voltage The high analog reference voltage is applied to the VREFH pin, and the low analog reference voltage is applied to the VREFL pin. The reference voltage between VREFH and VREFL is divided by 1024 (using ladder resistance) and compared with the analog input voltage for AD conversion. The switch between VREFH and VREFL can be turned off by writing 0 to ADMOD2 <VREFON>. When <VREFON> = 0, before the conversion can start, must be written to <VREFON> and a 3 s period must be allowed so that the internal reference voltage can stabilize (Regardless of fc) before 1 is written to ADMOD1 to <ADS>. (2) Analog input channels The analog input channel is selected by ADMOD2<ADCH2:0>. However, the channel which should be selected depends on the operation mode of the AD converter. In Fixed Analog Input mode, one channel is selected out of eight pins, AN0 to AN7, by <ADCH2:0>. In analog input channel scan mode, the number of channels to be scanned is specified by ADMOD2<ADCH2:0>, e.g., AN0 only, AN0AN1, AN0AN1AN2, AN0AN1AN2AN3, AN4AN5, AN4AN5AN6 or AN4AN5AN6AN7. When reset the AD conversion channel register will ADMOD2<ADCH2:0> = 000, so that the AN0 pin is selected. be initialized to The pins which are not used as analog input channels can be used as ordinary input port pins for port G. (3) Starting AD conversion AD conversion starts when 1 is written to the AD conversion register ADMOD1 <ADS>. When conversion starts, the conversion busy flag ADMOD1<ADBF>, which indicates that conversion is in progress, is set to 1. (4) AD conversion mode Both fixed AD conversion channel mode and conversion channel scan mode include two conversion modes; single and repeat conversion mode. In fixed channel repeat mode, conversion of the specified single channel is executed repeatedly. In scan repeat mode, scanning is executed repeatedly. The AD conversion mode is selected by ADMOD1<REPET, SCAN>. 94C251A-171 2005-05-10 TMP94C251A (5) AD conversion speed selection There are four AD conversion speed modes. The selection is made by the ADMOD2 <SPEED1:0> register. When reset, <SPEED1:0> is initialized to 00, selecting 160-state conversion mode (8 s at 20 MHz). (6) AD conversion end and interrupt * AD conversion single mode When AD conversion of the specified channel has finished (in fixed channel conversion mode) or when AD conversion of the last channel has finished (in channel scan mode), ADMOD<EOCF> is set to 1, the ADMOD<ADBF> flag is reset to 0, and the INTAD interrupt is generated. * AD conversion repeat mode For both fixed conversion channel mode and conversion channel scan mode, INTAD should be disabled in Repeat mode. Always set INTE0AD to 000, to disable the interrupt request. Write 0 to ADMOD1<REPET> to terminate Repeat mode. Repeat mode will be exited as soon as the conversion in progress is completed. (7) Storing the AD conversion result The results of AD conversion are stored in the registers ADREG04 to ADREG37 for each channel. The result registers are used as AN0 and AN4, AN1 and AN5, AN2 and AN6 and AN3 and AN7. However, the contents of the registers do not indicate which channel's data has been converted. In repeat mode, the registers are updated as soon as conversion ends. ADREG04 to ADREG37 are read-only registers. (8) Reading the AD conversion result The results of AD conversion are stored in the registers ADREG04 to ADREG37. When the one of the registers ADREG04, ADREG15, ADREG26 or ADREG37 are read, ADMOD1<EOCF> is cleared to 0. 94C251A-172 2005-05-10 TMP94C251A Setting example: [1] When the analog input voltage on the AN3 pin is AD-converted at 160-state speed and the result is transferred to the memory address 0100H by the AD interrupt INTAD routine. [2] When the analog input voltage of the four pins AN4 to AN7 are AD converted at 320-state speed and the channel is set to scan and repeat mode. Note: X: Don't care -: No change 94C251A-173 2005-05-10 TMP94C251A 3.12 8-Bit Voltage Output-type DA Converter TMP94C251A incorporates a 2-channel, 8-bit resolution DA converter with the following features. * String resistor method buffer output-type 8-bit resolution DA converter with two internal channels * Registers DAREG0 and DAREG1 to control the analog voltage output Figure 3.12.1 is a block diagram of the DA converter. Figure 3.12.1 DA Converter Block Diagram 94C251A-174 2005-05-10 TMP94C251A Figure 3.12.2 DA Converter Registers 94C251A-175 2005-05-10 TMP94C251A 3.12.1 Operation When DA converter drive register DADRV<DA1DR, DA0DR> is set to "1", the internal DA converter converts digital values in DA converter registers DAREG1 or DAREG0 to analog values, and outputs these values as voltages from pins DAOUT1 and DAOUT0. Figure 3.12.2 shows the relationship between input data and output voltage. As a reset clears <DA1DR> and <DA0DR> to "0", DAOUT1 and DAOUT0 pins output 0 V. After a reset, DAREG1 and DAREG0 are undefined. To output the relevant analog value using the DA converter, write input data in DAREG1 and DAREG0, then write "1" to the DADRV bit of the channel to be used. Be sure to write data to DAREG1 and DAREG0 first. If, after a reset, DADRV is set to "1" before the input data are written to DAREG1 and DAREG0, DAREG1 and DAREG0 are undefined, and the converter outputs undefined analog values. If the HALT instruction is executed after specifying STOP mode (WDMOD<HALTM1:0> = "01"), the DAOUT output varies with WDMOD<DRVE> and DADRV<DAnDR> as shown in Table 3.12.1. Table 3.12.1 DAOUT Output in STOP Mode Example: Set DAREFH = Vcc, DAREFL = GND. 94C251A-176 2005-05-10 TMP94C251A 3.13 Watchdog Timer (Runaway detection timer) TMP94C251A incorporates a watchdog timer for detecting runaways. The watchdog timer (WDT) returns the CPU to its normal state after the watchdog timer detects the start of a CPU malfunction (Runaway) due to noise, for example. When the watchdog timer detects a runaway, it generates a non-maskable interrupt to notify the CPU of the runaway and outputs a "0" signal from the watchdog timer out pin ( WDTOUT ) to notify any peripheral devices of the runaway. Connecting the watchdog timer output to the RESET pin (within the chip) forces a reset. 3.13.1 Configuration Figure 3.13.1 is a block diagram of the watchdog timer (WDT). Figure 3.13.1 Watchdog Timer Block Diagram 94C251A-177 2005-05-10 TMP94C251A The watchdog timer is a 22-step binary counter, which uses (2/fc) as the input clock. The WDMOD register selects the output of one of four binary counters: 216/fc, 218/fc, 220/fc, or 222/fc. Overflow from the selected counter generates a watchdog timer interrupt and outputs a signal to the watchdog timer out pin. As a result of watchdog timer overflow, the watchdog timer out pin ( WDTOUT ) outputs "0", which can be used as a reset signal for peripheral devices. Clearing the watchdog timer (writing the clear code (4EH) to the WDCR register) sets the WDTOUT pin to "1". In normal mode, the WDOUT pin continually outputs "0" until the clear code is written to the WDCR register. The watchdog timer output can also be connected to the RESET pin internally. In this case, the watchdog timer out pin ( WDTOUT ) outputs "0" for 16/fc to 40/fc (800 ns - 2 s at 20 MHz), resetting itself at the same time. Figure 3.13.2 Normal Mode Figure 3.13.3 Reset Mode 94C251A-178 2005-05-10 TMP94C251A 3.13.2 Control Registers The watchdog timer (WDT) is controlled by three control registers: WDMOD, WDCR and CLKMOD. (1) Watchdog timer mode register WDMOD [1] Setting watchdog timer detection time <WDTP> This 2-bit register is used to set the watchdog timer interrupt time for detecting runaways. At reset, this register is initialized to "00" (WDMOD<WDTP1:0> is set to "00"), setting a detection time of 216/fc [s]. (The number of states is approximately 32,768.) [2] Watchdog timer enable/disable control <WDTE> At reset, the WDMOD<WDTE> bit is initialized to "1", enabling the watchdog timer. Disabling the watchdog timer requires both clearing WDTE to 0 and writing disable code B1H in the WDCR register. This two-step process makes it difficult for a runaway to disable the watchdog timer. To return from the disable state to the enable state, simply set the <WDTE> bit to "1". [3] Connection of watchdog timer output to reset pin <RESCR> This register determines whether or not the watchdog timer resets itself after a runaway is detected. At reset, WDMOD<RESCR> is initialized to 0, and the watchdog timer will therefore not trigger a reset. (2) Watchdog timer control register WDCR This register is used to disable the watchdog timer functions and to clear the binary counter. * Disable control After clearing the WDMOD<WDTE> register to 0, writing the disable code "B1H" to the WDCR register disables the watchdog timer. * Enable control Set WDMOD7<WDTE> to 1. * Clear control Writing clear code 4EH to the WDCR register clears the binary counter and resumes the count. 94C251A-179 2005-05-10 TMP94C251A (3) Clock mode register CLKMOD This register is used to set the warm-up time after the stop mode ends. Writing "0" to the CLKMOD <WARM> bit, 215/fc (Approximately 1.6 ms at 20 MHz) is selected and writing "1", 217/fc (Approximately 6.6 ms at 20 MHz) is selected. Also, the system clock output can be disabled by writing 0 to CLKMOD<CLKOE>. WDMOD (0110H) bit Symbol 7 6 5 4 WDTE WDTP1 WDTP0 - Read/Write After reset Function 3 2 1 0 HALTM1 HALTM0 RESCR DRVE 0 0 0 0 R/W 1 0 WDT control WDT detection time select 1: enable 00: 2 /fc 0 - Reserved Standby mode 00: RUN mode 16 01: STOP mode 18 01: 2 /fc 10: IDLE mode 20 10: 2 /fc 11: Don't care 22 11: 2 /fc 1: Internally 1: Drives connects pins in WDTOUT STOP pin to mode RESET pin. DREVE (See description of STOP mode in the section on standby function.) Controls watchdog timer output. 0 - 1 Connects WDTOUT pin to reset pin. Selects standby mode by HALT instruction 00 RUN mode (halts CPU only) 01 STOP mode (all circuits shut down) 10 IDLE mode (oscillator only in operation) 11 Don't care Selects watchdog timer detection time. 16 00 2 /fc (approximately 3.28 ms @ 20 MHz) 18 01 2 /fc (approximately 13.1 ms @ 20 MHz) 10 2 /fc (approximately 52.4 ms @ 20 MHz) 11 2 /fc (approximately 210 ms @ 20 MHz) 20 22 Controls watchdog timer enable/disable. 0 Disable 1 Enable Figure 3.13.4 Watchdog Timer Mode Register 94C251A-180 2005-05-10 TMP94C251A Figure 3.13.5 Watchdog Timer Control Register Figure 3.13.6 CLOCK Mode Register 94C251A-181 2005-05-10 TMP94C251A 3.13.3 Operation After the detection time set by the WDMOD<WDTP1:0> register is reached, the watchdog timer generates interrupt INTWD and outputs a low signal to the watchdog timer out pin WDTOUT . The binary counter for the watchdog timer must be cleared to 0 by software (Instruction) before INTWD is generated. If the CPU malfunctions (Runaway) due to causes such as noise and does not execute an instruction to clear the binary counter, the binary counter overflows and generates INTWD. The CPU interprets INTWD as a malfunction detection signal, which can be used to start the malfunction recovery program to return the system to normal. A CPU malfunction can also be fixed by connecting the watchdog timer output to a reset pin for peripheral devices. The watchdog timer begins operating immediately on release of the watchdog timer reset. The watchdog timer is reset and halted in IDLE and STOP modes. The watchdog counter continues counting during bus release ( BUSAK = Low). The watchdog timer operates in RUN mode; it can be disabled when RUN mode is entered. Examples: [1] Clear the binary counter. [2] Set the watchdog timer detection time to 218/fc. [3] Disable the watchdog timer. [4] Select IDLE mode. [5] Select STOP mode. (Warm-up time 217/fc) Note: X ; Don't care - ; No change 94C251A-182 2005-05-10 TMP94C251A 3.14 Bus Release Function TMP94C251A has a bus request pin ( BUSRQ also used as P75) for releasing the bus, and a bus acknowledge pin ( BUSAK also used as P76). Set these pins using P7CR and P7FC. 3.14.1 Operation When the bus release request pin ( BUSRQ ) is set to active (Low), TMP94C251A acknowledges a bus release request. When the operand cycle completes, TMP94C251A first sets the address bus (A23 to A0) and the bus control signals ( RD , WRL , WRH , CS0 to CS5 ) simultaneously to high, sets these signals and the output buffer for the data bus (D31 to D0) to off, and sets the BUSAK pin to low, indicating that the bus is released. When using as input port or output port modes, the bus release is not executed for the port, and the output buffer is not turned off. During bus release, TMP94C251A disables all access to the internal I/O registers, although the internal I/O functions are not affected. As the watchdog timer continues to count up during bus release, when using the bus release function, set the runaway detection time in accordance with the bus release time. When inputting "low" into BUSRQ terminal, continue "low" input until BUSAK terminal outputs "low". If the request is released before BUSAK terminal outputs "low", the memory controller may malfunction. 94C251A-183 2005-05-10 TMP94C251A 4. 4.1 Electrical Characteristics Maximum Ratings Note: 4.2 The maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no maximum rating value will ever be exceeded. DC Electrical Characteristics Vcc = 5 V 10%, TA = -20 to 70C X1 = 8 to 10 MHz (Internal operation = 16 to 20 MHz) Note: Typical value are for Ta = 25 C and Vcc = 5 V unless otherwise noted. 94C251A-184 2005-05-10 TMP94C251A 94C251A-185 2005-05-10 TMP94C251A 4.3 AC Electrical Characteristics 4.3.1 Basic Bus Cycle (1) Read cycle No. Symbol Parameter Max 100 125 50 62.5 at 20 MHz at 16 MHz Unit System Clock Period (= T) 50 62.5 3 tCL CLK Low Width 0.5 x T - 15 10 16 ns 4 tCH 5-1 tAD CLK High Width 0.5 x T - 15 10 16 ns A0 to A23 D0 to D31 Input at 0 waits 2.0 x T - 50 50 75 ns 5-2 tAD3 A0 to A23 D0 to D31 Input at 1 wait 3.0 x T - 50 100 138 ns 6-1 tRD RD Fall D0 to D31 Input at 0 waits 1.5 x T - 45 30 49 ns 6-2 tRD3 7-1 tRR RD Fall D0 to D31 Input at 1 wait 2.5 x T - 45 80 111 ns RD Low Width at 0 waits 1.5 x T - 20 55 74 ns 7-2 tRR3 RD Low Width at 1 wait 2.5 x T - 20 105 136 ns A0 to A23 Valid RD Fall 0.5 x T - 20 5 11 ns RD Fall CLK Fall 8 tAR 9 tRK OSC period (X1/X2) Min 1 tOSC 2 tCYC 100 125 ns ns 0.5 x T - 20 5 11 ns 10 tHA A0 to A23 Invalid D0 to D31 Hold 0 0 0 ns 11 tHR 12 tAPR RD Rise D0 to D31 Hold 0 0 0 ns A0 to A23 Valid PORT Input ns 13 tAPH A0 to A23 Valid PORT Hold 14 tTK 15 tKT WAIT Setup Time 2.0 x T - 120 WAIT Hold Time -20 5 2.0 x T 100 125 ns 15 15 15 ns 5 5 5 ns (2) Write cycle No. Symbol Parameter Min Max at 20 MHz at 16 MHz Unit 1 tOSC OSC Period (X1/X2) 100 125 100 2 tCYC 3 tCL System Clock Period (= T) 50 62.5 50 62.5 ns 10 16 ns 4 tCH 0.5 x T - 15 CLK Low Width 125 ns CLK High Width 0.5 x T - 15 10 16 ns 5-1 tDW D0 to D31 Valid WRx Rise at 0 waits 1.25 x T - 35 28 43 ns 5-2 tDW3 6-1 tWW D0 to D31 Valid WRx Rise at 1 wait 2.25 x T - 35 78 106 ns WRx Low Width at 0 waits 1.25 x T - 30 33 48 ns 6-2 tWW3 WRx Low Width at 1 wait 2.25 x T - 30 83 111 ns 0.5 x T - 20 5 11 ns 7 tAW 8 tWK A0 to A23 Valid WRx Fall WRx Fall CLK Fall 0.5 x T - 20 5 11 ns 9 tWA WRx Rise A0 to A23 Hold 0.25 x T - 5 8 11 ns 10 tWD WRx Rise D0 to D31 Hold 0.25 x T - 5 8 11 ns 11 tAPW A0 to A23 Valid PORT Output 12 tTK WAIT Setup Time 13 tKT 14 tRDO WAIT Hold Time RD Rise D0 to D15 Output 2.0 x T + 70 170 195 ns 15 15 15 ns 5 5 5 ns 0.5 x T - 5 20 26 ns AC Condition Output: P0 to P3 (D0 to D31), P4 to P6 (A0 to A23), P70 ( RD ), P71 to P74 ( WRx ) High = 2.0 V, Low = 0.8 V, CL = 50 pF Others High = 2.0 V, Low = 0.8 V, CL = 50 pF Input: P0 to P3 (D0 to D31) High = 2.4 V, Low = 0.45 V Others High = 0.8 Vcc, Low = 0.2 Vcc 94C251A-186 2005-05-10 TMP94C251A (1) Read cycle (0 waits) tOSC X1 tCYC tCL tCH CLK tTK tKT WAIT A0 to A23 tAD CS0 to CS5 tHA tAR tRK tHR RD tRR tRD D0 to D15 Data Input tAPH Port Input (Note) tAPR Port Input Note 1: The phase relation between X1 input signal and the other signals is unsettled. The timing chart above is an example. Note 2: Since the CPU accesses the internal area to read data from a port, the control signals of external pins such as RD and CS are not enabled. Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local Toshiba sales representative. 94C251A-187 2005-05-10 TMP94C251A (2) Write cycle (0 waits) tOSC X1 tCYC tCL tCH CLK tTK tKT WAIT A0 to A23 CS0 to CS5 tAW tWA tWK WRx tWW tDW D0 to D15 tWD Data Output tRDO RD tAPW Port Output (Note) Note 1: The phase relation between X1 input signal and the other signals is unsettled. The timing chart above is an example. Note 2: WRx shows WRL , WRH . Note 3: Since the CPU accesses the internal area to write data to a port, the control signals of external pins such as WR and CS are not enabled. Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local Toshiba sales representative. 94C251A-188 2005-05-10 TMP94C251A (3) Read cycle (1 wait) (4) Write cycle (1 wait) 94C251A-189 2005-05-10 TMP94C251A 4.3.2 Page ROM Read Cycle (1) 3-2-2-2 mode AC Condition Output: P4 to P6 (A0 to A23), P70 ( RD ) High = 2.0 V, Low = 0.8 V, CL = 50 pF CLK, P82 ( CS2 ) High = 2.0 V, Low = 0.8 V, CL = 50 pF Input: P0 to P1 (D0 to D15) High = 2.4 V, Low = 0.45 V (2) Page ROM read cycle (3-2-2-2 mode) 94C251A-190 2005-05-10 TMP94C251A 4.3.3 DRAM Bus Cycle No. Symbol Parameter Min Max 50 62.5 @ 20 MHz@ 16 MHz Unit 1 tCYC System Clock Period (= T) 2 tRC 3 tPC RAS Cycle Time 3.00 x T 150 50 188 62.5 ns ns Page Mode Cycle Time 2.00 x T 100 125 ns 4-1 tRAC RAS Access Time 1.75 x T - 45 43 64 ns 4-2 tRAC4 RAS Access Time @ 4 Clock Access 2.75 x T - 45 93 127 ns 5 tCAC 6-1 tAA CAS Access Time 1.00 x T - 40 10 23 ns Column Address Access Time 1.25 x T - 45 18 33 ns 6-2 tAA2 Column Address Access Time @ Page Mode 2.00 x T - 45 55 80 ns 6-3 tAA4 Column Address Access Time @ 4 Clock Access 2.25 x T - 45 68 96 ns 7 tCPA 8 tOFF CAS Pre-charge Access Time 2.00 x T - 45 55 80 ns Input Data Hold Time 0 0 0 ns 9 tRP RAS Pre-charge Time 1.25 x T - 20 43 58 ns RAS Width 1.75 x T - 20 68 89 ns RAS Width @ 4 Clock Access 2.75 x T - 20 118 152 ns RAS Hold Time 1.00 x T - 20 30 43 ns 12 tRHCP 13-1 tCSH CAS Pre-charge to RAS Hold Time 2.00 x T - 20 80 105 ns CAS Hold Time 1.75 x T - 20 68 89 ns 13-2 tCSH4 CAS Hold Time @ 4 Clock Access 2.75 x T - 20 118 152 ns 30 43 ns 21 30 ns 45 51 ns 10-1 tRAS 10-2 tRAS4 11 tRSH 14 tCAS 15 tRCD CAS Width 1.00 x T - 20 RAS - CAS Delay Time 0.75 x T - 17 16 tRAD RAS - Column Address Delay Time 17 tCRP 18-1 tCP 0.50 x T + 20 CAS - RAS Pre-charge Time 1.25 x T - 20 43 58 ns CAS Pre-charge Time @ Refresh 0.50 x T - 15 10 16 ns CAS Pre-charge Time @ Page Mode 1.00 x T - 20 30 43 ns Row Address Set-up Time 1.25 x T - 40 23 38 ns Row Address Hold Time 0.50 x T - 15 10 16 ns Column Address Set-up Time 0.25 x T - 12 1 4 ns Column Address Set-up Time @ Page Mode 1.00 x T - 20 30 43 ns 22 tCAH Column Address Hold Time 1.00 x T - 20 30 43 ns 23 tAR Column Address Hold Time from RAS 1.75 x T - 20 68 89 ns 24 tRAL 25 tRCS Column Address RAS Read Time 1.25 x T - 20 43 58 ns Read Command Set-up Time 2.00 x T - 40 60 85 ns 26 tRCH Read Command Hold Time from CAS 0.50 x T - 20 5 11 ns 27 tRRH 28 tWCH Read Command Hold Time from RAS 0.50 x T - 20 5 11 ns Write Command Hold Time 1.00 x T - 20 30 43 ns 29 tWCR Write Command Hold Time from RAS 1.75 x T - 20 68 89 ns 30 tWP Write Command Time 1.50 x T - 20 55 74 ns 31 tRWL Write Command RAS Read Time 1.50 x T - 20 55 74 ns 32 tCWL Write Command CAS Read Time 1.50 x T - 20 55 74 ns 33 tDS Data Output Set-up Time 1.50 x T - 30 45 58 ns 18-2 tCP2 19 tASR 20 tRAH 21-1 tASC 21-2 tASC2 94C251A-191 2005-05-10 TMP94C251A AC Condition Output: P0 to P1 (D0 to D15), P4 to P6 (A0 to A23), P70 ( RD ), P71 to P74 ( WRx ) High = 2.0 V, Low = 0.8 V, CL = 50 pF Others High = 2.0 V, Low = 0.8 V, CL = 50 pF Input: P0 to P1 (D0 to D15) High = 2.4 V, Low = 0.45 V Others High = 0.8 Vcc, Low = 0.2 Vcc 94C251A-192 2005-05-10 TMP94C251A (1) DRAM read cycle (3 clock access) 94C251A-193 2005-05-10 TMP94C251A (2) DRAM write cycle (3 clock access) 94C251A-194 2005-05-10 TMP94C251A (3) DRAM read cycle (4 clock access) 94C251A-195 2005-05-10 TMP94C251A (4) DRAM write cycle (4 clock access) 94C251A-196 2005-05-10 TMP94C251A (5) DRAM page mode read cycle (3-2-2-2 mode) 94C251A-197 2005-05-10 TMP94C251A (6) DRAM page mode write cycle (3-2-2-2 mode) 94C251A-198 2005-05-10 TMP94C251A (7) DRAM CAS before RAS interval refresh cycle (3 cycle mode) (8) DRAM CAS before RAS self refresh cycle 94C251A-199 2005-05-10 TMP94C251A 4.4 4.5 Event Counter (TI4, TI5, TI6, TI7, TI8, TI9, TIA, TIB) Serial Channel Timing (1) SCLK input mode (I/O interface mode) (2) SCLK output mode (I/O interface mode) (3) SCLK input mode (UART mode) 94C251A-200 2005-05-10 TMP94C251A 4.6 10-Bit AD Conversion Characteristics Note 1: 1LSB = (VREFH - VREFL)/1024 [V] Note 2: Power supply current ICC from the digital power supply includes the power supply from the AVCC pin. 4.7 8-Bit DA Conversion Characteristics Vcc = 5 V 10%, TA = -20 to 70C (Internal 16 to 20 MHz) Symbol Parameter Condition Min Typ Max DAREFH Analog reference voltage (+) 4.0 VCC DAREFL Analog reference voltage (-) VSS VSS Total error RL = 2.4 K Output voltage range RL = 2.4 K Settling time DAC output mode Note: 4.8 2.0 VSS + 0.5 RL = 2.4 K, CL = 100 pF Output impedance Resistive load VSS + 0.5 DAOUT VCC - 0.5 2.4 Unit V 4.0 LSB VSS - 0.5 V 5 s 5 k RL is the resistance load of the DA converter output in. Interrupt Operation 94C251A-201 2005-05-10 TMP94C251A 4.9 Bus Request/Bus Acknowledge Timing Note: The bus will be released after the WAIT request is inactive, when the BUSRQ is set to "Low" during "wait" cycle. 94C251A-202 2005-05-10 TMP94C251A 5. Table of Special Function Registers (SFRs) (SFR: Special function register) The special function registers (SFRs) include the I/O ports and peripheral control registers allocated to the 1024 byte addresses from 000000H to 0003FFH. (1) I/O port (2) Timer control (3) Watchdog timer control (4) Clock control (5) Serial channel control (6) AD converter control (7) DA converter control (8) Interrupt control (9) Memory control (10) DRAM control Configuration of the table Explanations of symbols R/W: Either read or write is possible R: Only read is possible W: Only write is possible W*: Either read or write is possible (Always read as "1") 1*: Always read as "1" No RMW: Prohibit read-modify-write. (Prohibit RES/SET/TSET/CHG/STCF/ANDCF/ORCF/XORCF etc.) 94C251A-203 2005-05-10 TMP94C251A Table 5.1 I/O Register Address Map 94C251A-204 2005-05-10 TMP94C251A Address Name Address Name Address Name Address Name WDMOD ADREG04L ADREG26L ADMOD1 DAREG0 111h 115h 119h 11Dh 121h 125h 129h 12Dh 131h 135h 139h 13Dh WDCR ADREG04H ADREG26H ADMOD2 DAREG1 112h 116h 11Ah 11Eh 122h 126h 12Ah 12Eh 132h 136h 13Ah 13Eh ADREG15L ADREG37L (reserved) DADRV 113h 117h 11Bh 11Fh 123h 127h 12Bh 12Fh 133h 137h 13Bh 13Fh ADREG15H ADREG37H 141h 145h 149h 14Dh 151h 155h 159h 15Dh 161h 165h B0CSH B1CSH B2CSH B3CSH B4CSH B5CSH DRAM0CRH DRAM1REF 142h 146h 14Ah 14Eh 152h 156h 15Ah 15Eh 162h 166h MAMR0 MAMR1 MAMR2 MAMR3 MAMR4 MAMR5 DRAM1CRL PMEMCR 143h 147h 14Bh 14Fh 153h 157h 15Bh 15Fh 163h 167h MSAR0 MSAR1 MSAR2 MSAR3 MSAR4 MSAR5 DRAM1CRH TLCS-90 type I/O 110h 114h 118h 11Ch 120h 124h 128h 12Ch 130h 134h 138h 13Ch TLCS-900/H2 type 8 bit I/O 140h 144h 148h 14Ch 150h 154h 158h 15Ch 160h 164h B0CSL B1CSL B2CSL B3CSL B4CSL B5CSL DRAMEXT DRAM0CRL DRAM0REF Note 1: TLCS-900/H2 type I/Os are always accessed by two clocks (100 ns at 20 MHz) Note 2: TLCS-90 type I/Os are accessed by five clocks min. (250 ns at 20 MHz) and eight clocks max. (400 ns at 20 MHz) 94C251A-205 2005-05-10 TMP94C251A (1) Input/output ports 94C251A-206 2005-05-10 TMP94C251A 94C251A-207 2005-05-10 TMP94C251A Port B Symbol PB Name PORTB Address 2Ch 7 6 5 4 3 2 1 0 - - - PB4 PB3 PB2 PB1 PB0 1 1 PB1F PB0F R/W - - - 1 1 1 Output - PORTB PBFC - PB4F PB3F PB2F W - Function Register - 2Fh - - (no RMW) 94C251A-208 0 0 0 0 0 0: PORT 0: PORT 1: WE1 1: reserved 1: reserved 1: UCAS1 0: PORT 0: PORT 0: PORT 1: CAS1 LCAS1 2005-05-10 TMP94C251A 94C251A-209 2005-05-10 TMP94C251A 94C251A-210 2005-05-10 TMP94C251A 94C251A-211 2005-05-10 TMP94C251A (2) Timer (no RMW) 94C251A-212 2005-05-10 TMP94C251A (no RMW) (no RMW) 94C251A-213 2005-05-10 TMP94C251A (no RMW) (no RMW) 94C251A-214 2005-05-10 TMP94C251A (no RMW) (no RMW) 94C251A-215 2005-05-10 TMP94C251A (no RMW) (no RMW) 94C251A-216 2005-05-10 TMP94C251A (3) Watchdog timer (4) Clock control 94C251A-217 2005-05-10 TMP94C251A (5) Serial channels Symbol SC0BUF Name Serial Channel 0 Buffer Address 7 6 5 4 3 2 1 0 D0h RB7 TB7 RB6 TB6 RB5 TB5 RB4 TB4 RB3 TB3 RB2 TB2 RB1 TB1 RB0 TB0 FERR SCLK IOC R (Receiving)/W (Transmission) (no RMW) Undefined RB8 EVEN R SC0CR Serial Channel 0 Control Undefi. D1h Receive Data bit 8 PE OERR 0 0 R/W 0 R (Clear 0 after reading) 0: Odd Parity Addition 1: Even 0: Disable Parity PERR 0 R/W 0 1: Error Overrun Parity 0 0 0: SCLK0 0: Baud rate genera. 1: SCLK0 1: SCLK0 pin input Framing 1: Enable TB8 CTSE - RXE SM1 SM0 R/W Undefi. Serial SC0MOD Channel 0 D2h Mode SC1 SC0 0 0 R/W 0 0 Transmission 0: CTS Disable 0: Receive Disable Data bit 8 1: CTS Enable 1: Receive Enable 0 0 Fix to "0" 0 00: I/O interface 00: TO2 Trigger 01: UART 7 bit 01: baudrate generator 10: UART 8 bit 10: Internal clock ph1 11: UART 9 bit 11: External clock SCLK0 - - BR0CK1 BR0CK0 BR0S3 0 - 0 0 0 BR0S2 BR0S1 BR0S0 0 0 0 R/W BR0CR Baud Rate Channel 0 D3h Fix to "0" 00: T0 (4/fc) Set of the Divided frequency 01: T2 (16/fc) 0000: 16 divisions 10: T8 (64/fc) 0001: Don't set 0010 1111: 2 to 15 divisions 11: T32 (256/fc) Serial SC1BUF Channel 1 D4h RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 TB7 TB6 TB5 TB4 TB3 TB2 TB1 TB0 FERR SCLK R (Receiving)/W (Transmission) Buffer Undefined RB8 EVEN R Serial SC1CR Channel 1 Undefi. D5h Control PE OERR R/W 0 Receive Parity Data bit 8 0: Odd 1: Even PERR R (Clear 0 after reading) 0 0 Parity Addition 0: Disable 0 0 1: Error Overrun Parity 0 0 0:SCLK1 0: Baud rate genera. 1: SCLK1 1: SCLK0 Pin input Framing 1: Enable TB8 CTSE - RXE SM1 SM0 R/W Serial SC1MOD Channel 1 Undefi. D6h Mode Transmission 0 1: CTS Enable 0 1: Receive Enable 0 Fix to "0" SC0 0 0 0 0 00: I/O interface 00: TO2 Trigger 01: UART 7 bit 01: baudrate generator 10: UART 8 bit 10: Internal clock ph1 11: External clock SCLK1 11: UART 9 bit - SC1 R/W Data bit 8 - IOC R/W BR1CK1 BR1CK0 BR1S3 BR1S2 BR1S1 BR1S0 0 0 0 R/W BR1CR Baud rate Channel 1 0 D7h Fix to "0" - 0 0 0 00: T0 (4/fc) Set of the Divided frequency 01: T2 (16/fc) 0000: 16 divisions 10: T8 (64/fc) 0001: Don't set 11: T32 (256/fc) 0010 1111: 2 to 15 divisions 94C251A-218 2005-05-10 TMP94C251A (6) AD converter 94C251A-219 2005-05-10 TMP94C251A (7) DA converter 94C251A-220 2005-05-10 TMP94C251A (8) Interrupt control 94C251A-221 2005-05-10 TMP94C251A (no RMW) 94C251A-222 2005-05-10 TMP94C251A (no RMW) 94C251A-223 2005-05-10 TMP94C251A (9) Memory controller 94C251A-224 2005-05-10 TMP94C251A 94C251A-225 2005-05-10 TMP94C251A 94C251A-226 2005-05-10 TMP94C251A (10) DRAM controller 94C251A-227 2005-05-10 TMP94C251A 6. Port Section Equivalent Circuit Diagram * Reading the circuit diagram Basically, the gate symbols written are the same as those used for the standard CMOS logic IC (74HCxx) series. The dedicated signal is described below. STOP: This signal becomes active "1" when the HALT mode setting register is set to the STOP mode (WDMOD<HALTM1:0> = 0, 1) and the CPU executes the HALT instruction. When the drive enable bit WDMOD<DRVE> is set to "1", however STOP remains at "0". * The input protection resistance ranges from several ohms to several hundreds of ohms. P0 (D0 to D7), P1 (D8 to D15), P4 (A0 to A7), P5 (A8 to A15), P6 (A16 to A23), P75 ( BUSRQ ), P86 ( WAIT ), PC, PD, PE, PF6 ( CTS1 , SCLK1), PF5 (RXD1), PF4 (TXD1), PF2 (CTS0, SCLK0), PF1 (RXD0), PF0 (TXD0), PH0 to PH3, PZ P76 ( BUSAK ), P70 to P74, P80 to P85 94C251A-228 2005-05-10 TMP94C251A PG (AN0 to AN7) PH4 (INT0) 94C251A-229 2005-05-10 TMP94C251A RESET X1, X2 VREFH, VREFL 94C251A-230 2005-05-10 TMP94C251A NMI WDTOUT CLK AM0 to AM1, TEST0 to TEST1 94C251A-231 2005-05-10 TMP94C251A 7. Care Points and Restriction (1) Special expression [1] Explanation of a built-in I/O register: Register Symbol<Bit symbol> ex) T8RUN<T0RUN>...Bit T0RUN of Register T8RUN [2] Read-modify-write Instructions An instruction which CPU executes following by one instruction. ex1) SET 3, (T8RUN) ...set bit3 of TRUN ex2) INC 1, (100H) ...increment the data of 100H * The read-modify-write Instructions in the TLCS-900 SET imm, mem , RES imm, mem CHG imm, mem , TSET imm, mem INC imm, mem , DEC RLD A, mem , ADD imm, reg imm, mem (2) Care points [1] Watchdog timer As the watchdog timer is enabled after a reset, disable the watchdog timer when it is not required. Note that during bus release, the I/O block including the watchdog timer, still operate. [2] When releasing the external reset using "built-in clock doubler" until the internal reset is released, the requiring time to stabilize the circuit is automatically set. See "3.1.2 Reset Operation" for details. Also when releasing standby mode in STOP mode using an interrupt until the internal circuit starts the operation, the stable time of the oscillator is automatically input. See 3.4 "Standby Function, (3) STOP mode" for details. [3] Undefined bit in the built-in I/O register When reading the undefined bit in the built-in I/O register, the undefined value is output. Thus, when creating program, it should not be depending on this bit condition. [4] Setting Data Bus When starting up with 8-bit data bus by setting AM0 and AM1 pin after the reset is released, the upper data bus is set to input port, thus, when using the upper data bus, change the port control register of its data bus pin. [5] POP SR instruction Please execute the POP SR instruction during DI condition. [6] Releasing the HALT mode by requesting an interruption Usually, interrupts can release all halts status. However, the interrupts =( NMI and INT0) which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 3 clocks of X1) with IDLE or STOP mode (RUN is not applicable to this case). (In this case, an interrupt request is kept on hold internally) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficulty. The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt. 94C251A-232 2005-05-10 TMP94C251A 8. Package Dimensions P-QFP144-2020-0.50 Unit: mm 94C251A-233 2005-05-10 TMP94C251A 94C251A-234 2005-05-10