1
®ISL54100, ISL54101, ISL54102
TMDS Regenerators with Multiplexers
The ISL54100, ISL54101, ISL54102 are high-performance
TMDS (Transition Minimized Differential Signaling) timing
regenerators and multiplexers. The receiver contains a
programmable equalizer and a clock data recovery (CDR)
function for each of the 3 TMDS pairs in an HDMI or DVI
signal. The TMDS data outputs of the ISL54100 are
regenerated and perfectly aligned to the regenerated
TMDS clock signal, creating an extremely clean, low-jitter
DVI/HDMI signal that can be easily decoded by any TMDS
receiver.
The ISL54100’s design and package footprint supports
many compound configurations. Two ISL54100s can create
a DualLink 4:1 mux, a 4:2 crosspoint, or an 8:1 mux.
Additional ISL54100s can create larger combinations of
these building blocks. The ISL54102 with its 2:1
multiplexing function serves applications with fewer inputs,
while the ISL54101 can be used as a cable extender, to
clean up a noisy/jittery TMDS source, or to provide a very
stable TMDS signal to a marginal DVI or HDMI receiver.
Certified HDMI 1.3a compliant by the HDMI ATC for the
following features: 12 bit Deep Color (1080i/720p
guaranteed, 1080p typical), x.v. Color™, and all HDMI1.3
audio formats and options.
Features
• ISL54100: 4:1 TMDS regenerator and multiplexer
• ISL54101: 1:1 TMDS regenerator
• ISL54102: 2:1 TMDS regenerator and multiplexer
• Clock Data Recovery and Retiming function enables use
as TMDS range extender
• Programmable pre-emphasis on output driver
• Channel activity detect based on input TMDS clock activity
• Symmetrical pinout enables high-performance DualLink,
4:2 crosspoint and 8:1 multiplexing options
• Programmable internal 50Ω, 100Ω, or high-Z termination
• External pins for channel select, activity dete ction
• Stand-alone or I2C software-controlled operation
• Hardware, software, or automatic channel selection
• Pb-free (RoHS compliant)
Applications
• KVM switches
• A/V receivers
• DVI/HDMI extenders
• Televisions/PC monitors/projectors
Block Diagrams
INTERNAL
TERMINATION
4X2
TMDS IN (A)
RECOVERY AND
REGENERATION
4X2
4X2
4X2
TMDS IN (B)
TMDS IN (C)
TMDS IN (D)
TMDS TX TMDS OUT
4X2
ISL54100
INTERNAL
TERMINATION
RECOVERY AND
REGENERATION
4X2
TMDS IN TMDS TX TMDS OUT
4X2
ISL54101
INTERNAL
TERMINATION
4X2
TMDS IN (A) RECOVERY AND
REGENERATION
4X2
TMDS IN (B) TMDS TX TMDS OUT
4X2
ISL54102
4:1 MUX2:1 MUX
Key Features
Data Sheet June 4, 2008
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006-2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
FN6275.5
NOT RECOMMENDED FOR NEW DESIGNS
SEE THE
ISL54100A, ISL54101A AND ISL54102A
2FN6275.5
June 4, 2008
Block Diagram of ISL54100 (ISL54101, ISL54102 identical except for number of chann els)
2TX1
2TX0
2TXC
2TX2
CONFIGURATION AND CONTROL
RES_BIAS
SCL
PD
RESET
CH_A_ACTIVE
CH_B_ACTIVE
CH_C_ACTIVE
CH_D_ACTIVE
AUTO_CH_SEL
CH_SEL_ 0
CH_SEL_1
7
ADDR
SDA
RX0_A
2
2
2
2
RXC_A
RX1_A
RX2_A
RX0_B
2
2
2
RXC_B
RX1_B
RX2_B
RX0_C
2
2
2
2
RXC_C
RX1_C
RX2_C
RX0_D
2
2
2
2
RXC_D
RX1_D
RX2_D
CDR
CH0
CDR
CH1
CDR
CH2
2
PLL
FIFO
RES_TERM
BIAS
GENERATION
TERMINATION
AND
EQUALIZATION
TERMINATION
TERMINATION
AND
EQUALIZATION
TERMINATION
TERMINATION
AND
EQUALIZATION
TERMINATION
TERMINATION
AND
EQUALIZATION
TERMINATION
Ordering Information
PART NUMBER
(Note) NUMBER OF
CHANNELS TEMP. RANGE
(°C) PACKAGE
(Pb-Free) PKG.
DWG. #
ISL54100CQZ 4 0 to +70 128 Ld MQFP MDP0055
ISL54101CQZ 1 0 to +70 128 Ld MQFP MDP0055
ISL54102CQZ 2 0 to +70 128 Ld MQFP MDP0055
NOTE : These Intersil Pb-free plastic packaged products employ special Pb-free material sets , molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
ISL54100, ISL54101, ISL54102
3FN6275.5
June 4, 2008
Absolute Maximum Ratings Thermal Information
Voltage on VD (referenced to GND). . . . . . . . . . . . . . . . . . . . . . 4.0V
Voltage on any Input Pin (referenced to GND) . . . -0.3V to VD+0.3V
Voltage on any “5V To lerant” Input Pin
(referenced to GND). . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V
Current into any Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA
ESD Classification
Human Body Model . . . >4 0 00 V, hi g he r volta g e t e stin g i n p ro g ress
Machine Model. . . . . . . .>200V, higher voltage testing in progress
Thermal Resistance (Typical, Note 1) θJA (°C/W)
MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Maximum Biased Junction Temperature . . . . . . . . . . . . . . . . +125°C
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VD = 3.3V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications S pecifications apply for VD = 3.3V, pixel rate = 165MHz, TA = +25°C, RES_TERM = 1kΩ, RES_BIAS = 3.16kΩ,
TMDS output load = 50Ω, TMDS output termination voltage VTERM = 3.0V unless otherwise noted.
SYMBOL PARAMETER COMMENT MIN
(Note 2) TYP MAX
(Note 2) UNIT
FULL CHANNEL CHARACTERISTICS
fDATA_MAX Maximum Rx Clock Frequency/Pixel Rate (Note 3) 165 225 MHz
fDATA_MIN Minimum Rx Clock Frequency/Pixel Rate 25 MHz
TMDS RECEIVER CHARACTERISTICS
VSENS Minimum Differential Input Sensitivity 50 150 mVP-P
R50 50Ω Termination Resistance 45 50 55 Ω
R100 100Ω Termination Resistance 90 97 110 Ω
CLKDUTY Rx Clock Duty Cycle 20 80 %
TMDS TRANSMITTER CHARACTERISTICS
jTX_CLOCK Total Jitter on Clock Outputs Independent of incoming jitter 32 ps
jTX_DATA Total Jitter on Data Outputs Independent of incoming jitter 52 ps
SKEWINTRA Intra-Pair (+ to -) Differential Skew ±4 ps
SKEWINTER Inter-Pair (channel-to-channel) Skew Added with respect to incoming
inter-pair skew 2UI
tRISE Rise Time into 50Ω Load to 3.3V 20% to 80% 80 240 ps
tFALL Fall Time into 50Ω Load to 3.3V 20% to 80% 80 240 ps
TX VOH Single-Ended High Level Output Voltage VTERM - 10 VTERM + 10 mV
TX VOL Single-Ended Low Level Output Voltage VTERM - 600 VTERM - 400 mV
DIGITAL SCHMITT INPUT CHARACTERISTICS
VIH High Threshold Voltage 2.0 V
VIL High to Low Threshold Voltage 0.8 V
I Input Leakage Current ±10 nA
RPU Internal Pull-Up Resistance SDA and SCL pins 65 kΩ
RPD Internal Pull-Down Resistance AUTO_CH_SEL, CH_SEL_x,
RESET, ADDRx, PD pins 60 kΩ
CIN Input Capacitance 5pF
ISL54100, ISL54101, ISL54102ISL54100, ISL54101, ISL54102
4FN6275.5
June 4, 2008
DIGITAL OUTPUT CHARACTERISTICS
VOH Output HIGH Voltage, IO = 8mA 2.4 V
VOL Output LOW Voltage, IO = -8mA 0.4 V
POWER SUPPLY REQUIREMENTS
VDSupply Voltage 3 3.3 3.6 V
IDSupply Current All available inputs driven by
165Mpixel/s TMDS signals.
Default register settings
ISL54100 387 435 mA
ISL54101 357 405 mA
ISL54102 370 415 mA
IDSupply Current in Power-down Mode All available inputs driven by
165Mpixel/s TMDS signals. 20 26 mA
AC TIMING CHARACTERISTICS (2-WIRE INTERFACE)
fSCL SCL Clock Frequency 0 400 kHz
tAA SCL LOW to SDA Data Out Valid 200 470 ns
tBUF Time the Bus Must be Free Before a New
Transmission Can Start 1.3 µs
tLOW Clock LOW Time 1.3 0.1 µs
tHIGH Clock HIGH Time 0.6 0.2 µs
tSU:STA Start Condition Setup Time 0.6 0.03 µs
tHD:STA Start Condition Hold Time 0.6 0.07 µs
tSU:DAT Data In Setup Time 100 0.03 ns
tHD:DAT Data In Hold Time 0 ns
tSU:STO Stop Condition Setup Time 0.6 µs
tDH Data Output Hold Time 160 ns
NOTE:
2. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. T emperature limits established by characterization
and are not production tested.
3. Operation up to 165MHz is guaranteed. While many parts will typically operate up to 225MHz, operation above 165MHz is not guaranteed.
Electrical Specifications S pecifications apply for VD = 3.3V, pixel rate = 165MHz, TA = +25°C, RES_TERM = 1kΩ, RES_BIAS = 3.16kΩ,
TMDS output load = 50Ω, TMDS output termination voltage VTERM = 3.0V unless otherwise noted.
SYMBOL PARAMETER COMMENT MIN
(Note 2) TYP MAX
(Note 2) UNIT
tSU:STO
tDH
tHIGH
tSU:STA tHD:STA
tHD:DAT
tSU:DAT
SCL
SDA IN
SDA OUT
tFtLOW
tBUF
tAA
tR
FIGURE 1. 2-WIRE INTERFACE TIMING
ISL54100, ISL54101, ISL54102
5FN6275.5
June 4, 2008
ISL54100 Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
37
34
35
36
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
RXC-_D
VD
RXC+_D
VD
VD
GND
CH_D_ACTIVE
CH_SEL_0
RESET
PD
VD_ESD
VD
CH_C_ACTIVE
CH_B_ACTIVE
CH_A_ACTIVE
CH_SEL_1
TX0-
TX0+
TX1-
GND
TX1+
TX2-
GND
TX2+
TXC-
GND
TXC+
ADDR6
RES_BIAS
ADDR5
GND
GND
VD_ESD
RX0+_A
VD
RX0-_A
RX1-_A
RX1+_A
RX2-_A
VD
RX2+_A
VD
VD
RX0+_D
VD
RX0-_D
RX1-_D
RX1+_D
RX2-_D
VD
RX2+_D
VD
VD
VD
GND
GND
VD
GND
RX1-_C
RX1+_C
RX2-_C
RX2+_C
VD
VD
VD
ADDR4
VD
ADDR3
RX0+_C
RX0-_C
GND
VD
RXC-_C
RXC+_C
VD
GND
GND
VD
GND
VD
GND
RXC-_B
VD
RXC+_B
VD
RXC-_A
RXC+_A
VD
GND
VD
RX2+_B
RX2-_B
ADDR2
ADDR1
RX0+_B
RX0-_B
RX1-_B
RX1+_B
VD
VD
GND
VD
VD
ADDR0
VD
GND
GND
VD
RES_TERM
VD
GND
AUTO_CH_SEL
SDA
SCL
TEST
GND
GND
GND
VD
GND
GND
VD
VD
GND
VD
GND
GND
VD
ISL54100, ISL54101, ISL54102
6FN6275.5
June 4, 2008
ISL54101 Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
37
34
35
36
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
NC
VD
NC
VD
VD
GND
NC
NC
RESET
PD
VD_ESD
VD
NC
NC
CH_A_ACTIVE
NC
TX0-
TX0+
TX1-
GND
TX1+
TX2-
GND
TX2+
TXC-
GND
TXC+
ADDR6
RES_BIAS
ADDR5
GND
GND
VD_ESD
RX0+_A
VD
RX0-_A
RX1-_A
RX1+_A
RX2-_A
VD
RX2+_A
VD
VD
NC
VD
NC
NC
NC
NC
VD
NC
VD
VD
VD
GND
GND
VD
GND
NC
NC
NC
NC
VD
VD
VD
ADDR4
VD
ADDR3
NC
NC
GND
VD
NC
NC
VD
GND
GND
VD
GND
VD
GND
NC
VD
NC
VD
RXC-_A
RXC+_A
VD
GND
VD
NC
NC
ADDR2
ADDR1
NC
NC
NC
NC
VD
VD
GND
VD
VD
ADDR0
VD
GND
GND
VD
RES_TERM
VD
GND
GND
SDA
SCL
TEST
GND
GND
GND
VD
GND
GND
VD
VD
GND
VD
GND
GND
VD
ISL54100, ISL54101, ISL54102
7FN6275.5
June 4, 2008
ISL54102 Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
37
34
35
36
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
NC
VD
NC
VD
VD
GND
NC
CH_SEL_0
RESET
PD
VD_ESD
VD
NC
CH_B_ACTIVE
CH_A_ACTIVE
NC
TX0-
TX0+
TX1-
GND
TX1+
TX2-
GND
TX2+
TXC-
GND
TXC+
ADDR6
RES_BIAS
ADDR5
GND
GND
VD_ESD
RX0+_A
VD
RX0-_A
RX1-_A
RX1+_A
RX2-_A
VD
RX2+_A
VD
VD
NC
VD
NC
NC
NC
NC
VD
NC
VD
VD
VD
GND
GND
VD
GND
NC
NC
NC
NC
VD
VD
VD
ADDR4
VD
ADDR3
NC
NC
GND
VD
NC
NC
VD
GND
GND
VD
GND
VD
GND
RXC-_B
VD
RXC+_B
VD
RXC-_A
RXC+_A
VD
GND
VD
RX2+_B
RX2-_B
ADDR2
ADDR1
RX0+_B
RX0-_B
RX1-_B
RX1+_B
VD
VD
GND
VD
VD
ADDR0
VD
GND
GND
VD
RES_TERM
VD
GND
AUTO_CH_SEL
SDA
SCL
TEST
GND
GND
GND
VD
GND
GND
VD
VD
GND
VD
GND
GND
VD
ISL54100, ISL54101, ISL54102
8FN6275.5
June 4, 2008
Pin Desc riptions
SYMBOL DESCRIPTION
RX0-_A, RX0+_A, RX1-_A, RX1+_A,
RX2-_A, RX2+_A TMDS Inputs. Incoming TMDS data signals for Channel A.
RX0-_B, RX0+_B, RX1-_B, RX1+_B,
RX2-_B, RX2+_B TMDS Inputs. Incoming TMDS data signals for Channel B (ISL54100 and ISL54102 only).
RX0-_C, RX0+_C, RX1-_C, RX1+_C,
RX2-_C, RX2+_C TMDS Inputs. Incoming TMDS data signals for Channel C (ISL54100 only).
RX0-_D, RX0+_D, RX1-_D, RX1+_D,
RX2-_D, RX2+_D TMDS Inputs. Incoming TMDS data signals for Channel D (ISL54100 only).
RXC-_A, RXC+_A, RXC-_B, RXC+_B,
RXC-_C, RXC+_C, RXC-_D, RXC+_D TMDS Inputs. Incoming TMDS clock signals for Channels A, B, C and D (ISL54100), Channels A and B
(ISL54102), or Channel A (ISL54101).
TX0-, TX0+, TX1-, TX1+, TX1-, TX1+ TMDS Outputs. TMDS output data for selected channel.
TXC-, TXC+ TMDS Outputs. TMDS output clock for selected channel.
SCL Digital input, 5V tolerant, 500mV hysteresis. Serial data clock for 2-wire interface.
Note: Internal 65kΩ pull-up to VD.
SDA Bidirectional Digital I/O, open drain, 5V tolerant. Serial data I/O for 2-wire interface.
Note: Internal 65kΩ pull-up to VD.
ADDR[6:0] Digital inputs, 5V tolerant. 7-Bit address for serial interface.
Note: Internal 60kΩ pull-down to GND.
CH_SEL_0, CH_SEL_1 Digital I/Os, 3.3V. Channel select inputs (for stand-alone operation), selected channel outputs (for
software configured or auto channel select modes).
CH_SEL_1 should be left unconnected for the ISL54102.
CH_SEL_0 and CH_SEL_1 should both be left unconnected for the ISL54101.
Note: The state of these outputs becomes random when the chip is in the Power-down mode.
AUTO_CH_SEL Digital Input. Pull high to have the mux automatically select the highest channel (A is highest, D is lowest)
with an active TMDS clock. Low is manual channel select.
CHA_Active, CHB_Active,
CHC_Active, CHD_Active Digital Outputs, 3.3V. Output goes high when there is an active TMDS clock on that channel's input. Used
for activity detect in a stand-alone configuration.
CHC_Active and CHD_Active are NC (do Not Connect) for the ISL54102.
CHB_Active, CHC_Active and CHD_Active are NC (do Not Connect) for the ISL54101.
RES_BIAS Tie to GND through a 3.16k external resistor. Sets up internal bias currents.
RES_TERM T ie to VD through a 1.0k 1% external resistor. During calibration, the termination resistor closest in value
to RES_TERM/20 (= 50Ω) is selected.
PD Digital Input, 3.3V. PD = Power-down. Pull high to put the ISL5410x in a minimum power consumption
mode.
Note: To ensure proper operation, this pin must be held low during power-up. It may be taken high 100ms
after the power supplies have settled to 3.3V ±10%.
When exiting Power-down, a termination resistor Recalibration cycle must be run to re-trim the
termination resistors (see register 0x03[7]).
Note: Internal 60kΩ pull-down to GND.
RESET Digital Input, 3.3V. Pull high then low to reset the mux. Tie to GND in final application.
Note: Internal 60k pull-down to GND.
TEST Digital Input. Used for production testing only. Tie to GND in final application. This pin has an internal
pulldown to GND, so it is also acceptable to leave this pin floating.
VDPower supply. Connect to a 3.3V supply and bypass each pin to GND with 0.1µF.
VD_ESD Power supply for ESD protection diodes. Connect one of these pins (pin 74 or 95) to the 3.3V VD supply
rail with a low VF (0.4V or lower) Schottky diode, with the cathode connected to VD_ESD and the anode
connected to VD. Bypass each pin to GND with 0.1µF.
GND Ground return for VD.
ISL54100, ISL54101, ISL54102
9FN6275.5
June 4, 2008
Register Listing
ADDRESS REGISTER (DEFAULT VALUE) BIT(S) FUNCTION NAME DESCRIPTION
0x00 Device ID (read only) 3:0 Device Revision 1 = initial silicon, 2 = second revision, etc.
7:4 Device ID 3 = ISL5410x
0x01 Channel Activity Detect (read only) 0 Channel A Active 0: TMDS clock not present on Channel A
1: TMDS clock detected on Channel A
1 Channel B Active 0: TMDS clock not present on Channel B
1: TMDS clock detected on Channel B
2 Channel C Active 0: TMDS clock not present on Channel C
1: TMDS clock detected on Channel C
3 Channel D Active 0: TMDS clock not present on Channel D
1: TMDS clock detected on Channel D
0x02 Channel Selection (0x0C) 1:0 Channel Select Selects the input channel for the mux. These 2 bits are Read
Only if Auto Channel Select is enabled.
0: Channel A selected
1: Channel B selected
2: Channel C selected
3: Channel D selected
2 Auto Channel Select 0: Manual Channel Select (using bits 0 and 1).
1: Auto Channel Select. Mux always selects the active
channel with the highest priority. A = 1st (highest), B = 2nd,
C = 3rd, D = 4th (lowest) priority.
An active channel is a channel that has clock activity on its
TMDS clock lines. If no channels are active, the A channel
is selected. (default)
3 Hardware Channel
Select 0: Software channel selection (using bit s 0-2 of this register)
1: Hardware channel selection (using “Auto Channel Select”
and “CH Sel 0/1” external pins) (default)
4 Reset Full chip reset. Write a 1 to reset. Will set itself to 0 when
reset is complete.
5 Power-down 0: Normal Operation
1: Puts the chip in a minimal power consumption mode,
turning off all TMDS outputs and open-circuiting all TMDS
inputs.
This bit is OR'ed with the Power-down input pin. If either is
set, the chip will enter power-down. Serial
I/O stays operational in PD mode.
Note: When exiting Power-down, a termination resistor
Recalibration cycle must be run to re-trim the termination
resistors (see register 0x03[7]).
ISL54100, ISL54101, ISL54102
10 FN6275.5
June 4, 2008
0x03 Input Control (0x12)
Recommended default: 0x62 0 Tri-state Unselected
Clock Inputs 0: Normal Operation
1: Termination of unselected TMDS clock inputs is tri-stated
to save power . Setting this bit will disable the activity detect
function. This bit should not be set in crosspoint
configuration because it will make the clock termination
resistance variable depending on which 2 inputs are
selected. In general, this bit should always be set to 0.
1 Tri-state Unselected
Data Inputs 0: Normal Operation
1: Unselected Data inputs are tri-st ated to save power . This
bit should not be set in crosspoint configuration because it
will make the data input termination resistance variable
depending on which 2 inputs are selected. (default)
2 Tri-state Selected
Clock Inputs 0: Selected Clock inputs are terminated into
50Ω/100Ω.
1: Selected Clock inputs are tri-stated (to allow chip to
operate in parallel with another TMDS receiver with fixed
50Ω termination)
3 Tri-state Selected
Data Inputs 0: Selected Data inputs are terminated into
50Ω/100Ω.
1: Selected Data inputs are tri-stated (to allow chip to
operate in parallel with another TMDS receiver with fixed
50Ω termination)
4 Activity Detect Mode 0: AC Activity. Activity detection is based on the presence of
AC activity on TMDS clock inputs. This setting (along with a
hysteresis of 20mV enabled) provides reliable activity
detection. (recommended setting)
1: Common Mode Voltage. If the common mode voltage is
above ~3.05V, the input is considered inactive. This method
has been found to be unreliable with small signal swings and
should not be used. This setting is the silicon default but
should be changed in software for more reliable activity
detection.
5 Clock Rx Hysteresis Enables hysteresis for the clock inputs to prevent false clock
detection when both inputs are high. Data inputs do not get
hysteresis.
0: TMDS input hysteresis disabled
1: TMDS input hysteresis enabled. Eliminates false activity
detects on unconnected channels. (recommended setting)
6 Clock Rx Hysteresis
Magnitude Controls the amount of hysteresis in the clock inputs.
0: 10mV
1: 20mV (recommended setting)
7 Recalibrate 0: Normal Operation
1: Recalibrates termination resistance. To recalibrate, take
this bit high, wait at least 1ms, then take this bit low.
Calibration is automatically done after power-on, but
performing a recalibration after the supply voltage and
temperature have stabilized may result in termination
resistances closer to the desired 50Ω.
Register Listing (Continued)
ADDRESS REGISTER (DEFAULT VALUE) BIT(S) FUNCTION NAME DESCRIPTION
ISL54100, ISL54101, ISL54102
11 FN6275.5
June 4, 2008
0x04 Termination Control (0x00) 0 Data Termination A 0: Channel A TMDS Data inputs terminated into 50Ω
(normal operation)
1: Channel A TMDS Data inputs terminated into 100Ω (for
paralleled inputs)
1 Data Termination B 0: Channel B TMDS Data inputs terminated into 50Ω
(normal operation)
1: Channel B TMDS Data inputs terminated into 100Ω (for
paralleled inputs)
2 Data Termination C 0: Channel C TMDS Data inputs terminated into 50Ω
(normal operation)
1: Channel C TMDS Data inputs terminated into 100Ω (for
paralleled inputs)
3 Data Termination D 0: Channel D TMDS Data inputs terminated into 50Ω
(normal operation)
1: Channel D TMDS Data inputs terminated into 100Ω (for
paralleled inputs)
4 Clk Termination A 0: Channel A TMDS Clock inputs terminated into 50Ω
(normal operation)
1: Channel A TMDS Clock inputs terminated into 100Ω (for
paralleled inputs)
5 Clk Termination B 0: Channel B TMDS Clock inputs terminated into 50Ω
(normal operation)
1: Channel B TMDS Clock inputs terminated into 100Ω (for
paralleled inputs)
6 Clk Termination C 0: Channel C TMDS Clock inputs terminated into 50Ω
(normal operation)
1: Channel C TMDS Clock inputs terminated into 100Ω (for
paralleled inputs)
7 Clk Termination D 0: Channel D TMDS Data inputs terminated into 50Ω
(normal operation)
1: Channel D TMDS Data inputs terminated into 100Ω (for
paralleled inputs)
0x05 Output Options (0x00) 0 Tri-state Clock
Outputs 0: Normal Operation
1: Clock outputs tri-stated (allows another chip to drive the
output clock pins)
1 Tri-state Data
Outputs 0: Normal Operation
1: Data outputs tri-stated (allows another chip to drive the
output data pins)
2 Invert Output
Polarity 0: Normal Operation
1: The polarity of the TMDS data outputs is inverted
(+ becomes -, - becomes +). TMDS clock unchanged.
3 Reverse Output
Order 0: Normal Operation
1: CH0 data is output on CH2 and CH2 data is output on
CH0. No change to CH1.
0x06 Data Output Drive (0x00) 3:0 Transmit Current Transmit Drive Current for data signals, adjustable in
0.125mA steps. Clock current is fixed at 10mA.
0x0: 10mA
0x8: 11mA
0xF: 11.875mA
7:4 Transmit
Pre-emphasis Drive boost (in 0.125mA steps) added during first half of
each bit period for data signals. Clock signals do not have
pre-emphasis.
0x0: 0mA
0x8: 1mA
0xF: 1.875mA
Register Listing (Continued)
ADDRESS REGISTER (DEFAULT VALUE) BIT(S) FUNCTION NAME DESCRIPTION
ISL54100, ISL54101, ISL54102
12 FN6275.5
June 4, 2008
0x07 Equalization 1 (0xCC) 3:0 Channel A Equalizer
Gain Boost (dB) = 1dB + <gain value> * 0.8dB
0x0: 1dB boost at 800MHz
0xC: 10.6dB boost at 800MHz (default)
0xF: 13dB boost at 800MHz
7:4 Channel B Equalizer
Gain
0x08 Equalization 2 (0xCC) 3:0 Channel C Equalizer
Gain Boost (dB) = 1dB + <gain value> * 0.8dB
0x0: 1dB boost at 800MHz
0xC: 10.6dB boost at 800MHz (default)
0xF: 13dB boost at 800MHz
7:4 Channel D Equalizer
Gain
0x09 Test Pattern Generator (0x00) 1:0 Generator Mode When a 25MHz to 165MHz clock is applied to the selected
channel’s clock input, this function will output a PRBS7
pattern on the TX pins.
0: Normal operation (test patterns disabled)
1: PRBS7 pattern
2: Low frequency toggle (0000011111…)
3: High frequency toggle (1010101010…)
Note: When switching from the high frequency toggle
pattern to the low frequency toggle pattern, you must first
select normal operation.
2 Enable PRBS7 Error
Counter Enables PRBS7 error counter in registers 0x0A to 0x0C.
0: Disable PRBS7 Error Counter
1: Enable PRBS7 Error Counter
0x0A PRBS7 Error Counter Link 0 (read only) 7:0 PRBS7 Error
Counter Link 0 PRBS7 Error Counter of Link 0. Saturates at 0xFF. Reading
this register clears this register at end of read
0x0B PRBS7 Error Counter Link 1 (read only) 7:0 PRBS7 Error
Counter Link 1 PRBS7 Error Counter of Link 1. Saturates at 0xFF. Reading
this register clears this register at end of read
0x0C PRBS7 Error Counter Link 2 (read only) 7:0 PRBS7 Error
Counter Link 2 PRBS7 Error Counter of Link 2. Saturates at 0xFF. Reading
this register clears this register at end of read
0x10 PLL Bandwidth (0x10)
Recommended default: 0x12 1:0 PLL Bandwidth Selects between 4 PLL bandwidth settings
0: 4MHz (silicon default)
1: 2MHz
2: 1MHz (recommended default)
3: 500kHz
1MHz provides slightly better performance with high jitter/
high noise signals.
7:2 Reserved Keep set to 000100 binary.
Register Listing (Continued)
ADDRESS REGISTER (DEFAULT VALUE) BIT(S) FUNCTION NAME DESCRIPTION
ISL54100, ISL54101, ISL54102
13 FN6275.5
June 4, 2008
Application Information
The ISL54100, ISL54101, and ISL54102 are TMDS
regenerators, locking to the incoming DVI or HDMI signal
with triple Clock Data Recovery units (CDRs) and a Phase
Locked Loop (PLL). The PLL generates a low jitter pixel
clock from the incoming TMDS clock. The TMDS data
signals are equalized, sliced by the CDR, re-al igned to the
PLL clock, and sent out the TMDS outputs. The ISL54100
and ISL54102 also include an input multiplexer.
Multiplexer Operation
The ISL54100 and ISL54102 have 4:1 and 2:1 (respectively)
input multiplexers. After power-up or a hardware reset, the
IC defaults to hardware channel selection, using the
AUTO_CH_SEL and CH_SEL_x pins. If AUTO_CH_SEL is
pulled high, the highest priority channel with an active TMDS
clock will be automatically selected (Channel A = highest
priority, B = second highest priority, C = second lowest, and
D = lowest priority). If, for example, a DVD player is attached
to Channel A, a set-top-box (STB) is attached to Channel B,
and a video game is attached to Channel C, the DVD player
will have the highest priority, overriding the STB and the
video game whenever the DVD player is transmitting a
TMDS clock. Likewise, the STB will have higher priority than
the video game. Table 1 shows the auto channel selecti on
priority matrix.
In the auto channel select mode, the CH_SEL_x pins are
outputs indicating the selected channels. Note that in the
Power-down mode, the state of the CH_SEL_x pins is
undetermined/random.
If manual channel selectio n is desired, the AUTO_CH_SEL
pin should be tied to ground, and the CH_SEL_x pins are
inputs, selecting the desired channel.
The input multiplexer can also be contro lled by software via
the I2C interface. Software control is initiated by writing a 0 to
the Hardware Channel Select bit (bit 3 of register 0x02). In
this case, the Auto Channel Select bit (bit 2 of register 0x02)
and the Channel Select bits (bits 0 and 1 of register 0x02)
perform the same functions as the external pins described
above. In the Auto Channel Select mode, the Channel
Select bits are read only, indicating the currently selected
channel. In the Manual Channel Select mode, the Channel
Select bits are read/write, and used to select the channel.
Activity Detection
A channel is considered active using o ne of two methods. The
original default activi ty detect me thod (reg ister 0x03b4 = 1) is
to measure the common mode of the TMDS clock input for
each channel. If the common mode is 3.3V, it indicates that
there is nothing connected to that input, or that whateve r is
connected is turned off (inacti ve). This has been found to be
relatively unreliable, parti cularl y with weak signal s.
The preferred method of activity detection is looking for an
active AC signal on the TMDS clock input for that channel
(register 0x03b 4 = 1). This is more robust, however
disconnected inputs will cause both inputs to the differential
receiver to be the same level - 3.3V. If the offset error of the
differential TMDS receiver is very small, the receiver can not
resolve a 1 or a 0 and will randomly switch between states,
which may be detected as an active clock. Register 0x03 bit s
5 a nd 6 allow a 10mV or 20mV offset to be added to the input
stage of the clock inputs, eliminating this problem. This offset
will slightly reduce the sensitivity of TMDS receiver for the
clock lines, but since the clock signals are much lower
frequency than the data, they will not be nearly as
attenuated, so this is not a problem in practice.
Again, using the AC activity detecti on method (register
0x03b4 = 0) is recommended.
Rx Equalization
Registers 0x07 and 0x08 control the amount of equalization
applied to the TMDS inputs, with 4 bits of control for each
channel. The equalization range available is from a minimum
of 1dB boost to a maximum of 13dB at 800MHz, in 0.8dB
increments. Ideally, the equalizatio n is adjusted in the final
application to provide optimal performance with the specific
DVI/HDMI transmitter and cable used. In gene ral, the
amount of equalization required is proportional to the cable
length. If the equalization must be fixed (can not be adjusted
in the final application), an equalization setting of 0xA works
well with short cables as well as medium to longer cables.
Tx Pre-emphasis
The transmit pre-emphasis function sinks additional current
during the first bit after every transition, increasing the slew
rate for a given capacitance, and helping to maintain the
slew rate when using longer/higher capacitance cables.
Pre-emphasi s is con t rol l ed by register 0x 06 bi ts 7:4, an d
ranges from a minimum of 0mA (no pre-emphasis) to
1.875mA (max pre-emphasis).
PLL Bandwidth
The 2-bit PLL Bandwidth register controls the loop
bandwidth of the PLL used to recover the incoming clock
signal. The default 4MHz setting works well in most
applications, however a lower bandwidth of 1MHz has
proven to work just as well with good TMDS sources and
slightly better with marginal sources.
T ABLE 1. AUTO CHANNEL SELECTION PRIORITIES
(ISL54102 OPTIONS IN BLUE)
CHANNEL A CHANNEL B CHANNEL C CHANNEL D OUTPUT
Inactive Inactive Inactive Inactive Inactive
Active Don’t Care Don’t Care Don’t Care Channel A
Inactive Active Don’t Care Don’t Care Channel B
Inactive Inactive Active Don’t Care Channel C
Inactive Inactive Inactive Active Channel D
ISL54100, ISL54101, ISL54102
14 FN6275.5
June 4, 2008
Power-down
The chip can be placed in a Power-down mode when not in
use to conserve power. Setting the Power-down bit (register
0x02 bit 5) to a 1 or pulling the PD input pin high places the
chip in a minimal power consumption mode, turning off all
TMDS outputs and disconnecting all TMDS inputs. Serial I/O
stays operational in PD mode. Note that the PD pin must be
low during power-on in order to initialize the I2C interface.
Note: When exiting Power-down, a termination resistor
Recalibration cycle must be run to re-trim the termination
resistors (see register 0x03[7]).
Power Dissipation and Supply Current
Due to the large number of TMDS inputs and outputs, a
significant amount of current flows into and out of the
SL5410x. This makes calculating the total power dissipation
of the ISL5410x slightly more complicated than simply
multiplying the supply current by the supply voltage.
The supply current measureme nt includes the current
flowing through all the active TMDS termination resistors.
This current is supplied by the ISL54100's VD supplies, but
only 15% of it (0.5V*10mA per TMDS pair) is dissipated as
power inside the ISL54100. The majority of the power (2.8V
* 10mA per active TMDS pair) is dissipated in the TMDS
transmitter driving the ISL5410 0. Likewise, the ISL54100
dissipates 85% of the power generated by the current from
the external receiver attached to the ISL54100's Tx pins.
Any worst-case on-chip power dissipation calculation needs
to account for this.
Inter-Pair (Channel-to-Channel) Skew
The read pointers for Channel 0, 1, and 2 of the FIFO that
follows the CDR all have the same clock, so all 3 channels
transition within a few picoseconds of each other - there is
essentially no skew between the transitions of the three
channels.
However the FIFO read pointers may be positioned up to 2
bits apart relative to each other, introducing a random, fixed
channel-to-channel skew of skew of 1 or (much less
frequently) 2 bits. The random skew is introduced whenever
there is a discontinuity in the input signal (typically a video
mode change or a new mux channel selection). After the
CDRs and PLL lock, the skew is fixed until the next
discontinuity . This adds up to 2 bits of skew in addition to any
incoming skew, as shown in the following examples.
Figure 2 shows an input (the top three signals) with
essentially no skew. After the ISL5410x locks on to the
signal, there may be 1 bit of skew on the output, as shown in
Figure 2.
When there is pre-existing skew on the input, the ISL5410x
can add up to 2 bits to the channel-to-channel skew. In the
example in Figure 3, the incoming red channel has 2.3 bits of
skew relative to the incoming green and blue. The FIFO’s
quantization (worst case) increases the total skew to 4.0 bits.
While increasing skew is not desirable, DVI and HDMI
receivers are re qu i red to have a minimum of 6 bits of inter -
pair skew tolerance, so the addition of 2 bits of skew is only a
problem with the most pathological cables and transmitters.
It does, however, limit the number of ISL5410xs that can be
put in series (although statistically it is unlikely that all the
skews would line up in a worst-case configuration).
FIGURE 2. MAXIMUM ADDITIONAL INTERCHANNEL SKEW
FOR INPUTS WITH NO OR LITTLE SKEW
Bit 4Bit 5Bit 6Bit 7 Bit 0Bit 1Bit 2Bit 3
B
Bit 8Bit 9
Bit 4Bit 5Bit 6Bit 7 Bit 0Bit 1Bit 2Bit 3
B
Bit 8Bit 9
Bit 4Bit 5Bit 6Bit 7 Bit 0Bit 1Bit 2Bit 3
B
Bit 8Bit 9
Bit 4Bit 5Bit 6 Bit 0Bit 1Bit 2Bit 3
B
Bit 7Bit 8Bit 9
Bit 4Bit 5Bit 6Bit 7 Bit 0Bit 1Bit 2Bit 3
B
Bit 8Bit 9
Bit 4Bit 5Bit 6Bit 7 Bit 0Bit 1Bit 2Bit 3
B
Bit 8Bit 9
INPUT SKEW
(none, in this
example)
OUTPUT SKEW
(1 bit – 615ps at
162.5Mpixels/s)
Bit 4Bit 5 Bit 0Bit 1Bit 2Bit 3 Bit 7Bit 8Bit 9
Bit 4Bit 5Bit 6Bit 7 Bit 0Bit 1Bit 2Bit 3
B
Bit 8Bit 9
Bit 4Bit 5Bit 6Bit 7 Bit 0Bit 1Bit 2Bit 3
B
Bit 8Bit 9
Bit 4 Bit 0Bit 1Bit 2Bit 3 Bit 6Bit 7
Bit 8
Bit 9
Bit 4Bit 5Bit 6Bit 7 Bit 0Bit 1Bit 2Bit 3
B
Bit 8Bit 9
Bit 4Bit 5Bit 6Bit 7 Bit 0Bit 1Bit 2Bit 3
B
Bit 9
INPUT SKEW
(2.3 bits/1.4ns
in this ex ample)
OUTPUT SKEW
(4 bits/2.5ns a t
162.5Mpixels/s)
Bit Bit 6
B
Bit 5
Bit 8
FIGURE 3. MAXIMUM ADDITIONAL INTERCHANNEL SKEW
FOR INPUTS WITH MODERATE TO LARGE
SKEW
ISL54100, ISL54101, ISL54102
15 FN6275.5
June 4, 2008
Typical Performance
Setup A (Figure 4) was used to capture th e TMD S eye
diagrams shown in Figure 5 and Figure 6:
The 162.5Mpixel/s (UXGA 60Hz) DVI output of the Chroma
2326 was terminated into a TPA2 Plug adapter and
measured with a LeCroy differential probe and 6MHz SDA
using the LeCroy’s software clock recovery. As Figure 5
shows, the amplitude of the TMDS signal is slightly low, but
the eye is otherwise acceptable.
Next, a 15m DualLink DVI cable was attached and
terminated into a female TPA2 adapter and the eye captured
in Figure 6.
The eye is not meeting the minimum requirements of either
the HDMI or DVI standards and the Dell Monitor is unable to
recover the data and display an image.
Setup B inserts an ISL54100 and an additional 15m cable
between the pattern generator and the monitor:
Given the input signal shown in Figure 6, the ISL54100’s
TMDS output signal (Figure 8) is extremely clean. The
output is an improvement over the original signal coming
from the pattern generator in both amplitude and jitter.
The cleaner signa l generated at the outp ut of the ISL54100
results in an improved eye at the end of another 15m cable
(Figure 9). The eye is open enough that the Dell 2000FP can
now display a UXGA image with no visible sparkle or other
artifacts.
CHROMA 2326
VIDEO PATTERN
GENERATOR @
UXGA 60Hz
DELL 2000FP
UXGA MONITOR
15m DUAL- L I NK
DVI CABLE
FIGURE 4. TEST SETUP A
FIGURE 5 FIGURE 6
FIGURE 5. EYE DIAGRAM A T OUTPUT OF CHRO MA
GENERATOR
FIGURE 6. CHROMA EYE DIAGRAM AFTER 15m CABLE
CHROMA 2326
VIDEO PATTERN
GENERATOR
15m DUAL-LINK
DVI CABLE
DELL 2000FP
UXGA MONITOR
ISL54100 15m DUAL-LINK
DVI CABLE
FIGURE 7. TEST SETUP B
FIGURE 8
FIGURE 5
FIGURE 6 FIGURE 9
FIGURE 8. EYE DIAGRAM AT OUTPUT OF ISL54100
ISL54100, ISL54101, ISL54102
16 FN6275.5
June 4, 2008
Tx Loading Considerations
When the ISL54100 is powered-up and its Tx outputs are
disabled, via either the PD (power down) pin, the
power-down re gi ster bit (register 0x 02 [ 5] ) , or th e tri -state
outputs bits (register 0x05[1:0]), the Tx pins are high
impedance. In this state they will draw no current from the
Rx pins of any TMDS receiver they may be connected to.
However if power to the ISL54100 is removed, the Tx pins
are no longer high-impedance. Figure 10 shows the relevant
equivalent circuit, including the internal ESD protection
diodes. For simplicity, only one of the eight T x outputs, ESD
protection diodes, and Rx termination resistors are shown.
When VD to the ISL54100 drops below ~2.7V and power is
applied to the external TMDS receiver, ESD protection
diodes inside the ISL54100 can become forward-biased,
drawing current from the external TMDS receiver it is
attached to.
This is non-ideal and will cause the ISL5410x to fail HDMI
Compliance Test 7-3 (“VOFF”). VOFF is the voltage across
each 50Ω RxN resistor when the power is removed from the
device containing the ISL54100.
Modifying the PCB layout per Figure 11 to add a Schottky
diode between the VD power net and the VD_ESD pins,
eliminates current flow from the ESD bus into VD. This
reduces the amount of current drawn from the Tx supply, but
there is still some circuitry attached to the internal ESD bus
that will sink some current. So the current drawn from Rx will
be lower than if the diode were not there (reducing the VOFF
magnitude), but still not low enough to pass Test 7-3.
Intersil is currently sampling the ISL54100A, the ISL54101A,
and the ISL54102A, all of which are fully compliant with Test
7-3 when applied using the circuit shown in Figure 1 1. These
“A” versions are 100% drop-in compatible with the original
version with the sole exception of the CH_SEL_0 and
CH_SEL_1 pins, which are bidirectional on the original
version but beco me inpu ts only on th e A versi o n.
Using the new version in a layout designed for the original
version (Figure 10) will result in the same behavior as the
original version (unless you are using the CH_SEL pins as
outputs). See Table 2 for the full matrix.
Intersil recommends adding the Schottky circuit to all
designs to reduce Rx current drain in systems using the
original version and completely eliminate it in systems using
the “A” version.
PCB Layout Recommendations
Because of the high speed of the TMDS signals, careful
PCB layout is critical to maximize performance. The
following guidelines should be adhered to as closely as
possible:
• All TMDS pair traces should have a characteristic
impedance of 50Ω with respect to the power/ground
FIGURE 9. ISL54100 EYE DIAGRAM AFTER 15m CABLE
FIGURE 10. ISL5410x ESD PROTECTION DIODES
ISL5410x
VD
VD_ESD (74 , 9 5)
3.3VTX
TxN
Tx
3.3VRX
50RxN
TABLE 2. VERSION/LAYOUT MATRIX
VERSION Figure 10 Figure 11
ISL5410x Fails 7-3,
CH_SEL pins are bidirectional Fails 7-3 (not as badly)
CH_SEL pins are bidirect ional
ISL5410xA Fails 7-3,
CH_SEL pins are input only Passes 7-3,
CH_SEL pins are input only
FIGURE 11. SCHOTTKY DIODE MODIFICATION
ISL5410x
VD
VD_ESD (74 , 9 5)
3.3VTX
TxN
Tx
3.3VRX
50RxN
D1
C1
0.1μF
ISL54100, ISL54101, ISL54102
17 FN6275.5
June 4, 2008
planes and 100Ω with respect to each other. Failure to
meet this requirement will increase reflections, shrinking
the available eye.
• Avoid vias for all 3 high speed TMDS pairs. Vias add
inductance which ca use s a di scontinuity in th e
characteristic impedance of the trace. Keep all the traces
on the top (or the bottom) of the PCB. The TMDS clock
can have vias if necessary, since it is lower speed and less
critical. If you must use a via, ensure the vias are
symmetrical (put identical vias in both lines of the
differential pair).
• For each TMDS channel, the trace lengths of the 3 TMDS
pairs (0, 1 and 2) should ideally be the same to reduce
inter channel skew introduced by the board.
• The trace length of the clock pair is not critical at all.
Since the clock is only used as a frequency reference, its
phase/delay is inconsequential. In addition, since the
TMDS clock frequency is 1/10th the pixel rate, the clock
signal itself is much more noise-immune. So liberties
(such as vias and circuitous paths) can be taken when
routing the cl ock lines.
• Minimize capacitance on all TMDS lines. The lower the
capacitance, the sharper the rise and fall times.
• Maintain a constant, solid ground (or power) plane under
the 3 high speed TMDS signals. Do not route the signals
over gaps in the ground plane or over other traces.
• Ideally each supply should be bypassed to ground with a
0.1µF capacitor. Minimize trace length and vias to
minimize indu ctance and maximize noise rejection.
Figure 12 demonstrates a common but non-ideal PCB
layout and its equivalent circuit. The additional trace
resistance between the bypass capacitor and the power
supply/IC reduces its effectiveness. Figure 13
demonstrates a better layout. In this case there is still
series trace resistance (it is impossible to completely
eliminate it), but now it is being put to good use, as part of
a “T” filter , attenuating supply noise before it gets to the IC,
and reducing the amount of IC-generated noise th at gets
injected into the supply. Follow the good supply bypassing
rules shown in Figure 13 to the extent possible.
CBYPASS
RTRACE
V+
RTRACE
IC
V+
GND
GROUND PLANE
POWER PLANE
CBYPASS IC
V+
GND
VIAS
TO
GND
VIA TO
POWE R
PLANE
EQUIVALENT CIRCUIT
RVIA
FIGURE 12. SUB-OPTIMAL BYPASS CAPACITOR LAYOUT
FIGURE 13. OPTIMAL (“T”) BYPASS CAPACITOR LAYOUT
CBYPASS
RTRACE
V+
RTRACE
IC
V+
GND
GROUND PLANE
C BYPASS IC
V+
GND
VIAS
TO
GND
VIA TO
POWER
PLANE
EQUIVALENT CIRCUIT
POWER PLANE
RVIA
ISL54100, ISL54101, ISL54102
18 FN6275.5
June 4, 2008
ISL5410x Serial Communication
Overview
The ISL5410x uses a 2-wire serial bus for communication
with its host. SCL is the Serial Clock line, driven by the host
and SDA is the Serial Data line, which can be dr iven by all
devices on th e bu s. SDA is open drain to al l ow multiple
devices to share the same bus simultaneously.
Communication is accomplished in three steps:
1. The Host selects the ISL5410x it wishes to communicate
with.
2. The Host writes the initial ISL5410x Configuration
Register address it wishes to write to or read from.
3. The Host writes to or reads from the ISL5410x’s
Configuration Register . The ISL5410x’ s internal address
pointer auto increments, so to read registers 0x00
through 0x1B, for example, one would write 0x00 in step
2, then repeat step three 28 times, with each read
returning the ne xt re gister value.
The ISL5410x has a 7-bit address on the serial bus,
determined by the ADDR0-ADDR6 bits. This allows up to
128 ISL5410xs to be independently controlled by the same
serial bus.
The bus is nominally inactive, with SDA and SCL high.
Communication begins when the host issues a START
command by taking SDA low while SCL is high (Figure 14).
The ISL5410x continuously monitors the SDA and SCL lines
for the start condition and will not respond to any command
until this condition has been met. The host then transmits the
7-bit serial address plus a R/W bit, indicating if the next
transaction will be a Read (R/W = 1) or a Write (R/W = 0). If
the address transmitted matches that of any device on the
bus, that device must respond with an ACKNOWLEDGE
(Figure 15).
Once the serial address has been transmitted and
acknowledged, one or more bytes of information can be
written to or read from the slave. Communication with the
selected device in the selected direction (read or write) is
ended by a STOP command, where SDA rises while SCL is
high (Figure 14), or a second START command, which is
commonly used to reverse data direction without
relinquishing the bus.
Data on the serial bus must be valid for the entire time SCL
is high (Figure 16). To achieve this, data being written to the
ISL5410x is latched on a delayed version of the rising edge
of SCL. SCL is delayed and deglitched inside the ISL5410x
for three crystal clock periods (120ns for a 25MHz crystal) to
eliminate spurious clock pulses that could disrupt serial
communication.
When the contents of the ISL5410x are being read, the SDA
line is updated after the fallin g edge of SCL, delayed and
deglitched in the same manner.
Configuration Register Write
Figure 17 shows two views of the steps necessary to write
one or more words to the Configuration Register.
Configuration Register Read
Figure 18 shows two views of the steps necessary to read
one or more words from the Configuration Register.
SCL
SDA
START STOP
FIGURE 14. VALID START AND STOP CONDITIONS
SCL FROM
HOST
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
81 9
START ACKNOWLEDGE
FIGURE 15. ACKNOWLEDGE RESPONSE FROM RECEIVER
ISL54100, ISL54101, ISL54102
19 FN6275.5
June 4, 2008
SCL
SDA
DATA STABLE DATA CHANGE DATA STABLE
FIGURE 16. VALID DATA CHANGES ON THE SDA BUS
D7 D6 D5 D2D4 D3 D1 D0
A0A7 A2A4 A3 A1
ISL5410x Register Data Write(s)
This is the data to be written to the ISL5410x’s configuration register.
Note: The ISL5410x’s Configuration Register’s address pointer auto
increments after each data write: repeat this step to write multiple
sequential bytes of data to the Configuration Register.
A6 A5
0
R/W
ISL5410x Register Address Write
This is the address of the ISL5410x’s configuration register that
the following byte will be written to.
ISL5410x Serial Bus
FIGURE 17. CONFIGURATION REGISTER WRITE
START Command
STOP Command
(Repeat if desired)
Signals the beginning of serial I/O
Signals the ending of serial I/O
S
T
A
R
T
S
T
O
P
Data
Write*
Register
Address
Serial Bus
Address
A
C
K
AAAAAAAA A
C
K
dddddddd
A
C
K
aaaaaaa0
* The data write step may be repeated to write to the
ISL5410x’s Configuration Register sequentially, beginning at
the Register Address written in the previous step.
SDA Bus
Signals from
the ISL5410x
Signals from
the Host
ISL5410x Device Select Address Write
The first 7 bits of the first byte select the ISL54100 on the 2-wire
bus at the address set by the ADDR[6:0} pins. The R/W bit is a
0, indicating that the next transaction will be a write.
ADDR1 ADDR0ADDR3 ADDR2ADDR5 ADDR4ADDR6
ISL54100, ISL54101, ISL54102
20 FN6275.5
June 4, 2008
Datasheet Changes from FN6275.4
• Added note to description on front page describing specific
HDMI 1.3a features supported. Spelled out TMDS acronym.
• Added additional information to pins 74 and 95, noting that
they are called VD_ESD pins and should be connected to
VD_ESD via a Schottky diode.
• Fixed typo on Register 0x05’s Reverse Output Order bit . It
was labelled as bit 4, it is now correctly labelled as bit 3.
• Added TEST pin to Pin Descriptions table.
• Added Note 2 (emphasizing that operation above 165MHz
is not guaranteed) to electrical specs.
• Changed description of register 0x03’s Activity Detect bits
and recommended new settings to improve accuracy of
the activity detect function.
• Added note to recommend Recalibration (register 0x03b7)
after supply and temp have settled.
• Changed recommended PLL Bandwidth (register 0x10)
setting to 1MHz
• Added “Tx Loading Considerations” section on page 16.
• Updated Pb-free note to new ve rbiage.
• Updated Note 2 to new verbiage.
FIGURE 18. CONFIGURATION REGISTER READ
A0A7 A2A4 A3 A1A6 A5
R/W
ISL5410x Register Address Write
This sets the initial address of the ISL5410x’s configuration
register for subsequent reading.
ISL5410x Serial Bus
START Command Signals the beginning of serial I/O
ISL5410x Serial Bus Address Write
This is the same 7-bit address that was sent previously, however
the R/W bit is now a 1, indicating that the next transaction(s) will
be a read.
D7 D6 D5 D2D4 D3 D1 D0 ISL5410x Register Data Read(s)
This is the data read from the ISL5410x’s configuration register.
Note: The ISL5410x’s Configuration Register’s address pointer
auto increments after each data read: repeat this step to read
multiple sequential bytes of data from the Configuration Register.
R/W
ISL5410x Serial Bus
START Command
STOP Command
(Repeat if desired)
Ends the previous transaction and starts a new one
Signals the ending of serial I/O
S
T
A
R
T
S
T
O
P
Data
Read*
SDA Bus
Signals from
the ISL5410x
Signals from
the Host Register
Address
Serial Bus
Address
A
C
K
AAAAAAAA
A
C
K
dddddddd
A
C
K
aaaaaaa0
* The data read step may be repeated to read
from the ISL5410x’s Configuration Register
sequentially, beginning at the Register
Address written in the two steps previous.
R
E
S
T
A
R
T
Serial Bus
Address
A
C
K
aaaaaaa1
ISL5410x Device Select Address Write
The first 7 bits of the first byte select the ISL54100 on the 2-wire
bus at the address set by the ADDR[6:0} pins. R/W = 0,
indicating that the next transaction will be a write.
0
ADDR1 ADDR0ADDR3 ADDR2ADDR5 ADDR4ADDR6
1
ADDR1 ADDR0ADDR3 ADDR2ADDR5 ADDR4ADDR6
ISL54100, ISL54101, ISL54102
21
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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For information regarding Intersil Corporation and its products, see www .intersil.com
FN6275.5
June 4, 2008
ISL54100, ISL54101, ISL54102
Metric Plastic Quad Flatpack Packages (MQFP)
Y
ALL AROUND
DROP IN HEAT SPREADER
4 STAND POINTS MAY BE EXPOSED
PIN 1 ID
D1
D
E
E1
18.500 REF
12.500 REF
C0.600x0.350
(4X)
19.870 ±0.100
20.000 ±0.100
(E1)
13.870 ±0.100
14.000 ±0.100
A
A
12°
ALL
AROUND
(D1)
1
1SECTION A-A
T
b
b1
T1
ccc C
A2
A
A1
R0.13 MIN
R0.25 TYP
C
ddd C
M
L1
0° MIN
0.200 MIN
α
T
GAUGE
PLANE
DETAIL Y
0.13~0.30
128
1
L
b
e
SEATING
PLANE 0.25 BASE
DO NOT TR Y TO CONNECT ELECTRICALLY
MDP0055
14x20mm 128 LEAD MQFP (WITH AND WITHOUT HEAT
SPREADER) 3.2mm FOOTPRINT
SYMBOL
DIMENSIONS
(MILLIMETERS) REMARKS
A Max 3.40 Overall height
A1 0.250~0.500 Standoff
A2 2.750 ±0.250 Package thickness
α0°~7° Foot angle
b 0.220 ±0.050 Lead width
b1 0.200 ±0.030 Lead base metal width
D 17.200 ±0.250 Lead tip to tip
D1 14.000 ±0.100 Package length
E 23.200 ±0.250 Lead tip to tip
E1 20.000 ±0.100 Package width
e 0.500 Base Lead pitch
L 0.880 ±0.150 Foot length
L1 1.600 Ref. Lead length
T 0.170 ±0.060 Frame thickness
T1 0.152 ±0.040 Frame base metal thickness
ccc 0.100 Foot coplanarity
ddd 0.100 Foot position
Rev. 2 2/07
NOTES:
1. General tolerance: Distance ±0.100, Angle +2.5°.
2. Matte finish on package body surface except ejection and
pin 1 marking (Ra 0.8~2.0um).
3. All molded body sharp corner RADII unless otherwise specified
(Max RO.200).
4. Package/Leadframe misalignment (X, Y): Max. 0.127
5. Top/Bottom misalignment (X, Y): Max. 0.127
6. Drawing does not include plastic or metal protrusion or cutting
burr.
7. Compliant to JEDEC MS-022.
1
1
1
1
1
2
