DC1529A-B - Linear Technology

LTC2657

2657f

BLOCK DIAGRAM

DESCRIPTION

Octal I2C 16-/12-Bit

Rail-to-Rail DACs with

10ppm/°C Max Reference

The LTC

2657 is a family of octal I2C 16-/12-Bit Rail-to-

Rail DACs with Integrated 10ppm/°C Max Reference. The

DACs have built-in high performance, rail-to-rail, output

buffers and are guaranteed monotonic. The LTC2657-L has

a full-scale output of 2.5V with the integrated reference and

operates from a single 2.7V to 5.5V supply. The LTC2657-H

has a full-scale output of 4.096V with the integrated reference

and operates from a 4.5V to 5.5V supply. Each DAC can also

operate with an external reference, which sets the full-scale

output to 2 times the external reference voltage.

The parts use a 2-wire I2C compatible serial interface. The

LTC2657 operates in both the standard mode (maximum

clock rate of 100kHz) and the fast mode (maximum clock

rate of 400kHz). The LTC2657 incorporates a power-on reset

circuit that is controlled by the PORSEL pin. If PORSEL is tied

to GND the DACs reset to zero-scale at power-up. If PORSEL

is tied to VCC, the DACs reset to mid-scale at power-up.

L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other

trademarks are the property of their respective owners. Protected by U.S. Patents including

5396245, 6891433 and patent pending.

FEATURES

APPLICATIONS

n Integrated Reference 10ppm/°C Max

n Maximum INL Error: ±4LSB

n Guaranteed Monotonic Over Temperature

n Selectable Internal or External Reference

n 2.7V to 5.5V Supply Range (LTC2657-L)

n Integrated Reference Buffers

n Ultralow Crosstalk between DACs(0.8nV•s)

n Power-On-Reset to Zero-Scale/Mid-Scale

n 400kHz I2C Interface

n Tiny 20-Lead 4mm × 5mm QFN and 20-Lead

Thermally enhanced TSSOP packages

n Mobile Communications

n Process Control and Industrial Automation

n Instrumentation

n Automatic Test Equipment

n Automotive

INTERNAL REFERENCE

POWER-ON RESET

REFCOMP REFIN/OUT

VCC

GND

DAC A

REF

DAC H VOUTH

DAC G VOUTG

DAC F VOUTF

DAC E VOUTE

PORSEL

SDA

SCL

REFLO

VOUTA

DAC B

VOUTB

DAC C

VOUTC

DAC D

VOUTD

CA2

LDAC

CA0

CA1

2-WIRE INTERFACE

32-BIT SHIFT REGISTER

2657 BD

INL vs Code (LTC2657-16)

CODE

128

INL (LSB)

65535

2657 TA01

–1

–2

–4 16384 32768 49152

–3

DAC A

DAC B

DAC C

DAC D

DAC E

DAC F

DAC G

DAC H

LTC2657

2657f

PIN CONFIGURATION

ABSOLUTE MAXIMUM RATINGS

Supply Voltage (VCC) ................................... –0.3V to 6V

SCL, SDA, LDAC, REFLO ..............................–0.3V to 6V

VOUTA to VOUTH .................–0.3V to Min(VCC + 0.3V, 6V)

REFIN/OUT, REFCOMP ......–0.3V to Min(VCC + 0.3V, 6V)

PORSEL, CA0, CA1, CA2 ...–0.3V to Min(VCC + 0.3V, 6V)

(Notes 1, 2)

FE PACKAGE

20-LEAD PLASTIC TSSOP

TOP VIEW

REFLO

VOUTA

VOUTB

REFCOMP

VOUTC

VOUTD

REFIN/OUT

LDAC

CA2

SCL

GND

VCC

VOUTH

VOUTG

VOUTF

VOUTE

PORSEL

CA0

CA1

SDA

TJMAX = 150°C, θJA = 38°C/W, θJC = 10°C/W

EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB

20 19 18 17

7 8

TOP VIEW

UFD PACKAGE

20-LEAD (4mm s 5mm) PLASTIC QFN

9 10

VOUTB

REFCOMP

VOUTC

VOUTD

REFIN/OUT

LDAC

VOUTH

VOUTG

VOUTF

VOUTE

PORSEL

CA0

VOUTA

REFLO

GND

VCC

CA2

SCL

SDA

CA1

TJMAX = 150°C, θJA = 43°C/W

EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB

Operating Temperature Range

LTC2657C ................................................ 0°C to 70°C

LTC2657I..............................................–40°C to 85°C

Maximum Junction Temperature........................... 150°C

Storage Temperature Range .......................–65 to 150°C

Lead Temperature (Soldering FE-Package, 10 sec) .. 300°C

LTC2657

2657f

PRODUCT SELECTOR GUIDE

LTC2657 B C UFD -L 16 #TR PBF

LEAD FREE DESIGNATOR

TAPE AND REEL

TR = Tape and Reel

RESOLUTION

16 = 16-Bit

12 = 12-Bit

FULL-SCALE VOLTAGE, INTERNAL REFERENCE MODE

L = 2.5V

H = 4.096V

PACKAGE TYPE

UFD = 20-Lead (4mm × 5mm) Plastic QFN

FE = 20-Lead Thermally Enhanced TSSOP

TEMPERATURE GRADE

C = Commercial Temperature Range (0°C to 70°C)

I = Industrial Temperature Range (–40°C to 85°C)

ELECTRICAL GRADE (OPTIONAL)

B = ±4LSB INL (MAX)

PRODUCT PART NUMBER

Consult LTC Marketing for information on non-standard lead based ﬁ nish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁ cations, go to: http://www.linear.com/tapeandreel/

LTC2657

2657f

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE

RANGE

MAXIMUM

INL

LTC2657BCFE-L16#PBF LTC2657BCFE-L16#TRPBF LTC2657FE-L16 20-Lead Thermally Enhanced TSSOP 0°C to 70°C ±4

LTC2657BIFE-L16#PBF LTC2657BIFE-L16#TRPBF LTC2657FE-L16 20-Lead Thermally Enhanced TSSOP –40°C to 85°C ±4

LTC2657BCUFD-L16#PBF LTC2657BCUFD-L16#TRPBF 57L16 20-Lead (4mm × 5mm) Plastic QFN 0°C to 70°C ±4

LTC2657BIUFD-L16#PBF LTC2657BIUFD-L16#TRPBF 57L16 20-Lead (4mm × 5mm) Plastic QFN –40°C to 85°C ±4

LTC2657BCFE-H16#PBF LTC2657BCFE-H16#TRPBF LTC2657FE-H16 20-Lead Thermally Enhanced TSSOP 0°C to 70°C ±4

LTC2657BIFE-H16#PBF LTC2657BIFE-H16#TRPBF LTC2657FE-H16 20-Lead Thermally Enhanced TSSOP –40°C to 85°C ±4

LTC2657BCUFD-H16#PBF LTC2657BCUFD-H16#TRPBF 57H16 20-Lead (4mm × 5mm) Plastic QFN 0°C to 70°C ±4

LTC2657BIUFD-H16#PBF LTC2657BIUFD-H16#TRPBF 57H16 20-Lead (4mm × 5mm) Plastic QFN –40°C to 85°C ±4

LTC2657CFE-L12#PBF LTC2657CFE-L12#TRPBF LTC2657FE-L12 20-Lead Thermally Enhanced TSSOP 0°C to 70°C ±1

LTC2657IFE-L12#PBF LTC2657IFE-L12#TRPBF LTC2657FE-L12 20-Lead Thermally Enhanced TSSOP –40°C to 85°C ±1

LTC2657CUFD-L12#PBF LTC2657CUFD-L12#TRPBF 57L12 20-Lead (4mm × 5mm) Plastic QFN 0°C to 70°C ±1

LTC2657IUFD-L12#PBF LTC2657IUFD-L12#TRPBF 57L12 20-Lead (4mm × 5mm) Plastic QFN –40°C to 85°C ±1

LTC2657CFE-H12#PBF LTC2657CFE-H12#TRPBF LTC2657FE-H12 20-Lead Thermally Enhanced TSSOP 0°C to 70°C ±1

LTC2657IFE-H12#PBF LTC2657IFE-H12#TRPBF LTC2657FE-H12 20-Lead Thermally Enhanced TSSOP –40°C to 85°C ±1

LTC2657CUFD-H12#PBF LTC2657CUFD-H12#TRPBF 57H12 20-Lead (4mm × 5mm) Plastic QFN 0°C to 70°C ±1

LTC2657IUFD-H12#PBF LTC2657IUFD-H12#TRPBF 57H12 20-Lead (4mm × 5mm) Plastic QFN –40°C to 85°C ±1

Consult LTC Marketing for parts speciﬁ ed with wider operating temperature ranges. *The temperature grade is identiﬁ ed by a label on the

shipping container.Consult LTC Marketing for information on non-standard lead based ﬁ nish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁ

cations, go to: http://www.linear.com/tapeandreel/

ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise speciﬁ ed.

LTC2657B-L16/LTC2657-L12 (Internal Reference = 1.25V)

SYMBOL PARAMETER CONDITIONS

LTC2657-12 LTC2657B-16

UNITSMIN TYP MAX MIN TYP MAX

DC Performance

Resolution l12 16 Bits

Monotonicity (Note 3) l12 16 Bits

DNL Differential Nonlinearity (Note 3) l±0.1 ±0.5 ±0.3 ±1 LSB

INL Integral Nonlinearity (Note 3) VCC = 5.5V, VREF = 2.5V l±0.5 ±1 ±2 ±4 LSB

Load Regulation VCC = 5V ±10%, Internal Reference, Mid-Scale,

–15mA ≤ IOUT ≤ 15mA

l0.04 0.125 0.6 2 LSB/mA

VCC = 3V ±10%, Internal Reference, Mid-Scale,

–7.5mA ≤ IOUT ≤ 7.5mA

l0.06 0.25 1 4 LSB/mA

ZSE Zero-Scale Error l13 13 mV

VOS Offset Error (Note 4) VREF = 1.25V l±1 ±2 ±1 ±2 mV

VOS Temperature Coefﬁ cient 2 2 µV/°C

GE Gain Error l±0.02 ±0.1 ±0.02 ±0.1 %FSR

Gain Temperature Coefﬁ cient 1 1 ppm/°C

LTC2657

2657f

ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise speciﬁ ed.

LTC2657B-L16/LTC2657-L12 (Internal Reference = 1.25V)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VOUT DAC Output Span Internal Reference

External Reference = VEXTREF

0 to 2.5

0 to 2 • VEXTREF

PSR Power Supply Rejection VCC ±10% –80 dB

ROUT DC Output Impedance VCC = 5V ±10%, Internal Reference, Mid-Scale,

–15mA ≤ IOUT ≤ 15mA

l0.04 0.15 

VCC = 3V ±10%, Internal Reference, Mid-Scale,

–7.5mA ≤ IOUT ≤ 7.5mA

l0.04 0.15 

DC Crosstalk (Note 5) Due to Full-Scale Output Change

Due to Load Current Change

Due to Powering Down (per Channel)

±1.5

±2

±1

µV

µV/mA

µV

ISC Short-Circuit Output Current (Note 6) VCC = 5.5V, VEXTREF = 2.8V

Code: Zero-Scale, Forcing Output to VCC

Code: Full-Scale, Forcing Output to GND

VCC = 2.7V, VEXTREF = 1.4V

Code: Zero-Scale, Forcing Output to VCC

Code: Full-Scale, Forcing Output to GND

Reference

Reference Output Voltage 1.248 1.25 1.252 V

Reference Temperature Coefﬁ cient (Note 7) C-Grade Only ±2 ±10 ppm/°C

Reference Line Regulation VCC ±10% –80 dB

Reference Short-Circuit Current VCC = 5.5V, Forcing REFIN/OUT to GND l5mA

REFCOMP Pin Short-Circuit Current VCC = 5.5V, Forcing REFCOMP to GND l200 µA

Reference Load Regulation VCC = 3V ±10% or 5V ±10%, IOUT = 100µA

Sourcing

40 mV/mA

Reference Output Voltage Noise Density CREFCOMP = CREFIN/OUT = 0.1µF at f = 1kHz 30 nV/√Hz

Reference Input Range External Reference Mode (Note 14) l0.5 VCC/2 V

Reference Input Current l0.001 1 µA

Reference Input Capacitance (Note 9) 40 pF

Power Supply

VCC Positive Supply Voltage For Speciﬁ ed Performance l2.7 5.5 V

ICC Supply Current (Note 8) VCC = 5V, Internal Reference On

VCC = 5V, Internal Reference Off

VCC = 3V, Internal Reference On

VCC = 3V, Internal Reference Off

3.1

2.7

2.6

4.25

3.7

3.8

3.2

ISD Supply Current in Shutdown Mode

(Note 8)

VCC = 5V l3µA

Digital I/O

VIL Low Level Input Voltage

(SDA and SCL)

l0.3VCC V

VIH High Level Input Voltage

(SDA and SCL)

l0.7VCC V

VIL(LDAC)Low Level Input Voltage (LDAC)V

CC = 4.5V to 5.5V l0.8 V

VCC = 2.7V to 4.5V l0.6 V

VIH(LDAC)High Level Input Voltage (LDAC)V

CC = 3.6V to 5.5V l2.4 V

VCC = 2.7V to 3.6V l2 V

LTC2657

2657f

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIL(CA) Low Level Input Voltage (CA0 and CA2) See Test Circuit 1 l0.15VCC V

VIH(CA) High Level Input Voltage (CA0 and CA2) See Test Circuit 1 l0.85VCC V

RINH Resistance from CA

(n = 0,1, 2)

to VCC to Set CA

= VCC

See Test Circuit 2 l10 k

RINL Resistance from CA

(n = 0,1, 2)

to GND to Set CA

= GND

See Test Circuit 2 l10 k

RINF Resistance from CA

(n = 0,1, 2)

to VCC or GND to Set CA

=FLOAT

See Test Circuit 2 l2M

VOL Low Level Output Voltage Sink Current = 3mA l0 0.4 V

tOF Output Fall Time VO = VIH(MIN) to VO = VIL(MAX),

CB = 10pF to 400pF (Note 13)

l20+0.1CB250 ns

tSP Pulse Width of Spikes Suppressed by

Input Filter

l050ns

IIN Input Leakage 0.1VCC ≤ VIN ≤ 0.9VCC l1µA

CIN I/O Pin Capacitance (Note 9) l10 pF

CBCapacitance Load for Each Bus Line l400 pF

CCA

External Capacitive Load on Address

Pins CA0, CA1 and CA2

l10 pF

ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise speciﬁ ed.

LTC2657B-L16/LTC2657-L12 (Internal Reference = 1.25V)

The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C.

VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise speciﬁ ed. LTC2657B-H16/LTC2657-H12 (Internal Reference = 2.048V)

SYMBOL PARAMETER CONDITIONS

LTC2657-12 LTC2657B-16

UNITSMIN TYP MAX MIN TYP MAX

DC Performance

Resolution l12 16 Bits

Monotonicity (Note 3) l12 16 Bits

DNL Differential Nonlinearity (Note 3) l±0.1 ±0.5 ±0.3 ±1 LSB

INL Integral Nonlinearity (Note 3) VCC = 5.5V, VREF = 2.5V l±0.5 ±1 ±2 ±4 LSB

Load Regulation VCC = 5V ±10%, Internal Reference,

Mid-Scale, –15mA ≤ IOUT ≤ 15mA

l0.04 0.125 0.6 2 LSB/mA

ZSE Zero-Scale Error l13 13 mV

VOS Offset Error (Note 4) VREF = 2.048V l±1 ±2 ±1 ±2 mV

VOS Temperature Coefﬁ cient 2 2 µV/°C

GE Gain Error l±0.02 ±0.1 ±0.02 ±0.1 %FSR

Gain Temperature Coefﬁ cient 1 1 ppm/°C

LTC2657

2657f

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VOUT DAC Output Span Internal Reference

External Reference = VEXTREF

0 to 4.096

0 to 2 • VEXTREF

PSR Power Supply Rejection VCC ±10% –80 dB

ROUT DC Output Impedance VCC = 5V ±10%, Internal Reference, Mid-

Scale,

–15mA ≤ IOUT ≤ 15mA

l0.04 0.15 

DC Crosstalk Due to Full-Scale Output Change

Due to Load Current Change

Due to Powering Down (per Channel)

±1.5

±2

±1

µV

µV/mA

µV

ISC Short-Circuit Output Current (Note 4) VCC = 5.5V, VEXTREF = 2.8V

Code: Zero-Scale, Forcing Output to VCC

Code: Full-Scale, Forcing Output to GND

Reference

Reference Output Voltage 2.044 2.048 2.052 V

Reference Temperature Coefﬁ cient (Note 7) C-Grade Only ±2 ±10 ppm/°C

Reference Line Regulation VCC ±10% –80 dB

Reference Short-Circuit Current VCC = 5.5V, Forcing REFIN/OUT to GND l5mA

REFCOMP Pin Short-Circuit Current VCC = 5.5V, Forcing REFCOMP to GND l200 µA

Reference Load Regulation VCC = 3V ±10% or 5V ±10%, IOUT = 100µA

Sourcing

40 mV/mA

Reference Output Voltage Noise Density CREFCOMP = CREFIN/OUT = 0.1µF at f = 1kHz 35 nV/√Hz

Reference Input Range External Reference Mode (Note 14) l0.5 VCC/2 V

Reference Input Current l0.001 1 µA

Reference Input Capacitance (Note 9) l40 pF

Power Supply

VCC Positive Supply Voltage For Speciﬁ ed Performance l4.5 5.5 V

ICC Supply Current (Note 8) VCC = 5V, Internal Reference On

VCC = 5V, Internal Reference Off

3.3

4.25

3.7

ISD Supply Current in Shutdown Mode (Note 8) VCC = 5V l3µA

Digital I/O

VIL Low Level Input Voltage (SDA and SCL) l0.3VCC V

VIH High Level Input Voltage (SDA and SCL) l0.7VCC V

VIL(LDAC)Low Level Input Voltage (LDAC) VCC = 4.5V to 5.5V l0.8V V

VIH(LDAC)High Level Input Voltage (LDAC) VCC = 4.5V to 5.5V l2.4 V

VIL(CA) Low Level Input Voltage (CA0 to CA2) See Test Circuit 1 l0.15VCC V

VIH(CA) High Level Input Voltage (CA0 to CA2) See Test Circuit 1 l0.85VCC V

RINH Resistance from CA

(n = 0,1, 2)

to VCC to Set CA

= VCC

See Test Circuit 2 l10 k

RINL Resistance from CA

(n = 0,1, 2)

to GND to Set CA

= GND

See Test Circuit 2 l10 k

RINF Resistance from CA

(n = 0,1, 2)

to VCC or GND to Set CA

= FLOAT

See Test Circuit 2 l2M

VOL Low Level Ouput Voltage Sink Current = 3mA l0 0.4 V

ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise speciﬁ ed.

LTC2657B-H16/LTC2657-H12 (Internal Reference = 2.048V)

LTC2657

2657f

ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise speciﬁ ed.

LTC2657B-H16/LTC2657-H12 (Internal Reference = 2.048V)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

tOF Output Fall Time VO = VIH(MIN) to VO = VIL(MAX),

CB = 10pF to 400pF (Note 13)

l20+0.1CB250 ns

tSP Pulse Width of Spikes Suppressed by Input

Filter

l050ns

IIN Input Leakage 0.1VCC ≤ VIN ≤ 0.9VCC l1µA

CIN I/O Pin Capacitance (Note 9) l10 pF

CBCapacitance Load for Each Bus Line l400 pF

CCA

External Capacitive Load on Address Pins

CA0, CA1 and CA2

l10 pF

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

AC Performance

tSSettling Time (Note 10) ±0.024% (±1LSB at 12 Bits)

±0.0015% (±1LSB at 16 Bits)

3.9

9.1

µs

Settling Time for 1LSB Step ±0.024% (±1LSB at 12 Bits)

±0.0015% (±1LSB at 16 Bits)

2.4

4.5

µs

Voltage Output Slew Rate 1.8 V/µs

Capacitive Load Driving 1000 pF

Glitch Impulse (Note 11) At Mid-Scale Transition, L-Option 4 nV•s

At Mid-Scale Transition, H-Option 7 nV•s

DAC-to-DAC Crosstalk (Note 12) CREFCOMP = CREFIN/OUT = 0.22µF 0.8 nV•s

Multiplying Bandwidth 150 kHz

enOutput Voltage Noise Density At f = 1kHz

At f = 10kHz

nV/√Hz

Output Voltage Noise 0.1Hz to 10Hz, Internal Reference (L-Options)

0.1Hz to 10Hz, Internal Reference (H-Options)

0.1Hz to 200kHz, Internal Reference (L-Options)

0.1Hz to 200kHz, Internal Reference (H-Options)

600

650

µVP-P

The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C.

VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise speciﬁ ed. LTC2657B-H16/LTC2657-H12/ LTC2657B-L16/LTC2657-L12

LTC2657

2657f

TIMING CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltages are with respect to GND.

Note 3: Linearity and monotonicity are deﬁ ned from code kL to code

2N – 1, where N is the resolution and kL is the lower end code for which

no output limiting occurs. For VREF = 2.5V and N = 16, kL = 128 and

linearity is deﬁ ned from code 128 to code 65535. For VREF = 2.5V and

N = 12, kL = 8 and linearity is deﬁ ned from code 8 to code 4,095.

Note 4: Inferred from measurement at code 128 (LTC2657-16) or code 8

(LTC2657-12).

Note 5: DC crosstalk is measured with VCC = 5V and using internal

reference with the measured DAC at mid-scale.

Note 6: This IC includes current limiting that is intended to protect the

device during momentary overload conditions. Junction temperature can

exceed the rated maximum during current limiting. Continuous operation

above the speciﬁ ed maximum operating junction temperature may impair

device reliability.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VCC = 2.7V to 5.5V

fSCL SCL Clock Frequency l0 400 kHz

tHD(STA) Hold Time (Repeated) Start Condition l0.6 µs

tLOW Low Period of the SCL Clock Pin l1.3 µs

tHIGH High Period of the SCL Clock Pin l0.6 µs

tSU(STA) Set-Up Time for a Repeated Start Program l0.6 µs

tHD(DAT) Data Hold Time l0 0.9 µs

tSU(DAT) Data Set-Up Time l100 ns

trRise Time of Both SDA and SCL Signals l20+0.1CB300 ns

tfFall Time of Both SDA and SCL Signals l20+0.1CB300 ns

tSU(STO) Set-Up Time for Stop Condition l0.6 µs

tBUF Bus Free Time Between a Stop and Start Condition l1.3 µs

t1Falling edge of the 9th Clock of the 3rd Input Byte

to LDAC High or Low Transition

l400 ns

t2LDAC Low Pulse Width l20 ns

The l denotes the speciﬁ cations which apply over the full operating temperature

range, otherwise speciﬁ cations are at TA = 25°C. LTC2657B-L16/LTC2657-L12/LTC2657B-H16/LTC2657-H12 (see Figure 1).

Note 7: Temperature coefﬁ cient is calculated by dividing the maximum

change in output voltage by the speciﬁ ed temperature range.

Note 8: Digital inputs at 0V or VCC.

Note 9: Guaranteed by design and not production tested.

Note 10: Internal reference mode. DAC is stepped 1/4 scale to 3/4 scale

and 3/4 scale to 1/4 scale. Load is 2k in parallel with 200pF to GND.

Note 11: VCC = 5V (H-Options) or VCC = 3V (L-Options), internal reference

mode. DAC is stepped ±1LSB between half-scale and half-scale –1. Load is

2k in parallel with 200pF to GND.

Note 12: DAC-to-DAC crosstalk is the glitch that appears at the output

of one DAC due to a full-scale change at the output of another DAC. It is

measured with VCC = 5V, using internal reference, with the measured DAC

at mid-scale.

Note 13: CB = capacitance of one bus line in pF.

Note 14: Gain error speciﬁ cation may be degraded for reference input

voltages less than 1V. See Gain Error vs Reference Input curve in the

Typical Performance Characteristics section.

LTC2657

2657f

TYPICAL PERFORMANCE CHARACTERISTICS

TEMPERATURE (°C)

–50

VREFIN/OUT (V)

1.251

1.250

1.249

1.248

1.247

1.252

–10 30 50 130

2657 G05

–30 10 70 90 110

1.253 VCC = 3V

DNL vs Temperature

REFIN/OUT Output Voltage

vs Temperature

Settling to ±1LSB Rising Settling to ±1LSB Falling

Integral Nonlinearity (INL) Differential Nonlinearity (DNL) INL vs Temperature

LTC2657-L16, TA = 25°C unless otherwise noted.

CODE

128

–4

INL (LSB)

–1

–2

–3

16384 6553532768

2657 G01

49152

VCC = 3V

CODE

128

–1

DNL (LSB)

0.5

–0.5

16384 6553532768

2657 G02

49152

VCC = 3V

TEMPERATURE (°C)

–50

–4

INL (LSB)

–1

–2

–3

–30 70 90 110 130–10 10 30

2657 G03

VCC = 3V

INL (POS)

INL (NEG)

TEMPERATURE (°C)

–50

–1

DNL (LSB)

0.5

–0.5

–30 70 90 110 130–10 10 30

3586 G35

DNL (POS)

VCC = 3V

DNL (NEG)

2µs/DIV

SCL

3V/DIV

VOUT

150µV/DIV

2657 G07

1/4 SCALE TO 3/4

SCALE STEP

VCC = 3V, VFS = 2.5V

RL = 2k, CL = 200pF

AVERAGE OF 2048

EVENTS

9TH CLOCK OF

3RD DATA BYTE

9µs

2µs/DIV

SCL

3V/DIV

VOUT

100µV/DIV

2657 G08

8.6µs

9TH CLOCK OF

3RD DATA BYTE

3/4 SCALE TO 1/4 SCALE STEP

VCC = 3V, VFS = 2.5V

RL = 2k, CL = 200pF

AVERAGE OF 2048 EVENTS

LTC2657

2657f

TEMPERATURE (°C)

–50

VREFIN/OUT (V)

2.050

2.048

2.046

2.044

2.042

2.052

–10 30 50 130

2657 G14

–30 10 70 90 110

2.054 VCC = 5V

DNL vs Temperature

REFIN/OUT Output Voltage

vs Temperature

Settling to ±1LSB Rising Settling to ±1LSB Falling

Integral Nonlinearity (INL) Differential Nonlinearity (DNL) INL vs Temperature

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2657-H16, TA = 25°C unless otherwise noted.

CODE

128

–4

INL (LSB)

–1

–2

–3

6553516384 32768 49152

2657 G10

VCC = 5V

CODE

128

–1

DNL (LSB)

0.5

–0.5

6553516384 32768

2657 G011

49152

VCC = 5V

TEMPERATURE (°C)

–50

–4

INL (LSB)

–1

–2

–3

–30 70 90 110 130–10 10 30

3586 G35

VCC = 5V

INL (POS)

INL (NEG)

TEMPERATURE (°C)

–50

–1

DNL (LSB)

0.5

–0.5

–30 70 90 110 130–10 10 30

2657 G13

VCC = 5V

DNL (POS)

DNL (NEG)

2µs/DIV

2657 G16

VOUT

250µV/DIV

SCL

5V/DIV

9TH CLOCK OF

3RD DATA BYTE

9.7µs

1/4 SCALE TO 3/4

SCALE STEP

VCC = 5V, VFS = 4.096V

RL = 2k, CL = 200pF

AVERAGE OF 2048 EVENTS

2µs/DIV

2657 G17

VOUT

250µV/DIV

SCL

5V/DIV

9.2µs

9TH CLOCK OF

3RD DATA BYTE

3/4 SCALE TO 1/4 SCALE

STEP

VCC = 5V, VFS = 4.096V

RL = 2k, CL = 200pF

AVERAGE OF 2048

EVENTS

LTC2657

2657f

IOUT (mA)

–50

∆VOUT (mV)

2657 G22

–4

–2

–6

–8

–10 –30–40 –10–20 10 20 40

050

VCC = 5V (LTC2657-H)

VCC = 3V (LTC2657-L)

INTERNAL REF.

CODE = MID-SCALE

IOUT (mA)

–50

∆VOUT (V)

0.10

0.20

2657 G23

–0.10

–0.05

0.05

0.15

–0.15

–0.20 –30–40 –10–20 10 20 40

050

VCC = 5V (LTC2657-H)

VCC = 3V (LTC2657-L)

INTERNAL REF.

CODE = MID-SCALE

IOUT (mA)

VOUT (V)

3.0

4.0

5.0

2657 G24

2.0

1.0

2.5

3.5

4.5

1.5

0.5

021 43 67 9

510

5V SOURCING

SINKING

3V SOURCING

(LTC2657-L)

3V SINKING

(LTC2657-L)

Load Regulation Current Limiting

Headroom at Rails

vs Output Current

Offset Error vs Temperature Zero-Scale Error vs Temperature Gain Eror vs Temperature

Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Settling to ±1LSB

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2657-12, TA = 25°C unless otherwise noted.

CODE

–1

INL(LSB)

0.5

–0.5

40951024 2048

2657 G19

3072

VCC = 5V

VREF = 2.048V

CODE

–1

DNL(LSB)

0.5

–0.5

40951024 2048

2657 G20

3072

VCC = 5V

VREF = 2.048V

2µs/DIV

2657 G21

VOUT

500µV/DIV

SCL

3V/DIV

3.5µs

9TH CLOCK OF

3RD DATA BYTE

3/4 SCALE TO 1/4 SCALE STEP

VCC = 3V, VFS = 2.5V

RL = 2k, CL = 200pF

AVERAGE OF 2048 EVENTS

TEMPERATURE (°C)

–50

–1

OFFSET ERROR (mV)

0.75

0.25

0.5

–0.25

–0.5

–0.75

–30 70 90 110 130–10 10 30

2657 G25

TEMPERATURE (°C)

–50

ZERO-SCALE ERROR (mV)

2.5

1.5

0.5

–30 70 90 110 130–10 10 30

2657 G26

TEMPERATURE (°C)

–50

–64

GAIN ERROR (LSB)

–16

–32

–48

–30 70 90 110 130–10 10 30

2657 G27

LTC2657

2657f

Supply Current vs Logic Voltage Supply Current vs Temperature ICC Shutdown vs Temperature

Multiplying Bandwidth Large Signal Response Mid-Scale Glitch Impulse

Offset Error vs Reference Input Gain Error vs Reference Input ICC Shutdown vs VCC

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2657, TA = 25°C unless otherwise noted.

REFERENCE VOLTAGE (V)

0.5

–2

OFFSET ERROR (mV)

1.5

0.5

–0.5

–1

–1.5

2.51 1.5

2657 G28

VCC = 5.5V

GAIN ERROR OF 8 CHANNELS

REFERENCE VOLTAGE (V)

0.5

–64

GAIN ERROR (LSB)

–16

–32

–48

2.51 1.5

2657 G29

VCC = 5.5V

GAIN ERROR OF 8 CHANNELS

VCC (V)

2.5

ICC (nA)

400

350

300

250

200

150

100

450

3.0 5.0 5.53.5 4.0 4.5

2657 G30

LOGIC VOLTAGE (V)

2.0

ICC (mA)

3.6

3.2

2.8

2.4

4.0

15234

2657 G31

VCC = 5V

(LTC2657-H)

VCC = 3V

(LTC2657-L)

SWEEP SCL, SDA

BETWEEN OV AND VCC

TEMPERATURE (°C)

–50

2.0

SUPPLY CURRENT (mA)

3.5

3.0

2.5

4.0

–30 70 90 110 130–10 10 30

2657 G32

LTC2657-H

VCC = 5V, CODE = MID-SCALE

INTERNAL REFERENCE

LTC2657-L

VCC = 3V, CODE = MID-SCALE

INTERNAL REFERENCE

TEMPERATURE (°C)

–50

ICC SHUTDOWN (µA)

–30 70 90 110 130–10 10 30

2657 G33

LTC2657-H

VCC = 5V

LTC2657-L

VCC = 3V

FREQUENCY (Hz)

–12

AMPLITUDE (dB)

–2

–4

–6

–8

–10

1M10k

2657 G34

100k

VCC = 5V

VREF(DC) = 2V

VREF(AC) = 0.2VPP

CODE = FULL-SCALE

2µs/DIV

2657 G35

VOUT

0.5V/DIV VCC = 5V

VREF = 2.048V

ZERO SCALE

TO FULL SCALE

2µs/DIV

2657 G36

SCL

5V/DIV

VOUT

5mV/DIV

LTC2657-H16,

VCC = 5V

7nV-s TYP

LTC2657-L16,

VCC = 3V

4nV-s TYP

9th CLOCK OF

3RD DATA BYTE

LTC2657

2657f

2657 G38

200µs/DIV

VCC

2V/DIV

VOUT

10mV/DIV ZERO-SCALE

2657 G39

250µs/DIV

VCC

2V/DIV

VOUT

1V/DIV

LTC2657-H

FREQUENCY (Hz)

110

NOISE VOLTAGE (nV/√Hz)

200

400

600

800

100 1k 10k 100k 1M

2657 G40

1000

1200

LTC2657-H

LTC2657-L

VCC = 5V

CODE = MID-SCALE

INTERNAL REF

CREFCOMP = CREFOUT = 0.1µF

2µV/DIV

2657 G42

1 SEC/DIV

VREFOUT = 1.25V

CREFCOMP = CREFOUT = 0.1µF

Noise Voltage Density

vs Frequency

DAC Output 0.1Hz to 10Hz

Voltage Noise

Reference Output 0.1Hz to 10Hz

Voltage Noise

DAC to DAC Crosstalk (Dynamic) Power On Reset to Zero-Scale Power On Reset to Mid-Scale

5µV/DIV

2657 G41

1 SEC/DIV

VCC = 5V, VFS = 2.5V

CODE = MID-SCALE

INTERNAL REF

CREFCOMP = CREFOUT = 0.1µF

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2657

2µs/DIV

2657 G37

VOUT

0.5mV/DIV

ONE DAC

SWITCH FS-0

2V/DIV

LTC2657-H16, VCC = 5V, 0.8nV • s TYP

CREFCOMP = CREFOUT = 0.22µF

LTC2657

2657f

PIN FUNCTIONS

VOUTA to VOUTH (Pins 1, 3, 4, 13, 14, 15, 16, 20/Pins 2,

3, 5, 6, 15, 16, 17, 18): DAC Analog Voltage Outputs.

The output range is 0V to 2 times the voltage at the

REFIN/OUT pin.

REFCOMP (Pin 2/Pin 4): Internal Ref erence Compensation

pin. For low noise and reference stability, tie 0.1µF cap

to GND. Connect to GND to use an external reference

at start-up. Command 0111b must still be issued to

turn off internal reference.

REFIN/OUT (Pin 5/Pin 7): This pin acts as the Internal

Reference output in Internal Reference mode and acts

as the Reference Input pin in External Reference mode.

When acting as an output the nominal voltage at this

pin is 1.25V for-L Options and 2.048V for-H Options.

For low noise and reference stability tie a capacitor

to GND. Capacitor value must be <= CREFCOMP.

In External Reference mode, the allowable reference

input voltage range is 0.5V to

VCC/2

LDAC (Pin 6/Pin 8): Asynchronous DAC Update Pin.

A falling edge on this input after four bytes have been

written into the part immediately updates the DAC

on this input without a complete 32-bit (four bytes

including the slave address) data write transfer to the

part does not update the DAC output. Software power-

down is disabled when LDAC is low.

CA2 (Pin 9/Pin 7): Chip Address Bit 2. Tie this pin

to VCC, GND or leave it ﬂ oating to select an I2C slave

address for the part (See Table 2).

SCL (Pin 8/Pin 10): Serial Clock Input Pin. Data is

shifted into the SDA pin at the rising edges of the clock.

This high impedance pin requires a pull-up resistor or

current source to VCC.

SDA (Pin 9/Pin 11 ): Serial Data Bidi rectional Pin. Data

is shifted into the SDA pin and acknowledged by the

SDA pin. This is a high impedance pin while data is

shifted in. It is an open-drain N-channel output during

acknowledgement. This pin requires a pull-up resistor

or current source to VCC.

CA1 (Pin 10/Pin 12): Chip Address Bit 1. Tie this pin

to VCC, GND or leave it ﬂ oating to select an I2C slave

address for the part (See Table 2)

CA0 (Pin 11/Pin 13): Chip Address Bit 0. Tie this pin

to VCC, GND or leave it ﬂ oating to select an I2C slave

address for the part (See Table 2).

PORSEL (Pin 12/Pin 14): Power-On-Reset Select pin. If

tied to GND, the part resets to Zero-Scale at power up. If

tied to VCC, the part resets to Mid-Scale at power up.

VCC (Pin 17/Pin 19): Supply Voltage Input. For –L

Options, 2.7V ≤ VCC ≤ 5.5V, and for –H Options, 4.5V

≤ VCC ≤ 5.5V. Bypass to ground with a 0.1µF capacitor

placed as close to pin as possible.

GND (Pin 18/Pin 20): Ground.

REFLO (Pin 19/Pin 1): Reference Low pin. The voltage

at this pin sets the zero-scale voltage of all DACs. This

pin should be tied to GND.

Exposed Pad (Pin 21/Pin 21): Ground. Must be Soldered

to PCB Ground.

(QFN/TSSOP)

LTC2657

2657f

BLOCK DIAGRAM

TEST CIRCUIT

INTERNAL REFERENCE

POWER-ON RESET

REFCOMP REFIN/OUT

VCC

GND

DAC A

REF

DAC H VOUTH

DAC G VOUTG

DAC F VOUTF

DAC E VOUTE

PORSEL

SDA

SCL

REFLO

VOUTA

DAC B

VOUTB

DAC C

VOUTC

DAC D

VOUTD

CA2

LDAC

CA0

CA1

2-WIRE INTERFACE

32-BIT SHIFT REGISTER

2657 BD

1007

RINH/RINL/RINF

VIH(CAn)/VIL(CAn)

CAn

GND

2606 TC

VDD

Test Circuit 2Test Circuit 1

CAn

LTC2657

2657f

TIMING DIAGRAM

SDA

tLOW

tHD(STA)

ALL VOLTAGE LEVELS REFER TO VIH(MIN) AND VIL(MAX) LEVELS

tHD(DAT)

tSU(DAT)

tSU(STA)

tHD(STA)

tSU(STO)

tSP tBUF

tHIGH

SCL

SrP S 2657 F01

9TH CLOCK

OF 3RD

DATA BYTE

SCL

LDAC

2657 F01b

Figure 1

LTC2657

2657f

OPERATION

The LTC2657 is a family of octal voltage output DACs

in 20-lead 4mm × 5mm QFN and in 20-lead thermally

enhanced TSSOP packages. Each DAC can operate rail-

to-rail in external reference mode, or with its full-scale

voltage set by an integrated reference. Four combinations

of accuracy (16- and 12-bit), and full-scale voltage (2.5V

or 4.096V) are available. The LTC2657 is controlled using

a 2-wire I2C compatible interface.

Power-On Reset

The LTC2657-L/-H clear the output to zero-scale if the

PORSEL pin is tied to GND when power is ﬁ rst applied,

making system initialization consistent and repeatable. For

some applications, downstream circuits are active during

DAC power-up, and may be sensitive to nonzero outputs

from the DAC during this time. The LTC2657 contains

circuitry to reduce the power-on glitch. The analog outputs

typically rise less than 10mV above zero-scale during power

on if the power supply is ramped to 5V in 1ms or more. In

general, the glitch amplitude decreases as the power supply

ramp time is increased. See “Power-On Reset Glitch” in

the Typical Performance Characteristics section.

Alternatively, if PORSEL is tied to VCC, The LTC2657-L/-H

set the output to mid-scale when power is ﬁ rst applied.

Power Supply Sequencing and Start-Up

For the LTC2657 family of parts, the internal reference is

powered-up at start-up by default. If an external reference is

to be used, the REFCOMP pin (Pin 4 –TSSOP, Pin 2 -QFN )

must be hardwired to GND. This conﬁ guration allows the

use of an external reference at start-up and converts the

REFIN/OUT pin to an input. However, the internal reference

will still be ON and draw supply current. In order to use

an external reference, command 0111b should be used

to turn the Internal Reference OFF.(See Table1.)

The voltage at REFIN/OUT (Pin 7 –TSSOP, Pin 5 -QFN)

should be kept within the range –0.3V ≤ REFIN/OUT

≤ VCC + 0.3V (see Absolute Maximum Ratings). Particular

care should be taken to observe these limits during power

supply turn-on and turn-off sequences, when the voltage

at VCC (Pin 19 –TSSOP, Pin 17 -QFN ) is in transition.

Transfer Function

The digital-to-analog transfer function is:

VkV REFLO REFL

OUT IDEAL NREF() •=

⎛

⎝

⎜

⎞

⎠

⎟•−

⎡

⎣⎤

⎦+

22OO

where k is the decimal equivalent of the binary DAC input

code, N is the resolution, and VREF is the voltage at the

REFIN/OUT Pin. The resulting DAC output span is 0V to

2 • VREF, as it is necessary to tie REFLO to GND. VREF is

nominally 1.25V for LTC2657-L and 2.048V for LTC2657-H,

in Internal Reference Mode.

Table 1. Command and Address Codes

COMMAND*

C3 C2 C1 C0

0 0 0 0 Write to Input Register n

0 0 0 1 Update (Power Up) DAC Register n

0 0 1 0 Write to Input Register n, Update (Power Up) All

0 0 1 1 Write to and Update (Power Up) n

0 1 0 0 Power Down n

0 1 0 1 Power Down Chip (All DACs and Reference)

0 1 1 0 Select Internal Reference (Power-Up Reference)

0 1 1 1 Select External Reference (Power-Down

Reference)

1 1 1 1 No Operation

ADDRESS (n)*

A3 A2 A1 A0

0 0 0 0 DAC A

0 0 0 1 DAC B

0 0 1 0 DAC C

0 0 1 1 DAC D

0 1 0 0 DAC E

0 1 0 1 DAC F

0 1 1 0 DAC G

0 1 1 1 DAC H

1 1 1 1 All DACs

*Command and address codes not shown are reserved and should not be used.

Serial Interface

The LTC2657 communicates with a host using the stan-

dard 2-wire I2C interface. The Timing Diagrams (Figures

1 and 2) show the timing relationship of the signals on

the bus. The two bus lines, SDA and SCL, must be high

when the bus is not in use. External pull-up resistors or

current sources are required on these lines. The value of

LTC2657

2657f

OPERATION

these pull-up resistors is dependent on the power supply

and can be obtained from the I2C speciﬁ cations. For an

I2C bus operating in the fast mode, an active pull-up will

be necessary if the bus capacitance is greater than 200pF.

The LTC2657 is a receive-only (slave) device. The master

can write to the LTC2657. The LTC2657 does not respond

to a read command from the master.

The START (S) and STOP (P) Conditions

When the bus is not in use, both SCL and SDA must be high.

A bus master signals the beginning of a communication

to a slave device by transmitting a START condition (See

Figure 1). A START condition is generated by transitioning

SDA from high to low while SCL is high. When the master

has ﬁ nished communicating with the slave, it issues a STOP

condition. A STOP condition is generated by transitioning

SDA from low to high while SCL is high. The bus is then

free for communication with another I2C device.

Acknowledge

The Acknowledge signal is used for handshaking between

the master and the slave. An Acknowledge (active LOW)

generated by the slave lets the master know that the

latest byte of information was received. The Acknowledge

related clock pulse is generated by the master. The master

releases the SDA line (HIGH) during the Acknowledge

clock pulse. The slave-receiver must pull down the SDA

bus line during the Acknowledge clock pulse so that it

remains a stable LOW during the HIGH period of this clock

pulse. The LTC2657 responds to a write by a master in

this manner. The LTC2657 does not acknowledge a read

(retains SDA HIGH during the period of the Acknowledge

clock pulse).

Chip Address

The state of CA0, CA1 and CA2 decides the slave address

of the part. The pins CA0, CA1 and CA2 can be each set

to any one of three states: VCC, GND or ﬂ oat. This results

in 27 selectable addresses for the part. The slave address

assignments are shown in Table 2.

Table 2. Slave Address Map

CA2 CA1 CA0 A6 A5 A4 A3 A2 A1 A0

GND GND GND 0 0 1 0 0 0 0

GND GND FLOAT 0 0 1 0 0 0 1

GND GND VCC 0010010

GND FLOAT GND 0 0 1 0 0 1 1

GND FLOAT FLOAT 0 1 0 0 0 0 0

GND FLOAT VCC 0100001

GND VCC GND0100010

GND VCC FLOAT 0 1 0 0 0 1 1

GND VCC VCC 0110000

FLOAT GND GND 0 1 1 0 0 0 1

FLOAT GND FLOAT 0 1 1 0 0 1 0

FLOAT GND VCC 0110011

FLOAT FLOAT GND 1 0 0 0 0 0 0

FLOAT FLOAT FLOAT 1 0 0 0 0 0 1

FLOAT FLOAT VCC 1000010

FLOAT VCC GND1000011

FLOAT VCC FLOAT 1 0 1 0 0 0 0

FLOAT VCC VCC 1010001

VCC GND GND 1 0 1 0 0 1 0

VCC GND FLOAT 1 0 1 0 0 1 1

VCC GND VCC 1100000

VCC FLOAT GND 1 1 0 0 0 0 1

VCC FLOAT FLOAT 1 1 0 0 0 1 0

VCC FLOAT VCC 1100011

VCC VCC GND1110000

VCC VCC FLOAT 1 1 1 0 0 0 1

VCC VCC VCC 1110010

GLOBAL ADDRESS 1 1 1 0 0 1 1

In addition to the address selected by the address pins, the

parts also respond to a global address. This address allows

a common write to all LTC2657 parts to be accomplished

with one 3-byte write transaction on the I2C bus. The

global address is a 7-bit on-chip hardwired address and

is not selectable by CA0, CA1 and CA2. The addresses

corresponding to the states of CA0, CA1 and CA2 and

the global address are shown in Table 2. The maximum

capacitive load allowed on the address pins (CA0, CA1

and CA2) is 10pF, as these pins are driven during address

detection to determine if they are ﬂ oating.

LTC2657

2657f

OPERATION

Write Word Protocol

The master initiates communication with the LTC2657

with a START condition and a 7-bit slave address followed

by the Write bit (W) = 0. The LTC2657 acknowledges by

pulling the SDA pin low at the 9th clock if the 7-bit slave

address matches the address of the part (set by CA0, CA1

and CA2) or the global address. The master then transmits

three bytes of write data. The LTC2657 acknowledges each

byte of data by pulling the SDA line low at the 9th clock of

each data byte transmission. After receiving three complete

bytes of data, the LTC2657 executes the command speciﬁ ed

in the 24-bit input word. If more than three data bytes are

transmitted after a valid 7-bit slave address, the LTC2657

does not acknowledge the extra bytes of data (SDA is

high during the 9th clock). The ﬁ rst byte of the input word

consists of the 4-bit command followed by 4-bit address.

The next two bytes consist of the 16-bit data word. The

16-bit data word consists of the 16- or 12-bit input code,

MSB to LSB, followed by 0 or 4 don’t care bits (LTC2657-

16 and LTC2657-12, respectively). A typical LTC2657 write

transaction is shown in Figure 2. The command (C3-C0)

and address (A3-A0) assignments are shown in Table 1.

The ﬁ rst four commands in the table consist of write and

update operations. A write operation loads a 16-bit data

word from the 32-bit shift register into the input register.

In an update operation, the data word is copied from the

input register to the DAC register and converted to an analog

voltage at the DAC output. The update operation also powers

up the DAC if it had been in power-down mode. The data

path and registers are shown in the Block Diagram.

Power-Down Mode

For power-constrained applications, power-down mode

can be used to reduce the supply current whenever less

than eight outputs are needed. When in power-down, the

buffer ampliﬁ ers, bias circuits and integrated reference

circuits are disabled, and draw essentially zero current.

The DAC outputs are put into a high-impedance state, and

the output pins are passively pulled to ground through

individual 80k resistors. Input- and DAC-register contents

are not disturbed during power-down.

Any channel or combination of channels can be put

into power-down mode by using command 0100b in

combination with the appropriate DAC address, (n). The

integrated reference is automatically powered down when

external reference mode is selected using command

0111b. In addition, all the DAC channels and the integrated

reference together can be put into power-down mode

using “Power-Down Chip” command 0101b. For all power-

down commands the 16-bit data word is ignored, but still

required in order to complete a full communication cycle.

Normal operation resumes by executing any command

which includes a DAC update, in software as shown in Table

1 or using the asynchronous LDAC pin. The selected DAC

is powered up as its voltage output is updated. When a

DAC which is in a powered-down state is powered up and

updated, normal settling is delayed. If less than eight DACs

are in a powered-down state prior to the update command,

the power-up delay time is 12s. If on the other hand,

all eight DACs and the integrated reference are powered

down, then the main bias generation circuit block has been

automatically shut down in addition to the individual DAC

ampliﬁ ers and reference inputs. In this case, the power

up delay time is 14s. The power up of the integrated

reference depends on the command that powered it down.

If the reference is powered down using the “Select External

Reference” command (0111b), then it can only be powered

back up by sending “Select Internal Reference” command

(0110b). However if the reference was powered down by

sending “Power Down Chip” command (0101b), then in

addition to “Select Internal Reference” command (0110b),

any command that powers up the DACs will also power

up the integrated reference.

Reference Modes

For applications where an accurate external reference is

not available, the LTC2657 has a user-selectable, integrated

reference. The LTC2657-L has a 1.25V reference that

provides a full-scale output of 2.5V. The LTC2657-H has

a 2.048V reference that provides a full-scale output of

4.096V. Both references exhibit a typical temperature drift

of 2ppm/°C. Internal Reference mode can be selected

by using command 0110b, and is the power-on default.

A buffer is needed if the internal reference is required to

drive external circuitry. For reference stability and low

noise, it is recommended that a 0.1µF capacitor be tied

between REFCOMP and GND. In this conﬁ guration, the

LTC2657

2657f

internal reference can drive up to 0.1µF capacitive load

without any stability problems. In order to ensure stable

operation, the capacitive load on the REFIN/OUT pin should

not exceed the capacitive load on the REFCOMP pin.

The DAC can also operate in External Reference mode using

command 0111b. In this mode, the REFIN/OUT pin acts as

an input that sets the DAC’s reference voltage. The input is

high impedance and does not load the external reference

source. The acceptable voltage range at this pin is 0.5V ≤

REFIN/OUT ≤ VCC/2. The resulting full-scale output voltage

is 2 • VREFIN/OUT. For using External Reference at Start-Up,

see the Power Supply Sequencing and Start-Up Section.

Integrated Reference Buffers

Each of the eight DACs in LTC2657 has its own integrated

high performance reference buffer. The buffers have very

high input impedance and do not load the reference voltage

source. These buffers shield the Reference Voltage from

glitches caused by DAC switching and thus minimize

DAC-to-DAC Dynamic Crosstalk. See the curve DAC-

to-DAC Crosstalk (Dynamic) in the Typical Performance

Characteristics section.

Voltage Outputs

Each of the eight rail-to-rail ampliﬁ ers contained in LTC2657

has guaranteed load regulation when sourcing or sinking

up to 15mA at 5V (7.5mA at 3V).

Load regulation is a measure of the ampliﬁ er’s ability to

maintain the rated voltage accuracy over a wide range of

load conditions. The measured change in output voltage

per milliampere of forced load current change is expressed

in LSB/mA.

DC output impedance is equivalent to load regulation, and

may be derived from it by simply calculating a change in units

from LSB/mA to Ohms. The ampliﬁ ers’ DC output impedance

is 0.040 when driving a load well away from the rails.

When drawing a load current from either rail, the output

voltage headroom with respect to that rail is limited by the

30 typical channel resistance of the output devices; e.g.,

when sinking 1mA, the minimum output voltage = 30 • 1mA

= 30mV. See the graph Headroom at Rails vs Output Current

in the Typical Performance Characteristics section.

OPERATION

The ampliﬁ ers are stable driving capacitive loads of up

to 1000pF.

Board Layout

The excellent load regulation and DC crosstalk performance

of these devices is achieved in part by keeping “signal”

and “power” grounds separate.

The PC board should have separate areas for the analog

and digital sections of the circuit. This keeps digital signals

away from sensitive analog signals and facilitates the use

of separate digital and analog ground planes which have

minimal capacitive and resistive interaction with each

other.

Digital and analog ground planes should be joined at only

one point, establishing a system star ground as close to

the device’s ground pin as possible. Ideally, the analog

ground plane should be located on the component side of

the board, and should be allowed to run under the part to

shield it from noise. Analog ground should be a continuous

and uninterrupted plane, except for necessary lead pads

and vias, with signal traces on another layer.

The GND pin functions as a return path for power supply

currents in the device and should be con-nected to analog

ground. The REFLO pin should be connected to system

star ground. Resistance from the REFLO pin to system

star ground should be as low as possible.

Rail-to-Rail Output Considerations

In any rail-to-rail voltage output device, the output is limited

to voltages within the supply range.

Since the analog outputs of the device cannot go below

ground, they may limit for the lowest codes as shown in

Figure 3b. Similarly, limiting can occur in External Refer-

ence mode near full-scale when the REFIN/OUT pin is at

VCC/2 . If VREFIN/OUT = VCC/2 and the DAC full-scale error

(FSE) is positive, the output for the highest codes limits

at VCC as shown in Figure 3c. No full-scale limiting can

occur if VREFIN/OUT ≤ (VCC – FSE)/2.

Offset and linearity are deﬁ ned and tested over the region

of the DAC transfer function where no output limiting can

occur.

LTC2657

2657f

OPERATION

ACK ACK

123456789123456789123456789123456789

2657 F02

ACK

START STOP

FULL-SCALE

VOLTAGE

ZERO-SCALE

VOLTAGE

SDA SA6 SA5 SA4 SA3 SA2 SA1 SA0

SCL

VOUT

C2C3

C3 C2 C1 C0 A3 A2 A1 A0

C1 C0 A3 A2 A1 A0 ACK

COMMAND/ADDRESS BYTE

D15 D14 D13 D12 D11 D10 D9 D8

MS DATA BYTE

D7 D6 D5 D4 D3 D2 D1 D0

LS DATA BYTE

SA6 SA5 SA4 SA3 SA2 SA1 SA0 WR

SLAVE ADDRESS

Figure 2. Typical LTC2657 Input Waveform –Programming DAC Output for Full-Scale

LTC2657

2657f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

OPERATION

2657 F03

INPUT CODE

(b)

OUTPUT

VOLTAGE

NEGATIVE

OFFSET

32, 7680 65, 535

INPUT CODE

OUTPUT

VOLTAGE

(a)

VREF = VCC

(c)

INPUT CODE

OUTPUT

VOLTAGE

POSITIVE

FSE

Figure 3. Effects of Rail-to-Rail Operation on a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of

Negative Offset for Codes Near Zero-Scale (c) Effect of Positive Full-Scale Error for Codes Near Full-Scale

FE20 (CB) TSSOP 0204

0.09 – 0.20

(.0035 – .0079)

0° – 8°

0.25

REF

RECOMMENDED SOLDER PAD LAYOUT

0.50 – 0.75

(.020 – .030)

4.30 – 4.50*

(.169 – .177)

134

5678910

111214 13

6.40 – 6.60*

(.252 – .260)

3.86

(.152)

2.74

(.108)

20 1918 17 16 15

1.20

(.047)

MAX

0.05 – 0.15

(.002 – .006)

0.65

(.0256)

BSC 0.195 – 0.30

(.0077 – .0118)

TYP

2.74

(.108)

0.45 ±0.05

0.65 BSC

4.50 ±0.10

6.60 ±0.10

1.05 ±0.10

3.86

(.152)

MILLIMETERS

(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.150mm (.006") PER SIDE

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

SEE NOTE 4

4. RECOMMENDED MINIMUM PCB METAL SIZE

FOR EXPOSED PAD ATTACHMENT

6.40

(.252)

BSC

PACKAGE DESCRIPTION

FE Package

20-Lead Plastic TSSOP (4.4mm)

(Reference LTC DWG # 05-08-1663)

Exposed Pad Variation CB

LTC2657

2657f

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

LT 0909 • PRINTED IN USA

PACKAGE DESCRIPTION

UFD Package

20-Lead Plastic QFN (4mm × 5mm)

(Reference LTC DWG # 05-08-1711 Rev B)

4.00 ± 0.10

(2 SIDES)

5.00 ± 0.10

(2 SIDES)

NOTE:

1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

PIN 1

TOP MARK

(NOTE 6)

0.75 ± 0.05

0.200 REF

0.00 – 0.05

1.50 REF

0.40 ± 0.10

19 20

BOTTOM VIEW—EXPOSED PAD

2.50 REF

R = 0.115

TYP

PIN 1 NOTCH

R = 0.20 OR

C = 0.35

0.25 ± 0.05

0.50 BSC

(UFD20) QFN 0506 REV B

R = 0.05 TYP

2.65 ± 0.10

3.65 ± 0.10

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.70 ±0.05

0.25 ±0.05

2.65 ± 0.05

2.50 REF

4.10 ± 0.05

5.50 ± 0.05

1.50 REF

3.10 ± 0.05

4.50 ± 0.05

PACKAGE

OUTLINE

3.65 ± 0.05

0.50 BSC

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

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