LTC1450/LTC1450L Parallel Input, 12-Bit Rail-to-Rail Micropower DACs in SSOP DESCRIPTION U FEATURES The LTC(R)1450/LTC1450L are complete single supply, railto-rail voltage output, 12-bit digital-to-analog converters (DACs) in a 24-pin SSOP or PDIP package. They include an output buffer amplifier, reference and a double buffered parallel digital interface. Guaranteed Monotonic Buffered True Rail-to-Rail Voltage Output 12-Bit Resolution 3V Operation (LTC1450L) ICC: 250A Typ 5V Operation (LTC1450) ICC: 400A Typ Parallel 12-Bit or 8 + 4-Bit Double Buffered Digital Input Internal Reference Output Buffer Configurable to Gain of 1 or 2 Configurable as a Multiplying DAC Internal Power-On Reset Maximum DNL Error: 0.5LSB The LTC1450 operates from a 4.5V to 5.5V supply. The output can be pin strapped for 4.095V or 2.048V full-scale. It has a 2.048V internal reference. The LTC1450L operates from a 2.7V to 5.5V supply. The output can be pin strapped for 2.5V or 1.22V full-scale. It has a 1.22V internal reference. U APPLICATIONS The LTC1450/LTC1450L offer true stand-alone performance. In addition, the reference output, high and low reference inputs and gain setting resistor are brought to pins for maximum flexibility. Digital Calibration Industrial Process Control Automatic Test Equipment Arbitrary Function Generators Battery-Powered Data Conversion Products Feedback Control Loops and Gain Control , LTC and LT are registered trademarks of Linear Technology Corporation. U TYPICAL APPLICATION LTC1450: 5V LTC1450L: 3V TO 5V REFOUT D11 (MSB) DATA IN FROM MICROPROCESSOR DATA BUS D7 VCC REFHI REFERENCE LTC1450: 2.048V LTC1450L: 1.22V 12-BIT DAC LATCH Differential Nonlinearity vs Input Code 0.5 12-BIT DAC + LOWER 8-BIT INPUT LATCH VOUT - D0 (LSB) CSMSB FROM MICROPROCESSOR DECODE LOGIC 0.0 WR CSLSB LDAC FROM SYSTEM RESET LTC1450: 0V TO 4.095V LTC1450L: 0V TO 2.5V DNL ERROR (LSB) D8 UPPER 4-BIT INPUT LATCH CLR -0.5 0 POWER-ON RESET GND REFLO X1/X2 LTC1450 LTC1450L 512 1024 1536 2048 2560 3072 3584 4095 CODE 1450/50L TA02 1450/50L TA01 1 LTC1450/LTC1450L U W U U W W W ABSOLUTE MAXIMUM RATINGS PACKAGE/ORDER INFORMATION VCC to GND .............................................. - 0.5V to 7.5V Logic Inputs to GND ................................ - 0.5V to 7.5V VOUT .............................................. - 0.5V to VCC + 0.5V REFOUT, REFLO, REFHI, X1/X2 ..... - 0.5V to VCC + 0.5V Maximum Junction Temperature .......................... 125C Operating Temperature Range Commercial ........................................... 0C to 70C Industrial ......................................... - 40C to 85C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C ORDER PART NUMBER TOP VIEW WR 1 24 LDAC CSLSB 2 23 CLR CSMSB 3 22 X1/X2 (LSB) D0 4 21 VOUT D1 5 20 VCC D2 6 19 REFOUT D3 7 18 REFHI D4 8 17 REFLO D5 9 16 GND D6 10 15 D11(MSB) D7 11 14 D10 D8 12 13 D9 G PACKAGE 24-LEAD PLASTIC SSOP LTC1450CG LTC1450CN LTC1450IG LTC1450IN LTC1450LCG LTC1450LCN LTC1450LIG LTC1450LIN N PACKAGE 24-LEAD PLASTIC PDIP TJMAX = 125C, JA = 95C/ W (G) TJMAX = 125C, JA = 58C/ W (N) Consult factory for Military grade parts. ELECTRICAL CHARACTERISTICS VCC = 4.5V to 5.5V (LTC1450), 2.7V to 5.5V (LTC1450L), VOUT unloaded, REFOUT = REFHI, REFLO = GND = X1/X2, TA = TMIN to TMAX, unless otherwise noted. SYMBOL PARAMETER DAC Resolution DNL Differential Nonlinearity INL Integral Nonlinearity VOS Offset Error VOS TC VFS Offset Error Temperature Coefficient Full-Scale Voltage CONDITIONS MIN Guaranteed Monotonic (Note 1) TA = 25C (Note 1) TA = 25C TYP 12 0.5 3.5 4.0 12 18 VFS TC Full-Scale Voltage Temperature Coefficient Reference Output (REFOUT) Reference Output Voltage Reference Output Temperature Coefficient Reference Line Regulation Reference Load Regulation Short-Circuit Current 2 Using Internal Reference, LTC1450, TA = 25C Using Internal Reference, LTC1450 External 2.048V Reference, LTC1450 Using Internal Reference, LTC1450L, TA = 25C Using Internal Reference, LTC1450L External 1.22V Reference, LTC1450L Using Internal Reference, LTC1450 Using External Reference, LTC1450/LTC1450L Using Internal Reference, LTC1450L LTC1450L LTC1450 4.065 4.045 4.075 2.470 2.460 2.480 1.195 2.008 0 IOUT 100A, LTC1450L LTC1450 REFOUT Shorted to GND MAX 15 4.095 4.095 4.095 2.500 2.500 2.500 0.10 0.02 0.10 1.220 2.048 0.08 0.7 0.6 0.2 4.125 4.145 4.115 2.530 2.540 2.520 1.245 2.088 2 3.0 1.5 80 UNITS Bits LSB LSB LSB mV mV V/C V V V V V V LSB/C LSB/C LSB/C V V LSB/C LSB/V LSB LSB mA LTC1450/LTC1450L ELECTRICAL CHARACTERISTICS VCC = 4.5V to 5.5V (LTC1450), 2.7V to 5.5V (LTC1450L), VOUT unloaded, REFOUT = REFHI, REFLO = GND = X1/X2, TA = TMIN to TMAX, unless otherwise noted. SYMBOL PARAMETER Reference Input (REFLO = GND) REFHI Input Range REFHI Input Resistance REFHI Input Capacitance Power Supply Positive Supply Voltage VCC ICC Supply Current Op Amp DC Performance Short-Circuit Current Low Short-Circuit Current High Output Impedance to GND AC Performance Voltage Output Slew Rate Voltage Output Settling Time Digital Feedthrough AC Feedthrough SINAD Signal-to-Noise + Distortion Digital Inputs VIH Digital Input High Voltage VIL Digital Input Low Voltage VLTH ILEAK CIN Logic Threshold Voltage Digital Input Leakage Digital Input Capacitance CONDITIONS MIN TYP 8 18 15 For Specified Performance, LTC1450L LTC1450 4.5V VCC 5.5V (Note 4) LTC1450 2.7V VCC 5.5V (Note 4) LTC1450L 2.7 4.5 300 150 VOUT Shorted to GND VOUT Shorted to VCC Input Code = 0 (Note 2) (Notes 2, 3) to 0.5LSB LDAC = 1 REFHI = 1kHz, 2VP-P REFHI = 1kHz, 2VP-P (Code: All 1's) 0.5 VCC = 3V, LTC1450L VCC = 5V, LTC1450 VCC = 3V, LTC1450L VCC = 5V, LTC1450 LTC1450L VCC = 5V, VIN = GND to VCC Guaranteed by Design. Not Subject to Test 2.2 2.4 VREFHI VCC - 1.5V MAX UNITS VCC /2 30 V k pF 400 250 5.5 5.5 620 500 V V A A 40 100 120 120 mA mA 1.0 14 5 - 95 85 V/s s (nV)(s) dB dB 0.8 0.8 VCC/2 - 10 10 10 V V V V V A pF 3 LTC1450/LTC1450L ELECTRICAL CHARACTERISTICS VCC = 4.5V to 5.5V (LTC1450), VCC = 2.7V to 3.6V (LTC1450L), TA = TMIN to TMAX, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Switching Characteristics (Note 5) tCS CS (MSB or LSB) Pulse Width 40 ns tWR WR Pulse Width 40 ns tCWS CS to WR Setup 0 ns tCWH CS to WR Hold 0 ns tDWS Data Valid to WR Setup VCC = 4.5V to 5.5V (LTC1450) VCC = 2.7V to 3.6V (LTC1450L) VCC = 5V (LTC1450L) 40 40 15 15 10 ns ns ns tDWH Data Valid to WR Hold VCC = 4.5V to 5.5V (LTC1450) VCC = 2.7V to 3.6V (LTC1450L) VCC = 5V (LTC1450L) 0 0 - 10 - 10 -5 ns ns ns tLDAC LDAC Pulse Width 40 ns tCLR CLR Pulse Width 40 ns The denotes specifications which apply over the full operating temperature range. Note 1: Nonlinearity is defined from the first code that is greater than or equal to the maximum offset specification to code 4095 (full-scale). Note 2: Load is 5k in parallel with 100pF. Note 3: DAC switched all 1's and the code corresponding to VOS(MAX) for the part. Note 4: Digital inputs at 0V or VCC. Note 5: Digital inputs swing 10% to 90% of VCC, tr = tf = 5ns and timing measurements are from VCC/2. U W TYPICAL PERFORMANCE CHARACTERISTICS Minimum Supply Voltage vs Load Current 4.0 3.8 5.2 3.6 3.4 5.0 4.8 3.2 4.6 3.0 4.4 2.8 4.2 2.6 4.0 0.01 0.1 1 10 LOAD CURRENT (mA) 2.4 100 1450/50L G01 4 Supply Current vs Logic Input Voltage 450 8 440 7 VCC = 5V ALL LOGIC INPUTS TIED TOGETHER 430 420 410 SUPPLY CURRENT (mA) 5.4 4.2 VOUT < 1LSB LTC1450 LTC1450L SUPPLY CURRENT (A) 5.6 LTC1450L MINIMUM SUPPLY VOLTAGE (V) LTC1450 MINIMUM SUPPLY VOLTAGE (V) 5.8 LTC1450 Supply Current vs Temperature VCC = 5.5V VCC = 5V 400 390 VCC = 4.5V 380 370 LTC1450 5 LTC1450L 4 3 2 1 360 350 - 55 - 35 -15 6 5 25 45 65 85 105 125 TEMPERATURE (C) 1450/50L G02 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 LOGIC INPUT VOLTAGE (V) 1450/50L G03 LTC1450/LTC1450L U W TYPICAL PERFORMANCE CHARACTERISTICS 4.5 1600 VCC = 3V ALL LOGIC INPUTS TIED TOGETHER 800 600 FULL SCALE RL TIED TO GND 3.5 1200 1000 1000 4.0 OUTPUT SWING (V) SUPPLY CURRENT (A) 1400 400 3.0 2.5 VCC = 5V 2.0 1.5 1.0 200 0 LTC1450 Pull-Down Voltage vs Output Sink Current Capability LTC1450 Output Swing vs Load Resistance ZERO SCALE RL TIED TO VCC 0.5 OUTPUT PULL-DOWN VOLTAGE (mV) LTC1450L Supply Current vs Logic Input Voltage 0 0 10 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 LOGIC INPUT VOLTAGE (V) 100 1k LOAD RESISTANCE () 125C 100 25C 10 -55C 1 0.1 0.0001 0.001 0.01 0.1 1 10 OUTPUT SINK CURRENT (mA) 10k 1450/50L G06 1450/50L G05 1450/50L G04 LTC1450 Output Offset Voltage vs Temperature LTC1450 Integral Nonlinearity (INL) LTC1450 Differential Nonlinearity (DNL) 0.2 5.0 100 2 3.5 3.0 2.5 2.0 1.5 ERROR (LSB) 4.0 DNL ERROR (LSB) OUTPUT OFFSET VOLTAGE (mV) 4.5 0 0 1.0 0.5 0 - 55 -35 -15 - 0.2 512 1024 1536 2048 2560 3072 3584 4095 CODE 0 5 25 45 65 85 105 125 TEMPERATURE (C) CODE = FFFH 70 PSRR (dB) 60 50 VOUT REFOUT 30 20 10 0 1 10 1k 100 FREQUENCY (Hz) LTC1450 Broadband Output Noise 10k 10M 1450/50L G10 -40 -50 VCC = 5V VREFHI = 2VP-P VOUT = 4VP-P CODE = FFFH X1/X2 = GND BW = 3Hz to 1.2MHz TOTAL = 0.35mVRMS -60 1mV/DIV 90 512 1024 1536 2048 2560 3072 3584 4095 CODE 1450/50L G09 LTC1450 Total Harmonic Distortion + Noise vs Frequency TOTAL HARMONIC DISTORTION + NOISE (dB) Power Supply Rejection vs Frequency 40 0 1450/50L G08 1450/50L G07 80 -2 -70 -80 -90 -100 100 1k 10k FREQUENCY (Hz) 100k 1450/50L G11 5ms/DIV 1450/50L G12 5 LTC1450/LTC1450L U W TYPICAL PERFORMANCE CHARACTERISTICS LTC1450 Midscale Transition Data = 2048 to 2047 LTC1450 Large-Scale Settling (Rising) LTC1450 Large-Scale Settling (Falling) DATA INPUTS RISING EDGE 20mV/DIV VOUT DATA INPUTS FALLING EDGE 5V 5V 0V 0V 4V 4V 3V 2V LDAC 3V VOUT NO LOAD 2V 5V 1V 1V 0V 0V 0V 500ns/DIV 2s/DIV 2s/DIV 1450/50L G13 1450/50L G14 Output Voltage Full-Scale Settling 0V DATA IN 000H TO FFFH 1450/50L G15 Output Voltage Zero-Scale Settling 5V 5V VOUT NO LOAD LTC1450 Digital Feedthrough 4V DATA IN FFFH TO 000H 0V 0V ALL DATA INPUTS TOGGLING VOUT 1mV/DIV VOUT 1mV/DIV OUTPUT LOAD 5k//10pF OUTPUT LOAD 5k//10pF 5s/DIV 6 2s/DIV 5s/DIV 1450/50L G16 VOUT = 5mV/DIV VOUT(DC) = 4V RL = NO LOAD 1450/50L G17 1450/50L G18 LTC1450/LTC1450L U U U PIN FUNCTIONS WR (Pin 1): Write Input (Active Low). Used with CSMSB and/or CSLSB to load data into the input latches. While WR and CSMSB and/or CSLSB are held low the enabled input latches are transparent. The rising edge of WR will latch data into all input latches. CSLSB (Pin 2): Chip Select Least Significant Byte (Active Low). Used with WR to load data into the eight LSB input latches. While WR and CSLSB are held low the eight LSB input latches are transparent. The rising edge will latch data into the eight LSB input latches. Can be connected to CSMSB for simultaneous loading of both sets of input latches on a 12-bit bus. CSMSB (Pin 3): Chip Select Most Significant Byte (Active Low). Used with WR to load data into the four MSB input latches. While WR and CSMSB are held low the four MSB input latches are transparent. The rising edge will latch data into the four MSB input latches. Can be connected to CSLSB for simultaneous loading of both sets of input latches on a 12-bit bus. An input code of (000H) will connect the positive input of the output buffer to this end. Can be used to offset the zero scale above ground. REFHI (Pin 18): Upper input terminal of the DAC's internal resistor string. Typically connected to REFOUT. An input code of (FFFH) will connect the positive input of the output buffer to 1LSB from this end. REFOUT (Pin 19): Output of the internal 2.048V/1.22V reference. Typically connected to REFHI to drive internal DAC resistor string. VCC (Pin 20): Positive Power Supply Input. 4.5V VCC 5.5V (LTC1450) and 2.7V VCC 5.5V (LTC1450L). Requires a bypass capacitor to ground. VOUT (Pin 21): Buffered DAC Output. X1/X2 (Pin 22): Gain Setting Resistor Pin. Connect to GND for G = 2 or to VOUT for G = 1. Should always be tied to a low impedance source, such as ground or VOUT, to ensure stability of the output buffer when driving capacitive loads. D0 to D7 (Pins 4 to 11): Input data for the Least Significant Byte. Loaded into LSB input latch when WR = 0 and CSLSB = 0. CLR (Pin 23): Clear Input (Asynchronous Active Low). A low on this pin asynchronously resets all internal latches to 0s. D8, D9, D10, D11 (Pins 12, 13, 14, 15): Input data for the Most Significant Byte. Loaded into MSB input latch when WR = 0 and CSMSB = 0. Can be connected to D0 to D3 for multiplexed operation on an 8-bit bus. LDAC (Pin 24): Load DAC (Asynchronous Active Low). Used to asynchronously transfer the contents of the input latches to the DAC latches which updates the output voltage. The rising edge latches the data into the DAC latches. If held low the DAC latches are transparent and data from the input latches will immediately update VOUT. GND (Pin 16): Ground. REFLO (Pin 17): Lower input terminal of the DAC's internal resistor string. Typically connected to Analog Ground. 7 LTC1450/LTC1450L U DIGITAL INTERFACE TRUTH TABLE CLR CSMSB CSLSB WR LDAC H H H H H H H H H H L H H H L L H H L L X L L H H H H H L L X L L L L H H L L X H H H H H H L L X FUNCTION Loads the eight LSBs into the input latch Latches the eight LSBs into the input latch Latches the eight LSBs into the input latch Loads the four MSBs into the input latch Latches the four MSBs into the input latch Latches the four MSBs into the input latch Loads the input latch data into the DAC latch Latches the input latch data into the DAC latch Loads input data into DAC latches (latches transparent) Latches input data into DAC latches All zeros loaded into input and DAC latches W UW TIMING DIAGRAM t CS CSLSB t CS CSMSB t WR t CWS t CWH t WR WR t LDAC LDAC t DWH t DWS DAC UPDATE DATA VALID DATA DATA VALID LTC1450/50L * TD01 W BLOCK DIAGRAM 20 VCC 19 18 17 22 REFOUT REFHI REFLO X1/X 2 - VOUT 21 REFERENCE LTC1450: 2.048V LTC1450L: 1.22V + DAC GND 24 LDAC 12-BIT DAC LATCH 23 CLR 3 CSMSB 1 WR POWER-ON RESET UPPER 4-BIT INPUT LATCH LOWER 8-BIT INPUT LATCH 2 CSLSB D11 (MSB) D10 D9 D8 D0 D7 D6 D5 D4 D3 D2 D1 (LSB) 15 11 10 9 14 13 12 8 7 6 5 4 LTC1450/50L * BD 8 16 LTC1450/LTC1450L U U DEFI ITIO S Resolution (n): Resolution is defined as the number of digital input bits (n). It defines the number of DAC output states (2n) that divide the full-scale range. The resolution does not imply linearity. Full-Scale Voltage (VFS): This is the output of the DAC when all bits are set to 1. Voltage Offset Error (VOS): The theoretical voltage at the output when the DAC is loaded with all zeros. The output amplifier can have a true negative offset, but because the part is operated from a single supply, the output cannot go below zero. If the offset is negative, the output will remain near 0V resulting in the transfer curve shown in Figure 1. The offset of the part is measured at the code that corresponds to the maximum offset specification: VOS = VOUT - [(Code)(VFS)/(2n - 1)] Least Significant Bit (LSB): One LSB is the ideal voltage difference between two successive codes. LSB = (VFS - VOS)/(2n - 1) = (VFS - VOS)/4095 Nominal LSBs: LTC1450 LTC1450L LSB = 4.095V/4095 = 1mV LSB = 2.5V/4095 = 0.610mV Integral Nonlinearity (INL): End-point INL is the maximum deviation from a straight line passing through the end points of the DAC transfer curve. Because the part operates from a single supply and the output cannot go below zero, the linearity is measured between full scale and the code corresponding to the maximum offset specification. The INL error at a given input code is calculated as follows: INL = [VOUT - VOS - (VFS - VOS)(code/4095)]/LSB VOUT = The output voltage of the DAC measured at the given input code Differential Nonlinearity (DNL): DNL is the difference between the measured change and the ideal one LSB change between any two adjacent codes. The DNL error between any two codes is calculated as follows: DNL = (VOUT - LSB)/LSB VOUT = The measured voltage difference between two adjacent codes Digital Feedthrough: The glitch that appears at the analog output caused by AC coupling from the digital inputs when they change state. The area of the glitch is specified in (nV)(s). OUTPUT VOLTAGE NEGATIVE OFFSET 0V DAC CODE 1450/50L * F01 Figure 1. Effect of Negative Offset 9 LTC1450/LTC1450L U OPERATION Parallel Interface The data on the input of the DAC is loaded into the DAC's input latches when Chip Select (CSLSB and/or CSMSB) and WR are at a logic low. The data that is loaded into the input latches will depend on which of the Chip Selects are at a logic low (see Digital Interface Truth Table). If WR and CSLSB are both low and CSMSB is high, then only data on the eight LSBs (D0 to D7) is loaded into the input latches. Similarly if WR and CSMSB are both low and CSLSB is high then only data on the four MSBs (D8 to D11) is loaded into the input latches. Data is loaded into both the Least Significant Data Bits (D0 to D7) and the Most Significant Bits (D8 to D11) at the same time if WR, CSLSB and CSMSB are low. The input data is latched into the input latches on the rising edge of either the WR or one of the Chip Selects. The WR transition high will latch the data in both input latches. A rising edge on CSMSB will latch data bits D8 to D11. A rising edge on CSLSB will latch data bits D0 to D7. Once data is loaded into the input latches, it can be loaded into the DAC latch. This will update the analog voltage output of the DAC. The DAC latch is loaded by a logic low on LDAC. The data that is loaded into the DAC latch will be latched on the rising edge of LDAC. When WR, CSLSB, CSMSB and LDAC are all low the latches are transparent and data on pins D0 to D11 loads directly into the DAC latch. Power-On Reset The LTC1450/LTC1450L have an internal power-on reset that resets all internal latches to 0's on power-up (equivalent to the CLR pin function). Reference The LTC1450 includes an internal 2.048V reference, giving the LTC1450 a full-scale range of 4.095V in the gain of 2 configuration. The LTC1450L has an internal 1.22V reference with a full-scale range of 2.5V and a gain of 2.05 in the gain of 2 configuration. The onboard reference in the LTC1450 and LTC1450L is not internally connected to the DAC's reference resistor string but is provided on an adjacent pin for flexibility. Because the internal reference 10 is not internally connected to the DAC resistor string, an external reference can be used or the resistor string can be driven with an external source in multiplying configuration. The external reference or source must be capable of driving the 8k minimum DAC ladder resistance. The reference output noise can be reduced with a bypass capacitor to ground. (Note: The reference does not require a bypass capacitor to ground for proper operation.) When bypassing the reference a small value resistor in series with the capacitor is recommended to help reduce peaking on the output. A 10 resistor in series with a 4.7F capacitor is optimum for reducing reference generated noise. DAC Ladder Resistor String The high and low end of the DAC ladder resistor string (REFHI and REFLO respectively) are not connected internally on this part. Typically REFHI will be connected to REFOUT and REFLO will be connected to GND. This will give the LTC1450 a full-scale range of 4.095V. The fullscale range for the LTC1450L will be 2.5V Either of these pins can be driven up to VCC - 1.5V when using the buffer in the gain of 1 configuration. The resistor string pins can be driven to VCC/2 when the buffer is in the gain of 2 configuration (2.05 for the LTC1450L). The resistance between these two pins is typically 18k (8k min). Voltage Output The output buffer for the LTC1450/LTC1450L can be configured for two different gain settings. By tying the X1/X2 pin to GND the gain is set to 2 (2.05 for the LTC1450L). By tying the X1/X2 pin to VOUT the gain is set to one. The LTC1450 family's rail-to-rail buffered output can source or sink 5mA over the entire operating temperature range while pulling to within 300mV of the positive supply voltage or GND. The output swings to within a few millivolts of either supply rail when unloaded and has an equivalent output resistance of 40 when driving a load to the rails. LTC1450/LTC1450L U TYPICAL APPLICATIONS N Filter VREF to Lower Output Noise (0.18mVRMS at VOUT) 5V 0.1F DIN FROM P DATA BUS 10 4.7F DATA (0:11) VCC REFOUT REFHI CSLSB CSMSB FROM P AND DECODE LOGIC LTC1450 LTC1450L WR VOUT X1/X2 LDAC FROM SYSTEM RESET OUTPUT CLR GND REFLO LTC1450/50L * TA03 Digitally Programmable Noninverting Amplifier LTC1450: VIN = 0V TO 2.048V (VCC = 4.5V TO 5V) LTC1450L: VIN = 0V TO 1.22V (VCC = 2.7V TO 5.5V) LTC1450L: VIN = 0V TO 2.048V (VCC = 4.5V TO 5.5V) VCC 0.1F DIN FROM P DATA BUS DATA (0:11) VCC REFOUT REFHI CSLSB FROM P AND DECODE LOGIC CSMSB WR CLR VOUT X1/X2 LDAC FROM SYSTEM RESET LTC1450: VOUT = LTC1450 LTC1450L GND ( ) DIN * 2 VIN 4096 ( ) DIN LTC1450L: VOUT = * 2.05 VIN 4096 REFLO LTC1450/50L * TA04 11 LTC1450/LTC1450L U TYPICAL APPLICATIONS N Bipolar Output 12-Bit DAC 5V 10k VREF 5V 3 0.1F DATA (0:11) VCC 6 LT (R)1097 10k 2 DIN FROM P DATA BUS 7 + - 4 REFOUT REFLO* VOUT - 2.048V TO 2.047V (1mV/LSB) - 5V CSLSB 2.047V CSMSB FROM P AND DECODE LOGIC LTC1450 VOUT WR X1/X2 LDAC FROM SYSTEM RESET CLR GND 10k VDAC 10k VOUT VOUT = 2.048 + REFHI* ( ) 2048 4095 DIN - 2.048V DIN - 4096 4.096 4096 *REFLO IS TIED TO REFOUT AND REFHI IS TIED TO GND TYING REFLO TO REFOUT AND REFHI TO GND IN THIS APPLICATION OVERCOMES THE NEED FOR A PULL-DOWN RESISTOR ON THE REFOUT PIN. REFOUT SEES A CONSTANT LOAD TO GND INDEPENDENT OF VOUT LTC1450/50L * TA05 Digitally Programmable Bilateral Current Source/Sink VREF R1 20k R6 20k 15V VCC 2 0.1F R2 22.6k 2.047mA 7 - 6 LT1097 DIN FROM P DATA BUS 3 DATA (0:11) VCC REFOUT REFHI CSLSB FROM P AND DECODE LOGIC CSMSB LTC1450 WR X1/X2 LDAC FROM SYSTEM RESET 12 VOUT CLR GND REFLO VDAC 4 -15V R3 20k IOUT = + ( R4 21.5k ) IOUT R5 1.13k 2048 4095 - 2.048mA IOUT - 2.048mA TO 2.047mA (1A/LSB) DIN R2 * 4.096 - VREF 4096 (R1)(R5) R1 = R3 R2 = R4 + R5 (R1)(R5)(R3 + R4) ZOUT = (R2)(R3) - R1(R4 + R5) LTC1450/50L * TA06 DIN LTC1450/LTC1450L U TYPICAL APPLICATIONS N 4-Quadrant Multiplying DAC Application Table 1. Binary Code Table for 4-Quadrant, Multiplying DAC Application This application shows the LTC1450L configured as a single supply 4-quadrant multiplying DAC. It uses a 5V supply and only one external component, a 5k resistor tied from REFOUT to ground. (The LTC1450 can be used in a similar fashion.) The multiplying DAC allows the user to digitally change the amplitude and polarity of an AC input signal whose voltage is centered around an offset signal ground provided by the 1.22V reference voltage. The transfer function is shown in the following equations. ( BINARY DIGITAL INPUT CODE IN DAC REGISTER MSB ) DIN VOUT = (VIN - VREF) Gain - 1 + 1 + VREF 4096 ANALOG OUTPUT (VOUT) LSB 1111 1111 1111 (4094/4096)(VIN - VREF) + VREF 1100 0001 1001 0.5(VIN - VREF) + VREF 1000 0011 0010 VREF 0100 0100 1011 - 0.5(VIN - VREF) + VREF 0000 0110 0100 - 1.0(VIN - VREF) + VREF 0000 0000 0000 - 1.05(VIN - VREF) + VREF Clean 4-Quadrant Multiplying Is Shown in the Output Waveforms for Zero-Scale and Full-Scale DAC Settings For the LTC1450L Gain = 2.05 and VREF = 1.22V VOUT = (VIN - 1.22V) 2.05 ( ) DIN - 1.05 + 1.22V 4096 Table 1 shows the expressions for VOUT as a function of VIN, VREF and DIN. The scope photo shows a 12.5kHz, 2.3VP-P triangle wave input signal and the corresponding output waveforms for zero-scale and full-scale DAC codes. VIN 1.22V 1.15V AT 12.5kHz 2V/DIV VOUT D IN = 0 1V/DIV VOUT DIN = 4095 1V/DIV 20s/DIV 1450/50L TA08 Internal Reference, REFLO/REFHI Pins, Gain Adjust and Wide Supply Voltage Range Allow 4-Quadrant Mulitplying on a 5V Single Supply VIN 1.22V 1.15V 5V REFHI DIN WR CSMSB CSLSB DOUBLEBUFFERED DAC LATCHES X1/X2 R VCC LTC1450L 1.05R - 12-BIT DAC VOUT 1.22V 1.21V + LDAC CLR POWER-ON RESET REFERENCE 1.22V REFOUT REFLO GND 1450/50L TA07 5k VREF 13 LTC1450/LTC1450L U PACKAGE DESCRIPTION Dimensions in Inches (millimeters) unless otherwise noted. G Package 24-Lead Plastic SSOP (0.209) (LTC DWG # 05-08-1640) 0.318 - 0.328* (8.07 - 8.33) 24 23 22 21 20 19 18 17 16 15 14 13 0.301 - 0.311 (7.65 - 7.90) 1 2 3 4 5 6 7 8 9 10 11 12 0.205 - 0.212** (5.20 - 5.38) 0.068 - 0.078 (1.73 - 1.99) 0 - 8 0.005 - 0.009 (0.13 - 0.22) 0.022 - 0.037 (0.55 - 0.95) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 14 0.0256 (0.65) BSC 0.010 - 0.015 (0.25 - 0.38) 0.002 - 0.008 (0.05 - 0.21) G24 SSOP 0595 LTC1450/LTC1450L U PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. N Package 24-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510) 1.265* (32.131) 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 0.255 0.015* (6.477 0.381) 0.300 - 0.325 (7.620 - 8.255) 0.130 0.005 (3.302 0.127) 0.045 - 0.065 (1.143 - 1.651) 0.015 (0.381) MIN 0.009 - 0.015 (0.229 - 0.381) 0.125 (3.175) MIN 0.005 (0.127) MIN +0.635 8.255 0.100 0.010 -0.381 (2.540 0.254) *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm) ( +0.025 0.325 -0.015 ) 0.065 (1.651) TYP 0.018 0.003 (0.457 0.076) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. N24 0695 15 LTC1450/LTC1450L RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1257 Complete Serial I/O VOUT 12-Bit DAC 5V to 15V Single Supply in 8-Pin SO and PDIP LTC1451/LTC1452/LTC1453 Complete Serial I/O VOUT 12-Bit DACs 3V/5V Single Supply, Rail-to-Rail in 8-Pin SO and PDIP LTC1446/LTC1446L Dual 12-Bit VOUT DACs in SO-8 Package LTC1446: VCC = 4.5V TO 5.5V, VOUT = 0V TO 4.095V LTC1446L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V LTC1454/LTC1454L Dual 12-Bit VOUT DACs in a 16-Pin SO Package with Added Functionality LTC1454: VCC = 4.5V to 5.5V, VOUT = 0V TO 4.095V LTC1454L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V LTC1458/LTC1458L Quad 12-Bit VOUT DACs in 28-Lead SW and SSOP Packages LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V LTC7541A Parallel I/O Multiplying 12-Bit DAC 12-Bit Wide Input LTC7543/LTC8143 Serial Multiplying 12-Bit DACs Daisy-Chainable, Flexible Analog and Digital Interface LTC7545A Parallel Latched Input Multiplying 12-Bit DAC 12-Bit Wide Latched Input LTC8043 Serial Multiplying 12-Bit DAC 8-Pin SO and PDIP 16 Linear Technology Corporation LT/GP 0896 7K * PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 TELEX: 499-3977 LINEAR TECHNOLOGY CORPORATION 1996