1
Under
development
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
------Table of Contents------
Description
The M30201 group of single-chip microcomputers are built using the high-performance silicon gate CMOS
process using a M16C/60 Series CPU core. M30201 group is packaged in a 52-pin plastic molded SDIP, or
56-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions
featuring a high level of instruction efficiency. With 1M bytes of address space, they are capable of execut-
ing instructions at high speed.
The M30201 group includes a wide range of products with different internal memory types and sizes and
various package types.
Features
• Basic machine instructions ..................Compatible with the M16C/60 series
• Memory capacity..................................ROM/RAM (See figure 1.4. ROM expansion.)
• Shortest instruction execution time......
100ns (f(XIN)=10MHz)
• Supply voltage .....................................4.0 to 5.5V (f(XIN)=10MHz) :mask ROM version
2.7 to 5.5V (f(XIN)=7MHz with software one-wait):mask ROM
version
4.0 to 5.5V (f(XIN)=10MHz) :flash memory version
• Interrupts..............................................9 internal and 3 external interrupt sources, 4 software
(including key input interrupt)
• Multifunction 16-bit timer......................Timer A x 1, timer B x 2, timer X x 3
• Clock output
• Serial I/O..............................................
1
channel
for UART or clock synchronous, 1 for UART
• A-D converter.......................................10 bits X 8 channels (Expandable up to 13 channels)
• Watchdog timer....................................1 line
• Programmable I/O ...............................43 lines
• LED drive ports ....................................8 ports
• Clock generating circuit .......................2 built-in clock generation circuits
(built-in feedback resistor, and external ceramic or quartz oscillator)
Applications
Home appliances, Audio, office equipment, Automobiles
Timer.............................................................36
Serial I/O .......................................................63
A-D Converter ...............................................77
Programmable I/O Ports ...............................87
Electric Characteristics .................................94
Flash Memory version.................................125
Central Processing Unit (CPU) .....................11
Reset.............................................................14
Clock Generating Circuit ...............................18
Protection......................................................25
Interrupts.......................................................26
Watchdog Timer............................................34
Specifications written in this manual are believed to
be accurate, but are not guaranteed to be entirely
free of error.
Specifications in this manual may be changed for
functional or performance improvements. Please
make sure your manual is the latest edition.
Under
development
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
P6
3
/AN
3
P6
2
/AN
2
P6
1
/AN
1
P6
0
/AN
0
V
REF
X
IN
X
OUT
P5
0
/T
X
D
0
/AN
50
P6
7
/AN
7
P6
6
/AN
6
P6
5
/AN
5
P6
4
/AN
4
V
SS
RESET
V
CC
CNV
SS
P5
1
/R
X
D
0
/AN
51
P5
2
/CLK
0
/AN
52
AV
SS
P4
5
/TX2
INOUT
P7
0
/TB0
IN
/X
COUT
P7
1
/TB1
IN
/X
CIN
P5
4
/CK
OUT
/AN
54
P5
3
/CLKS/AN
53
AV
CC
P0
7
/KI
7
P0
6
/KI
6
P0
5
/KI
5
P0
4
/KI
4
P0
3
/KI
3
P0
2
/KI
2
P0
1
/KI
1
P1
0
(LED
0
)
P1
1
(LED
1
)
P1
2
(LED
2
)
P1
3
(LED
3
)
P1
4
(LED
4
)
P1
5
(LED
5
)
P1
6
(LED
6
)
P1
7
(LED
7
)
M30201MX-XXXSP
M30201MXT-XXXSP
M30201F6SP
M30201F6TSP
P0
0
/KI
0
P3
0
P3
1
P3
2
P3
3
P3
4
P3
5
P4
0
/TA0
IN
/T
X
D
1
P4
1
/TA0
OUT
P4
2
/R
X
D
1
P4
4
/INT
1
/TX1
INOUT
P4
3
/INT
0
/TX0
INOUT
Pin Configuration
Figures 1.1 to 1.2 show the pin configurations (top view).
PIN CONFIGURATION (top view)
Package: 52P4B
Figure 1.1. Pin configuration for the M30201 group (shrink DIP product) (top view)
3
Under
development
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
X
IN
X
OUT
P5
0
/T
X
D
0
/AN
50
P6
7
/AN
7
V
SS
RESET
V
CC
CNV
SS
P5
1
/R
X
D
0
/AN
51
P5
2
/CLK
0
/AN
52
P4
5
/TX2
INOUT
P7
1
/TB1
IN
/X
CIN
P7
0
/TB0
IN
/X
COUT
P4
1
/TA0
OUT
P4
0
/TA0
IN
/T
X
D
1
P4
2
/R
X
D
1
P5
4
/CK
OUT
/AN
54
P5
3
/CLKS/AN
53
V
REF
P6
0
/AN
0
P6
1
/AN
1
AV
SS
AV
CC
P1
0
(LED
0
)
P1
4
(LED
4
)
M30201MX-XXXFP
M30201MXT-XXXFP
M30201F6FP
M30201F6TFP
N.C.
N.C.
N.C.
N.C.
P0
0
/KI
0
P6
2
/AN
2
P6
3
/AN
3
P6
4
/AN
4
P6
5
/AN
5
P6
6
/AN
6
P0
1
/KI
1
P0
2
/KI
2
P0
3
/KI
3
P0
4
/KI
4
P0
5
/KI
5
P0
6
/KI
6
P0
7
/KI
7
P1
1
(LED
1
)
P1
2
(LED
2
)
P1
3
(LED
3
)
P1
5
(LED
5
)
P1
6
(LED
6
)
P1
7
(LED
7
)
P3
0
P3
1
P3
2
P3
3
P3
4
P3
5
P4
4
/INT
1
/TX1
INOUT
P4
3
/INT
0
/TX0
INOUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
56
55
54
53
27
28
Figure 1.2. Pin configuration for the M30201 group (QFP product) (top view)
Package: 56P6S-A
PIN CONFIGURATION (top view)
Under
development
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
4
Description
Figure 1.3. Block diagram for the M30201 group
AAAAA
AAAAA
Timer
Timer TA0 (16 bits)
Timer TB0 (16 bits)
Timer TB1 (16 bits)
Timer TX0 (16 bits)
Timer TX1 (16 bits)
Timer TX2 (16 bits)
Internal peripheral functions
Watchdog timer
(15 bits)
A-D converter
(10 bits
X
8 channels
Expandable up to 13 channels)
UART/clock synchronous SI/O
(8 bits
X
1 channel)
System clock generator
XIN-XOUT
XCIN-XCOUT
M16C/60 series16-bit CPU core
I/O ports
Port P0
8
Port P1
8
Port P3
6
Port P4
6
Port P5
5
Port P6
8
R0LR0H
R1H R1L
R2
R3
A0
A1
FB
R0LR0H
R1H R1L
R2
R3
A0
A1
FB
Registers
ISP
USP
Stack pointer
Vector table
INTB
UART
(8 bits
X
1 channel)
Multiplier
2
Port P7
AAAAAAA
A
AAAAA
A
A
AAAAA
A
A
AAAAA
A
AAAAAAA
Memory
ROM
(Note 1)
RAM
(Note 2)
SB FLG
PC
Program counter
Note 1: ROM size depends on MCU type.
Note 2: RAM size depends on MCU type.
Block Diagram
Figure 1.3 is a block diagram of the M30201 group.
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Under
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Table 1.1. Performance outline of M30201 group
Performance Outline
Table 1.1 is performance outline of M30201 group.
Item Performance
Number of basic instructions 91 instructions
Shortest instruction execution time 100ns (f(XIN)=10MHz
Memory ROM (See figure 4. ROM expansion.)
capacity RAM (See figure 4. ROM expansion.)
I/O port P0 to P7 43 lines
Multifunction TA0 16 bits x 1
timer TB0, TB1 16 bits x 2
TX0, TX1, TX2 16 bits x 3
Serial I/O UART0 (UART or clock synchronous) x 1
UART1 UART x 1
A-D converter 10 bits x 8 channels (Expandable up to 13 channels)
Watchdog timer 15 bits x 1 (with prescaler)
Interrupt 9 internal and 3 external sources, 4 software sources
Clock generating circuit 2 built-in clock generation circuits
(built-in feedback resistor, and external ceramic or
quartz oscillator)
Supply voltage 4.0 to 5.5V (f(XIN)=10MHz) :mask ROM version
2.7 to 5.5V (f(XIN)=7MHz with software one-wait) :mask
ROM version
4.0 to 5.5V (f(XIN)=10MHz) :flash memory version
Power consumption 18mW (f(XIN)=7MHz with software one-wait, Vcc=3V)
:mask ROM version
95mW (f(XIN)=10MHz no wait, Vcc=5V) :flash memory version
I/O I/O withstand voltage 5V
characteristics Output current 5mA (15mA:LED drive port)
Device configuration CMOS silicon gate
Package 52-pin plastic mold SDIP
56-pin plastic mold QFP
Under
development
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
6
Description
Mitsubishi plans to release the following products in the M30201 group:
(1) Support for mask ROM version and flash memory version
(2) ROM capacity
(3) Package
52P4B : Plastic molded SDIP (mask ROM version and flash memory version)
56P6S-A : Plastic molded QFP (mask ROM version and flash memory version)
RAM Size
(Byte)
1K
16K 32K
M30201M4-XXXSP/FP
M30201M4T-XXXSP/FP
512
ROM Size
(Byte)
M30201M2-XXXSP/FP
M30201M2T-XXXSP/FP
Under development
Under planning
2K M30201F6SP/FP
M30201F6TSP/FP
48K
Under development
Figure 1.4. ROM expansion
July 1998
Package type:
SP : Package 52P4B
FP : Package 56P6S-A
ROM No.
Omitted for flash memory version
Shows difference of characteristics
and usage etc:
Nothing : Common
T : Automobiles
Memory type:
M : Mask ROM version
F : Flash memory version
Type No. M 3 0 2 0 1 M 4 T – X X X S P
M16C/20 Group
M16C Family
Shows pin count, etc
(The value itself has no specific meaning)
ROM capacity:
2 : 16K bytes
4 : 32K bytes
6 : 48K bytes
Figure 1.5. Type No., memory size, and package
7
Pin Description
Under
development
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
V
CC
, V
SS
CNV
SS
X
IN
X
OUT
AV
CC
AV
SS
V
REF
P0
0
to P0
7
P1
0
to P1
7
P3
0
to P3
5
P4
0
to P4
5
Signal name
Power supply
input
CNV
SS
Reset input
Clock input
Clock output
Analog power
supply input
Reference
voltage input
I/O port P0
I/O port P1
I/O port P3
I/O port P4
Supply 2.7 to 5.5 V to the V
CC
pin. Supply 0 V to the V
SS
pin.
Function
Connect it to the V
SS
pin.
A “L” on this input resets the microcomputer.
These pins are provided for the main clock generating circuit.
Connect a ceramic resonator or crystal between the X
IN
and the
X
OUT
pins. To use an externally derived clock, input it to the
X
IN
pin and leave the X
OUT
pin open.
This pin is a power supply input for the A-D converter. Connect
it to V
CC
.
This pin is a power supply input for the A-D converter. Connect
it to V
SS
.
This pin is a reference voltage input for the A-D converter.
This is an 8-bit CMOS I/O port. It has an input/output port
direction register that allows the user to set each pin for input or
output individually. When set for input, the user can specify in
units of four bits via software whether or not they are tied to a
pull-up resistor.
This is an 8-bit I/O port equivalent to P0.
This is a 6-bit I/O port equivalent to P0.
This is a 6-bit I/O port equivalent to P0. The P4
0
pin is shared
with timer A0 input and serial I/O output TxD1. The P4
1
pin is
shared with timer A0 output. The P4
2
pin is shared with serial
I/O input RxD1. The P4
3
pin is shared with external interrupt
INT0 and timer X0 input/output TX0
INOUT
. The P4
4
pin is
shared with external interrupt INT1 and timer X1 input/output
TX1
INOUT
. The P4
5
pin is shared with timer X2 input/output
TX2
INOUT
.
Pin name
Input
Input
Input
Output
Input
Input/output
Input/output
I/O type
Analog power
supply input
Input/output
Input/output
RESET
I/O port P5 Input/output
Input/output
Input/output
I/O port P6
I/O port P7
P5
0
to P5
4
P6
0
to P6
7
P7
0
to P7
1
This is a 5-bit I/O port equivalent to P0. The P5
0
, P5
1
, P5
2
, and
P5
3
pins are shared with serial I/O pins TxD
0
, RxD
0
, CLK
0
,
and CLKS. The P5
4
pin is shared with clock output CLK
OUT
.
Also, these pins are shared with analog input pins AN
50
through AN
54
.
This is an 8-bit I/O port equivalent to P0. These pins are shared
with analog input pins AN
0
through AN
7
.
This is a 2-bit I/O port equivalent to P0 . These pins are used
for input/output to and from the oscillator circuit for the clock.
Connect a crystal oscillator between the X
CIN
and the X
COUT
pins.
Pin Description
8
Under
development
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory
Operation of Functional Blocks
The M30201 accommodates certain units in a single chip. These units include ROM and RAM to store
instructions and data and the central processing unit (CPU) to execute arithmetic/logic operations. Also
included are peripheral units such as timers, serial I/O, A-D converter, and I/O ports.
The following explains each unit.
Memory
Figure 1.6 is a memory map of the M30201. The address space extends the 1M bytes from address
0000016 to FFFFF16. From FFFFF16 down is ROM. For example, in the M30201M4-XXXFP, there is 32K
bytes of internal ROM from F800016 to FFFFF16. The vector table for fixed interrupts such as the reset are
mapped to FFFDC16 to FFFFF16. The starting address of the interrupt routine is stored here. The address
of the vector table for timer interrupts, etc., can be set as desired using the internal register (INTB). See the
section on interrupts for details.
From 0040016 up is RAM. For example, in the M30201M4-XXXFP, there is 1K byte of internal RAM from
0040016 to 007FF16. In addition to storing data, the RAM also stores the stack used when calling subrou-
tines and when interrupts are generated.
The SFR area is mapped to 0000016 to 003FF16. This area accommodates the control registers for periph-
eral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Any part of the SFR area that is not
occupied is reserved and cannot be used for other purposes.
The special page vector table is mapped to FFE0016 to FFFDB16. If the starting addresses of subroutines
or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions
can be used as 2-byte instructions, reducing the number of program steps.
Figure 1.6. Memory map
00000
16
YYYYY
16
FFFFF
16
00400
16
XXXXX
16
Internal ROM area
SFR area
For details, see
Figures 1.7 to 1.8
Internal RAM area
FFE00
16
FFFDC
16
FFFFF
16
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Watchdog timer
Reset
Special page
vector table
DBC
Address
XXXXX
16
007FF
16
F8000
16
005FF
16
FC000
16
M30201M2
M30201M4
Type No. Address
YYYYY
16
00BFF
16
F4000
16
M30201F6
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Under
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory
0000
16
0001
16
0002
16
0003
16
0004
16
0005
16
0006
16
0007
16
0008
16
0009
16
000A
16
000B
16
000C
16
000D
16
000E
16
000F
16
0010
16
0011
16
0012
16
0013
16
0014
16
0015
16
0016
16
0017
16
0018
16
0019
16
001A
16
001B
16
001C
16
001D
16
001E
16
001F
16
0020
16
0021
16
0022
16
0023
16
0024
16
0025
16
0026
16
0027
16
0028
16
0029
16
002A
16
002B
16
002C
16
002D
16
002E
16
002F
16
0030
16
0031
16
0032
16
0033
16
0034
16
0035
16
0036
16
0037
16
0038
16
0039
16
003A
16
003B
16
003C
16
003D
16
003E
16
003F
16
0040
16
0041
16
0042
16
0043
16
0044
16
0045
16
0046
16
0047
16
0048
16
0049
16
004A
16
004B
16
004C
16
004D
16
004E
16
004F
16
0050
16
0051
16
0052
16
0053
16
0054
16
0055
16
0056
16
0057
16
0058
16
0059
16
005A
16
005B
16
005C
16
005D
16
005E
16
005F
16
Watchdog timer start register (WDTS)
Watchdog timer control register (WDC)
Processor mode register 0 (PM0)
Address match interrupt register 0 (RMAD0)
Address match interrupt register 1 (RMAD1)
System clock control register 0 (CM0)
System clock control register 1 (CM1)
Address match interrupt enable register (AIER)
Protect register (PRCR)
Processor mode register 1(PM1)
Timer X0 interrupt control register (TX0IC)
UART0 transmit interrupt control register (S0TIC)
Timer A0 interrupt control register (TA0IC)
Timer X1 interrupt control register (TX1IC)
UART0 receive interrupt control register (S0RIC)
UART1 transmit interrupt control register (S1TIC)
UART1 receive interrupt control register (S1RIC)
Key input interrupt control register (KUPIC)
A-D conversion interrupt control register (ADIC)
INT1 interrupt control register (INT1IC)
Timer B0 interrupt control register (TB0IC)
Timer X2 interrupt control register (TX2IC)
INT0 interrupt control register (INT0IC)
Timer B1 interrupt control register (TB1IC)
Figure 1.7. Location of peripheral unit control registers (1)
10
Under
development
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory
Figure 1.8. Location of peripheral unit control registers (2)
038016
038116
038216
038316
038416
038516
038616
038716
038816
038916
038A16
038B16
038C16
038D16
038E16
038F16
039016
039116
039216
039316
039416
039516
039616
039716
039816
039916
039A16
039B16
039C16
039D16
039E16
039F16
03A016
03A116
03A216
03A316
03A416
03A516
03A616
03A716
03A816
03A916
03AA16
03AB16
03AC16
03AD16
03AE16
03AF16
03B016
03B116
03B216
03B316
03B416
03B516
03B616
03B716
03B816
03B916
03BA16
03BB16
03BC16
03BD16
03BE16
03BF16
Timer A0 (TA0)
Timer X0 (TX0)
Timer X1 (TX1)
Timer B0 (TB0)
Timer B1 (TB1)
Count start flag (TABSR)
One-shot start flag (ONSF)
Timer A0 mode register (TA0MR)
Timer X0 mode register (TX0MR)
Timer X1 mode register (TX1MR)
Timer B0 mode register (TB0MR)
Timer B1 mode register (TB1MR)
Up-down flag (UDF)
Timer X2 (TX2)
Clock divided counter (CDC)
Timer X2 mode register (TX2MR)
Trigger select register (TRGSR)
Clock prescaler reset flag (CPSRF)
UART0 transmit/receive mode register (U0MR)
UART0 transmit buffer register (U0TB)
UART0 receive buffer register (U0RB)
UART1 transmit/receive mode register (U1MR)
UART1 transmit buffer register (U1TB)
UART1 receive buffer register (U1RB)
UART0 bit rate generator (U0BRG)
UART0 transmit/receive control register 0 (U0C0)
UART0 transmit/receive control register 1 (U0C1)
UART1 bit rate generator (U1BRG)
UART1 transmit/receive control register 0 (U1C0)
UART1 transmit/receive control register 1 (U1C1)
UART transmit/receive control register 2 (UCON)
Flash memory control register 0 (FCON0) (Note)
Flash memory control register 1 (FCON1) (Note)
Flash command register (FCMD) (Note)
Note: This re
g
ister is onl
y
exist in flash memor
y
version.
03C016
03C116
03C216
03C316
03C416
03C516
03C616
03C716
03C816
03C916
03CA16
03CB16
03CC16
03CD16
03CE16
03CF16
03D016
03D116
03D216
03D316
03D416
03D516
03D616
03D716
03D816
03D916
03DA16
03DB16
03DC16
03DD16
03DE16
03DF16
03E016
03E116
03E216
03E316
03E416
03E516
03E616
03E716
03E816
03E916
03EA16
03EB16
03EC16
03ED16
03EE16
03EF16
03F016
03F116
03F216
03F316
03F416
03F516
03F616
03F716
03F816
03F916
03FA16
03FB16
03FC16
03FD16
03FE16
03FF16
A-D register 7 (AD7)
A-D register 0 (AD0)
A-D register 1 (AD1)
A-D register 2 (AD2)
A-D register 3 (AD3)
A-D register 4 (AD4)
A-D register 5 (AD5)
A-D register 6 (AD6)
Port P0 (P0)
Port P0 direction register (PD0)
Port P1 (P1)
Port P1 direction register (PD1)
Port P2 (P2) (Reserved)
Port P2 direction register (PD2) (Reserved)
Port P3 (P3)
Port P3 direction register (PD3)
Port P4 (P4)
Port P4 direction register (PD4)
Port P5 (P5)
Port P5 direction register (PD5)
Port P6 (P6)
Port P6 direction register (PD6)
Port P7 (P7)
Port P7 direction register (PD7)
Pull-up control register 0 (PUR0)
Pull-up control register 1 (PUR1)
Port P1 drive control register (DRR)
A-D control register 0 (ADCON0)
A-D control register 1 (ADCON1)
A-D control register 2 (ADCON2)
11
Under
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU
Central Processing Unit (CPU)
The CPU has a total of 13 registers shown in Figure 1.9. Seven of these registers (R0, R1, R2, R3, A0, A1,
and FB) come in two sets; therefore, these have two register banks.
(1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3)
Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and
arithmetic/logic operations.
Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H, R1H),
and low-order bits as (R0L, R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can
use as 32-bit data registers (R2R0, R3R1).
(2) Address registers (A0 and A1)
Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data
registers. These registers can also be used for address register indirect addressing and address register
relative addressing.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
Figure 1.9. Central processing unit register
AAAAAA
AAAAAA
HL
b15 b8 b7 b0
R0
(Note)
AAAAAA
AAAAAA
HL
b15 b8 b7 b0
R1
(Note)
R2
(Note)
AAAAAA
AAAAAA
b15 b0
R3
(Note)
AAAAAA
AAAAAA
b15 b0
A0
(Note)
AAAAAA
AAAAAA
b15 b0
A1
(Note)
AAAAAA
AAAAAA
b15 b0
FB
(Note)
AAAAAA
AAAAAA
b15 b0
Data
registers
Address
registers
Frame base
registers
b15 b0
b15 b0
b15 b0
b15 b0
b0
b19
b0
b19
HL
Program counter
Interrupt table
register
User stack pointer
Interrupt stack
pointer
Static base
register
Flag register
PC
INTB
USP
ISP
SB
FLG
Note: These registers consist of two register banks.
AA
AA
AA
AA
A
A
AA
AA
AAAAAA
AAAAAA
AA
AA
AA
AA
A
A
AA
AA
AA
AA
CDZSBOIU
IPL
12
Under
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU
(3) Frame base register (FB)
Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing.
(4) Program counter (PC)
Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed.
(5) Interrupt table register (INTB)
Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector
table.
(6) Stack pointer (USP/ISP)
Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each config-
ured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag).
This flag is located at the position of bit 7 in the flag register (FLG).
(7) Static base register (SB)
Static base register (SB) is configured with 16 bits, and is used for SB relative addressing.
(8) Flag register (FLG)
Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.10 shows the flag
register (FLG). The following explains the function of each flag:
• Bit 0: Carry flag (C flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
• Bit 1: Debug flag (D flag)
This flag enables a single-step interrupt.
When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is
cleared to “0” when the interrupt is acknowledged.
• Bit 2: Zero flag (Z flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”.
• Bit 3: Sign flag (S flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, cleared to
“0”.
• Bit 4: Register bank select flag (B flag)
This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is
selected when this flag is “1”.
• Bit 5: Overflow flag (O flag)
This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”.
• Bit 6: Interrupt enable flag (I flag)
This flag enables a maskable interrupt.
An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to
“0” when the interrupt is acknowledged.
13
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU
• Bit 7: Stack pointer select flag (U flag)
Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected
when this flag is “1”.
This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software
interrupt Nos. 0 to 31 is executed.
• Bits 8 to 11: Reserved area
• Bits 12 to 14: Processor interrupt priority level (IPL)
Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight
processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt
is enabled.
• Bit 15: Reserved area
The C, Z, S, and O flags are changed when instructions are executed. See the software manual for
details.
Figure 1.10. Flag register (FLG)
AAAAAAA
AAAAAAA
HL
b15 b8 b7 b0
R0
(Note)
AAAAAAA
AAAAAAA
HL
b15 b8 b7 b0
R1
(Note)
R2
(Note)
AAAAAAA
AAAAAAA
b15 b0
R3
(Note)
AAAAAAA
AAAAAAA
b15 b0
A0
(Note)
AAAAAAA
AAAAAAA
b15 b0
A1
(Note)
AAAAAAA
AAAAAAA
b15 b0
FB
(Note)
AAAAAAA
AAAAAAA
b15 b0
Data
registers
Address
registers
Frame base
registers
b15 b0
b15 b0
b15 b0
b15 b0
b0
b19
b0
b19
HL
Program cou
n
Interrupt tabl
e
register
User stack p
o
Interrupt stac
k
pointer
Static base
register
Flag register
PC
INTB
USP
ISP
SB
FLG
AAAAAA
AAAAAA
CDZSBOIU
IPL
14
Under
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
Figure 1.12. Reset sequence
Reset
There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset.
(See “Software Reset” for details of software resets.) This section explains on hardware resets.
When the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the
reset pin level “L” (0.2VCC max.) for at least 20 cycles. When the reset pin level is then returned to the “H”
level while main clock is stable, the reset status is cancelled and program execution resumes from the
address in the reset vector table.
Figure 1.11 shows the example reset circuit. Figure 1.12 shows the reset sequence.
Figure 1.11. Example reset circuit
RESET V
CC
0.8V
RESET
V
CC
0V
0V
5V
5V
4.0V
Example when V
CC
= 5V
.
BCLK
Address
BCLK 24cycles
FFFFC
16
FFFFE
16
Content of reset vector
X
IN
RESET
More than 20 cycles are needed
(Internal clock)
(Internal address
signal)
15
Under
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
Figure 1.13. Device's internal status after a reset is cleared
x : Nothing is mapped to this bit
? : Undefined
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values
must therefore be set.
(1) (000416)···
Processor mode register 0
(2) (000516)···
Processor mode register 1
(3) (000616)···
System clock control register 0
(4) (000716)···
System clock control register 1
(5)
(6)
(000916)···
Address match interrupt
enable register
(7)
(000A16)···
(9)
(000F16)···
Watchdog timer control register
(11)
(001416)···
(001516)···
(001616)···
(12)
(13)
(21)
(22)
(23)
(004D16)···
Key input interrupt control register
(20)
(8)
Protect register
(001016)···
Address match interrupt
register 0
(001116)···
(001216)···
(10)
(14)
(15)
(16)
(17)
(18)
(19)
(24)
A-D conversion interrupt
control register
(25)
(26)
(004E16)···
(27)
(28)
(29)
(30)
UART0 transmit interrupt control
register
UART0 receive interrupt control
register
UART1 transmit interrupt control
register
UART1 receive interrupt control
register
(31)
(32)
(33)
(34)
(35)
(36)
(37)
Timer A0 interrupt control register
Timer X0 interrupt control register
Timer X1 interrupt control register
Timer X2 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
(38)
(39)
INT0 interrupt control register
(40)
INT1 interrupt control register
(41)
(005116)···
(005216)···
(005316)···
(005416)···
(005516)···
(005616)···
(005716)···
(005816)···
(005A16)···
(005B16)···
(005D16)···
(005E16)···
(038316)···
Trigger select flag
(038416)···
Up-down flag
(039616)···
Timer A0 mode register
(039716)···
Timer X0 mode register
(039816)···
Timer X1 mode register
(039B16)···
Timer B0 mode register
(039C16)···
Timer B1 mode register
(039916)···
Timer X2 mode register
(038216)···
One-shot start flag
(03A816)···
UART1 transmit/receive control
register 0
(03AD16)···
UART1 transmit/receive control
register 1
(03B016)···
UART transmit/receive control
register 2
(03A016)···
UART0 transmit/receive mode
register
(03A416)···
UART0 transmit/receive control
register 0
(03A516)···
UART0 transmit/receive control
register 1
Count start flag (038016)···
(038116)···Clock prescaler reset flag
01001000
00
000 00001
000
000?????
0000
0
0016
0016
0016
0016
0016
0016
0016
0000
0016
0016
00
000?
000?
000?
000?
000?
000?
000?
000?
000?
000?
000?
000?
00 000?
00 000?
0000
0
0000000
00
0000000
00010000
00000100
00010000
00000100
0016
0016
00 0000?
00 0000?
(03AC16)···
UART1 transmit/receive mode
register
Address match interrupt
register 1
(48)
(49)
(46)
(47)
(45)
(50)
(51)
(52)
(53)
(59)
(57)
(58)
(55)
(56)
(54)
(64)
(63)
(65)
(66)
(62)
(03D416)···
A-D control register 2
(03D616)···
A-D control register 0
(03D716)···
A-D control register 1
(60)
(61)
(03E216)···
Port P0 direction register
(03E316)···
Port P1 direction register
(03E616)···
Port P2 direction register
(03E716)···
Port P3 direction register
(03EA16)···
Port P4 direction register
(03EB16)···
Port P5 direction register
(03EE16)···
Port P6 direction register
(03EF16)···
Port P7 direction register
(03FC16)···
Pull-up control register 0
(03FD16)···
Pull-up control register 1
(03FE16)···
Port P1 drive capacity control
register
Frame base register (FB)
Address registers (A0/A1)
Interrupt table register (INTB)
User stack pointer (USP)
Interrupt stack pointer (ISP)
Static base register (SB)
Flag register (FLG)
Data registers (R0/R1/R2/R3)
00000???
0016
0016
0016
0016
0016
0016
0016
000016
000016
000016
0000016
000016
000016
000016
000016
0
0000000
000000
000000
00000
00
000
(43)
(44)
(42) (03B416)···
Flash memory control register 0
(Note )
(03B516)···
Flash memory control register 1
(Note)
(03B616)···
Flash command register
00
0016
0000
0000
0100
Note: This register is only exist in flash memory version.
16
Under
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
Software Reset
Writing “1” to bit 3 of the processor mode register 0 (address 000416) applies a (software) reset to the
microcomputer. A software reset has almost the same effect as a hardware reset. The contents of internal
RAM are preserved.
Figure 1.14 shows the processor mode register 0 and 1.
Software Reset
Figure 1.14. Processor mode register 0 and 1.
Processor mode register 0 (Note)
Symbol Address When reset
PM0 0004
16
XXXX0000
2
Bit name FunctionBit symbol
WR
b7 b6 b5 b4 b3 b2 b1 b0
PM03
Reserved bit
Software reset bit The device is reset when this bit
is set to “1”. The value of this bit
is “0” when read.
Note: Set bit 1 of the protect register (address 000A
16
) to “1” when writing new
values to this register.
Processor mode register 1 (Note)
Symbol Address When reset
PM1 0005
16
00XXXXX0
2
Bit name FunctionBit symbol
WR
b7 b6 b5 b4 b3 b2 b1 b0
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
Reserved bit Must always be set to “0”
0
Note: Set bit 1 of the protect register (address 000A
16
) to “1” when writing new values
to this register.
A
A
A
A
A
A
PM17
Wait bit 0 : No wait state
1 : Wait state inserted
A
A
Must always be set to “0”
0
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
0000
0
17
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Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Software Wait
Software wait
The wait bit (bit 7) of the processor mode register 1 (address 000516)(note) allows you to insert software
wait states for the internal ROM/RAM areas. If this bit is 0, the bus cycle is executed in one BCLK (internal
clock) period; if the bit is 1, the bus cycle is executed in two BCLK periods. This bit is cleared to 0 after a
reset.
The SFR area is unaffected by this control bit; it is always accessed in two BCLK periods.
Table 1.2 shows the relationship between software wait states and bus cycles.
Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect
register (address 000A16) to “1”.
Area Wait bit Bus cycle
1 2 BCLK cycles
SFR
Internal
ROM/RAM 0 1 BCLK cycle
Invalid 2 BCLK cycles
Table 1.2. Software waits and bus cycles
18
Clock Generating Circuit
Under
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Figure 1.16. Examples of sub-clock
Table 1.3. Main clock and sub-clock generating circuits
Clock Generating Circuit
The clock generating circuit contains two oscillator circuits that supply the operating clock sources to the
CPU and internal peripheral units.
Example of oscillator circuit
Figure 1.15 shows some examples of the main clock circuit, one using an oscillator connected to the circuit,
and the other one using an externally derived clock for input. Figure 1.16 shows some examples of sub-
clock circuits, one using an oscillator connected to the circuit, and the other one using an externally derived
clock for input. Circuit constants in Figures 15 and 16 vary with each oscillator used. Use the values
recommended by the manufacturer of your oscillator.
Figure 1.15. Examples of main clock
Main clock generating circuit Sub clock generating circuit
Use of clock • CPU’s operating clock source • CPU’s operating clock source
• Internal peripheral units’ • Timer A/B/X’s count clock
operating clock source source
Usable oscillator Ceramic or crystal oscillator Crystal oscillator
Pins to connect oscillator XIN, XOUT XCIN, XCOUT
Oscillation stop/restart function Available Available
Oscillator status immediately after reset
Oscillating Stopped
Other Externally derived clock can be input
M30201
(Built-in feedback resistor)
X
IN
X
OUT
Externally derived clock
Open
Vcc
Vss
M30201
(Built-in feedback resistor)
X
IN
X
OUT
R
d
C
IN
C
OUT
(Note)
Note: Insert a damping resistor if
required. The resistance will
vary depending on the
oscillator and the oscillation
drive capacity setting. Use the
value recommended by the
maker of the oscillator.
When the oscillation drive
capacity is set to low, check
that oscillation is stable. Also,
if the oscillator manufacturer's
data sheet specifies that a
feedback resistor be added
external to the chip, insert a
feedback resistor between X
IN
and X
OUT
following the
instruction.
M30201
(Built-in feedback resistor)
XCIN XCOUT
Externally derived clock
Open
Vcc
Vss
M30201
(Built-in feedback resistor)
XCIN XCOUT
(Note)
CCIN CCOUT
RCd
Note: Insert a damping resistor if
required. The resistance will
vary depending on the oscillator
and the oscillation drive
capacity setting. Use the value
recommended by the maker of
the oscillator.
When the oscillation drive
capacity is set to low, check that
oscillation is stable. Also,
if the oscillator manufacturer's
data sheet specifies that a
feedback resistor be added
external to the chip, insert a
feedback resistor between
XCIN and XCOUT following the
instruction.
19
Clock Generating Circuit
Under
development
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Control
Figure 1.17 shows the block diagram of the clock generating circuit.
Sub clock
CM04
f
C32
CM0i : Bit i at address 0006
16
CM1i : Bit i at address 0007
16
WDCi : Bit i at address 000F
16
X
CIN
CM10 “1”
Write signal
1/32
X
COUT
QS
R
WAIT instruction
X
OUT
Main clock
CM05
f
C
CM02
f
1
QS
R
Interrupt request
level judgment output
RESET
Software reset f
C
CM07=0
CM07=1
f
AD
AAA
AAA
Divider
ad
1/2 1/2 1/2 1/2
CM06=0
CM17,CM16=00
CM06=0
CM17,CM16=01
CM06=0
CM17,CM16=10
CM06=1
CM06=0
CM17,CM16=11
d
a
Details of divider
X
IN
f
8
f
32
c
b
b
1/2
c
BCLK
Figure 1.17. Clock generating circuit
20
Clock Generating Circuit
Under
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The following paragraphs describes the clocks generated by the clock generating circuit.
(1) Main clock
The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to
BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 000616). Stopping the
clock, after switching the operating clock source of CPU to the sub-clock, reduces the power dissipation.
After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock
oscillation circuit can be reduced using the XIN-XOUT drive capacity select bit (bit 5 at address 000716).
Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. This bit
changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is re-
tained.
(2) Sub-clock
The sub-clock is generated by the sub-clock oscillation circuit. No sub-clock is generated after a reset.
After oscillation is started using the port Xc select bit (bit 4 at address 000616), the sub-clock can be
selected as BCLK by using the system clock select bit (bit 7 at address 000616). However, be sure that the
sub-clock oscillation has fully stabilized before switching.
After the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the sub-clock
oscillation circuit can be reduced using the XCIN-XCOUT drive capacity select bit (bit 3 at address 000616).
Reducing the drive capacity of the sub-clock oscillation circuit reduces the power dissipation. This bit
changes to “1” when shifting to stop mode and at a reset.
(3) BCLK
The BCLK is the clock that drives the CPU, and is fc or the clock is derived by dividing the main clock by
1, 2, 4, 8, or 16. The BCLK is derived by dividing the main clock by 8 after a reset.
The main clock division select bit 0(bit 6 at address 000616) changes to “1” when shifting from high-
speed/medium-speed to stop mode and at reset. When shifting from low-speed/low power dissipation
mode to stop mode, the value before stop mode is retained.
(4) Peripheral function clock (f1, f8, f32, fAD)
The clock for the peripheral devices is derived from the main clock or by dividing it by 8 or 32. The
peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral
function clock stop bit (bit 2 at 000616) to “1” and then executing a WAIT instruction.
(5) fC32
This clock is derived by dividing the sub-clock by 32. It is used for the timer A, timer B and timer X counts.
(6) fC
This clock has the same frequency as the sub-clock. It is used for BCLK and for the watchdog timer.
21
Clock Generating Circuit
Under
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Figure 1.18 shows the system clock control registers 0 and 1.
Figure 1.18. Clock control registers 0 and 1
System clock control register 0 (Note 1)
Symbol Address When reset
CM0 0006
16
48
16
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
0 0 : I/O port P5
4
0 1 : f
C
output
1 0 : f
8
output
1 1 : Clock divide counter output
b1 b0
CM07
CM05
CM04
CM03
CM01
CM02
CM00
CM06
Clock output function
select bit
WAIT peripheral function
clock stop bit
0 : Do not stop peripheral function clock in wait mode
1 : Stop peripheral function clock in wait mode (Note 8)
X
CIN
-X
COUT
drive capacity
select bit (Note 2) 0 : LOW
1 : HIGH
Port X
C
select bit 0 : I/O port
1 : X
CIN
-X
COUT
generation
Main clock (X
IN
-X
OUT
)
stop bit (Note 3,4,5) 0 : On
1 : Off
Main clock division select
bit 0 (Note 7) 0 : CM16 and CM17 valid
1 : Division by 8 mode
System clock select bit
(Note 6) 0 : X
IN
, X
OUT
1 : X
CIN
, X
COUT
Note 1: Set bit 0 of the protect register (address 000A
16
) to “1” before writing to this register.
Note 2: Changes to “1” when shifting to stop mode and at a reset.
Note 3: This bit is used to stop the main clock when placing the device in a low-power mode. If you want to operate with X
IN
after exiting from the stop mode, set this bit to “0”. When operating with a self-excited oscillator, set the system clock
select bit (CM07) to “1” before setting this bit to “1”.
Note 4: When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable.
Note 5: If this bit is set to “1”, X
OUT
turns “H”. The built-in feedback resistor remains being connected, so X
IN
turns pulled up to
X
OUT
(“H”) via the feedback resistor.
Note 6: Set port Xc select bit (CM04) to “1” and stabilize the sub-clock oscillating before setting to this bit from “0” to “1”.
Do not write to both bits at the same time. And also, set the main clock stop bit (CM05) to “0” and stabilize the main clock
oscillating before setting this bit from “1” to “0”.
Note 7: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When shifting
from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
Note 8: f
C32
is not included.
System clock control register 1 (Note 1)
Symbol Address When reset
CM1 0007
16
20
16
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
CM10 All clock stop control bit
(Note 4) 0 : Clock on
1 : All clocks off (stop mode)
CM15 X
IN
-X
OUT
drive capacity
select bit (Note 2) 0 : LOW
1 : HIGH
WR
WR
CM16
CM17
Reserved bit Always set to
“0”
Reserved bit Always set to
“0”
Main clock division
select bit 1 (Note 3) 0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
b7 b6
00
Reserved bit Always set to
“0”
Reserved bit Always set to
“0”
00
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Note 1: Set bit 0 of the protect register (address 000A
16
) to “1” before writing to this register.
Note 2: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When shifting
from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
Note 3: Can be selected when bit 6 of the system clock control register 0 (address 000616) is “0”. If “1”, division mode is fixed at 8.
Note 4: If this bit is set to “1”, X
OUT
turns “H”, and the built-in feedback resistor is cut off. X
CIN
and X
COUT
turn high-impedance state.
22
Clock Generating Circuit
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Output
The clock output function select bit allows you to choose the clock from f8, or a divide-by-n clock that is
output from the P54/CKOUT pin. The clock divide counter is an 8-bit counter whose count source is f32, and
its divide ratio can be set in the range of 0016 to FF16. Figure 1.19 shows a block diagram of clock output.
Figure 1.19. Block diagram of clock output
Clock source
selection
Reload register (8)
Low-order 8 bits
Data bus low-order bits
P5
4
f
8
f
C
1/2
Division n+1 n=00
16
to FF
16
Clock divided couter (8)
Example:
When f(X
IN
)=10MHz
n=07
16 :
approx. 16.5kHz
n=26
16 :
approx. 4.0kHz
n=4D
16 :
approx. 2.0kHz
n=9B
16 :
approx. 1.0kHz
P5
4
/CK
OUT
f
32
Address 038E
16
23
Clock Generating Circuit
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pin States
Port
Retains status before wait mode
CLKOUT When fC selected Does not stop
When f8, clock devided Does not stop when the WAIT
counter output selected peripheral function clock stop bit is “0”.
When the WAIT peripheralfunction
clock stop bit is “1”,the status immedi-
ately prior to entering wait mode is
maintained.
Wait Mode
When a WAIT instruction is executed, BCLK stops and the microcomputer enters the wait mode. In this
mode, oscillation continues but BCLK and watchdog timer stop. Writing “1” to the WAIT peripheral function
clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal peripheral
functions, allowing power dissipation to be reduced. Table 1.5 shows the status of the ports in wait mode.
Wait mode is cancelled by a hardware reset or interrupt. If an interrupt is used to cancel wait mode, the
microcomputer restarts from the interrupt routine using as BCLK, the clock that had been selected when the
WAIT instruction was executed.
Table 1.5. Port status during wait mode
Table 1.4. Port status during stop mode
Wait Mode
Pin States
Port Retains status before stop mode
CLKOUT When fC selected “H”
When f8, clock devided Retains status before stop mode
counter output selected
Stop Mode
Writing “1” to the all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the microcom-
puter enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC remains
above 2V.
Because the oscillation of BCLK, f1 to f32, fc32, and fAD stops in stop mode, peripheral functions such as
the A-D converter and watchdog timer do not function. However, timer A, timer B and timer X operate
provided that the event counter mode is set to an external pulse, and UART0 functions provided an external
clock is selected. Table 1.4 shows the status of the ports in stop mode.
Stop mode is cancelled by a hardware reset or an interrupt. If an interrupt is to be used to cancel stop mode,
that interrupt must first have been enabled. If returning by an interrupt, that interrupt routine is executed.
When shifting from high-speed/medium-speed mode to stop mode and at a reset, the main clock division
select bit 0 (bit 6 at address 000616) is set to “1”. When shifting from low-speed/low power dissipation mode
to stop mode, the value before stop mode is retained.
24
Clock Generating Circuit
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0 1 0 0 0 Invalid Division by 2 mode
1 0 0 0 0 Invalid Division by 4 mode
Invalid Invalid 0 1 0 Invalid Division by 8 mode
1 1 0 0 0 Invalid Division by 16 mode
0 0 0 0 0 Invalid No-division mode
Invalid Invalid 1 Invalid 0 1 Low-speed mode
Invalid Invalid 1 Invalid 1 1 Low power dissipation mode
Status Transition of BCLK
Power dissipation can be reduced and low-voltage operation achieved by changing the count source for
BCLK. Table 1.6 shows the operating modes corresponding to the settings of system clock control regis-
ters 0 and 1.
When reset, the device starts in division by 8 mode. The main clock division select bit 0(bit 6 at address
000616) changes to “1” when shifting from high-speed/medium-speed to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
The following shows the operational modes of BCLK.
(1) Division by 2 mode
The main clock is divided by 2 to obtain the BCLK.
(2) Division by 4 mode
The main clock is divided by 4 to obtain the BCLK.
(3) Division by 8 mode
The main clock is divided by 8 to obtain the BCLK. When reset, the device starts operating from this
mode. Before the user can go from this mode to no division mode, division by 2 mode, or division by 4
mode, the main clock must be oscillating stably. When going to low-speed or lower power consumption
mode, make sure the sub-clock is oscillating stably.
(4) Division by 16 mode
The main clock is divided by 16 to obtain the BCLK.
(5) No-division mode
The main clock is divided by 1 to obtain the BCLK.
(6) Low-speed mode
fC is used as BCLK. Note that oscillation of both the main and sub-clocks must have stabilized before
transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the sub-
clock starts. Therefore, the program must be written to wait until this clock has stabilized immediately
after powering up and after stop mode is cancelled.
(7) Low power dissipation mode
fC is the BCLK and the main clock is stopped.
CM17 CM16 CM07 CM06 CM05 CM04 Operating mode of BCLK
Status Transition of BCLK
Table 1.6. Operating modes dictated by settings of system clock control registers 0 and 1
Note : Before the count source for BCLK can be changed from XIN to XCIN or vice versa, the clock to which
the count source is going to be switched must be oscillating stably. Allow a wait time in software for
the oscillation to stabilize before switching over the clock.
25
Clock Generating Circuit
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Power Saving
There are three power save modes.
(1) Normal operating mode
• High-speed mode
In this mode, one main clock cycle forms BCLK. The CPU operates on the BCLK. The peripheral
functions operate on the clocks specified for each respective function.
• Medium-speed mode
In this mode, the main clock is divided into 2, 4, 8, or 16 to form BCLK. The CPU operates on the
BCLK. The peripheral functions operated on the clocks specified for each respective function.
• Low-speed mode
In this mode, fc forms BCLK. The CPU operates on the fc clock. fc is the clock supplied by the
subclock. The peripheral functions operate on the clocks specified for each respective function.
• Low power-dissipation mode
This mode is selected when the main clock is stopped from low-speed mode. The CPU operates on
the fc clock. fc is the clock supplied by the subclock. Only the peripheral functions for which the
subclock was selected as the count source continue to run.
(2) Wait mode
CPU operation is halted in this mode. The oscillator continues to run.
(3) Stop mode
All oscillators stop in this mode. The CPU and internal peripheral functions all stop. Of all 3 power saving
modes, power savings are greatest in this mode.
Figure 1.20 shows the transition between each of the three modes, (1), (2), and (3).
Power Saving
26
Clock Generating Circuit
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Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Figure 1.20. Clock transition
Transition of stop mode, wait mode
Transition of normal mode
Reset
Medium-speed mode
(divided-by-8 mode)
Interrupt
CM10 = “1”
All oscillators stopped CPU operation stopped
Medium-speed mode
(divided-by-8 mode)
BCLK : f(XIN)/8
CM07 = “0” CM06 = “1”
Low-speed mode
High-speed mode
Main clock is oscillating
Sub clock is stopped
Main clock is oscillating
Sub clock is stopped
Main clock is stopped
Sub clock is oscillating
Main clock is oscillating
Sub clock is oscillating
Low power dissipation mode
High-speed/medium-
speed mode
Low-speed/low power
dissipation mode
Normal mode
Stop mode
Stop mode
Stop mode
All oscillators stopped
All oscillators stopped
Wait mode
Wait mode
Wait mode
CPU operation stopped
CPU operation stopped
Interrupt
WAIT
instruction
Interrupt
WAIT
instruction
Interrupt
WAIT
instruction
CM10 = “1”
Interrupt
Interrupt
CM10 = “1”
BCLK : f(XIN)/2
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “1”
Medium-speed mode
(divided-by-2 mode)
BCLK : f(XIN)/16
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “1”
Medium-speed mode
(divided-by-16 mode)
BCLK : f(XIN)/4
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “0”
Medium-speed mode
(divided-by-4 mode)
BCLK : f(XIN)
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “0” BCLK : f(XIN)/8
Medium-speed mode
(divided-by-8 mode)
CM07 = “0”
CM06 = “1”
High-speed mode
BCLK : f(XIN)/2
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “1”
Medium-speed mode
(divided-by-2 mode)
BCLK : f(XIN)/16
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “1”
Medium-speed mode
(divided-by-16 mode)
BCLK : f(XIN)/4
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “0”
Medium-speed mode
(divided-by-4 mode)
BCLK : f(XIN)
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “0”
BCLK : f(XCIN)
CM07 = “1”
BCLK : f(XCIN)
CM07 = “1”
Main clock is oscillating
Sub clock is oscillating
CM07 = “0”
(Note 1, 3)
CM07 = “0” (Note 1)
CM06 = “1”
CM04 = “0”
CM07 = “1”
(Note 2)
CM07 = “0” (Note 1)
CM06 = “0” (Note 3)
CM04 = “1”
CM07 = “1” (Note 2)
CM05 = “1”
CM05 = “0” CM05 = “1”
CM04 = “0” CM04 = “1”
CM06 = “0”
(Notes 1,3)
CM06 = “1”
CM04 = “0” CM04 = “1”
(Notes 1, 3)
Note 1: Switch clock after oscillation of main clock is sufficiently stable.
Note 2: Switch clock after oscillation of sub clock is sufficiently stable.
Note 3: Change CM06 after changing CM17 and CM16.
Note 4: Transit in accordance with arrow.
(Refer to the following for the transition of normal mode.)
Power Saving
27
Clock Generating Circuit
Under
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Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Protection
The protection function is provided so that the values in important registers cannot be changed in the event
that the program runs out of control. Figure 1.21 shows the protect register. The values in the processor
mode register 0 (address 000416), processor mode register 1 (address 000516), system clock control reg-
ister 0 (address 000616), system clock control register 1 (address 0007 16) and port P4 direction register
(address 03EA16) can only be changed when the respective bit in the protect register is set to “1”. There-
fore, important outputs can be allocated to port P4.
If, after “1” (write-enabled) has been written to the port P4 direction register write-enable bit (bit 2 at address
000A16), a value is written to any address, the bit automatically reverts to “0” (write-inhibited). However, the
system clock control registers 0 and 1 write-enable bit (bit 0 at 000A16) and processor mode register 0 and
1 write-enable bit (bit 1 at 000A16) do not automatically return to “0” after a value has been written to an
address. The program must therefore be written to return these bits to “0”.
Protect register
Symbol Address When reset
PRCR 000A
16
XXXXX000
2
Bit nameBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
0 : Write-inhibited
1 : Write-enabled
PRC1
PRC0
PRC2
Enables writing to processor mode
registers 0 and 1 (addresses 0004
16
and 0005
16
)
Function
0 : Write-inhibited
1 : Write-enabled
Enables writing to system clock
control registers 0 and 1 (addresses
0006
16
and 0007
16
)
Enables writing to port P4 direction
register (address 03EA
16
) (Note
)
0 : Write-inhibited
1 : Write-enabled
WR
Nothing is assigned.
These bits can neither be set nor reset. When read, their contents are
indeterminate.
Note: Writing a value to an address after “1” is written to this bit returns the bit
to “0” . Other bits do not automatically return to “0” and they must therefore
be reset by the program.
A
A
A
A
A
A
Figure 1.21. Protect register
Protection
28
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Interrupts
Special
Peripheral I/O*1
Overview of Interrupt
Type of Interrupts
Figure 1.22 lists the types of interrupts.
Figure 1.22. Classification of interrupts
• Maskable interrupt : An interrupt which can be enabled (disabled) by the interrupt enable flag (I
flag) or whose interrupt priority can be changed by priority level.
• Non-maskable interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority cannot be changed by priority level.
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
INT instruction
Software
Hardware
Interrupt Reset
________
DBC
Watchdog timer
Single step
Address matched
*1
Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system.
29
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Interrupts
Software Interrupts
A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable
interrupts.
• Undefined instruction interrupt
An undefined instruction interrupt occurs when executing the UND instruction.
• Overflow interrupt
An overflow interrupt occurs when executing the INTO instruction with the overflow flag (O flag) set to “1”.
The following are instructions whose O flag changes by arithmetic:
ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
• BRK interrupt
A BRK interrupt occurs when executing the BRK instruction.
• INT interrupt
An INT interrupt occurs when assigning one of software interrupt numbers 0 through 63 and executing the
INT instruction. Software interrupt numbers 0 through 31 are assigned to peripheral I/O interrupts, so
executing the INT instruction allows executing the same interrupt routine that a peripheral I/O interrupt
does.
The stack pointer (SP) used for the INT interrupt is dependent on which software interrupt number is
involved.
So far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack
pointer assignment flag (U flag) when it accepts an interrupt request. If change the U flag to “0” and select
the interrupt stack pointer (ISP), and then execute an interrupt sequence. When returning from the
interrupt routine, the U flag is returned to the state it was before the acceptance of interrupt request. So
far as software numbers 32 through 63 are concerned, the stack pointer does not make a shift.
30
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Interrupts
Hardware Interrupts
Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts.
(1) Special interrupts
Special interrupts are non-maskable interrupts.
• Reset
Reset occurs if an “L” is input to the RESET pin.
• DBC interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances.
• Watchdog timer interrupt
Generated by the watchdog timer.
• Single-step interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug flag
(D flag) set to “1”, a single-step interrupt occurs after one instruction is executed.
• Address match interrupt
An address match interrupt occurs immediately before the instruction held in the address indicated by
the address match interrupt register is executed with the address match interrupt enable bit set to “1”.
If an address other than the first address of the instruction in the address match interrupt register is
set, no address match interrupt occurs.
(2) Peripheral I/O interrupts
A peripheral I/O interrupt is generated by one of built-in peripheral functions. The interrupt vector table is
the same as the one for software interrupt numbers 0 through 31 the INT instruction uses. Peripheral I/O
interrupts are maskable interrupts.
• Key-input interrupt ___
A key-input interrupt occurs if an “L” is input to the KI pin.
• A-D conversion interrupt
This is an interrupt that the A-D converter generates.
• UART0 and UART1 transmission interrupt
These are interrupts that the serial I/O transmission generates.
• UART0 and UART1 reception interrupt
These are interrupts that the serial I/O reception generates.
• Timer A0 interrupt
This is an interrupts that timer A0 generates.
• Timer B0 and timer B2 interrupt
These are interrupts that timer B generates.
• Timer X0 to timer X2 interrupt
These are interrupts that timer X generates.
________ ________
• INT0 and INT1 interrupt
______ ______
An INT interrupt occurs if either a rising edge or a falling edge is input to the INT pin.
31
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Interrupts
Interrupts and Interrupt Vector Tables
If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector
table. Set the first address of the interrupt routine in each vector table. Figure 1.23 shows format for
specifying interrupt vector addresses.
Two types of interrupt vector tables are available — fixed vector table in which addresses are fixed and
variable vector table in which addresses can be varied by the setting.
Interrupt source Vector table addresses Remarks
Address (L) to address (H)
Undefined instruction FFFDC16 to FFFDF16 Interrupt on UND instruction
Overflow FFFE016 to FFFE316 Interrupt on INTO instruction
BRK instruction FFFE416 to FFFE716
If the vector is filled with FF
16
, program execution starts from
the address shown by the vector in the variable vector table
Address match FFFE816 to FFFEB16 There is an address-matching interrupt enable bit
Single step (Note) FFFEC16 to FFFEF16 Do not use
Watchdog timer FFFF016 to FFFF316
________
DBC (Note) FFFF416 to FFFF716 Do not use
- FFFF816 to FFFFB16 -
Reset FFFFC16 to FFFFF16
Table 1.7. Interrupt and fixed vector address
Figure 1.23. Format for specifying interrupt vector addresses
Note: Interrupts used for debugging purposes only.
AAAAAAAA
AAAAAAAA
Mid address
AAAAAAAA
AAAAAAAA
Low address
AAAAAAAA
AAAAAAAA
0 0 0 0 High address
AAAAAAAA
AAAAAAAA
0 0 0 0 0 0 0 0
Vector address + 0
Vector address + 1
Vector address + 2
Vector address + 3
LSB
MSB
• Fixed vector tables
The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area
extending from FFFDC16 to FFFFF16. One vector table comprises four bytes. Set the first address of
interrupt routine in each vector table. Table 1.7 shows the interrupts assigned to the fixed vector tables
and addresses of vector tables.
32
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Interrupts
Table 1.8. Interrupt causes (variable interrupt vector addresses)
Software interrupt number Interrupt source
Vector table address
Address (L) to address (H)
Remarks
Cannot be masked by I flag+0 to +3 (Note) BRK instructionSoftware interrupt number 0
+44 to +47 (Note) Software interrupt number 11
+48 to +51 (Note)Software interrupt number 12
+52 to +55 (Note)Software interrupt number 13
+56 to +59 (Note)Software interrupt number 14
+68 to +71 (Note)Software interrupt number 17
+72 to +75 (Note)Software interrupt number 18
+76 to +79 (Note)Software interrupt number 19
+80 to +83 (Note)Software interrupt number 20
+84 to +87 (Note)Software interrupt number 21
+88 to +91 (Note)Software interrupt number 22
+92 to +95 (Note)Software interrupt number 23
+96 to +99 (Note)Software interrupt number 24
+100 to +103 (Note)Software interrupt number 25
+104 to +107 (Note)Software interrupt number 26
+108 to +111 (Note)Software interrupt number 27
+112 to +115 (Note)Software interrupt number 28
+116 to +119 (Note)Software interrupt number 29
+120 to +123 (Note)Software interrupt number 30
+124 to +127 (Note)Software interrupt number 31
+128 to +131 (Note)Software interrupt number 32
+252 to +255 (Note)Software interrupt number 63
to
Note : Address relative to address in interrupt table register (INTB).
to
Key input interrupt
A-D
UART0 transmit
UART0 receive
UART1 transmit
UART1 receive
Timer A0
Timer X0
Timer X1
Timer X2
Timer B0
Timer B1
INT0
INT1
Software interrupt Cannot be masked by I flag
• Variable vector tables
The addresses in the variable vector table can be modified, according to the user’s settings. Indicate the
first address using the interrupt table register (INTB). The 256-byte area subsequent to the address the
INTB indicates becomes the area for the variable vector tables. One vector table comprises four bytes.
Set the first address of the interrupt routine in each vector table. Table 1.8 shows the interrupts assigned
to the variable vector tables and addresses of vector tables.
33
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Interrupts
Interrupt Control
Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the
priority to be accepted. What is described here does not apply to non-maskable interrupts.
Enable or disable a maskable interrupt using the interrupt enable flag (I flag), interrupt priority level select
bit, and processor interrupt priority level (IPL). Whether an interrupt request is present or absent is indi-
cated by the interrupt request bit. The interrupt request bit and the interrupt priority level selection bit are
located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I flag) and the IPL
are located in the flag register (FLG).
Figure 1.24 shows the interrupt control registers.
34
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Interrupts
Figure 1.24. Interrupt control register
Symbol Address When reset
INTiIC(i=0, 1) 005D
16
, 005E
16
XX00X000
2
Bit name FunctionBit symbol
WR
b7 b6 b5 b4 b3 b2 b1 b0
A
A
AA
AA
ILVL0
IR
POL
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
Interrupt priority level
select bit
Interrupt request bit
Polarity select bit
Reserved bit
0: Interrupt not requested
1: Interrupt requested
0 : Selects falling edge
1 : Selects rising edge
Always set to “0”
ILVL1
ILVL2
Note: This bit can only be accessed for reset (= 0), but cannot be accessed
for set (= 1).
(Note)
Interrupt control register
b7 b6 b5 b4 b3 b2 b1 b0
A
A
AA
AA
AA
AA
A
A
Bit name FunctionBit symbol
WR
Symbol Address When reset
KUPIC 004D
16
XXXXX000
2
ADIC 004E
16
XXXXX000
2
SiTIC(i=0, 1) 0051
16
, 0053
16
XXXXX000
2
SiRIC(i=0, 1) 0052
16
, 0054
16
XXXXX000
2
TAiIC(i=0) 0055
16
XXXXX000
2
TXiIC(i=0 to 2) 0056
16
to 0058
16
XXXXX000
2
TBiIC(i=0, 1) 005A
16
, 005B
16
XXXXX000
2
ILVL0
IR
Interrupt priority level
select bit
Interrupt request bit 0 : Interrupt not requested
1 : Interrupt requested
ILVL1
ILVL2
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
(Note)
Note: This bit can only be accessed for reset (= 0), but cannot be accessed
for set (= 1).
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b2 b1 b0
0
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
35
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Interrupts
Interrupt Enable Flag
The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this
flag to “1” enables all maskable interrupts; setting it to “0” disables all maskable interrupts. This flag is set
to “0” after reset.
Interrupt Request Bit
The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt is
accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. The
interrupt request bit can also be set to "0" by software. (Do not set this bit to "1").
Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)
Set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits
of the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared
with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL.
Therefore, setting the interrupt priority level to “0” disables the interrupt.
Table 1.9 shows the settings of interrupt priority levels and Table 1.10 shows the interrupt levels enabled,
according to the consist of the IPL.
The following are conditions under which an interrupt is accepted:
· interrupt enable flag (I flag) = 1
· interrupt request bit = 1
· interrupt priority level > IPL
The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are
independent, and they are not affected by one another.
Table 1.10. Interrupt levels enabled according
to the contents of the IPL
Table 1.9. Settings of interrupt priority levels
Interrupt priority
level select bit Interrupt priority
level Priority
order
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Level 0
(interrupt disabled)
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
Low
High
b2 b1 b0
Enabled interrupt priority levels
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Interrupt levels 1 and above are enabled
Interrupt levels 2 and above are enabled
Interrupt levels 3 and above are enabled
Interrupt levels 4 and above are enabled
Interrupt levels 5 and above are enabled
Interrupt levels 6 and above are enabled
Interrupt levels 7 and above are enabled
All maskable interrupts are disabled
IPL
2
IPL
1
IPL
0
IPL
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Interrupts
Changing the Interrupt Control Register
< Program examples >
The program examples are described as follow:
Example 1:
INT_SWITCH1:
FCLR I ; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
NOP ; Four NOP instructions are required when using HOLD function.
NOP
FSET I ; Enable interrupts.
Example 2:
INT_SWITCH2:
FCLR I ; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
MOV.W MEM, R0 ; Dummy read.
FSET I ; Enable interrupts.
Example 3:
INT_SWITCH3:
PUSHC FLG ; Push Flag register onto stack
FCLR I ; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
POPC FLG ; Enable interrupts.
The reason why two NOP instructions or dummy read are inserted before FSET I in Examples 1 and
2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten
due to effects of the instruction queue.
If changing the interrupt control register using an instruction other than the instructions listed hear, and
if an interrupt occurs associated with this register during execution of the instruction, there can be
instances in which the interrupt request bit is not set. To avoid this problem, use one of the instruc-
tions given below to change the register.
Following instructions: AND, OR, BCLR or BSET
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Interrupts
Interrupt Sequence
An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the
instant the interrupt routine is executed — is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed, and transfers control to the interrupt sequence from the next
cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction,
the processor temporarily suspends the instruction being executed, and transfers control to the interrupt
sequence.
In the interrupt sequence, the processor carries out the following in sequence given:
(1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading
address 0000016. After this, the corresponding interrupt request bit becomes "0".
(2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt
sequence in the temporary register (Note) within the CPU.
(3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U
flag) to “0” (the U flag, however, does not change if the INT instruction, in software interrupt
numbers 32 through 63, is executed).
(4) Saves the content of the temporary register (Note) within the CPU in the stack area.
(5) Saves the content of the program counter (PC) in the stack area.
(6) Sets the interrupt priority level of the accepted instruction in the IPL.
Interrupt Response Time
'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first
instruction within the interrupt routine has been executed. This time comprises the period from the
occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the
time required for executing the interrupt sequence (b). Figure 1.25 shows the interrupt response time.
Instruction Interrupt sequence Instruction in
interrupt routine
Time
Interrupt response time
(a) (b)
Interrupt request acknowledgedInterrupt request generated
(a) Time from interrupt request is generated to when the instruction then under execution is completed.
(b) Time in which the instruction sequence is executed.
Figure 1.25. Interrupt response time
After the interrupt sequence is completed, the processor resumes executing instructions from the first
address of the interrupt routine.
Note: This register cannot be utilized by the user.
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Interrupts
Interrupt sources without priority levels
7
Value set in the IPL
Watchdog timer
Other Not changed
0
Variation of IPL when Interrupt Request is Accepted
If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL.
If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown
in Table 1.12 is set in the IPL.
Table 1.12. Relationship between interrupts without interrupt priority levels and IPL
Table 1.11. Time required for executing the interrupt sequence
Reset
Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the
DIVX instruction (without wait).
Time (b) is as shown in Table 1.11.
________
Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address match
interrupt or of a single-step interrupt.
Note 2: Locate an interrupt vector address in an even address, if possible.
Figure 1.26. Time required for executing the interrupt sequence
Stack pointer (SP) valueInterrupt vector address 16-bit bus, without wait 8-bit bus, without wait
Even
Even
Odd (Note 2)
Odd (Note 2)
Even
Odd
Even
Odd
18 cycles (Note 1)
19 cycles (Note 1)
19 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
Indeterminate
123456789 101112 13 14 15 16 17 18
The indeterminate segment is dependent on the queue buffer.
If the queue buffer is ready to take an instruction, a read cycle occurs.
Indeterminate SP-2
contents SP-4
contents vec
contents vec+2
contents
Interrupt
information
Address
0000
16
Indeterminate SP-2 SP-4 vec vec+2 PC
BCLK
Address bus
Data bus
W
R
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Interrupts
Saving Registers
In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter
(PC) are saved in the stack area.
First, the processor saves the 4 high-order bits of the program counter, and 4 high-order bits and 8 low-
order bits of the FLG register, 16 bits in total, in the stack area, then saves 16 low-order bits of the
program counter. Figure 1.27 shows the state of the stack as it was before the acceptance of the interrupt
request, and the state the stack after the acceptance of the interrupt request.
Save other necessary registers at the beginning of the interrupt routine using software. Using the
PUSHM instruction alone can save all the registers except the stack pointer (SP).
Figure 1.27. State of stack before and after acceptance of interrupt request
Address
Content of previous stack
Stack area
[SP]
Stack pointer
value before
interrupt occurs
m
m – 1
m – 2
m – 3
m – 4
Stack status before interrupt request
is acknowledged Stack status after interrupt request
is acknowledged
Content of previous stack
m + 1
MSB LSB
m
m – 1
m – 2
m – 3
m – 4
Address
Flag register (FLG
L
)
Content of previous stack
Stack area
Flag register
(FLG
H
)Program
counter (PC
H
)
[SP]
New stack
pointer value
Content of previous stack
m + 1
MSB LSB
Program counter (PC
L
)
Program counter (PC
M
)
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Interrupts
Figure 1.28. Operation of saving registers
The operation of saving registers carried out in the interrupt sequence is dependent on whether the
content of the stack pointer (Note), at the time of acceptance of an interrupt request, is even or odd. If the
content of the stack pointer (Note) is even, the content of the flag register (FLG) and the content of the
program counter (PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at
a time. Figure 1.28 shows the operation of the saving registers.
Note: Stack pointer indicated by U flag.
(2) Stack pointer (SP) contains odd number
[SP] (Odd)
[SP] – 1 (Even)
[SP] – 2(Odd)
[SP] – 3 (Even)
[SP] – 4(Odd)
[SP] – 5 (Even)
Address Sequence in which order
registers are saved
(2)
(1)
Finished saving registers
in four operations.
(3)
(4)
(1) Stack pointer (SP) contains even number
[SP] (Even)
[SP] – 1(Odd)
[SP] – 2 (Even)
[SP] – 3(Odd)
[SP] – 4 (Even)
[SP] – 5 (Odd)
Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
Address
Program counter (PC
M
)
Stack area
Flag register (FLG
L
)
Program counter (PC
L
)
Sequence in which order
registers are saved
(2) Saved simultaneously,
all 16 bits
(1) Saved simultaneously,
all 16 bits
Finished saving registers
in two operations.
Program counter (PC
M
)
Stack area
Flag register (FLG
L
)
Program counter (PC
L
)
Saved simultaneously,
all 8 bits
Flag register
(FLG
H
)Program
counter (PC
H
)
Flag register
(FLG
H
)Program
counter (PC
H
)
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Interrupts
Returning from an Interrupt Routine
Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register
(FLG) as it was immediately before the start of interrupt sequence and the contents of the program
counter (PC), both of which have been saved in the stack area. Then control returns to the program that
was being executed before the acceptance of the interrupt request, so that the suspended process re-
sumes.
Return the other registers saved by software within the interrupt routine using the POPM or similar in-
struction before executing the REIT instruction.
Interrupt Priority
If there are two or more interrupt requests occurring at a point in time within a single sampling (checking
whether interrupt requests are made), the interrupt assigned a higher priority is accepted.
Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority
level select bit. If the same interrupt priority level is assigned, however, the interrupt assigned a higher
hardware priority is accepted.
Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest priority),
watchdog timer interrupt, etc. are regulated by hardware.
Figure 1.29 shows the priorities of hardware interrupts.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches
invariably to the interrupt routine.
Interrupt Priority Level Judge Circuit
This circuit selects the interrupt with the highest priority level when two or more interrupts are generated
simultaneously.
Figure 1.30 shows the interrupt resolution circuit.
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Interrupts
Figure 1.30. Interrupt resolution circuit
Timer B0
Timer X2
Timer X0
Timer B1
Timer X1
UART1 reception
UART0 reception
A-D conversion
Timer A0
UART1 transmission
UART0 transmission
Key input interrupt
Processor interrupt priority level
(IPL)
Interrupt enable flag (I flag)
INT1
INT0
Watchdog timer
Reset
DBC
Interrupt
request
accepted
Level 0 (initial value)
Priority level of each interrupt
High
Low
Priority of peripheral I/O
interrupts
(if priority levels are same)
Address match
Interrupt request level judgment output
Figure 1.29. Hardware interrupts priorities
________
Reset > DBC > Watchdog timer > Peripheral I/O > Single step > Address match
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Interrupts
Key Input Interrupt
Key Input Interrupt
If the direction register of any of P00 to P07 is set for input and a falling edge is input to that port, a key input
interrupt is generated. A key input interrupt can also be used as a key-on wakeup function for cancelling the
wait mode or stop mode. Figure 1.31 shows the block diagram of the key input interrupt. Note that if an “L”
level is input to any pin that has not been disabled for input, inputs to the other pins are not detected as an
interrupt.
Figure 1.31. Block diagram of key input interrupt
Interrupt control
circuit
Key input interrupt control register (address 004D
16
)
Key input interrupt
request
P0
7
/KI
7
P0
6
/KI
6
P0
1
/KI
1
P0
0
/KI
0
Port P0
4
-P0
7
pull-up select
bit
Port P0
7
direction
register
Pull-up
transistor
Port P0
7
direction register
Port P0
6
direction
register
Port P0
1
direction
register
Port P0
0
direction
register
Pull-up
transistor
Pull-up
transistor
Pull-up
transistor
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Interrupts
Address Match Interrupt
An address match interrupt is generated when the address match interrupt address register contents match
the program counter value. Two address match interrupts can be set, each of which can be enabled and
disabled by an address match interrupt enable bit. Address match interrupts are not affected by the inter-
rupt enable flag (I flag) and processor interrupt priority level (IPL).
Figure 1.32 shows the address match interrupt-related registers.
Bit nameBit symbol
Symbol Address When reset
AIER 0009
16
XXXXXX00
2
Address match interrupt enable register
Function WR
AAAAAAAAAAAAAA
A
AAAAAAAAAAAA
A
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
A
AAAAAAAAAAAA
A
AAAAAAAAAAAAAA
Address match interrupt 0
enable bit 0 : Interrupt disabled
1 : Interrupt enabled
AIER0
Address match interrupt 1
enable bit
AIER1
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
Symbol Address When reset
RMAD0 0012
16
to 0010
16
X00000
16
RMAD1 0016
16
to 0014
16
X00000
16
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
b7 b6 b5 b4 b3 b2 b1 b0
WR
Address setting register for address match interrupt
Function Values that can be set
Address match interrupt register i (i = 0, 1)
00000
16
to FFFFF
16
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
0 : Interrupt disabled
1 : Interrupt enabled
b0 b7 b0b3
(b19) (b16) b7 b0
(b15) (b8)
b7
(b23)
AA
A
AA
A
AA
AA
A
A
Address Match Interrupt
Figure 1.32. Address match interrupt-related registers
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Interrupts
Precautions for Interrupts
(1) Reading address 0000016
• When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and
interrupt request level) in the interrupt sequence.
The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”.
Reading address 0000016 by software sets enabled highest priority interrupt source request bit to “0”.
Though the interrupt is generated, the interrupt routine may not be executed.
Do not read address 0000016 by software.
(2) Setting the stack pointer
• The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt
before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in the
stack pointer before accepting an interrupt. Concerning the first instruction immediately after reset,
generating any interrupts is prohibited.
(3) External interrupt ________
• Either an “L” level or an “H” level of at least 250 ns width is necessary for the signal input to pins INT0
________
and INT1 regardless of the CPU operation clock.
________ ________
• When changing a polarity of pins INT0 and INT1, the interrupt request bit may become "1". Clear the
______
interrupt request bit after changing the polarity. Figure 1.33 shows the switching condition of INT inter-
rupt request.
______
Figure 1.33. Switching condition of INT interrupt request
(4) Changing interrupt control register
See "Changing Interrupt Control Register".
Set the interrupt priority level to level 0
(Disable
INTi
interrupt)
Set the polarity select bit
Clear the interrupt request bit to “0”
Set the interrupt priority level to level 1 to 7
(Enable the accepting of INTi interrupt request)
Clear the interrupt enable flag to “0”
(Disable interrupt)
Set the interrupt enable flag to “1”
(Enable interrupt)
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Watchdog Timer
Write to the watchdog timer
start register
(address 000E
16
)
RESET
Watchdog timer
interrupt request
Watchdog timer
Set to
“7FFF
16
”
1/128
1/16
“CM07 = 0”
“WDC7 = 1”
“CM07 = 0”
“WDC7 = 0”
“CM07 = 1”
BCLK
1/2
Prescaler
Figure 1.34. Block diagram of watchdog timer
Watchdog Timer
The watchdog timer has the function of detecting when the program is out of control. The watchdog timer is
a 15-bit counter which down-counts the clock derived by dividing the BCLK using the prescaler. A watchdog
timer interrupt is generated when an underflow occurs in the watchdog timer. When XIN is selected for the
BCLK, bit 7 of the watchdog timer control register (address 000F16) selects the prescaler division ratio (by
16 or by 128). When XCIN is selected as the BCLK, the prescaler is set for division by 2 regardless of bit 7
of the watchdog timer control register (address 000F16).
When XIN is selected in BCLK
Watchdog timer cycle =
When XCIN is selected in BCLK
Watchdog timer cycle =
For example, when BCLK is 10MHz and the prescaler division ratio is set to 16, the watchdog timer cycle is
approximately 52.4 ms.
The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when
a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is
reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by
writing to the watchdog timer start register (address 000E16).
Figure 1.34 shows the block diagram of the watchdog timer. Figure 1.35 shows the watchdog timer-related
registers.
Prescaler division ratio (16 or 128) x watchdog timer count (32768)
BCLK
Prescaler division ratio (2) x watchdog timer count (32768)
BCLK
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Watchdog Timer
Watchdog timer control register
Symbol Address When reset
WDC 000F
16
000XXXXX
2
FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
High-order bit of watchdog timer
WDC7
Bit name
Prescaler select bit 0 : Divided by 16
1 : Divided by 128
Watchdog timer start register
Symbol Address When reset
WDTS 000E
16
Indeterminate
WR
b7 b0
Function
The watchdog timer is initialized and starts counting after a write instruction to
this register. The watchdog timer value is always initialized to “7FFF
16
”
regardless of whatever value is written.
Reserved bit
Reserved bit Must always be set to “0”
Must always be set to “0”
00
AA
AA
A
AA
A
AA
A
A
Figure 1.35. Watchdog timer control and start registers
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Timer A
Timer
There are six 16-bit timers. These timers can be classified by function into timer A (one), timers B (two) and
timers X (three). All these timers function independently. Figure 1.36 show the block diagram of timers.
Figure 1.36. Timer block diagram
TA0
IN
TX0
INOUT
TB0
IN
TB1
IN
f
1
f
8
f
32
f
c32
1/32 f
C32
1/8
1/4
f
1
f
8
f
32
X
IN
X
CIN
TX1
INOUT
TX2
INOUT
Noise
filter
Noise
filter
Noise
filter
Noise
filter
Noise
filter
Noise
filter
• Event counter mode
• Event counter mode
• Event counter mode
• Timer mode
• One-shot mode
• PWM mode
• Timer mode
• One-shot mode
• PWM mode
• Pulse width measuring mode
• Timer mode
• One-shot mode
• PWM mode
• Pulse width measuring mode
• Event counter mode
• Event counter mode
• Event counter mode
• Timer mode
• One-shot mode
• PWM mode
• Pulse width measuring mode
• Timer mode
• Pulse width measuring mode
• Timer mode
• Pulse width measuring mode
Timer A0
Timer X0
Timer X1
Timer X2
Timer B0
Timer B1
Timer A0
Timer X0
Timer X1
Timer X2
Timer B0
Timer B1
Clock prescaler reset flag (bit 7
at address 0381
16
) set to “1”
Reset
Clock prescaler
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Timer A
Timer A
Figure 1.37 shows the block diagram of timer A. Figures 1.38 to 1.40 show the timer A-related registers.
Use the timer A0 mode register bits 0 and 1 to choose the desired mode.
Timer A has the four operation modes listed as follows:
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external source or a timer over flow.
• One-shot timer mode: The timer stops counting when the count reaches “000016”.
• Pulse width modulation (PWM) mode: The timer outputs pulses of a given width.
Figure 1.38. Timer A-related registers (1)
Figure 1.37. Block diagram of timer A
Count start flag
Up count/down count
Always down count except
in event counter mode
Reload register (16)
Counter (16)
Low-order
8 bits
AAA
High-order
8 bits
Clock source
selection
• Timer
(gate function)
• Timer
• One shot
• PWM
f
1
f
8
f
32
External
trigger
TA0
IN
TB1 overflow
• Event counter
f
C32
Clock selection
TX0 overflow
Pulse output
Toggle flip-flop
TA0
OUT
Data bus low-order bits
Data bus high-order bits
A
A
Up/down flag
Down count
TX2 overflow
Polarity
selection
Timer A0 mode register
Symbol Address When reset
TA0MR 0396
16
00
16
Bit name FunctionBit symbol
WR
b7 b6 b5 b4 b3 b2 b1 b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot timer mode
1 1 : Pulse width modulation
(PWM) mode
b1 b0
TCK1
MR3
MR2
MR1
TMOD1
MR0
TMOD0
TCK0
Function varies with each operation mode
Count source select bit
(Function varies with each operation mode)
Operation mode select bit
AA
AA
A
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
AA
A
A
AA
A
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Timer A
Figure 1.39. Timer A-related registers (2)
Timer A0 up/down flag
Timer A0 two-phase
pulse signal processing
select bit
Symbol Address When reset
UDF 0384
16
XXX0XXX0
2
TA0P
Up/down flag
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
TA0UD 0 : Down count
1 : Up count
This specification becomes valid
when the up/down flag content is
selected for up/down switching
cause
0 : two-phase pulse signal
processing disabled
1 : two-phase pulse signal
processing enabled
When not using the two-phase
pulse signal processing function,
set the select bit to “0”
Symbol Address When reset
TABSR 0380
16
000X0000
2
Count start flag
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
Clock devided count start flag
Timer B1 count start flag
Timer B0 count start flag
Timer X2 count start flag
Timer X1 count start flag
Timer X0 count start flag
Timer A0 count start flag 0 : Stops counting
1 : Starts counting
CDCS
TB1S
TB0S
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
TX2S
TX1S
TX0S
TA0S
Symbol Address When reset
TA0 0387
16
,0386
16
Indeterminate
b7 b0b7 b0
(b15) (b8)
Timer A0 register (Note)
WR
• Timer mode 0000
16
to FFFF
16
Counts an internal count source
Function
Values that can be set
• Event counter mode 0000
16
to FFFF
16
Counts pulses from an external source or timer overflow
• One-shot timer mode 0000
16
to FFFF
16
Counts a one shot width
• Pulse width modulation mode (16-bit PWM)
Functions as a 16-bit pulse width modulator
• Pulse width modulation mode (8-bit PWM)
Timer low-order address functions as an 8-bit
prescaler and high-order address functions as an 8-bit
pulse width modulator
00
16
to FF
16
(High-order
addresses)
00
16
to FE
16
(Low-
order addresses)
0000
16
to FFFE
16
Note: Read and write data in 16-bit units.
AA
A
AA
AA
A
A
AA
AA
A
A
AA
A
AA
A
AA
A
AA
A
AA
A
A
AA
A
AA
AA
A
A
A
A
A
A
0 : Stops counting
1 : Starts counting
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
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Timer A
Figure 1.40. Timer A-related registers (3)
Symbol Address When reset
CPSRF 038116 0XXXXXXX2
Clock prescaler reset flag
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
AAAAAAAAAAAAAAA
A
AAAAAAAAAAAAA
A
AAAAAAAAAAAAAAA
Clock prescaler reset flag 0 : No effect
1 : Prescaler is reset
(When read, the value is “0”)
CPSR
WR
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
TA0TGL
Symbol Address When reset
TRGSR 038316 0016
Timer A0 event/trigger
select bit 0 0 : Input on TA0IN is selected (Note)
0 1 : TB1 overflow is selected
1 0 : TX2 overflow is selected
1 1 : TX0 overflow is selected
Trigger select register
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
0 0 : Input on TX0INOUT is selected (Note)
0 1 : TB1 overflow is selected
1 0 : TA0 overflow is selected
1 1 : TX1 overflow is selected
0 0 : Input on TX1INOUT is selected (Note)
0 1 : TB1 overflow is selected
1 0 : TX0 overflow is selected
1 1 : TX2 overflow is selected
0 0 : Input on TX2INOUT is selected (Note)
0 1 : TB1 overflow is selected
1 0 : TX1 overflow is selected
1 1 : TA0 overflow is selected
Timer X0 event/trigger
select bit
Timer X1 event/trigger
select bit
Timer X2 event/trigger
select bit
WR
TA0TGH
TX0TGL
TX0TGH
TX1TGL
TX1TGH
TX2TGL
TX2TGH
b1 b0
b3 b2
b5 b4
b7 b6
Note: Set the corresponding port direction register to “0”(input mode).
TX0OS
TX1OS
TA0OS
One-shot start flag Symbol Address When reset
ONSF 038216 XXXX00002
Timer A0 one-shot start flag
Timer X0 one-shot start flag
Timer X1 one-shot start flag
Timer X2 one-shot start flag
TX2OS
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Nothing is assigned.
When write, set "0". When read, its content is indeterminate.
WR
1 : Timer start
When read, the value is “0”
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
52
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Item Specification
Count source f1, f8, f32, fc32
Count operation • Down count
• When the timer underflows, it reloads the reload register contents before
continuing counting
Divide ratio 1/(n+1) n : Set value
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
Interrupt request generation timing
When the timer underflows
TA0IN pin function Programmable I/O port or gate input
TA0OUT pin function Programmable I/O port or pulse output
Read from timer Count value can be read out by reading timer A0 register
Write to timer • When counting stopped
When a value is written to timer A0 register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer A0 register, it is written to only reload register
(Transferred to counter at next reload time)
Select function • Gate function
Counting can be started and stopped by the TA0IN pin’s input signal
• Pulse output function
Each time the timer underflows, the TA0OUT pin’s polarity is reversed
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 1.13.) Figure 1.41 shows
the timer A0 mode register in timer mode.
Table 1.13. Specifications of timer mode
Figure 1.41. Timer A0 mode register in timer mode
Note 1: Set the corresponding port direction register to “1” (output mode).
Note 2: The bit can be “0” or “1”.
Note 3: Set the corresponding port direction register to “0” (input mode).
Timer A0 mode register
Symbol Address When reset
TA0MR 0396
16
00
16
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode
select bit 0 0 : Timer mode
b1 b0
TMOD1
TMOD0
MR0 Pulse output function
select bit 0 : Pulse is not output
(TA0
OUT
pin is a normal port pin)
1 : Pulse is output (Note 1)
(TA0
OUT
pin is a pulse output pin)
Gate function select bit 0 X
(Note 2)
: Gate function not available
(TA0
IN
pin is a normal port pin)
1 0 : Timer counts only when TA0
IN
pin
is held “L” (Note 3)
1 1 : Timer counts only when TA0
IN
pin
is held “H” (Note 3)
b4 b3
MR2
MR1
MR3 0 (Must always be fixed to “0” in timer mode)
0 0 : f
1
0 1 : f
8
1 0 : f
32
1 1 : f
C32
b7 b6
TCK1
TCK0 Count source select bit
000
AA
A
AA
A
AA
A
AA
A
AA
AA
A
A
AA
A
AA
AA
A
A
AA
AA
A
A
53
Under
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Item Specification
Count source
•
External signals input to TA0
IN
pin (effective edge can be selected by software)
• TB1 overflow, TX0 overflow, TX2 overflow
Count operation • Up count or down count can be selected by external signal or software
• When the timer overflows or underflows, it reloads the reload register con
tents before continuing counting (Note)
Divide ratio 1/ (FFFF16 - n + 1) for up count
1/ (n + 1) for down count n : Set value
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
Interrupt request generation timing
The timer overflows or underflows
TA0IN pin function Programmable I/O port or count source input
TA0OUT pin function Programmable I/O port, pulse output, or up/down count select input
Read from timer Count value can be read out by reading timer A0 register
Write to timer • When counting stopped
When a value is written to timer A0 register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer A0 register, it is written to only reload register
(Transferred to counter at next reload time)
Select function • Free-run count function
Even when the timer overflows or underflows, the reload register content is not reloaded to it
• Pulse output function
Each time the timer overflows or underflows, the TA0OUT pin’s polarity isreversed
Note: This does not apply when the free-run function is selected.
(2) Event counter mode
In this mode, the timer counts an external signal or an internal timer’s overflow. Timer A0 can count a
single-phase and a two-phase external signal. Table 1.14 lists timer specifications when counting a
single-phase external signal. Figure 1.42 shows the timer A0 mode register in event counter mode.
Table 1.15 lists timer specifications when counting a two-phase external signal. Figure 1.43 shows the
timer A0 mode register in event counter mode.
Table 1.14.
Timer specifications in event counter mode (when not processing two-phase pulse signal)
Figure 1.42. Timer A0 mode register in event counter mode
Timer A0 mode register
(When not using two-phase pulse signal processing)
Note 1: Set the corresponding port direction register to “1” (output mode).
Note 2: This bit is valid when only counting an external signal.
Note 3: Set the corresponding port direction register to “0” (input mode).
Note 4: When performing two-phase pulse signal processing, make sure the two-phase
pulse signal processing operation select bit (address 038416) is set to “1” and
event/trigger select bits (addresses 038316) to “00”.
Symbol Address When reset
TA0MR 039616 0016
WR
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode select bit 0 1 : Event counter mode
b1 b0
TMOD0
MR0 Pulse output function
select bit 0 : Pulse is not output
(TA0OUT pin is a normal port pin)
1 : Pulse is output (Note 1)
(TA0OUT pin is a pulse output pin)
Count polarity
select bit (Note 2)
MR2
MR1
MR3 0 (Must always be fixed to “0” in event counter mode)
TCK0 Count operation type
select bit
010
0 : Counts external signal's falling edge
1 : Counts external signal's rising edge
Up/down switching
cause select bit 0 : Up/down flag's content
1 : TAiOUT pin's input signal (Note 3)
0 : Reload type
1 : Free-run type
Bit symbol Bit name Function RW
TCK1
TMOD1
A
A
AA
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
Two-phase pulse operation
select bit (Note 4) 0 : Normal processing operation
1 : Multiply-by-4 processing operation
54
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Item Specification
Count source • Two-phase pulse signals input to TA0IN or TA0OUT pin
Count operation • Up count or down count can be selected by two-phase pulse signal
• When the timer overflows or underflows, the reload register content is
reloaded and the timer starts over again (Note)
Divide ratio • 1/ (FFFF16 - n + 1) for up count
• 1/ (n + 1) for down count n : Set value
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
Interrupt request generation timing
Timer overflows or underflows
TA0IN pin function Two-phase pulse input
TA0OUT pin function Two-phase pulse input
Read from timer Count value can be read out by reading timer A0 register
Write to timer • When counting stopped
When a value is written to timer A0 register, it is written to both reload regis-
ter and counter
• When counting in progress
When a value is written to timer A0 register, it is written to only reload regis-
ter. (Transferred to counter at next reload time.)
Select function • Normal processing operation
The timer counts up rising edges or counts down falling edges on the TA0IN
pin when input signal on the TA0OUT pin is “H”
• Multiply-by-4 processing operation
If the phase relationship is such that the TA0IN pin goes “H” when the input
signal on the TA0OUT pin is “H”, the timer counts up rising and falling edges
on the TA0OUT and TA0IN pins. If the phase relationship is such that the
TA0IN pin goes “L” when the input signal on the TA0OUT pin is “H”, the timer
counts down rising and falling edges on the TA0OUT and TA0IN pins.
Note: This does not apply when the free-run function is selected.
Table 1.15. Timer specifications in event counter mode (when processing two-phase pulse signal)
TA0
OUT
Up
count Up
count Up
count Down
count Down
count Down
count
TA0
IN
TA0
OUT
TA0
IN
Count up all edges
Count up all edges
Count down all edges
Count down all edges
55
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Figure 1.43. Timer A0 mode register in event counter mode
Note: When performing two-phase pulse signal processing, make sure the two-phase
pulse signal processing operation select bit (address 0384
16
) is set to “1”. Also,
always be sure to set the event/trigger select bit (addresses 0383
16
) to “00”.
Timer A0 mode register
(When using two-phase pulse signal processing)
Symbol Address When reset
TA0MR 0396
16
00
16
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode select bit 0 1 : Event counter mode
b1 b0
TMOD1
TMOD0
MR0 0 (Must always be “0” when using two-phase pulse signal
processing)
0 (Must always be “0” when using two-phase pulse signal
processing)
MR2
MR1
MR3 0 (Must always be “0” when using two-phase pulse signal
processing)
TCK1
TCK0
010
1 (Must always be “1” when using two-phase pulse signal
processing)
Bit name Function
WR
Count operation type
select bit
Two-phase pulse
processing operation
select bit (Note)
0 : Reload type
1 : Free-run type
0 : Normal processing operation
1 : Multiply-by-4 processing operation
001
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
56
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Item Specification
Count source f1, f8, f32, fC32
Count operation • The timer counts down
• When the count reaches 0000
16
, the timer stops counting after reloading a new count
• If a trigger occurs when counting, the timer reloads a new count and restarts counting
Divide ratio 1/n n : Set value
Count start condition • An external trigger is input
• The timer overflows
• The one-shot start flag is set (= 1)
Count stop condition • A new count is reloaded after the count has reached 000016
• The count start flag is reset (= 0)
Interrupt request generation timing
The count reaches 000016
TA0IN pin function Programmable I/O port or trigger input
TA0OUT pin function Programmable I/O port or pulse output
Read from timer When timer A0 register is read, it indicates an indeterminate value
Write to timer • When counting stopped
When a value is written to timer A0 register, it is written to both reload
register and counter
• When counting in progress
When a value is written to timer A0 register, it is written to only reload register
(Transferred to counter at next reload time)
Table 1.16. Timer specifications in one-shot timer mode
Figure 1.44. Timer A0 mode register in one-shot timer mode
(3) One-shot timer mode
In this mode, the timer operates only once. (See Table 1.16.) When a trigger occurs, the timer starts up
and continues operating for a given period. Figure 1.44 shows the timer A0 mode register in one-shot
timer mode.
Bit name Function
Bit symbol
Operation mode select bit 1 0 : One-shot timer mode
b1 b0
TMOD1
TMOD0
MR0 Pulse output function
select bit 0 : Pulse is not output
(TA0
OUT
pin is a normal port pin)
1 : Pulse is output (Note 1)
(TA0
OUT
pin is a pulse output pin)
MR2
MR1
MR3 0 (Must always be “0” in one-shot timer mode)
0 0 : f
1
0 1 : f
8
1 0 : f
32
1 1 : f
C32
b7 b6
TCK1
TCK0 Count source select bit
100
0 : One-shot start flag is valid
1 : Selected by event/trigger select
register
Trigger select bit
External trigger select
bit (Note 2)
0 : Falling edge of TA0
IN
pin's input signal (Note 3)
1 : Rising edge of TA0
IN
pin's input signal (Note 3)
WR
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Note 1: Set the corresponding port direction register to “1” (output mode).
Note 2:
Valid only when the TA0
IN
pin is selected by the event/trigger select bit
(addresses 0383
16
). If timer overflow is selected, this bit can be “1” or “0”.
Note 3: Set the corresponding port direction register to “0” (input mode).
Timer A0 mode register
Symbol Address When reset
TA0MR 0396
16
00
16
b7 b6 b5 b4 b3 b2 b1 b0
57
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M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
(4) Pulse width modulation (PWM) mode
In this mode, the timer outputs pulses of a given width in succession. (See Table 1.17.) In this mode, the counter
functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Figure 1.45 shows the timer
A0 mode register in pulse width modulation mode. Figure 1.46 shows the example of how a 16-bit pulse width
modulator operates. Figure 1.47 shows the example of how an 8-bit pulse width modulator operates.
Figure 1.45. Timer A0 mode register in pulse width modulation mode
Table 1.17. Timer specifications in pulse width modulation mode
Item Specification
Count source f1, f8, f32, fc32
Count operation •
The timer counts down (operating as an 8-bit or a 16-bit pulse width modulator)
•
The timer reloads a new count at a rising edge of PWM pulse and continues counting
• The timer is not affected by a trigger that occurs when counting
16-bit PWM • High level width n / fi n : Set value
• Cycle time (216-1) / fi fixed
8-bit PWM
•
High level width n (m+1) / fi n : values set to timer A0 register’s high-order address
• Cycle time (28-1) (m+1) / fi m : values set to timer A0 register’s low-order address
Count start condition • External trigger is input
• The timer overflows
• The count start flag is set (= 1)
Count stop condition • The count start flag is reset (= 0)
8 bits PWM • Set value of "H" level width is except FF16, 0016 : PWM pulse goes “L”
• Set value of "H" level width is FF
16
, 00
16
: Timing that count value goes to 01
16
16 bits PWM • Set value of "H" level width is except FFFF16, 000016 : PWM pulse goes “L”
• Set value of "H" level width is FFFF
16
, 0000
16
: Timing that count value goes to 0001
16
TA0IN pin function Programmable I/O port or trigger input
TA0OUT pin function Pulse output
Read from timer When timer A0 register is read, it indicates an indeterminate value
Write to timer • When counting stopped :When a value is written to timer A0 register, it is
written to both reload register and counter
• When counting in progress : When a value is written to timer A0 register, it is
written to only reload register (Transferred to counter at next reload time)
Bit name FunctionBit symbol
Operation mode
select bit 1 1 : PWM mode
b1 b0
TMOD1
TMOD0
MR0
MR2
MR1
MR3
0 0 : f
1
0 1 : f
8
1 0 : f
32
1 1 : f
C32
b7 b6
TCK1
TCK0 Count source select bit
WR
111
1 (Must always be “1” in PWM mode)
16/8-bit PWM mode
select bit
0: Functions as a 16-bit pulse width modulator
1: Functions as an 8-bit pulse width modulator
Trigger select bit
External trigger select
bit (Note 1)
0: Falling edge of TA0
IN
pin's input signal (Note 2)
1: Rising edge of TA0
IN
pin's input signal (Note 2)
0: Count start flag is valid
1: Selected by event/trigger select register
Note 1: Valid only when the TA0
IN
pin is selected by the event/trigger select bit
(addresses 0383
16
). If timer overflow is selected, this bit can be “1” or “0”.
Note 2: Set the corresponding port direction register to “0” (input mode).
Note 3: Set the corresponding port direction register to “1” (output mode) when the pulse is output.
AA
AA
A
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
Timer A0 mode register
Symbol Address When reset
TA0MR 0396
16
00
16
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt
request
generation
timing
Note: When set value of "H" level width is 00
16
or 0000
16
, pulse outputs "L" level and inversion value, FF
16
or FFFF
16
is set to timer.
58
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Figure 1.46. Example of how a 16-bit pulse width modulator operates
Figure 1.47. Example of how an 8-bit pulse width modulator operates
1 / f
i
X
(2 – 1)
16
Count source
TA0
IN
pin
input signal
PWM pulse output
from TA0
OUT
pin
Condition : Reload register = 000316, when external trigger
(rising edge of TA0IN pin input signal) is selected
Trigger is not generated by this signal
“H”
“H”
“L”
“L”
Timer A0 interrupt
request bit
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
f
i
: Frequency of count source
(f
1
, f
8
, f
32
, f
C32
)
Note: n = 0000
16
to FFFF
16
.
1 / f
i X
n
Count source (Note1)
TA0
IN
pin input signal
Underflow signal of
8-bit prescaler (Note2)
PWM pulse output
from TA0
OUT
pin
“H”
“H”
“H”
“L”
“L”
“L”
“1”
“0”
Timer A0 interrupt
request bit
Cleared to “0” when interrupt request is accepted, or cleaerd by software
f
i
: Frequency of count source
(f
1
, f
8
, f
32
, f
C32
)
Note 1: The 8-bit prescaler counts the count source.
Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal.
Note 3: m = 00
16
to FF
16
; n = 00
16
to FF
16
.
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
Condition : Reload register high-order 8 bits = 02
16
Reload register low-order 8 bits = 02
16
External trigger (falling edge of TA0
IN
pin input signal) is selected
1 / f
i
X (m
+ 1) X (2 – 1)
8
1 / f
i
X (m + 1) X n
1 / f
i
X (m + 1)
59
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
Timer B
Figure 1.48 shows the block diagram of timer B. Figures 1.49 and 1.50 show the timer B-related registers.
Use the timer Bi mode register (i = 0, 1) bits 0 and 1 to choose the desired mode.
Timer B has three operation modes listed as follows:
• Timer mode : The timer counts an internal count source.
• Event counter mode : The timer counts pulses from an external source or a timer overflow.
• Pulse period/pulse width measuring mode : The timer measures an external signal's pulse period or
pulse width.
Figure 1.48. Block diagram of timer B
Timer Bi mode register
Symbol Address When reset
TBiMR(i = 0, 1) 039B
16
, 039C
16
00XX0000
2
Bit name FunctionBit symbol
WR
b7 b6 b5 b4 b3 b2 b1 b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : Pulse period/pulse width
measurement mode
1 1 : Inhibited
b1 b0
TCK1
MR3
MR2
MR1
TMOD1
MR0
TMOD0
TCK0
Function varies with each operation mode
Count source select bit
(Function varies with each operation mode)
Operation mode select bit
(Note 1)
(Note 2)
Note 1: Timer B0.
Note 2: Timer B1.
Note 3: Must set “00” to operation mode select bit of M30200.
A
AA
A
A
AA
AA
A
A
AA
AA
A
AA
A
AA
A
AA
A
AA
A
A
Clock source selection
• Event counter
• Timer
• Pulse period/pulse width measurement Reload register (16)
Low-order 8 bits High-order 8 bits
Data bus low-order bits
Data bus high-order bits
f1
f8
f32
TBj overflow
(j = 1 when i = 0,
j = 0 when i = 1)
Can be selected in only
event counter mode
Count start flag
fC32
Polarity switching
and edge pulse
TBiIN
(i = 0, 1)
Counter reset circuit
Counter (16)
Figure 1.49. Timer B-related registers (1)
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M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
Symbol Address When reset
CPSRF 038116 0XXXXXXX2
Clock prescaler reset flag
Bit name Function
Bit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
AAAAAAAAAAAAAAA
A
AAAAAAAAAAAAA
A
AAAAAAAAAAAAAAA
Clock prescaler reset flag 0 : No effect
1 : Prescaler is reset
(When read, the value is “0”)
CPSR
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
A
A
Symbol Address When reset
TB0 039116, 039016 Indeterminate
TB1 039316, 039216 Indeterminate
b7 b0b7 b0
(b15) (b8)
Timer Bi register (Note)
WR
• Pulse period / pulse width measurement mode
Measures a pulse period or width
• Timer mode 000016 to FFFF16
Counts the timer's period
Function Values that can be set
• Event counter mode 000016 to FFFF16
Counts external pulses input or a timer overflow
Note1: Read and write data in 16-bit units.
A
A
A
A
A
A
Symbol Address When reset
TABSR 038016 000X00002
Count start flag
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
Clock devided count start flag
Timer B1 count start flag
Timer B0 count start flag
Timer X2 count start flag
Timer X1 count start flag
Timer X0 count start flag
Timer A0 count start flag 0 : Stops counting
1 : Starts counting
CDCS
TB1S
TB0S
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
TX2S
TX1S
TX0S
TA0S
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
0 : Stops counting
1 : Starts counting
Figure 1.50. Timer B-related registers (2)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
Item Specification
Count source f1, f8, f32, fC32
Count operation • Counts down
• When the timer underflows, it reloads the reload register contents before
continuing counting
Divide ratio 1/(n+1) n : Set value
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
Interrupt request generation timing
The timer underflows
TBiIN pin function Programmable I/O port
Read from timer Count value is read out by reading timer Bi register
Write to timer • When counting stopped
When a value is written to timer Bi register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Bi register, it is written to only reload register
(Transferred to counter at next reload time)
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 1.18.) Figure 1.51 shows
the timer Bi mode register in timer mode.
Table 1.18. Timer specifications in timer mode
Timer Bi mode register Symbol Address When reset
TBiMR(i=0, 1) 039B
16
to 039C
16
00XX0000
2
Bit name Function
Bit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
AA
AA
A
A
Operation mode select bit 0 0 : Timer mode
b1 b0
TMOD1
TMOD0
MR0 Invalid in timer mode
Can be “0” or “1”
MR1
MR3
0 0 : f
1
0 1 : f
8
1 0 : f
32
1 1 : f
C32
TCK1
TCK0 Count source select bit
0
Invalid in timer mode.
This bit can neither be set nor reset. When read in timer mode,
its content is indeterminate.
0
b7 b6
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
Figure 1.51. Timer Bi mode register in timer mode
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Timer B
Item Specification
Count source • External signals input to TBiIN pin
• Effective edge of count source can be a rising edge, a falling edge, or falling
and rising edges as selected by software
Count operation • Counts down
• When the timer underflows, it reloads the reload register contents before
continuing counting
Divide ratio 1/(n+1) n : Set value
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
Interrupt request generation timing
The timer underflows
TBiIN pin function Count source input
Read from timer Count value can be read out by reading timer Bi register
Write to timer • When counting stopped
When a value is written to timer Bi register, it is written to both reload register
and counter
• When counting in progress
When a value is written to timer Bi register, it is written to only reload register
(Transferred to counter at next reload time)
(2) Event counter mode
In this mode, the timer counts an external signal or an internal timer's overflow. (See Table 1.19.) Figure
1.52 shows the timer Bi mode register in event counter mode.
Table 1.19. Timer specifications in event counter mode
Figure 1.52. Timer Bi mode register in event counter mode
Timer Bi mode register
Symbol Address When reset
TBiMR(i=0, 1) 039B
16
to 039C
16
00XX0000
2
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
AA
Operation mode select bit 0 1 : Event counter mode
b1 b0
TMOD1
TMOD0
MR0 Count polarity select
bit (Note 1)
MR1
MR3 Invalid in event counter mode.
This bit can neither be set nor reset. When read in event
counter mode, its content is indeterminate.
TCK1
TCK0
01
0 0 : Counts external signal's
falling edges
0 1 : Counts external signal's
rising edges
1 0 : Counts external signal's
falling and rising edges
1 1 : Inhibited
b3 b2
Note 1: Valid only when input from the TBi
IN
pin is selected as the event clock.
If timer's overflow is selected, this bit can be “0” or “1”.
Note 2: Set the corresponding port direction register to “0” (input mode).
Invalid in event counter mode.
Can be “0” or “1”.
Event clock select 0 : Input from TBi
IN
pin (Note 2)
1 : TBj overflow
( j = 1 when i = 0,
j = 0 when i = 1)
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
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Timer B
Item Specification
Count source f1, f8, f32, fc32
Count operation • Up count
• Counter value “000016” is transferred to reload register at measurement
pulse's effective edge and the timer continues counting
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
Interrupt request generation timing
• When measurement pulse's effective edge is input (Note 1)
• When an overflow occurs. (Simultaneously, the timer Bi overflow flag
changes to “1”. The timer Bi overflow flag changes to “0” when the count
start flag is “1” and a value is written to the timer Bi mode register.)
TBiIN pin function Measurement pulse input
Read from timer When timer Bi register is read, it indicates the reload register’s content
(measurement result) (Note 2)
Write to timer Cannot be written to
(3) Pulse period/pulse width measurement mode
In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table 1.20.)
Figure 1.53 shows the timer Bi mode register in pulse period/pulse width measurement mode. Figure
1.54 shows the operation timing when measuring a pulse period. Figure 1.55 shows the operation timing
when measuring a pulse width.
Table 1.20. Timer specifications in pulse period/pulse width measurement mode
Figure 1.53. Timer Bi mode register in pulse period/pulse width measurement mode
Note 1:
An interrupt request is not generated when the first effective edge is input after the timer has started counting.
Note 2:
The value read out from the timer Bi register is indeterminate until the second effective edge is input after the timer.
Timer Bi mode register Symbol Address When reset
TBiMR(i=0 , 1) 039B
16
, 039C
16
00XX0000
2
Bit nameBit symbol
WR
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode
select bit 1 0 : Pulse period / pulse width
measurement mode
b1 b0
TMOD1
TMOD0
MR0 Measurement mode
select bit
MR1
MR3
TCK1
TCK0
01
0 0 : Pulse period measurement (Interval between
measurement pulse's falling edge to falling edge)
0 1 : Pulse period measurement (Interval between
measurement pulse's rising edge to rising edge)
1 0 : Pulse width measurement (Interval between
measurement pulse's falling edge to rising edge,
and between rising edge to falling edge)
1 1 : Inhibited
Function
b3 b2
Count source
select bit
Timer Bi overflow
flag ( Note) 0 : Timer did not overflow
1 : Timer has overflowed
0 0 : f
1
0 1 : f
8
1 0 : f
32
1 1 : f
C32
b7 b6
Note : The timer Bi overflow flag changes to “0” when the count start flag is “1” and a value is written to the
timer Bi mode register. This flag cannot be set to “1” by software.
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
Count source
Measurement pulse
Count start flag
Timer Bi interrupt
request bit
Timing at which counter
reaches “0000
16
”
“H”
“1”
Transfer
(indeterminate value)
“L”
“0”
“0”
Timer Bi overflow flag
“1”
“0”
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
(Note 1)(Note 1)
When measuring measurement pulse time interval from falling edge to falling edge
(Note 2)
Cleared to “0” when interrupt request is accepted, or cleared by software.
Transfer
(measured value)
“1”
Reload register counter
transfer timing
Figure 1.55. Operation timing when measuring a pulse width
Measurement pulse “H”
Count source
Count start flag
Timer Bi interrupt
request bit
Timing at which counter
reaches “000016”
“1”
“1”
Transfer
(measured value) Transfer
(measured value)
“L”
“0”
“0”
Timer Bi overflow flag “1”
“0”
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
(Note 1)(Note 1)(Note 1)
Transfer
(measured
value)
(Note 1)
Cleared to “0” when interrupt request is accepted, or cleared by software.
(Note 2)
Transfer
(indeterminate
value)
Reload register counter
transfer timing
Figure 1.54. Operation timing when measuring a pulse period
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X
Timer X
Figure 1.56 shows the block diagram of timer X. Figures 1.57 to 1.59 show the timer X-related registers.
Use the timer Xi mode register bits 0 and 1 to choose the desired mode.
Timer X has the five operation modes listed as follows:
• Timer mode : The timer counts an internal count source.
• Event counter mode : The timer counts pulses from an external source or a timer overflow.
• One-shot timer mode : The timer stops counting when the count reaches “000016”.
• Pulse period/pulse width measuring mode : The timer measures an external signal's pulse period or
pulse width.
• Pulse width modulation (PWM) mode : The timer outputs pulses of a given width.
Figure 1.57. Timer X-related registers (1)
Figure 1.56. Block diagram of timer X
Count start flag
Reload register (16)
Counter (16)
Low-order
8 bits
AAA
AAA
High-order
8 bits
Clock source
selection
• Timer
(gate function)
• Timer
• One shot
• PWM
• Pulse period/pulse width measurement
f
1
f
8
f
32
External
trigger
TXi
INOUT
(i=0 to 2)
TB1 overflow
• Event counter
f
C32
Clock selection
Pulse output
Toggle flip-flop
Data bus low-order bits
Data bus high-order bits
A
A
Polarity
switching and
edge pulse
Counter reset circuit
*1 = TA0, *2 = TX1 when TX0
*1 = TX0, *2 = TX2 when TX1
*1 = TX1, *2 = TA0 when TX2
*1
*2
Timer Xi mode register
Symbol Address When reset
TXiMR(i = 0 to 2) 039716 to 039916 0016
Bit name FunctionBit symbol
WR
b7 b6 b5 b4 b3 b2 b1 b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot timer mode or pulse period/
pulse width measurement mode
1 1 : Pulse width modulation (PWM) mode
b1 b0
TCK1
MR3
MR2
MR1
TMOD1
MR0
TMOD0
TCK0
Function varies with each operation mode
Count source select bit
(Function varies with each operation mode)
Operation mode
select bit
AA
A
AA
A
AA
A
AA
AA
A
A
AA
A
AA
AA
A
A
AA
A
AA
A
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Timer X
Figure 1.58. Timer X-related registers (2)
Symbol Address When reset
TABSR 038016 000X00002
Count start flag
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
Clock devided count start flag
Timer B1 count start flag
Timer B0 count start flag
Timer X2 count start flag
Timer X1 count start flag
Timer X0 count start flag
Timer A0 count start flag 0 : Stops counting
1 : Starts counting
CDCS
TB1S
TB0S
Nothing is assigned.
When write, set "0" When read, their contents are indeterminate.
TX2S
TX1S
TX0S
TA0S
Symbol Address When reset
TX0 038916,038816 Indeterminate
TX1 038B16,038A16 Indeterminate
TX2 038D16,038C16 Indeterminate
b7 b0b7 b0
(b15) (b8)
Timer Xi register (Note)
WR
• Timer mode 000016 to FFFF16
Counts an internal count source
Function Values that can be set
• Event counter mode 000016 to FFFF16
Counts pulses from an external source or timer overflow
• One-shot timer mode 000016 to FFFF16
Counts a one shot width
• Pulse width modulation mode (16-bit PWM)
Functions as a 16-bit pulse width modulator
• Pulse width modulation mode (8-bit PWM)
Timer low-order address functions as an 8-bit
prescaler and high-order address functions as an 8-bit
pulse width modulator
0016 to FF16
(High-order
addresses)
0016 to FF16 (Low-
order addresses)
000016 to FFFE16
Note: Read and write data in 16-bit units.
A
AA
A
AA
A
AA
A
A
AA
AA
A
AA
A
A
AA
AA
A
AA
A
A
AA
AA
A
AA
AA
AA
AA
0 : Stops counting
1 : Starts counting
• Pulse period / pulse width measurement mode
Measures a pulse period or width
A
A
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X
Figure 1.59. Timer X-related registers (3)
Symbol Address When reset
CPSRF 0381
16
0XXXXXXX
2
Clock prescaler reset flag
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
AAAAAAAAAAAAAAAA
A
AAAAAAAAAAAAAA
A
AAAAAAAAAAAAAAAA
Clock prescaler reset flag 0 : No effect
1 : Prescaler is reset
(When read, the value is “0”)
CPSR
WR
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
TA0TGL
Symbol Address When reset
TRGSR 0383
16
00
16
Timer A0 event/trigger
select bit 0 0 :
Input on TA0
IN
is selected (Note)
0 1 : TB1 overflow is selected
1 0 : TX2 overflow is selected
1 1 : TX0 overflow is selected
Trigger select register
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
0 0 :
Input on TX0
INOUT
is selected (Note)
0 1 : TB1 overflow is selected
1 0 : TA0 overflow is selected
1 1 : TX1 overflow is selected
0 0 :
Input on TX1
INOUT
is selected (Note)
0 1 : TB1 overflow is selected
1 0 : TX0 overflow is selected
1 1 : TX2 overflow is selected
0 0 :
Input on TX2
INOUT
is selected (Note)
0 1 : TB1 overflow is selected
1 0 : TX1 overflow is selected
1 1 : TA0 overflow is selected
Timer X0 event/trigger
select bit
Timer X1 event/trigger
select bit
Timer X2 event/trigger
select bit
WR
TA0TGH
TX0TGL
TX0TGH
TX1TGL
TX1TGH
TX2TGL
TX2TGH
b1 b0
b3 b2
b5 b4
b7 b6
Note: Set the corresponding port direction register to “0”(input mode).
TX0OS
TX1OS
TA0OS
One-shot start flag
Symbol Address When reset
ONSF 0382
16
XXXX0000
2
Timer A0 one-shot start flag
Timer X0 one-shot start flag
Timer X1 one-shot start flag
Timer X2 one-shot start flag
TX2OS
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Nothing is assigned.
When write, set "0". When read, its content is indeterminate.
WR
1 : Timer start
When read, the value is “0”
A
A
AA
AA
A
AA
A
AA
A
AA
A
A
AA
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
A
AA
AA
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Timer X
Item Specification
Count source f1, f8, f32, fC32
Count operation • Down count
•
When the timer underflows, it reloads the reload register contents before continuing counting
Divide ratio 1/(n+1) n : Set value
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
Interrupt request generation timing
When the timer underflows
TXiINOUT pin function Programmable I/O port, gate input or pulse output
Read from timer Count value can be read out by reading timer Xi register
Write to timer • When counting stopped
When a value is written to timer Xi register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Xi register, it is written to only reload register
(Transferred to counter at next reload time)
Select function • Gate function
Counting can be started and stopped by the TXiINOUT pin’s input signal
• Pulse output function
Each time the timer underflows, the TXiINOUT pin’s polarity is reversed
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 1.21.) Figure 1.60 shows
the timer Xi mode register in timer mode.
Table 1.21. Specifications of timer mode
Figure 1.60. Timer Xi mode register in timer mode
Note 1: Set the corresponding port direction register to “1” (output mode). Gate function
cannot be selected when pulse output function is selected.
Note 2: The bit can be “0” or “1”.
Note 3: Set the corresponding port direction register to “0” (input mode). Pulse output
function cannot be selected when gate function is selected.
Timer Xi mode register
Symbol Address When reset
TXiMR(i = 0 to 2) 0397
16
to 0399
16
00
16
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode
select bit 0 0 : Timer mode
b1 b0
TMOD1
TMOD0
MR0 Pulse output function
select bit 0 : Pulse is not output
(TXi
INOUT
pin is a normal port pin)
1 : Pulse is output (Note 1)
(TXi
INOUT
pin is a pulse output pin)
Gate function select bit 0 X
(Note 2)
: Gate function not available
(TXi
INOUT
pin is a normal port pin)
1 0 : Timer counts only when TXi
INOUT
pin is held “L” (Note 3)
1 1 : Timer counts only when TXi
INOUT
pin is held “H” (Note 3)
b4 b3
MR2
MR1
MR3 0 (Must always be fixed to “0” in timer mode)
0 0 : f
1
0 1 : f
8
1 0 : f
32
1 1 : f
C32
b7 b6
TCK1
TCK0 Count source select bit
000
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
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Timer X
Item Specification
Count source
•
External signals input to TXi
INOUT
pin (effective edge can be selected by software)
• TB1 overflow, TA0 overflow, TXi overflow
Count operation • Down count
• When the timer underflows, it reloads the reload register contents before
continuing counting (Note)
Divide ratio 1/ (n + 1) n : Set value
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
Interrupt request generation timing
The timer underflows
TXiINOUT pin function Programmable I/O port, count source input or pulse output
Read from timer Count value can be read out by reading timer Xi register
Write to timer • When counting stopped
When a value is written to timer Xi register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Xi register, it is written to only reload register
(Transferred to counter at next reload time)
Select function • Free-run count function
Even when the timer underflows, the reload register content is not reloaded to it
• Pulse output function
Each time the timer underflows, the TXiINOUT pin’s polarity is reversed
Note: This does not apply when the free-run function is selected.
(2) Event counter mode
In this mode, the timer counts an external signal or an internal timer’s overflow. (See Table 1.22.) Figure
1.61 shows the timer Xi mode register in event counter mode.
Table 1.22.
Timer specifications in event counter mode (when not processing two-phase pulse signal)
Figure 1.61. Timer Xi mode register in event counter mode
Timer Xi mode register
Note 1: Count source is selected by event/trigger select bit(address 0383
16
) in event counter mode.
Note 2: Set the corresponding port direction register to “1” (output mode). TXi
INOUT
pin input is not
selected as count source when pulse output function is selected.
Note 3: This bit is valid when only counting an external signal.
Symbol Address When reset
TXiMR(i = 0 to 2) 0397
16
to 0399
16
00
16
WR
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode select bit 0 1 : Event counter mode
(Note 1)
b1 b0
TMOD0
MR0 Pulse output function
select bit 0 : Pulse is not output
(TXi
INOUT
pin is a normal port pin)
1 : Pulse is output (Note 2)
(TXi
INOUT
pin is a pulse output pin)
Count polarity
select bit (Note 3)
MR2
MR1
MR3 0 (Must always be fixed to “0” in event counter mode)
TCK0 Count operation type
select bit
010
0 : Counts external signal's falling edge
1 : Counts external signal's rising edge
0 : Reload type
1 : Free-run type
Bit symbol Bit name Function RW
TCK1
TMOD1
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
Invalid in event counter mode.
Can be “0” or “1”.
Invalid in event counter mode.
Can be “0” or “1”.
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Timer X
Item Specification
Count source f1, f8, f32, fC32
Count operation • The timer counts down
• When the count reaches 000016, the timer stops counting after reloading a new count
• If a trigger occurs when counting, the timer reloads a new count and restarts counting
Divide ratio 1/n n : Set value
Count start condition • An external trigger is input
• The timer overflows
• The one-shot start flag is set (= 1)
Count stop condition • A new count is reloaded after the count has reached 000016
• The count start flag is reset (= 0)
Interrupt request generation timing
The count reaches 000016
TXiINOUT pin function Programmable I/O port, trigger input or pulse output
Read from timer When timer Xi register is read, it indicates an indeterminate value
Write to timer • When counting stopped
When a value is written to timer Xi register, it is written to both reload
register and counter
• When counting in progress
When a value is written to timer Xi register, it is written to only reload register
(Transferred to counter at next reload time)
Table 1.23. Timer specifications in one-shot timer mode
Figure 1.62. Timer Xi mode register in one-shot timer mode
(3) One-shot timer mode
In this mode, the timer operates only once. (See Table 1.23.) When a trigger occurs, the timer starts up and
continues operating for a given period. Figure 1.62 shows the timer Xi mode register in one-shot timer mode.
Bit name Function
Bit symbol
Operation mode
select bit 1 0 : One-shot timer mode or pulse period /
pulse width measurement mode
b1 b0
TMOD1
TMOD0
MR0 Pulse output function
select bit 0 : Pulse is not output
(TXi
INOOUT
pin is a normal port pin)
1 : Pulse is output (Note 1)
(TXi
INOOUT
pin is a pulse output pin)
MR2
MR1
MR3 0 (Must always be “0” in one-shot timer mode)
0 0 : f
1
0 1 : f
8
1 0 : f
32
1 1 : f
C32
b7 b6
TCK1
TCK0 Count source select bit
100
0 : One-shot start flag is valid
1 : Selected by event/trigger select register (Note 4)
Trigger select bit
External trigger select
bit (Note 2)
0 : Falling edge of TXi
INOOUT
pin's input signal (Note 3)
1 : Rising edge of TXi
INOOUT
pin's input signal (Note 3)
WR
A
AA
A
A
AA
AA
A
AA
A
A
AA
AA
A
AA
A
AA
A
AA
A
AA
Note 1: Set the corresponding port direction register to “1” (output mode). External trigger cannot be selected
as count start condition when pulse output function is selected.
Note 2: Valid only when the TXi
INOUT
pin is selected by the event/trigger select bit (addresses 0383
16
). If
timer overflow is selected, this bit can be “1” or “0”.
Note 3: Set the corresponding port direction register to “0” (input mode).
Note 4: Pulse output function cannot be selected when TXi
INOUT
pin is selected by the event/trigger select bit
(addresses 0383
16
).
Timer Xi mode register
Symbol Address When reset
TXiMR(i = 0 to 2) 0397
16
to 0399
16
00
16
b7 b6 b5 b4 b3 b2 b1 b0
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Timer X
Item Specification
Count source f1, f8, f32, fc32
Count operation • Up count
• Counter value “000016” is transferred to reload register at measurement
pulse's effective edge and the timer continues counting
Count start condition Count start flag is set (= 1)
Count stop condition Count start flag is reset (= 0)
Interrupt request generation timing
• When measurement pulse's effective edge is input (Note 1)
• When an overflow occurs. (Simultaneously, the timer Xi overflow flag
changes to “1”. The timer Xi overflow flag changes to “0” when the count
start flag is “1” and a value is written to the timer Xi mode register.)
TXiINOUT pin function Measurement pulse input
Read from timer When timer Xi register is read, it indicates the reload register’s content
(measurement result) (Note 2)
Write to timer Cannot be written to
(4) Pulse period/pulse width measurement mode
In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table 1.24.)
Figure 1.63 shows the timer Xi mode register in pulse period/pulse width measurement mode. Figure
1.64 shows the operation timing when measuring a pulse period. Figure 1.65 shows the operation timing
when measuring a pulse width.
Table 1.24. Timer specifications in pulse period/pulse width measurement mode
Figure 1.63. Timer Xi mode register in pulse period/pulse width measurement mode
Note 1:
An interrupt request is not generated when the first effective edge is input after the timer has started counting.
Note 2:
The value read out from the timer Xi register is indeterminate until the second effective edge is input after the timer.
Bit nameBit symbol
WR
b7 b6 b5 b4 b3 b2 b1 b0
Operation mode
select bit
b1 b0
TMOD1
TMOD0
MR0 Measurement mode
select bit
MR1
MR3
TCK1
TCK0
01
0 0 : Pulse period measurement (Interval between
measurement pulse's falling edge to falling edge)
0 1 : Pulse period measurement (Interval between
measurement pulse's rising edge to rising edge)
1 0 : Pulse width measurement (Interval between
measurement pulse's falling edge to rising edge,
and between rising edge to falling edge)
1 1 : Inhibited
Function
b3 b2
Count source
select bit
Timer Xi overflow
flag (Note) 0 : Timer did not overflow
1 : Timer has overflowed
0 0 : f
1
0 1 : f
8
1 0 : f
32
1 1 : f
C32
b7 b6
Note: The timer Xi overflow flag changes to “0” when the count start flag is “1” and a value is written to
the timer Xi mode register. This flag cannot be set to “1” by software.
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
Timer Xi mode register
Symbol Address When reset
TXiMR(i = 0 to 2) 0397
16
to 0399
16
00
2
1 0 : One-shot timer mode or pulse period /
pulse width measurement mode
MR
2
1 (Must always be “1” in pulse period / pulse width measurement mode)
AA
A
1
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M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X
Figure 1.65. Operation timing when measuring a pulse width
Figure 1.64. Operation timing when measuring a pulse period
Count source
Measurement pulse
Count start flag
Timer Xi interrupt
request bit
Timing at which counter
reaches “0000
16
”
“H”
“1”
Transfer
(indeterminate value)
“L”
“0”
“0”
Timer Xi overflow flag
“1”
“0”
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
(Note 1)(Note 1)
When measuring measurement pulse time interval from falling edge to falling edge
(Note 2)
Cleared to “0” when interrupt request is accepted, or cleared by software.
Transfer
(measured value)
“1”
Reload register counter
transfer timing
Measurement pulse
“H”
Count source
Count start flag
Timer Xi interrupt
request bit
Timing at which counter
reaches “0000
16
”
“1”
“1”
Transfer
(measured value) Transfer
(measured value)
“L”
“0”
“0”
Timer Xi overflow flag
“1”
“0”
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
(Note 1)(Note 1)(Note 1)
Transfer
(measured
value)
(Note 1)
Cleared to “0” when interrupt request is accepted, or cleared by software.
(Note 2)
Transfer
(indeterminate
value)
Reload register counter
transfer timing
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Timer X
Item Specification
f1, f8, f32, fC32
• Down counts (operating as an 8-bit or a 16-bit pulse width modulator)
•
The timer reloads a new count at a rising edge of PWM pulse and continues counting
• The timer is not affected by a trigger that occurs when counting
• "H" level width n / fi n : Set value
• Cycle time (216-1) / fi fixed
•
"H" level width n (m+1)/ fi n:values set to timer Xi register’s high-order address
•
Cycle time (2
8
-1) (m+1) / fi m : values set to timer Xi register’s low-order address
• The timer overflows
• The count start flag is set (= 1)
• The count start flag is reset (= 0)
• Set value of "H" level width is except FF16, 0016 : PWM pulse goes “L”
• Set value of "H" level width is FF
16
, 00
16
: Timing that count value goes to 01
16
• Set value of "H" level width is except FFFF16, 000016 : PWM pulse goes “L”
• Set value of "H" level width is FFFF
16
, 0000
16
: Timing that count value goes to 0001
16
Pulse output
When timer Xi register is read, it indicates an indeterminate value
• When counting stopped
When a value is written to timer Xi register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Xi register, it is written to only reload register
(Transferred to counter at next reload time)
(5) Pulse width modulation (PWM) mode
In this mode, the timer outputs pulses of a given width in succession. (See Table 1.25.) In this mode, the counter
functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Figure 1.66 shows the timer
Xi mode register in pulse width modulation mode. Figure 1.67 shows the example of how a 16-bit pulse width
modulator operates. Figure 1.68 shows the example of how an 8-bit pulse width modulator operates.
Figure 1.66. Timer Xi mode register in pulse width modulation mode
Table 1.25. Timer specifications in pulse width modulation mode
Bit name FunctionBit symbol
Operation mode
select bit 1 1 : PWM mode
b1 b0
TMOD1
TMOD0
MR0
MR2
MR1
MR3
0 0 : f
1
0 1 : f
8
1 0 : f
32
1 1 : f
C32
b7 b6
TCK1
TCK0 Count source select bit
WR
111
1 (Must always be “1” in PWM mode)
16/8-bit PWM mode
select bit
0: Functions as a 16-bit pulse width modulator
1: Functions as an 8-bit pulse width modulator
Trigger select bit 0: Count start flag is valid
1: Selected by event/trigger select register
Note 1: TXi
INOUT
pin inout cannot be selected by the event/trigger select bit(addresses 0383
16
).
Note 2: Set the corresponding port direction register to “1” (output mode).
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Timer Xi mode register
Symbol Address When reset
TXiMR(i = 0 to 2) 0397
16
to 0399
16
00
16
b7 b6 b5 b4 b3 b2 b1 b0
Invalid in PWM mode. Can be “0” or “1”.
(Note 1)
Count source
Count operation
16-bit PWM
8-bit PWM
Count start condition
Count stop condition
8 bits PWM
16 bits PWM
TXiINOUT pin function
Read from timer
Write to timer
Interrupt
request
generation
timing
Note: When set value of "H" level width is 00
16
or 0000
16
, pulse outputs "L" level and inversion value, FF
16
or FFFF
16
is set to timer.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X
Figure 1.67. Example of how a 16-bit pulse width modulator operates
Figure 1.68. Example of how an 8-bit pulse width modulator operates
1 / fi X (2 – 1)
16
Count source
Trigger signal
PWM pulse output
from TXiINOUT pin
Condition : Reload register = 000316, when trigger (timer overflow) is selected
Trigger is not generated by this signal
“H”
“H”
“L”
“L”
Timer Xi interrupt
request bit “1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
fi : Frequency of count source
(f1, f8, f32, fC32)
Note1: n = 000016 to FFFF16.
1 / fi X n
Count source (Note1)
Trigger signal
Underflow signal of
8-bit prescaler (Note2)
PWM pulse output
from TXi
INOUT
pin
“H”
“H”
“H”
“L”
“L”
“L”
“1”
“0”
Timer Xi interrupt
request bit
Cleared to “0” when interrupt request is accepted, or cleaerd by software
f
i
: Frequency of count source
(f
1
, f
8
, f
32
, f
C32
)
Note 1: The 8-bit prescaler counts the count source.
Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal.
Note 3: m = 00
16
to FF
16
; n = 00
16
to FF
16
.
AAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAA
Condition : Reload register high-order 8 bits = 02
16
Reload register low-order 8 bits = 02
16
Trigger (timer overflow) is selected 1 / fi X (m + 1) X (2 – 1)
8
1 / fi X (m + 1) X n
1 / fi X (m + 1)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
Figure 1.69. Block diagram of UARTi (i = 0, 1)
Serial I/O
Serial I/O is configured as two channels: UART0 and UART1.
UART0 and UART1 each have an exclusive timer to generate a transfer clock, so they operate indepen-
dently of each other.
Figure 1.69 shows the block diagram of UART0 and UART1. Figure 1.70 shows the block diagram of the
transmit/receive unit.
UART0 has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous serial I/
O mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses 03A016 and
03A816) determine whether UART0 is used as a clock synchronous serial I/O or as a UART.
UART1 is used as a UART only.
Figures 1.71 through 1.73 show the registers related to UARTi.
RxD
0
1 / (m+1)
1/2
Bit rate generator
Clock synchronous type
(when internal clock is selected)
UART reception
Clock synchronous type
UART transmission
Clock synchronous type
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is
selected)
Receive
clock
Transmit
clock
CLK
0
Clock source selection
f
1
f
8
f
32
Reception
control circuit
Transmission
control circuit
Internal
External
TxD
0
Transmit/
receive
unit
RxD
1
1 / (n+1)
Bit rate generator
Receive
clock
Transmit
clock
Clock source selection
f
1
f
8
f
32
Reception
control circuit
Transmission
control circuit
TxD
1
(UART1)
(UART0)
CLK
polarity
reversing
circuit
Transmit/
receive
unit
1/16
1/16
f
C
1/16
1/16
m : Values set to UART0 bit rate generator (BRG0)
n : Values set to UART1 bit rate generator (BRG1)
Clock output pin
select switch
CLKS
f
C
76
Serial I/O
Figure 1.70. Block diagram of transmit/receive unit
SP SP
PAR
2SP
1SP
UART
UART (7 bits)
UART (8 bits) UART (7 bits)
UART (9 bits)
Clock
synchronous
type
Clock
synchronous
type
TxDi
UARTi transmit register
PAR
enabled
PAR
disabled
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
SP: Stop bit
PAR: Parity bit
UARTi transmit
buffer register
MSB/LSB conversion circuit
UART (8 bits)
UART (9 bits)
Clock
synchronous
type
UARTi receive
buffer register
UARTi receive register
2SP
1SP
PAR
enabled
PAR
disabled
UART
UART (7 bits)
UART (9 bits)
Clock
synchronous
type
Clock
synchronous
type
UART (7 bits)
UART (8 bits)
RxDi
Clock
synchronous type
UART (8 bits)
UART (9 bits)
Data bus low-order bits
MSB/LSB conversion circuit
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
8
0000000
SP SP
PAR
“0”
Data bus high-order bits
Note: UART1 cannot be used in clock synchronous serial I/O.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
Figure 1.71. Serial I/O-related registers (1)
b7
UARTi bit rate generator
b0 Symbol Address When reset
U0BRG 03A116 Indeterminate
U1BRG 03A916 Indeterminate
Function
Assuming that set value = n, BRGi divides the
count source by n + 1 0016 to FF16
Values that can be set WR
A
b7 b0
(b15) (b8) b7 b0
UARTi transmit buffer register
Function
Transmit data
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
Symbol Address When reset
U0TB 03A316, 03A216 Indeterminate
U1TB 03AB16, 03AA16 Indeterminate
WR
A
(b15) Symbol Address When reset
U0RB 03A716, 03A616 Indeterminate
U1RB 03AF16, 03AE16 Indeterminate
b7 b0
(b8) b7 b0
UARTi receive buffer register
Function
(During UART mode)
Function (During clock
synchronous serial I/O
mode)
Bit name
Bit
symbol
0 : No framing error
1 : Framing error found
0 : No parity error
1 : Parity error found
0 : No error
1 : Error found
Note: Bits 15 through 12 are set to “0” when the receive enable bit is set to “0”. (Bit 15 is set
to “0” when bits 14 to 12 all are set to “0”.) Bits 14 and 13 are also set to “0” when the
lower byte of the UARTi receive buffer register (addresses 03A616, and 03AE16) is
read out.
Invalid
Invalid
Invalid
OER
FER
PER
SUM
Overrun error flag
(Note)
Framing error flag
(Note)
Parity error flag
(Note)
Error sum flag
(Note)
0 : No overrun error
1 : Overrun error found
0 : No overrun error
1 : Overrun error found
Nothing is assigned.
When write, set "0". When read, the value of these bits is “0”.
Receive data
WR
Receive data
A
A
A
A
A
A
A
78
Serial I/O
Figure 1.72. Serial I/O-related registers (2)
UARTi transmit/receive mode register
Symbol Address When reset
UiMR(i=0,1) 03A0
16
, 03A8
16
00
16
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Bit
symbol WR
Must be fixed to 001
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
b2 b1 b0
CKDIR
SMD1
SMD0 Serial I/O mode select bit
(Note 1)
SMD2
Internal/external clock
select bit (Note 2)
STPS
PRY
PRYE
SLEP
Parity enable bit
0 : Internal clock
1 : External clock
Stop bit length select bit
Odd/even parity select bit
Sleep select bit
0 : One stop bit
1 : Two stop bits
0 : Parity disabled
1 : Parity enabled
0 : Sleep mode deselected
1 : Sleep mode selected
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
b2 b1 b0
0 : Internal clock
1 : External clock
Invalid
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
Invalid
Invalid
Must always be “0”
Function
(During UART mode)
Function
(During clock synchronous
serial I/O mode)
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
UARTi transmit/receive control register 0
Symbol Address When reset
UiC0(i=0,1) 03A4
16
, 03AC
16
08
16
b7 b6 b5 b4 b3 b2 b1 b0
Function
(During UART mode) WR
Function (Note)
(During clock synchronous
serial I/O mode)
TXEPT
CLK1
CLK0
NCH
CKPOL
BRG count source
select bit
Transmit register empty
flag
0 : Transmit data is output at
falling edge of transfer clock
and receive data is input at
rising edge
1 : Transmit data is output at
rising edge of transfer clock
and receive data is input at
falling edge
CLK polarity select bit
Data output select bit
0 0 : f
1
is selected
0 1 : f
8
is selected
1 0 : f
32
is selected
1 1 : fc is selected
b1 b0
0 : LSB first
1 : MSB first
0 : Data present in transmit
register (during transmission)
1 : No data present in transmit
register (transmission
completed)
0 : TXDi pin is CMOS output
1 : TXDi pin is N-channel
open-drain output
UFORM Transfer format select bit
0 0 : f
1
is selected
0 1 : f
8
is selected
1 0 : f
32
is selected
1 1 : fc is selected
b1 b0
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit
register (transmission completed)
0: TXDi pin is CMOS output
1: TXDi pin is N-channel
open-drain output
Must always be “0”
Bit name
Bit
symbol
Must always be “0”
Note: UART1 cannot be used in clock synchronous serial I/O.
A
AA
A
AA
A
A
AA
AA
A
A
AA
A
AA
A
AA
A
AA
Note 1: UART1 cannot be used in clock synchronous serial I/O.
Note 2: UART1 can use only internal clock. Must set this bit to “1”.
Set this bit to “0”.
Set this bit to “1”.
10
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Serial I/O
Figure 1.73. Serial I/O-related registers (3)
UARTi transmit/receive control register 1
Symbol Address When reset
UiC1(i=0,1) 03A5
16
,
03AD
16
02
16
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Bit
symbol Function
(During UART mode)
Function (Note 1)
(During clock synchronous
serial I/O mode)
TE
TI
RE
RI
Transmit enable bit
Receive enable bit
(Note 2)
Receive complete flag
Transmit buffer
empty flag
0 : Transmission disabled
1 : Transmission enabled
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
0 : Reception disabled
1 : Reception enabled
0 : Transmission disabled
1 : Transmission enabled
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
0 : Reception disabled
1 : Reception enabled
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
Nothing is assigned.
When write, set "0". When read, the value of these bits is “0”.
Note 1: UART1 cannot be used in clock synchronous serial I/O.
Note 2: When using multiple pins to output the transfer clock, the following requirements must be met:
• UART0 internal/external clock select bit (bit 3 at address 03A0
16
) = “0”.
UART transmit/receive control register 2
Symbol Address When reset
UCON 03B0
16
XX000000
2
b7 b6 b5 b4 b3 b2 b1 b0
Bit
name
Bit
symbol Function
(During UART mode)
Function
(During clock synchronous
serial I/O mode)
CLKMD0
CLKMD1
UART0 transmit
interrupt cause select bit
UART0 continuous
receive mode enable bit 0 : Continuous receive
mode disabled
1 : Continuous receive
mode enable
Set this bit to “0”.
CLK/CLKS select bit 0
UART1 transmit
interrupt cause select bit
0 :
Transmit buffer empty
(Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Normal mode
(CLK output is CLK0 only)
1 : Transfer clock output
from multiple pins
function selected
Nothing is assigned.
When write, set "0". When read, its content is indeterminate.
0 : Transmit buffer empty
(Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Transmit buffer empty
(Tl = 1)
1 : Transmission completed
(TXEPT = 1)
Must always be “0”
U0IRS
U1IRS
U0RRM Invalid
Invalid
CLK/CLKS select
bit 1 (Note 2)
Valid when bit 5 = “1”
0 : Clock output to CLK1
1 : Clock output to CLKS1
Note 1: UART1 cannot be used in clock synchronous serial I/O.
Note 2: If you are using clock asynchronous serial I/O mode, you can enable 'receive enable bit' when
RxD port input is “H”. If RxD port input is “L” and you have enabled 'receive enable bit' , then
receive operation starts immediately.
WR
AA
A
AA
AA
AA
A
A
AA
WR
AA
AA
A
A
AA
A
AA
A
AA
A
AA
A
AA
A
Set this bit to “0”.
80
Serial I/O
(1) Clock synchronous serial I/O mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. (See Table
1.26.) Figure 1.65 shows the UART0 transmit/receive mode register.
Table 1.26. Specifications of clock synchronous serial I/O mode
Specification
• Transfer data length: 8 bits
• When internal clock is selected (bit 3 at address 03A016 = “0”) : fi/ 2(n+1) (Note 1)
fi = f1, f8, f32, fc
• When external clock is selected (bit 3 at address 03A016 = “1”) : Input from CLK0 pin
• To start transmission, the following requirements must be met:
_ Transmit enable bit (bit 0 at address 03A516) = “1”
_ Transmit buffer empty flag (bit 1 at addresses 03A516) = “0”
• Furthermore, if external clock is selected, the following requirements must also be met:
_ CLK0 polarity select bit (bit 6 at address 03A416) = “0”: CLK0 input level = “H”
_ CLK0 polarity select bit (bit 6 at address 03A416) = “1”: CLK0 input level = “L”
• To start reception, the following requirements must be met:
_ Receive enable bit (bit 2 at address 03A516) = “1”
_ Transmit enable bit (bit 0 at address 03A516) = “1”
_ Transmit buffer empty flag (bit 1 at address 03A516) = “0”
• Furthermore, if external clock is selected, the following requirements must also be met:
_ CLK0 polarity select bit (bit 6 at address 03A416) = “0”: CLK0 input level = “H”
_ CLK0 polarity select bit (bit 6 at address 03A416) = “1”: CLK0 input level = “L”
• When transmitting
_ Transmit interrupt cause select bit (bit 0 at address 03B016) = “0”: Interrupts re-
quested when data transfer from UART0 transfer buffer register to UART0 transmit
register is completed
_ Transmit interrupt cause select bit (bit 0 at address 03B016) = “1”: Interrupts re-
quested when data transmission from UART0 transfer register is completed
• When receiving
_ Interrupts requested when data transfer from UART0 receive register to UART0
receive buffer register is completed
• Overrun error (Note 2)
This error occurs when the next data is ready before contents of UART0receive
buffer register are read out
• CLK polarity selection
Whether transmit data is output/input at the rising edge or falling edge of the trans-
fer clock can be selected
• LSB first/MSB first selection
Whether transmission/reception begins with bit 0 or bit 7 can be selected
• Continuous receive mode selection
Reception is enabled simultaneously by a read from the receive buffer register
• Transfer clock output from multiple pins selection
UART0 transfer clock can be chosen by software to be output from one of the two
pins set
Clock synchronous serial I/O mode
Item
Transfer data format
Transfer clock
Transmission start
condition
Reception start
conditio
Interrupt request
generation timing
Error detection
Select function
Note 1: “n” denotes the value 0016 to FF16 that is set to the UART bit rate generator.
Note 2: If an overrun error occurs, the UART0 receive buffer will have the next data written in. Note also that the
UART0 receive interrupt request bit is not set to “1”.
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Serial I/O
Figure 1.74. UART0 transmit/receive mode register in clock synchronous serial I/O mode
Clock synchronous serial I/O mode
Symbol Address When reset
U0MR 03A0
16
00
16
CKDIR
UART0 transmit/receive mode registers
Internal/external clock
select bit
STPS
PRY
PRYE
SLEP
0 : Internal clock
1 : External clock
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
0 (Must always be “0” in clock synchronous serial I/O mode)
010
SMD0
SMD1
SMD2
Serial I/O mode select bit 0 0 1 : Clock synchronous serial
I/O mode
b2 b1 b0
0
Invalid in clock synchronous serial I/O mode
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Table 1.27 lists the functions of the input/output pins during clock synchronous serial I/O mode. Note that
for a period from when the UART0 operation mode is selected to when transfer starts, the TxD0 pin
outputs a “H”. (If the N-channel open-drain is selected, this pin is in floating state.)
Table 1.27. Input/output pin functions in clock synchronous serial I/O mode
Pin name Function Method of selection
TxD0
(P5
0
)Serial data output
Serial data input
Transfer clock output
Transfer clock input
Port P5
0
direction register (bit 0 at address 03EB
16
)= “1”
(Outputs dummy data when performing reception only)
RxD0
(P5
1
)
CLK0
(P5
2
)Internal/external clock select bit (bit 3 at address 03A0
16
) = “0”
Internal/external clock select bit (bit 3 at address 03A0
16
) = “1”
Port P5
2
direction register (bit 2 at address 03EB
16
) = “0”
Port P5
1
direction register (bit 1 at address 03EB
16
)= “0”
(Can be used as an input port when performing transmission only)
82
Serial I/O
Figure 1.75. Typical transmit/receive timings in clock synchronous serial I/O mode
• Example of transmit timing (when internal clock is selected)
• Example of receive timing (when external clock is selected)
Clock synchronous serial I/O mode
Tc = TCLK = 2(n + 1) / fi
fi: frequency of BRG0 count source (f
1
, f
8
, f
32
, fc)
n: value set to BRG0
Transfer clock
Transmit enable
bit (TE)
Transmit buffer
empty flag (Tl)
CLK0
TxD0
Transmit
register empty
flag (TXEPT)
“0”
“1”
“0”
“1”
“0”
“1”
The above timing applies to the following settings:
• Internal clock is selected.
• CLK polarity select bit = “0”.
• Transmit interrupt cause select bit = “0”.
Transmit interrupt
request bit (IR)
“0”
“1”
1 / fEXT
Dummy data is set in UART0 transmit buffer register
Transmit enable
bit (TE)
Transmit buffer
empty flag (Tl)
CLK0
RxD0
Receive complete
flag (Rl)
“0”
“1”
“0”
“1”
“0”
“1”
Receive enable
bit (RE)
“0”
“1”
Receive data is taken in
Transferred from UART0 transmit buffer register to UART0 transmit register
Read out from UART0 receive buffer register
The above timing applies to the following settings:
• External clock is selected.
• CLK polarity select bit = “0”.
f
EXT
: frequency of external clock
Transferred from UART0 receive register
to UART0 receive buffer register
Receive interrupt
request bit (IR)
“0”
“1”
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
Shown in ( ) are bit symbols.
Meet the following conditions are met when the CLK
input before data reception = “H”
• Transmit enable bit “1”
• Receive enable bit “1”
• Dummy data write to UART0 transmit buffer register
Shown in ( ) are bit symbols.
Cleared to “0” when interrupt request is accepted, or cleared by software
Tc
T
CLK
Stopped pulsing because transfer enable bit = “0”
Data is set in UART0 transmit buffer
register
Transferred from UART0 transmit buffer register to UART0
transmit register
Cleared to “0” when interrupt request is accepted, or cleared by software
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
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Serial I/O
(a) Polarity select function
As shown in Figure 1.76, the CLK polarity select bit (bit 6 at addresses 03A416) allows selection of the
polarity of the transfer clock.
Figure 1.76. Polarity of transfer clock
(b) LSB first/MSB first select function
As shown in Figure 1.77, when the transfer format select bit (bit 7 at addresses 03A416) = “0”, the
transfer format is “LSB first”; when the bit = “1”, the transfer format is “MSB first”.
Figure 1.77. Transfer format
LSB first
• When transfer format select bit = “0”
D0
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
1
D
2
D
3
D
4
D
5
D
6
D
7
T
X
D
0
R
X
D
0
CLK
0
• When transfer format select bit = “1”
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
T
X
D
0
R
X
D
0
CLK
0
MSB first
Note: This applies when the CLK polarity select bit = “0”.
Clock synchronous serial I/O mode
• When CLK polarity select bit = “1”
Note 2: The CLK0 pin level when not
transferring data is “L”.
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
0
T
X
D
0
R
X
D
0
CLK
0
• When CLK polarity select bit = “0”
Note 1: The CLK0 pin level when not
transferring data is “H”.
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
T
X
D
0
R
X
D
0
CLK
0
84
Serial I/O
(c) Transfer clock output from multiple pins function
This function allows the setting two transfer clock output pins and choosing one of the two to output a
clock by using the CLK and CLKS select bit (bits 4 and 5 at address 03B016). (See Figure 1.78.) The
multiple pins function is valid only when the internal clock is selected for UART0.
Figure 1.78. The transfer clock output from the multiple pins function usage
(d) Continuous receive mode
If the continuous receive mode enable bit (bits 2 and 3 at address 03B016) is set to “1”, the unit is
placed in continuous receive mode. In this mode, when the receive buffer register is read out, the unit
simultaneously goes to a receive enable state without having to set dummy data to the transmit buffer
register back again.
Clock synchronous serial I/O mode
Microcomputer
T
X
D
0
(P5
0
)
CLKS (P5
3
)
CLK
0
(P5
2
)IN
CLK
IN
CLK
Note: This applies when the internal clock is selected and transmission
is performed only in clock synchronous serial I/O mode.
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Serial I/O
Item Specification
• Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected
• Start bit: 1 bit
• Parity bit: Odd, even, or nothing as selected
• Stop bit: 1 bit or 2 bits as selected
• When internal clock is selected (bit 3 at addresses 03A016, 03A816 = “0”) :
fi/16(n+1) (Note 1) fi = f1, f8, f32, fC
• When external clock is selected (bit 3 at addresses 03A016=“1”) :
fEXT/16(n+1) (Note 1) (Note 2)
• To start transmission, the following requirements must be met:
- Transmit enable bit (bit 0 at addresses 03A516, 03AD16) = “1”
- Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16) = “0”
• To start reception, the following requirements must be met:
- Receive enable bit (bit 2 at addresses 03A516, 03AD16) = “1”
- Start bit detection
• When transmitting
- Transmit interrupt cause select bits (bits 0,1 at address 03B016) = “0”:
Interrupts requested when data transfer from UARTi transfer buffer register
to UARTi transmit register is completed
- Transmit interrupt cause select bits (bits 0, 1 at address 03B016) = “1”:
Interrupts requested when data transmission from UARTi transfer register is
completed
• When receiving
- Interrupts requested when data transfer from UARTi receive register to
UARTi receive buffer register is completed
• Overrun error (Note 3)
This error occurs when the next data is ready before contents of UARTi
receive buffer register are read out
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
This error occurs when if parity is enabled, the number of 1’s in parity and
character bits does not match the number of 1’s set
• Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is
encountered
• Sleep mode selection
This mode is used to transfer data to and from one of multiple slave micro-
computers
(2) Clock asynchronous serial I/O (UART) mode
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer
data format. (See Table 1.28.) Figure 1.79 shows the UARTi transmit/receive mode register.
Table 1.28. Specifications of UART Mode
Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UART bit rate generator.
Note 2: fEXT is input from the CLK0 pin. Since UART1 does not have this pin, cannot select external clock.
Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that
the UARTi receive interrupt request bit is not set to “1”.
Clock asynchronous serial I/O (UART) mode
Transfer data format
Transfer clock
Transmission start
condition
Reception start condi-
tion
Interrupt request gen-
eration timing
Error detection
Select function
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Serial I/O
Figure 1.79. UARTi transmit/receive mode register in UART mode
Clock asynchronous serial I/O (UART) mode
Symbol Address When reset
UiMR(i=0,1) 03A0
16
, 03A8
16
00
16
CKDIR
UARTi transmit / receive mode registers
Internal / external clock
select bit (Note)
STPS
PRY
PRYE
SLEP
0 : Internal clock
1 : External clock
Bit name FunctionBit symbol
WR
b7 b6 b5 b4 b3 b2 b1 b0
SMD0
SMD1
SMD2
Serial I/O mode select bit
b2 b1 b0
0 : One stop bit
1 : Two stop bits
0 : Parity disabled
1 : Parity enabled
0 : Sleep mode deselected
1 : Sleep mode selected
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
Stop bit length select bit
Odd / even parity
select bit
Parity enable bit
Sleep select bit
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Note: UART1 can use only internal clock. Must set this bit to “1”.
Table 1.29 lists the functions of the input/output pins during UART mode. Note that for a period from
when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a “H”. (If the N-
channel open-drain is selected, this pin is in floating state.)
Table 1.29. Input/output pin functions in UART mode
Pin name Function Method of selection
TxDi
(P50, P40)Serial data output
Serial data input
Programmable I/O port
Transfer clock input
RxDi
(P51, P42)
CLK0
(P52)Internal/external clock select bit (bit 3 at address 03A016) = “0”
Internal/external clock select bit (bit 3 at address 03A016) = “1”
Port P51 and P42 direction register (bit 1 at address 03EB16, bit 2 at
address 03EA16)= “0”
(Can be used as an input port when performing transmission only)
Port P51 and P42 direction register (bit 0 at address 03EB16, bit 0 at
address 03EA16)= “1”
(Can be used as an input port when performing reception only)
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Serial I/O
• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
• Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)
Figure 1.80. Typical transmit timings in UART mode
Clock asynchronous serial I/O (UART) mode
Transmit enable
bit(TE)
Transmit buffer
empty flag(TI)
Transmit register
empty flag
(TXEPT)
Start
bit Parity
bit
TxDi
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
• Transmit interrupt cause select bit = “1”.
“1”
“0”
“1”
“0”
“1”
Tc = 16 (n + 1) / fi or 16 (n + 1) / f
EXT
fi : frequency of BRGi count source (f1, f8, f32, fc)
fEXT : frequency of BRGi count source (external clock)
n : value set to BRGi
Transmit interrupt
request bit (IR) “0”
“1”
Cleared to “0” when interrupt request is accepted, or cleared by software
Transmit enable
bit(TE)
Transmit buffer
empty flag(TI)
TxDi
Transmit register
empty flag
(TXEPT)
“0”
“1”
“0”
“1”
“0”
“1”
The above timing applies to the following settings :
• Parity is disabled.
• Two stop bits.
• Transmit interrupt cause select bit = “0”.
Transfer clock
Tc
Tc = 16 (n + 1) / fi or 16 (n + 1) / f
EXT
fi : frequency of BRGi count source (f1, f8, f32)
fEXT : frequency of BRGi count source (external clock)
n : value set to BRGi
Transmit interrupt
request bit (IR) “0”
“1”
Shown in ( ) are bit symbols.
Shown in ( ) are bit symbols.
Tc
Transfer clock
D0D1D2D3D4D5D6D7
ST PD0D1D2D3D4D5D6D7SP ST PSP D0D1
ST
Stopped pulsing because transmit enable bit = “0”
Stop
bit
Transferred from UARTi transmit buffer register to UARTi transmit register
Start
bit
Data is set in UARTi transmit buffer register
D0D1D2D3D4D5D6D7
ST SP
D8D0D1D2D3D4D5D6D7
ST D8D0D1
ST
SPSP
Transferred from UARTi transmit buffer register to UARTi transmit register
Stop
bit Stop
bit
Data is set in UARTi transmit buffer register.
“0”
SP
Cleared to “0” when interrupt request is accepted, or cleared by software
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Serial I/O
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
Figure 1.81. Typical receive timing in UART mode
(a) Sleep mode
This mode is used to transfer data between specific microcomputers among multiple microcomputers
connected using UARTi. The sleep mode is selected when the sleep select bit (bit 7 at addresses
03A016, 03A816) is set to “1” during reception. In this mode, the unit performs receive operation when
the MSB of the received data = “1” and does not perform receive operation when the MSB = “0”.
Clock asynchronous serial I/O (UART) mode
D
0
Start bit
Sampled “L” Receive data taken in
BRGi count
source
Receive enable bit
RxDi
Transfer clock
Receive
complete flag
Stop bit
“1”
“0”
“0”
“1”
The above timing applies to the following settings :
•Parity is disabled.
•One stop bit.
Receive interrupt
request bit “0”
“1”
Transferred from UARTi receive register to
UARTi receive buffer register
Reception triggered when transfer clock
is generated by falling edge of start bit
D
7
D
1
Cleared to “0” when interrupt request is accepted, or cleared by software
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
Item Performance
Method of A-D conversion Successive approximation (capacitive coupling amplifier)
Analog input voltage (Note 1)
0V to AVCC (VCC)
Operating clock fAD (Note 2)
VCC = 5V fAD, divide-by-2 of fAD, divide-by-4 of fAD, fAD=f(XIN)
VCC = 3V divide-by-2 of fAD, divide-by-4 of fAD, fAD=f(XIN)
Resolution 8-bit or 10-bit (selectable)
Absolute precision VCC = 5V • Without sample and hold function
–3LSB
• With sample and hold function (8-bit resolution)
–2LSB
• With sample and hold function (10-bit resolution)
–3LSB
VCC = 3V • Without sample and hold function (8-bit resolution)
–2LSB
Operating modes One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,
and repeat sweep mode 1
Analog input pins 8 pins (AN0 to AN7) + 5 pins (AN50 to AN54)
A-D conversion start condition
• Software trigger
A-D conversion starts when the A-D conversion start flag changes to “1”
Conversion speed per pin • Without sample and hold function
8-bit resolution: 49
f
AD cycles
,
10-bit resolution: 59
f
AD cycles
• With sample and hold function
8-bit resolution: 28
f
AD cycles
,
10-bit resolution: 33
f
AD cycles
A-D Converter
The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive
coupling amplifier. Pins P60 to P67, and P50 to P54 also function as the analog signal input pins. The
direction registers of these pins for A-D conversion must therefore be set to input. The Vref connect bit (bit
5 at address 03D716) can be used to isolate the resistance ladder of the A-D converter from the reference
voltage input pin (VREF) when the A-D converter is not used. Doing so stops any current flowing into the
resistance ladder from VREF, reducing the power dissipation. When using the A-D converter, start A-D
conversion only after setting bit 5 of 03D716 to connect VREF.
The result of A-D conversion is stored in the A-D registers of the selected pins. When set to 10-bit precision,
the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit
precision, the low 8 bits are stored in the even addresses.
Table 1.30 shows the performance of the A-D converter. Figure 1.82 shows the block diagram of the A-D
converter, and Figures 1.83 and 1.84 show the A-D converter-related registers.
Note 1: Does not depend on use of sample and hold function.
Note 2: Without sample and hold function, set the
f
AD frequency to 250kHz min.
With the sample and hold function, set the
f
AD frequency to 1MHz min.
Table 1.30. Performance of A-D converter
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A-D Converter
Figure 1.82. Block diagram of A-D converter
1/2
fAD
1/2
fAD
A-D conversion rate
selection
(03C116, 03C016)
(03C316, 03C216)
(03C516, 03C416)
(03C716, 03C616)
(03C916, 03C816)
(03CB16, 03CA16)
(03CD16, 03CC16)
(03CF16, 03CE16)
CKS1=1
CKS0=0
A-D register 0(16)
A-D register 1(16)
A-D register 2(16)
A-D register 3(16)
A-D register 4(16)
A-D register 5(16)
A-D register 6(16)
A-D register 7(16)
Resistor ladder
Successive conversion register
A-D control register 0 (address 03D616)
A-D control register 1 (address 03D716)
Vref
VIN
Data bus high-order
Data bus low-order
VREF VCUT=0
AVSS VCUT=1
CKS0=1
CKS1=0
Decoder
Comparator
Addresses
P60/AN0
P61/AN1
P62/AN2
P63/AN3
P65/AN5
P66/AN6
P67/AN7
P64/AN4
CH2,CH1,CH0=000
CH2,CH1,CH0=001
CH2,CH1,CH0=010
CH2,CH1,CH0=011
CH2,CH1,CH0=100
CH2,CH1,CH0=101
CH2,CH1,CH0=110
CH2,CH1,CH0=111
P50/AN50
P52/AN52
P53/AN53
P54/AN54
P51/AN51
CH2,CH1,CH0=000
CH2,CH1,CH0=001
CH2,CH1,CH0=010
CH2,CH1,CH0=011
CH2,CH1,CH0=100
ADGSEL0=0
ADGSEL0=1
Port P6 group
Port P5 group
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A-D Converter
Figure 1.83. A-D converter-related registers (1)
A-D control register 0 (Note 1)
Symbol Address When reset
ADCON0 03D616 00000XXX2
b7 b6 b5 b4 b3 b2 b1 b0
Analog input pin select bit 0 0 0 : AN0 is selected
0 0 1 : AN1 is selected
0 1 0 : AN2 is selected
0 1 1 : AN3 is selected
1 0 0 : AN4 is selected
1 0 1 : AN5 is selected
1 1 0 : AN6 is selected
1 1 1 : AN7 is selected (Note 2)
CH0
Bit symbol Bit name Function
CH1
CH2
A-D operation mode
select bit 0 0 0 : One-shot mode
0 1 : Repeat mode
1 0 : Single sweep mode
1 1 : Repeat sweep mode 0
Repeat sweep mode 1
MD0
MD1
ADST A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
Frequency select bit 0 0 : fAD/4 is selected
1 : fAD/2 is selected
CKS0
WR
A-D control register 1 (Note 1)
Symbol Address When reset
ADCON1 03D716 0016
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
A-D sweep pin select bit
SCAN0
SCAN1
MD2
BITS 8/10-bit mode select bit 0 : 8-bit mode
1 : 10-bit mode
VCUT Vref connect bit
ADGSEL0
A-D operation mode
select bit 1 0 : Any mode other than repeat sweep
mode 1
1 : Repeat sweep mode 1
0 : Vref not connected
1 : Vref connected
A-D input group select bit
WR
b2 b1 b0
b4 b3
When single sweep and repeat sweep
mode 0 are selected
0 0 : AN0, AN1 (2 pins)
0 1 : AN0 to AN3 (4 pins)
1 0 : AN0 to AN5 (6 pins)
1 1 : AN0 to AN7 (8 pins)
b1 b0
When repeat sweep mode 1 is selected
0 0 : AN0 (1 pin)
0 1 : AN0, AN1 (2 pins)
1 0 : AN0 to AN2 (3 pins)
1 1 : AN0 to AN3 (4 pins)
b1 b0
0 : Port P6 group is selected
1 : Port P5 group is selected
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
Note 2: AN50 to AN54 can be used in the same way as for AN0 to AN4.
Frequency select bit 1 0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
CKS1
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
Note 2: AN50 to AN54 can be used in the same way as for AN0 to AN4.
Note 3: If the repeat sweep mode is selected for the port P5 group, the contents of A-D
registers 5 to 7 are indeterminate.
AA
A
AA
A
AA
A
AA
AA
A
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
A
A
AA
AA
0
Set this bit to “0”.
(Note 2, 3)
0
Set this bit to “0”.
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A-D Converter
Figure 1.84. A-D converter-related registers (2)
A-D control register 2 (Note)
Symbol Address When reset
ADCON2 03D416 XXXX00002
b7 b6 b5 b4 b3 b2 b1 b0
A-D conversion method
select bit 0 : Without sample and hold
1 : With sample and hold
Bit symbol Bit name Function R W
Note: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
A
A
A
A
Nothing is assigned.
When write, set "0". When read, their content is indeterminate.
A-D register i
Symbol Address When reset
ADi(i=0 to 7) 03C016 to 03CF16 Indeterminate
Eight low-order bits of A-D conversion result
Function R W
(b15) b7b7 b0 b0
(b8)
• During 10-bit mode
Two high-order bits of A-D conversion result
Nothing is assigned.
When write, set "0". When read, their content is
indeterminate.
• During 8-bit mode
When read, the content is indeterminate
A
A
A
A
SMP
000
A
A
A
A
Reserved bit Always set to “0”
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
(1) One-shot mode
In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A-D conver-
sion. (See Table 1.31.) Figure 1.85 shows the A-D control register in one-shot mode.
Figure 1.85. A-D conversion register in one-shot mode
Item Specification
Function
The pin selected by the analog input pin select bit is used for one A-D conversion
Start condition Writing “1” to A-D conversion start flag
Stop condition
•
End of A-D conversion (A-D conversion start flag changes to “0”)
• Writing “0” to A-D conversion start flag
Interrupt request generation timing
End of A-D conversion
Input pin One of AN0 to AN7, as selected (Note)
Reading of result of A-D converter
Read A-D register corresponding to selected pin
Note : AN50 to AN54 can be used in the same way as for AN0 to AN4.
A-D control register 0 (Note 1)
Symbol Address When reset
ADCON0 03D616 00000XXX2
b7 b6 b5 b4 b3 b2 b1 b0
Analog input pin select bit 0 0 0 : AN
0
is selected
0 0 1 : AN
1
is selected
0 1 0 : AN
2
is selected
0 1 1 : AN
3
is selected
1 0 0 : AN
4
is selected
1 0 1 : AN
5
is selected
1 1 0 : AN
6
is selected
1 1 1 : AN
7
is selected (Note 2)
CH0
Bit symbol Bit name Function
CH1
CH2
A-D operation mode
select bit 0 0 0 : One-shot mode
MD0
MD1
ADST A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
Frequency select bit 0 0 : f
AD
/4 is selected
1 : f
AD
/2 is selected
CKS0
WR
A-D control register 1 (Note)
Symbol Address When reset
ADCON1 03D716 0016
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
A-D sweep pin select bitSCAN0
SCAN1
MD2
BITS 8/10-bit mode select bit 0 : 8-bit mode
1 : 10-bit mode
VCUT Vref connect bit
ADGSEL0
A-D operation mode
select bit 1
1 : Vref connected
A-D input group select bit
WR
b2 b1 b0
b4 b3
0 : Port P6 group is selected
1 : Port P5 group is selected
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Note 2: AN
50
to AN
54
can be used in the same way as for AN
0
to AN
4
.
Frequency select bit 1 0 : f
AD
/2 or f
AD
/4 is selected
1 : f
AD
is selected
CKS1
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
AA
A
AA
A
AA
A
AA
A
AA
A
AA
AA
A
A
AA
A
AA
A
AA
AA
A
A
AA
A
AA
A
AA
A
AA
AA
A
A
AA
AA
A
A
AA
AA
A
A
A
A
AA
AA
0
Set this bit to “0”.
0
Set this bit to “0”.
00
01
Invalid in one-shot mode
Set this bit to “0” in this mode.
Table 1.31. One-shot mode specifications
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
(2) Repeat mode
In repeat mode, the pin selected using the analog input pin select bit is used for repeated A-D conversion.
(See Table 1.32.) Figure 1.86 shows the A-D control register in repeat mode.
Figure 1.86. A-D conversion register in repeat mode
Item Specification
Function
The pin selected by the analog input pin select bit is used for repeated A-D conversion
Start condition Writing “1” to A-D conversion start flag
Stop condition Writing “0” to A-D conversion start flag
Interrupt request generation timing
None generated
Input pin One of AN0 to AN7, as selected (Note)
Reading of result of A-D converter
Read A-D register corresponding to selected pin
Table 1.32. Repeat mode specifications
A-D control register 0 (Note 1)
Symbol Address When reset
ADCON0 03D6
16
00000XXX
2
b7 b6 b5 b4 b3 b2 b1 b0
Analog input pin select bit 0 0 0 : AN
0
is selected
0 0 1 : AN
1
is selected
0 1 0 : AN
2
is selected
0 1 1 : AN
3
is selected
1 0 0 : AN
4
is selected
1 0 1 : AN
5
is selected
1 1 0 : AN
6
is selected
1 1 1 : AN
7
is selected (Note 2)
CH0
Bit symbol Bit name Function
CH1
CH2
A-D operation mode
select bit 0 0 1 : Repeat mode
MD0
MD1
ADST A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
Frequency select bit 0 0 : f
AD
/4 is selected
1 : f
AD
/2 is selected
CKS0
WR
A-D control register 1 (Note)
Symbol Address When reset
ADCON1 03D7
16
00
16
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
A-D sweep pin select bitSCAN0
SCAN1
MD2
BITS 8/10-bit mode select bit 0 : 8-bit mode
1 : 10-bit mode
VCUT Vref connect bit
ADGSEL0
A-D operation mode
select bit 1
1 : Vref connected
A-D input group select bit
WR
b2 b1 b0
b4 b3
0 : Port P6 group is selected
1 : Port P5 group is selected
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Note 2: AN
50
to AN
54
can be used in the same way as for AN
0
to AN
4
.
Frequency select bit 1 0 : f
AD
/2 or f
AD
/4 is selected
1 : f
AD
is selected
CKS1
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
0
Set this bit to “0”.
0
Set this bit to “0”.
01
01
Invalid in repeat mode
Set this bit to “0” in this mode.
Note : AN50 to AN54 can be used in the same way as for AN0 to AN4.
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M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
(3) Single sweep mode
In single sweep mode, the pins selected using the A-D sweep pin select bit are used for one-by-one A-D
conversion. (See Table 1.33.) Figure 1.87 shows the A-D control register in single sweep mode.
Figure 1.87. A-D conversion register in single sweep mode
Item Specification
Function
The pins selected by the A-D sweep pin select bit are used for one-by-one A-D conversion
Start condition Writing “1” to A-D converter start flag
Stop condition • End of A-D conversion (A-D conversion start flag changes to “0”.)
• Writing “0” to A-D conversion start flag
Interrupt request generation timing
End of A-D conversion
Input pin
AN
0
and AN
1
(2 pins), AN
0
to AN
3
(4 pins), AN
0
to AN
5
(6 pins), or AN
0
to AN
7
(8 pins)(Note)
Reading of result of A-D converter
Read A-D register corresponding to selected pin
Note : AN50 to AN54 can be used in the same way as for AN0 to AN4.
A-D control register 0 (Note)
Symbol Address When reset
ADCON0 03D6
16
00000XXX
2
b7 b6 b5 b4 b3 b2 b1 b0
Analog input pin select bit Invalid in single sweep modeCH0
Bit symbol Bit name Function
CH1
CH2
A-D operation mode
select bit 0 1 0 : Single sweep mode
MD0
MD1
ADST A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
Frequency select bit 0 0 : f
AD
/4 is selected
1 : f
AD
/2 is selected
CKS0
WR
A-D control register 1 (Note 1)
Symbol Address When reset
ADCON1 03D7
16
00
16
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
A-D sweep pin select bit
SCAN0
SCAN1
MD2
BITS 8/10-bit mode select bit 0 : 8-bit mode
1 : 10-bit mode
VCUT Vref connect bit
ADGSEL0
A-D operation mode
select bit 1
1 : Vref connected
A-D input group select bit
WR
b4 b3
0 : Port P6 group is selected
1 : Port P5 group is selected
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Frequency select bit 1 0 : f
AD
/2 or f
AD
/4 is selected
1 : f
AD
is selected
CKS1
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Note 2: AN
50
to AN
54
can be used in the same way as for AN
0
to AN
4
.
Note 3: If port P5 group is selected, do not select 6 pins and 8 pins sweep mode.
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
0
Set this bit to “0”.
0
Set this bit to “0”.
10
01
When single sweep and repeat sweep
mode 0 are selected
0 0 : AN
0
, AN
1
(2 pins)
0 1 : AN
0
to AN
3
(4 pins)
1 0 : AN
0
to AN
5
(6 pins)
1 1 : AN
0
to AN
7
(8 pins)
b1 b0
(Note 2, 3)
Set this bit to “0” in this mode.
Table 1.33. Single sweep mode specifications
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
(4) Repeat sweep mode 0
In repeat sweep mode 0, the pins selected using the A-D sweep pin select bit are used for repeat sweep
A-D conversion. (See Table 1.34.) Figure 1.88 shows the A-D control register in repeat sweep mode 0.
Figure 1.88. A-D conversion register in repeat sweep mode 0
Item Specification
Function
The pins selected by the A-D sweep pin select bit are used for repeat sweep A-D conversion
Start condition Writing “1” to A-D conversion start flag
Stop condition Writing “0” to A-D conversion start flag
Interrupt request generation timing
None generated
Input pin
AN
0
and AN
1
(2 pins), AN
0
to AN
3
(4 pins), AN
0
to AN
5
(6 pins), or AN
0
to AN
7
(8 pins)(Note)
Reading of result of A-D converter
Read A-D register corresponding to selected pin (at any time)
Table 1.34. Repeat sweep mode 0 specifications
Note : AN50 to AN54 can be used in the same way as for AN0 to AN4.
A-D control register 0 (Note)
Symbol Address When reset
ADCON0 03D6
16
00000XXX
2
b7 b6 b5 b4 b3 b2 b1 b0
Analog input pin select bit Invalid in repeat sweep mode 0CH0
Bit symbol Bit name Function
CH1
CH2
A-D operation mode
select bit 0 1 1 : Repeat sweep mode 0
MD0
MD1
ADST A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
Frequency select bit 0 0 : f
AD
/4 is selected
1 : f
AD
/2 is selected
CKS0
WR
A-D control register 1 (Note 1)
Symbol Address When reset
ADCON1 03D7
16
00
16
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
A-D sweep pin select bit
SCAN0
SCAN1
MD2
BITS 8/10-bit mode select bit 0 : 8-bit mode
1 : 10-bit mode
VCUT Vref connect bit
ADGSEL0
A-D operation mode
select bit 1
1 : Vref connected
A-D input group select bit
WR
b4 b3
0 : Port P6 group is selected
1 : Port P5 group is selected
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Frequency select bit 1 0 : f
AD
/2 or f
AD
/4 is selected
1 : f
AD
is selected
CKS1
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Note 2: AN
50
to AN
54
can be used in the same way as for AN
0
to AN
4
.
Note 3: If port P5 group is selected, the contents of A-D registers 5 to 7 are indeterminate.
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
AA
AA
A
A
AA
AA
A
A
A
A
A
A
A
A
0
Set this bit to “0”.
0
Set this bit to “0”.
11
01
When single sweep and repeat sweep
mode 0 are selected
0 0 : AN
0
, AN
1
(2 pins)
0 1 : AN
0
to AN
3
(4 pins)
1 0 : AN
0
to AN
5
(6 pins)
1 1 : AN
0
to AN
7
(8 pins)
b1 b0
(Note 2, 3)
Set this bit to “0” in this mode.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
Item Specification
Function All pins perform repeat sweep A-D conversion, with emphasis on the pin or
pins selected by the A-D sweep pin select bit
Example : AN0 selected AN0 AN1 AN0 AN2 AN0 AN3, etc
Start condition Writing “1” to A-D conversion start flag
Stop condition Writing “0” to A-D conversion start flag
Interrupt request generation timing
None generated
Input pin
AN
0
(1 pin), AN
0
and AN
1
(2 pins), AN
0
to AN
2
(3 pins), AN
0
to AN
3
(4 pins) (Note)
Reading of result of A-D converter
Read A-D register corresponding to selected pin (at any time)
(5) Repeat sweep mode 1
In repeat sweep mode 1, all pins are used for A-D conversion with emphasis on the pin or pins selected using
the A-D sweep pin select bit. (See Table 1.35.) Figure 1.89 shows the A-D control register in repeat sweep mode
1.
Figure 1.89. A-D conversion register in repeat sweep mode 1
Table 1.35. Repeat sweep mode 1 specifications
A-D control register 0 (Note)
Symbol Address When reset
ADCON0 03D6
16
00000XXX
2
b7 b6 b5 b4 b3 b2 b1 b0
Analog input pin select bit Invalid in repeat sweep mode 1CH0
Bit symbol Bit name Function
CH1
CH2
A-D operation mode
select bit 0 1 1 : Repeat sweep mode 1
MD0
MD1
ADST A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
Frequency select bit 0 0 : f
AD
/4 is selected
1 : f
AD
/2 is selected
CKS0
WR
A-D control register 1 (Note 1)
Symbol Address When reset
ADCON1 03D7
16
00
16
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
A-D sweep pin select bit
SCAN0
SCAN1
MD2
BITS 8/10-bit mode select bit 0 : 8-bit mode
1 : 10-bit mode
VCUT Vref connect bit
ADGSEL0
A-D operation mode
select bit 1 Set “1” in this mode.
1 : Vref connected
A-D input group select bit
WR
b4 b3
0 : Port P6 group is selected
1 : Port P5 group is selected
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Frequency select bit 1 0 : f
AD
/2 or f
AD
/4 is selected
1 : f
AD
is selected
CKS1
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Note 2: AN
50
to AN
54
can be used in the same way as for AN
0
to AN
4
.
Note 3: If port P5 group is selected, the contents of A-D registers 5 to 7 are indeterminate.
A
AA
A
AA
A
A
AA
AA
A
A
AA
AA
A
AA
A
AA
A
AA
A
AA
A
A
AA
AA
A
AA
A
A
AA
AA
A
A
AA
AA
A
AA
A
AA
A
AA
AA
A
0
Set this bit to “0”.
0
Set this bit to “0”.
11
11
When single sweep and repeat sweep
mode 1 are selected
0 0 : AN
0
(1 pins)
0 1 : AN
0
, AN
1
(2 pins)
1 0 : AN
0
to AN
2
(3 pins)
1 1 : AN
0
to AN
3
(4 pins)
b1 b0
(Note 2, 3)
Note : AN50 to AN54 can be used in the same way as for AN0 to AN4.
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M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
• Sample and hold
Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 03D416) to “1”. When
sample and hold is selected, the rate of conversion of each pin increases. As a result, a 28 fAD cycle is
achieved with 8-bit resolution and 33 fAD with 10-bit resolution. Sample and hold can be selected in all
modes. However, in all modes, be sure to specify before starting A-D conversion whether sample and
hold is to be used.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Programmable I/O Ports
There are 43 programmable I/O ports: P0 to P7. Each port can be set independently for input or output
using the direction register. A pull-up resistance for each block of 4 ports can be set. The port P1 allows the
drive capacity of its N-channel output transistor to be set as necessary.
Figures 1.90 to 1.92 show the programmable I/O ports.
Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices.
To use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input
mode. When the pins are used as the outputs for the built-in peripheral devices, they function as outputs
regardless of the contents of the direction registers. See the descriptions of the respective functions for how
to set up the built-in peripheral devices.
(1) Direction registers
Figure 1.93 shows the direction registers.
These registers are used to choose the direction of the programmable I/O ports. Each bit in these regis-
ters corresponds one for one to each I/O pin.
(2) Port registers
Figure 1.94 shows the port registers.
These registers are used to write and read data for input and output to and from an external device. A
port register consists of a port latch to hold output data and a circuit to read the status of a pin. Each bit
in port registers corresponds one for one to each I/O pin.
(3) Pull-up control registers
Figure 1.95 shows the pull-up control registers.
The pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. When ports
are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is
set for input.
(4) Port P1 drive capacity control register
Figure 1.95 shows a structure of the port P1 drive capacity control register.
This register is used to control the drive capacity of the port P1's N-channel output transistor. Each bit in
this register corresponds one for one to the port pins.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Figure 1.90. Programmable I/O ports (1)
P3
0
to P3
5
Data bus
Direction register
Pull-up selection
Port latch
P0
0
to P0
7
, P4
2
, P7
1
Data bus
Pull-up selection
Input to respective peripheral functions
Direction register
Port latch
P4
1
, P7
0
Data bus
Pull-up selection
output
Direction register
Port latch
P4
0
, P4
3
, P4
4
Data bus
Pull-up selection
output
Input to respective peripheral functions
Direction register
Port latch
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Figure 1.91. Programmable I/O ports (2)
P10 to P17
Data bus
Pull-up selection
Drive capacity control register
Direction register
Port latch
P50, P53, P54
Data bus
Pull-up selection
output
Direction register
Port latch
Analog input
P52
Data bus
Pull-up selection
output
Direction register
Port latch
Analog input
Serial clock input
P51
Data bus
Pull-up selection
Analog input
Port latch
Direction register
Serial I/O input
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Figure 1.92. Programmable I/O ports (3)
P6
0
to P6
7
Data bus
Pull-up selection
Analog input
Port latch
Direction register
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Figure 1.93. Direction register
Port Pi direction register (Note 1)
Symbol Address When reset
PDi (i = 0 to 7) 03E2
16
, 03E3
16
, 03E7
16
, 03EA
16
,
00
16
03EB
16
, 03EE
16
, 03EF
16
00
16
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
PDi_0 Port Pi
0
direction register
PDi_1 Port Pi
1
direction register
PDi_2 Port Pi
2
direction register
PDi_3 Port Pi
3
direction register
PDi_4 Port Pi
4
direction register
PDi_5 Port Pi
5
direction register
PDi_6 Port Pi
6
direction register
PDi_7 Port Pi
7
direction register
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
(i = 0 to 7 except 2)
Note 1: Set bit 2 of protect register (address 000A
16
) to “1” before rewriting to the
port P4 direction register.
Note 2: Nothing is assigned in direction register of P3
6
, P3
7
, P4
6
, P4
7
, P5
5
to p5
7
,
P7
2
to P7
7
. These bits can either be set nor reset. When read, its contents
are indeterminate.
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Figure 1.94. Port register
Port Pi register
Bit name FunctionBit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
Pi_0 Port Pi
0
register
Pi_1 Port Pi
1
register
Pi_2 Port Pi
2
register
Pi_3 Port Pi
3
register
Pi_4 Port Pi
4
register
Pi_5 Port Pi
5
register
Pi_6 Port Pi
6
register
Pi_7 Port Pi
7
register
Data is input and output to and from
each pin by reading and writing to
and from each corresponding bit
0 : “L” level data
1 : “H” level data
(i = 0 to 7 except 2)
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Symbol Address When reset
Pi (i = 0 to 7) 03E0
16
, 03E1
16
, 03E5
16
, 03E8
16
, Indeterminate
03E9
16
, 03EC
16
, 03ED
16
Indeterminate
Note: Nothing is assigned in direction register of P3
6
, P3
7
, P4
6
, P4
7
, P5
5
to p5
7
, P7
2
to
P7
7
. This bit can either be set nor reset. When read, its content is indeterminate.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Figure 1.95. Pull-up control register
Pull-up control register 0
Symbol Address When reset
PUR0 03FC
16
00
16
Bit name Function Bit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
PU00 P0
0
to P0
3
pull-up
PU01 P0
4
to P0
7
pull-up
PU02 P1
0
to P1
3
pull-up
PU03 P1
4
to P1
7
pull-up
PU06 P3
0
to P3
3
pull-up
PU07 P3
4
to P3
5
pull-up
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
1 : Pulled high
A
AA
A
A
AA
AA
A
AA
A
AA
A
AA
A
AA
A
A
AA
AA
A
AA
Pull-up control register 1
Symbol Address When reset
PUR1 03FD
16
00
16
Bit name Function Bit symbol
WR
b7 b6 b5 b4 b3 b2 b1 b0
PU10 P4
0
to P4
3
pull-up
PU11 P4
4
to P4
7
pull-up
PU12 P5
0
to P5
3
pull-up
PU13 P5
4
pull-up
PU14 P6
0
to P6
3
pull-up
PU15 P6
4
to P6
7
pull-up
PU16 P7
0
to P7
1
pull-up
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
1 : Pulled high
A
A
AA
AA
A
AA
A
A
AA
AA
A
AA
A
AA
A
AA
A
AA
A
A
AA
AA
Port P1 drive capacity control register
Symbol Address When reset
DRR 03FE
16
00
16
Bit name Function Bit symbol
WR
b7 b6 b5 b4 b3 b2 b1 b0
DRR0 Port
P1
0
drive capacuty
DRR1 Port
P1
1
drive capacuty
DRR2 Port
P1
2
drive capacuty
DRR3 Port
P1
3
drive capacuty
DRR4 Port
P1
4
drive capacuty
DRR5 Port
P1
5
drive capacuty
DRR6 Port
P1
6
drive capacuty
DRR7 Port
P1
7
drive capacuty
Set P1 N-channel output
transistor drive capacity
0 : LOW
1 : HIGH
A
AA
A
A
AA
AA
A
AA
A
AA
A
A
AA
AA
A
AA
A
A
AA
AA
A
AA
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Example connection of unused pins
Table 1.36. Example connection of unused pins
Pin name Connection
Ports P0, P1, P3 to P7
X
OUT
(Note)
AV
SS
, V
REF
AV
CC
After setting for input mode, connect every pin to V
SS
(pull-down); or
after setting for output mode, leave these pins open.
Open
Connect to V
CC
Connect to V
SS
Note: With external clock input to X
IN
pin.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Usage precaution
Usage Precaution
Timer A (timer mode)
(1) Reading the timer A0 register while a count is in progress allows reading, with arbitrary timing, the
value of the counter. Reading the timer A0 register with the reload timing gets “FFFF16”. Reading
the timer A0 register after setting a value in the timer A0 register with a count halted but before the
counter starts counting gets a proper value.
Timer A (event counter mode)
(1) Reading the timer A0 register while a count is in progress allows reading, with arbitrary timing, the
value of the counter. Reading the timer A0 register with the reload timing gets “FFFF16” by under-
flow or “000016” by overflow. Reading the timer A0 register after setting a value in the timer A0
register with a count halted but before the counter starts counting gets a proper value.
(2) When stop counting in free run type, set timer again.
Timer A (one-shot timer mode)
(1) Setting the count start flag to “0” while a count is in progress causes as follows:
• The counter stops counting and a content of reload register is reloaded.
• The TA0OUT pin outputs “L” level.
• The interrupt request generated and the timer A0 interrupt request bit goes to “1”.
(2) The timer A0 interrupt request bit goes to “1” if the timer's operation mode is set using any of the
following procedures:
• Selecting one-shot timer mode after reset.
• Changing operation mode from timer mode to one-shot timer mode.
• Changing operation mode from event counter mode to one-shot timer mode.
Therefore, to use timer A0 interrupt (interrupt request bit), set timer A0 interrupt request bit to “0”
after the above listed changes have been made.
Timer A (pulse width modulation mode)
(1) The timer A0 interrupt request bit becomes “1” if setting operation mode of the timer in compliance
with any of the following procedures:
• Selecting PWM mode after reset.
• Changing operation mode from timer mode to PWM mode.
• Changing operation mode from event counter mode to PWM mode.
Therefore, to use timer A0 interrupt (interrupt request bit), set timer A0 interrupt request bit to “0”
after the above listed changes have been made.
(2) Setting the count start flag to “0” while PWM pulses are being output causes the counter to stop
counting. If the TA0OUT pin is outputting an “H” level in this instance, the output level goes to “L”,
and the timer A0 interrupt request bit goes to “1”. If the TA0OUT pin is outputting an “L” level in this
instance, the level does not change, and the timer A0 interrupt request bit does not becomes “1”.
108
Under
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Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Usage precaution
Timer B (timer mode, event counter mode)
(1) Reading the timer Bi register while a count is in progress allows reading , with arbitrary timing, the
value of the counter. Reading the timer Bi register with the reload timing gets “FFFF16”. Reading the
timer Bi register after setting a value in the timer Bi register with a count halted but before the counter
starts counting gets a proper value.
Timer B (pulse period/pulse width measurement mode)
(1) If changing the measurement mode select bit is set after a count is started, the timer Bi interrupt
request bit goes to “1”.
(2) When the first effective edge is input after a count is started, an indeterminate value is transferred to
the reload register. At this time, timer Bi interrupt request is not generated.
Timer X (timer mode)
(1) Reading the timer Xi register while a count is in progress allows reading, with arbitrary timing, the
value of the counter. Reading the timer Xi register with the reload timing gets “FFFF16”. Reading the
timer A0 register after setting a value in the timer Xi register with a count halted but before the counter
starts counting gets a proper value.
Timer X (event counter mode)
(1) Reading the timer Xi register while a count is in progress allows reading, with arbitrary timing, the
value of the counter. Reading the timer Xi register with the reload timing gets “FFFF16” by underflow
or “000016” by overflow. Reading the timer Xi register after setting a value in the timer Xi register with
a count halted but before the counter starts counting gets a proper value.
(2) When stop counting in free run type, set timer again.
Timer X (one-shot timer mode)
(1) Setting the count start flag to “0” while a count is in progress causes as follows:
• The counter stops counting and a content of reload register is reloaded.
• The TXiINOUT pin outputs “L” level.
• The interrupt request generated and the timer Xi interrupt request bit goes to “1”.
(2) The timer Xi interrupt request bit goes to “1” if the timer's operation mode is set using any of the
following procedures:
• Selecting one-shot timer mode after reset.
• Changing operation mode from timer mode to one-shot timer mode.
• Changing operation mode from event counter mode to one-shot timer mode.
Therefore, to use timer Xi interrupt (interrupt request bit), set timer Xi interrupt request bit to “0” after
the above listed changes have been made.
109
Under
development
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Usage precaution
Timer X (pulse width modulation mode)
(1) The timer Xi interrupt request bit becomes “1” if setting operation mode of the timer in compliance with
any of the following procedures:
• Selecting PWM mode after reset.
• Changing operation mode from timer mode to PWM mode.
• Changing operation mode from event counter mode to PWM mode.
Therefore, to use timer Xi interrupt (interrupt request bit), set timer Xi interrupt request bit to “0” after
the above listed changes have been made.
(2) Setting the count start flag to “0” while PWM pulses are being output causes the counter to stop
counting. If the TXiINOUT pin is outputting an “H” level in this instance, the output level goes to “L”, and
the timer Xi interrupt request bit goes to “1”. If the TXiINOUT pin is outputting an “L” level in this
instance, the level does not change, and the timer Xi interrupt request bit does not becomes “1”.
Timer X (pulse period/pulse width measurement mode)
(1) If changing the measurement mode select bit is set after a count is started, the timer Xi interrupt
request bit goes to “1”.
(2) When the first effective edge is input after a count is started, an indeterminate value is transferred to
the reload register. At this time, timer Xi interrupt request is not generated.
A-D Converter
(1) Write to each bit (except bit 6) of A-D control register 0, to each bit of A-D control register 1, and to bit
0 of A-D control register 2 when A-D conversion is stopped (before a trigger occurs).
In particular, when the Vref connection bit is changed from “0” to “1”, start A-D conversion after an
elapse of 1 ms or longer.
(2) When changing A-D operation mode, select analog input pin again.
(3) Using one-shot mode or single sweep mode
Read the correspondence A-D register after confirming A-D conversion is finished. (It is known by A-
D conversion interrupt request bit.)
(4) Using repeat mode, repeat sweep mode 0 or repeat sweep mode 1
Use the undivided main clock as the internal CPU clock.
Stop Mode and Wait Mode ____________
(1) When returning from stop mode by hardware reset, RESET pin must be set to “L” level until main clock
oscillation is stabilized.
(2) When shifting to WAIT mode or STOP mode, the program stops after reading 8 bytes from the WAIT
instruction and the instruction that sets all clock stop bits to “1” in the instruction queue. Therefore,
insert a minimum of 8 NOPs after the WAIT instruction and the instruction that sets all clock stop bits
to “1”.
110
Under
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Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Usage precaution
Interrupts
(1) Reading address 0000016
• When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and
interrupt request level) in the interrupt sequence.
The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”.
Reading address 0000016 by software sets enabled highest priority interrupt source request bit to
“0”.
Though the interrupt is generated, the interrupt routine may not be executed.
Do not read address 0000016 by software.
(2) Setting the stack pointer
• The value of the stack pointer immediately after reset is initialized to 000016. Accepting an inter-
rupt before setting a value in the stack pointer may become a factor of runaway. Be sure to set a
value in the stack pointer before accepting an interrupt.
Concerning the first instruction immediately after reset, generating any interrupt is prohibited.
(3) External interrupt ________ ________
• When changing a polarity of pins INT0 and INT1, the interrupt request bit may become "1". Clear
the interrupt request bit after changing the polarity.
(4) Changing interrupt control register
See "Changing Interrupt Control Register".
111
Electrical characteristics (Vcc = 5V)
Under
development
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.37. Absolute maximum ratings
Note 1: When writing to frash MCU, CNVss is –0.3 to 13 (V) . Note 3: Extended operating temperature version: -40 to 85 C.
Note 2: Flat package (56P6S-A) is 300 mW. Note 4: Extended operating temperature version: -65 to 150 C.
P70, P71, VREF, XIN
RESET, CNVss,
VO
- 0.3 to Vcc + 0.3
(Note 1)
- 0.3 to Vcc + 0.3
PdTa = 25 °C
- 0.3 to 7
- 0.3 to 7 V
V
V
°C
VI
AVcc
Vcc
Tstg
Topr
°C
mW
V
- 40 to 150 (Note 4)
1000 (Note 2)
- 20 to 85 (Note 3)
P40 to P45, P50 to P54, P60 to P67,
P00 to P07, P10 to P17, P30 to P35,
P70, P71, VREF, XIN
P50 to P54, P60 to P67,
P00 to P07, P10 to P17, P30 to P35, P40 to P45,
Parameter UnitRated valueConditionSymbol
Operating ambient temperature
Input voltage
Analog supply voltage
Supply voltage
Output voltage
Power dissipation
Storage temperature
Electrical characteristics
112
Electrical characteristics (Vcc = 5V)
Under
development
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 5V
2.7 5.5
Vcc 5.0
Vcc
AVcc V
V0
0
Vss
AVss
0.8Vcc
V
V
V
Vcc
0.2Vcc
0
- 5.0
- 10.0
10.0
5.0
f
(X
IN
)MHz
I
OL (peak)
mA
10
f
(Xc
IN
) kHz
5032.768
V
V
cc
=4.0V to 5.5V
With wait
5 x V
CC
MHz
P5
0
to P5
4,
P6
0
to P6
7
, P7
0
, P7
1
, X
IN
, RESET, CNV
SS
,
V
IH
V
IL
I
OH (avg)
I
OH (peak)
I
OL (peak)
P1
0
to P1
7
I
OL (avg)
mA
mA
mA
mA
30.0
P0
0
to P0
7
, P1
0
to P1
7,
P3
0
to P3
5
, P4
0
to P4
5
,
P5
0
to P5
4,
P6
0
to P6
7,
P7
0,
P7
1,
X
IN,
RESET, CNV
SS
P0
0
to P0
7
, P1
0
to P1
7,
P3
0
to P3
5
, P4
0
to P4
5
,
P5
0
to P5
4,
P6
0
to P6
7
, P7
0
, P7
1
P0
0
to P0
7
, P1
0
to P1
7,
P3
0
to P3
5
, P4
0
to P4
5
,
P5
0
to P5
4,
P6
0
to P6
7
, P7
0
, P7
1
P0
0
to P0
7
,
P3
0
to P3
5
, P4
0
to P4
5
,
P5
0
to P5
4,
P6
0
to P6
7
, P7
0
, P7
1
P0
0
to P0
7
, P1
0
to P1
7,
P3
0
to P3
5
, P4
0
to P4
5
,
P5
0
to P5
4,
P6
0
to P6
7
, P7
0
, P7
1
P0
0
to P0
7
,
P3
0
to P3
5
, P4
0
to P4
5
,
I
OL (avg)
P1
0
to P1
7
15.0 mA
10.0
HIGHPOWER
LOWPOWER
HIGHPOWER
LOWPOWER
5.0
0
0
V
cc
=2.7V to 4.0V - 10.000
MHz10
V
cc
=4.0V to 5.5V 2.31 x V
CC
MHz
0
0
V
cc
=2.7V to 4.0V +0.760
Without
wait
Typ. Max. UnitParameterSymbol Min Standard
Supply voltage (Note 2)
Analog supply voltage
Analog supply voltage
Supply voltage
LOW input voltage
HIGH input voltage
HIGH average output
current
HIGH peak output
current
LOW peak output
current
Main clock input
oscillation
frequency
LOW average output
current
Subclock oscillation frequency
LOW peak output
current
LOW average output
current
Mask ROM version
Flash memory version
4.0 5.55.0
Mask ROM version
Flash memory version MHz10
V
cc
=4.0V to 5.5V 0
Mask ROM version
Flash memory version MHz10
V
cc
=4.0V to 5.5V 0
Note 1:
Unless otherwise noted: V
CC
= 2.7V to 5.5V, Vss = 0V, Ta = – 20 to 85
o
C (Extended operating temperature version:– 40 to
85
o
C). Flash version: V
CC
= 4.0V to 5.5V, Vss = 0V, Ta = – 20 to 85
o
C (Extended operating temperature version:– 40 to 85
o
C.)
Note 2: Flash version: VCC = 4.0V to 5.5V
Note 3: The average output current is an average value measured over 100ms.
Note 4: Keep output current as follows:
The sum of port P3 and P4 IOL (peak) is under 40 mA. The sum of port P1 IOL (peak) is under 60 mA. The sum of port P1, P3
and P4 IOH (peak) is under 40 mA. The sum of port P0, P5, P6 and P7 IOL (peak) is under 80 mA. The sum of port P0, P5, P6
and P7 IOH (peak) is under 80 mA.
Table 1.38. Recommended operating conditions (Note 1)
AAA
AAA
AAA
5.54.02.7
0.0
3.5
10.0
Main clock input oscillation frequency
(Without wait)
Power supply voltage [V]
(
M
a
in
c
l
oc
k : n
o
d
ivi
s
i
o
n
)
Highest operation frequency [MHz]
5 x Vcc - 10.000MHz
AAA
AAA
AAA
5.54.02.7
0.0
10.0
Main clock input oscillation frequency
(With wait)
Power supply voltage [V]
(
M
a
in
c
l
oc
k : n
o
d
ivi
s
i
o
n
)
Highest operation frequency [MHz
]
7.0
2.31 x VCC + 0.760MHz
113
Electrical characteristics (Vcc = 5V)
Under
development
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.39. Electrical characteristics (Note1)
V
OH
V
OH
V
OL
V
4.7
V
2.0
3.0
I
OH
= - 5 mA
I
OH
= - 200 µA
I
OL
= 5 mA
P0
0
to P0
7
,P1
0
to P1
7
,P3
0
to P3
5
,
P4
0
to P4
5
,P5
0
to P5
4
,P6
0
to P6
7
,
P0
0
to P0
7
,P1
0
to P1
7
,P3
0
to P3
5
,
P4
0
to P4
5
,P5
0
to P5
4
,P6
0
to P6
7
,V
P0
0
to P0
7
,P3
0
to P3
5
,P4
0
to P4
5
P5
0
to P5
4
,P6
0
to P6
7
,P7
0
,P7
1
V
OL
I
OL
= 200 µA 0.45 V
V
OL
P1
0
to P1
7
I
OL
= 15mA V
2.0
I
OL
= 200 µA 0.3 V
V
OL
P1
0
to P1
7
P7
0
,P7
1
P7
0
,P7
1
P0
0
to P0
7
,P3
0
to P3
5
,P4
0
to P4
5
P5
0
to P5
4
,P6
0
to P6
7
,P7
0
,P7
1
I
IH
V
RAM
Icc
V
T+
-V
T-
V
T+
-V
T-
0.2 0.8 V
0.2 1.8 V
5.0 µA
µA
When clock is stopped 2.0 V
1.0
µA
mA
20.0
RESET
TA0
IN
,TX0
INOUT
,TX1
INOUT
,TX2
INOUT
TB0
IN
,TB1
IN
INT
0
,INT
1
,CLK
0
,KI
0
to KI
7
V
I
= 5V
V
I
= 0V -5.0
19.0 38.0
4.0
µA
90.0
P0
0
to P0
7
,P1
0
to P1
7
,P3
0
to P3
5
,
P4
0
to P4
5
,P5
0
to P5
4
,P6
0
to P6
7
P7
0
,P7
1
, RESET, CNVss
I
IL
P0
0
to P0
7
,P1
0
to P1
7
,P3
0
to P3
5
,
P4
0
to P4
5
,P5
0
to P5
4
,P6
0
to P6
7
,
V
OH
X
OUT
HIGHPOWER
LOWPOWER V
3.0
3.0
V
OL
X
OUT
HIGHPOWER
LOWPOWER V
2.0
2.0
I
OH
= 1 mA
I
OH
= 0.5 mA
I
OH
= - 1 mA
I
OH
= - 0.5 mA
HIGHPOWER
I
OL
= 5 mA 2.0
LOWPOWER
I
OL
= 200 µA 0.45
HIGHPOWER
LOWPOWER
kΩ167.050.030.0
Symbol Standard
Typ. UnitMeasuring condition Min. Max.
Parameter
HIGH output
voltage
LOW output
voltage
LOW output
voltage
LOW output
voltage
Hysteresis
Hysteresis
HIGH input
current
LOW input
current
RAM retention voltage
Power supply current
HIGH output
voltage
HIGH output
voltage
LOW output
voltage
LOW output
voltage
f(X
IN
)=10MHz
Square wave, no division
f(XCIN)=32kHz
Square wave
Ta=25 C when
clock is stopped
Ta=85 C when clock
is stopped
I/O pin
has no
load f(XCIN)=32kHz
With wait(Note2)
V
OH
X
COUT
HIGHPOWER
LOWPOWER V
3.0
1.6
No load
No load
HIGH output
voltage
V
OL
X
OUT
HIGHPOWER
LOWPOWER V
0
0
LOW output
voltage
V
I
= 0V
R
PULLUP
P0
0
to P0
7
,P1
0
to P1
7
,P3
0
to P3
5
,
P4
0
to P4
5
,P5
0
to P5
4
,P6
0
to P6
7
,P7
0
,P7
1
Pull-up
resistor
P7
0
,P7
1
, RESET, CNVss
MΩ1.0
R
XIN
X
IN
Feedback resistor
MΩ6.0
R
XCIN
X
CIN
Feedback resistor
µA
No load
No load
RxD
0
, RxD
1
Note 1: Unless otherwise noted: VCC = 5V, VSS = 0V at Ta = 25oC, f(XIN) = 10MHz)
Note 2: With one timer operated using fC32.
VCC = 5V
114
Electrical characteristics (Vcc = 5V)
Under
development
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.40. A-D conversion characteristics
VCC = 5V
–
–Bits
LSB
V
REF
=V
CC
±3
10
V
REF
=V
CC
= 5V
R
LADDER
t
CONV
kohm
µs
V
V
IA
V
REF
V
0
2
10
V
CC
V
REF
40
3.3 µs
2.8
t
CONV
t
SAMP
0.3 µs
V
REF
=V
CC
V
REF
=V
CC
= 5V LSB
±3
V
REF
= V
CC
= 5V ±2 LSB
Symbol Standard
Typ. Unit
Measuring condition Min. Max.
Parameter
Resolution
Absolute
accuracy
Ladder resistance
Conversion time(10bit)
Reference voltage
Analog input voltage
Conversion time(8bit)
Sampling time
Sample & hold function not available
Sample & hold function available(10bit)
Sample & hold function available(8bit)
115
Electrical characteristics (Vcc = 5V)
Under
development
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.42. Timer A input (counter input in event counter mode)
Table 1.43. Timer A input (gating input in timer mode)
Table 1.44. Timer A input (external trigger input in one-shot timer mode)
Table 1.45. Timer A input (external trigger input in pulse width modulation mode)
Table 1.46. Timer A input (up/down input in event counter mode)
Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = 25oC unless otherwise specified)
Table 1.41. External clock input
ns
t
r
ns
ns
ns
ns
t
c
t
w(H
)
t
w(L)
t
f
ParameterSymbol Standard Unit
Min. Max.
External clock input LOW pulse width
External clock input HIGH pulse width
External clock input cycle time
External clock fall time
External clock rise time 15
100
40
40 15
nst
w(TAL)
ns
ns
t
w(TAH)
t
c(TA)
ns
ns
ns
t
c(TA)
t
w(TAH)
t
w(TAL)
ns
ns
ns
t
c(TA)
t
w(TAH)
t
w(TAL)
ns
ns
t
w(TAH)
t
w(TAL)
ns
ns
ns
ns
ns
t
c(UP)
t
w(UPH)
t
w(UPL)
t
su(UP-T
IN
)
t
h(T
IN-
UP)
40
100
40
400
200
200
200
100
100
100
100
2000
1000
1000
400
400
TA0
IN
input LOW pulse width
TA0
IN
input HIGH pulse width
ParameterSymbol
TA0
IN
input cycle time
Standard Unit
Min. Max.
Symbol
Symbol
Symbol
Symbol
Parameter
Parameter
Parameter
Parameter
Standard Unit
Min. Max.
Standard Unit
Min. Max.
Standard Unit
Min. Max.
Standard Unit
Min. Max.
TA0
IN
input LOW pulse width
TA0
IN
input HIGH pulse width
TA0
IN
input cycle time
TA0
IN
input LOW pulse width
TA0
IN
input HIGH pulse width
TA0
IN
input cycle time
TA0
IN
input LOW pulse width
TA0
IN
input HIGH pulse width
TA0
OUT
input LOW pulse width
TA0
OUT
input HIGH pulse width
TA0
OUT
input cycle time
TA0
OUT
input hold time
TA0
OUT
input setup time
VCC = 5V
116
Electrical characteristics (Vcc = 5V)
Under
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
ns
ns
ns
t
c(TB)
t
w(TBH)
t
w(TBL)
t
c(TB)
t
w(TBL)
t
w(TBH)
ns
ns
ns
ns
ns
t
c(TB)
t
w(TBH)
t
w(TBL)
ns
ns
ns
t
c(TB)
t
w(TBL)
ns
t
w(TBH)
ns
ns
t
c(TX)
t
w(TXH)
t
w(TXL)
ns
ns
ns
t
c(TX)
t
w(TXL)
ns
t
w(TXH)
ns
ns
t
c(TX)
t
w(TXL)
ns
t
w(TXH)
ParameterSymbol Standard Unit
Min. Max.
ParameterSymbol Standard Unit
Min. Max.
ParameterSymbol Standard Unit
Min. Max.
ParameterSymbol Standard Unit
Min. Max.
ParameterSymbol Standard Unit
Min. Max.
ParameterSymbol Standard Unit
Min. Max.
TXi
INOUT
input LOW pulse width
TXi
INOUT
input HIGH pulse width
TXi
INOUT
input cycle time
TXi
INOUT
input LOW pulse width
TXi
INOUT
input HIGH pulse width
TXi
INOUT
input cycle time
TXi
INOUT
input LOW pulse width
TXi
INOUT
input HIGH pulse width
TXi
INOUT
input cycle time
TBi
IN
input LOW pulse width
TBi
IN
input HIGH pulse width
TBi
IN
input cycle time
TBi
IN
input LOW pulse width
TBi
IN
input HIGH pulse width
TBi
IN
input cycle time
TBi
IN
input LOW pulse width (counted on both edges)
TBi
IN
input HIGH pulse width (counted on both edges)
TBi
IN
input cycle time (counted on both edges)
TBi
IN
input LOW pulse width (counted on one edge)
TBi
IN
input HIGH pulse width (counted on one edge)
TBi
IN
input cycle time (counted on one edge) 100
40
40
80
80
200
400
200
200
400
200
200
100
40
40
400
200
200
200
100
100
Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = 25oC unless otherwise specified)
Table 1.47. Timer B input (counter input in event counter mode)
Table 1.48. Timer B input (pulse period measurement mode)
Table 1.49. Timer B input (pulse width measurement mode)
Table 1.50. Timer X input (counter input in event counter mode)
Table 1.51. Timer X input (gate input in timer mode)
Table 1.52. Timer X input (external trigger input in one-shot timer mode)
VCC = 5V
117
Electrical characteristics (Vcc = 5V)
Under
development
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.53. Timer X input (pulse period measurement mode)
Table 1.54. Timer X input (pulse width measurement mode)
Table 1.55. Serial I/O
ns
ns
t
c(TX)
t
w(TXH)
t
w(TXL)
ns
ns
ns
t
c(TX)
t
w(TXL)
ns
t
w(TXH)
ns
ns
t
w(INH)
t
w(INL)
ns
ns
ns
ns
ns
ns
ns
t
c(CK)
t
w(CKH)
t
w(CKL)
t
d(C-Q)
t
su(D-C)
t
h(C-Q)
t
h(C-D)
ParameterSymbol Standard Unit
Min. Max.
ParameterSymbol Standard Unit
Min. Max.
ParameterSymbol Standard Unit
Min. Max.
ParameterSymbol Standard Unit
Min. Max.
TXi
INOUT
input LOW pulse width
TXi
INOUT
input HIGH pulse width
TXi
INOUT
input cycle time
TXi
INOUT
input LOW pulse width
TXi
INOUT
input HIGH pulse width
TXi
INOUT
input cycle time
CLK0 input cycle time
CLK0 input HIGH pulse width
CLK0 input LOW pulse width
TxDi hold time
RxDi input setup time
TxDi output delay time
RxDi input hold time
INTi input LOW pulse width
INTi input HIGH pulse width
400
200
200
400
200
200
250
250
200
100
100
0
30
90
80
_______
Table 1.56. External interrupt INTi inputs
VCC = 5V
Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = 25oC unless otherwise specified)
118
Electrical characteristics (Vcc = 5V)
Under
development
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
t
su(D–C)
TA0
IN
input
TA0
OUT
input
During event counter mode
TBi
IN
input
CLK0
TxDi
RxDi
t
c(TA)
t
w(TAH)
t
w(TAL)
t
c(UP)
t
w(UPH)
t
w(UPL)
t
c(TB)
t
w(TBH)
t
w(TBL)
t
c(CK)
t
w(CKH)
t
w(CKL)
t
w(INL)
t
w(INH)
t
d(C–Q)
t
h(C–D)
t
h(C–Q)
t
h(T
IN
–UP)
t
su(UP–T
IN
)
TA0
IN
input
(When count on falling
edge is selected)
TA0
IN
input
(When count on rising
edge is selected)
TA0
OUT
input
(Up/down input)
INTi input
TXi
INOUT
input
t
c(TX)
t
w(TXH)
t
w(TXL)
VCC = 5V
119
Electrical characteristics (Vcc = 3V)
Under
development
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.57. Electrical characteristics (Note 1)
V
OH
V
OL
V
V
0.5
2.5
I
OH
= - 1mA
I
OL
= 1 mA
P0
0
to P0
7
,P1
0
to P1
7
,P3
0
to P3
5
,
P4
0
to P4
5
,P5
0
to P5
4
,P6
0
to P6
7
,
P0
0
to P0
7
,P3
0
to P3
5
,P4
0
to P4
5
P5
0
to P5
4
,P6
0
to P6
7
,P7
0
,P7
1
V
OL
P1
0
to P1
7
I
OL
= 3 mA V
0.5
P7
0
,P7
1
I
IH
V
RAM
Icc
V
T+
-V
T-
V
T+
-V
T-
0.2 0.8 V
0.2 1.8 V
4.0 µA
µA
When clock is stopped 2.0 V
1.0
µA
mA
20.0
RESET
V
I
= 3V
V
I
= 0V -4.0
6.0 15.0
2.8 µA
40.0
P0
0
to P0
7
,P1
0
to P1
7
,P3
0
to P3
5
,
P4
0
to P4
5
,P5
0
to P5
4
,P6
0
to P6
7
,
P7
0
,P7
1
, RESET, CNVss
I
IL
P0
0
to P0
7
,P1
0
to P1
7
,P3
0
to P3
5
,
P4
0
to P4
5
,P5
0
to P5
4
,P6
0
to P6
7
,
V
OH
X
OUT
HIGHPOWER
LOWPOWER V
2.5
2.5
V
OL
X
OUT
HIGHPOWER
LOWPOWER V
0.5
0.5
I
OH
= 0.1 mA
I
OH
= 50 µA
I
OH
= - 1 mA
I
OH
= - 50 µA
HIGHPOWER
I
OL
= 1 mA 0.5
LOWPOWER
kΩ500.0120.066.0
Symbol Standard
Typ. UnitMeasuring condition Min. Max.
Parameter
HIGH output
voltage
LOW output
voltage
LOW output
voltage
Hysteresis
Hysteresis
HIGH input
current
LOW input
current
RAM retention voltage
Power supply current
HIGH output
voltage
LOW output
voltage
f(X
IN
)=7MHz
Square wave, no division
f(X
CIN
)=32kHz
With wait.
Oscillation capacity HIGH (Note 2)
Ta=25 C when
clock is stopped
Ta=85 C when clock
is stopped
I/O pin
has no
load f(X
CIN
)=32kHz
With wait.
Oscillation capacity LOW (Note 2)
V
OH
X
COUT
HIGHPOWER
LOWPOWER V
3.0
1.6
No load
No load
HIGH output
voltage
V
OL
X
OUT
HIGHPOWER
LOWPOWER V
0
0
LOW output
voltage
V
I
= 0V
R
PULLUP
P0
0
to P0
7
,P1
0
to P1
7
,P3
0
to P3
5
,
P4
0
to P4
5
,P5
0
to P5
4
,P6
0
to P6
7
,P7
0
,P7
1
Pull-up
resistor
P7
0
,P7
1
, RESET, CNVss
MΩ3.0
R
XIN
X
IN
Feedback resistor
MΩ10.0
R
XIN
X
IN
Feedback resistor
µA
No load
No load
f(X
CIN
)=32kHz
Square wave
0.9
µA
TA0
IN
,TX0
INOUT
,TX1
INOUT
,TX2
INOUT
TB0
IN
,TB1
IN
INT
0
,INT
1
,CLK
0
,KI
0
to KI
7
RxD
0
, RxD
1
Note 1: Unless otherwise noted: VCC = 3V, VSS = 0V at Ta = 25oC, f(XIN) = 7MHz, with wait)
Note 2: With one timer operated using fC32.
VCC = 3V
120
Electrical characteristics (Vcc = 3V)
Under
development
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.58. A-D conversion characteristics
VCC = 3V
–
–Bits
LSB
V
REF
=V
CC
±2
10
VREF =VCC = 3V,
ØAD = fAD/2
R
LADDER
kohm
V
V
IA
V
REF
V
0
2.7
10
V
CC
V
REF
40 µs
14.0
t
CONV
VREF =VCC
Symbol Standard
Typ. Unit
Measuring condition Min. Max.
Parameter
Resolution
Absolute
accuracy
Ladder resistance
Reference voltage
Analog input voltage
Conversion time(8bit)
Sample & hold function not available
(8bit)
VCC = 3V
121
Electrical characteristics (Vcc = 3V)
Under
development
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.60. Timer A input (counter input in event counter mode)
Table 1.61. Timer A input (gating input in timer mode)
Table 1.62. Timer A input (external trigger input in one-shot timer mode)
Table 1.63. Timer A input (external trigger input in pulse width modulation mode)
Table 1.64. Timer A input (up/down input in event counter mode)
Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = 25oC unless otherwise specified)
Table 1.59. External clock input
ns
t
r
ns
ns
ns
ns
t
c
t
w(H
)
t
w(L)
t
f
ParameterSymbol Standard Unit
Min. Max.
External clock input LOW pulse width
External clock input HIGH pulse width
External clock input cycle time
External clock fall time
External clock rise time 18
143
60
60 18
VCC = 3V
nst
w(TAL)
ns
ns
t
w(TAH)
t
c(TA)
ns
ns
ns
t
c(TA)
t
w(TAH)
t
w(TAL)
ns
ns
ns
t
c(TA)
t
w(TAH)
t
w(TAL)
ns
ns
t
w(TAH)
t
w(TAL)
ns
ns
ns
ns
ns
t
c(UP)
t
w(UPH)
t
w(UPL)
t
su(UP-T
IN
)
t
h(T
IN-
UP)
60
150
60
600
300
300
300
150
150
150
150
3000
1500
1500
600
600
TA0
IN
input LOW pulse width
TA0
IN
input HIGH pulse width
ParameterSymbol
TA0
IN
input cycle time
Standard Unit
Min. Max.
Symbol
Symbol
Symbol
Symbol
Parameter
Parameter
Parameter
Parameter
Standard Unit
Min. Max.
Standard Unit
Min. Max.
Standard Unit
Min. Max.
Standard Unit
Min. Max.
TA0
IN
input LOW pulse width
TA0
IN
input HIGH pulse width
TA0
IN
input cycle time
TA0
IN
input LOW pulse width
TA0
IN
input HIGH pulse width
TA0
IN
input cycle time
TA0
IN
input LOW pulse width
TA0
IN
input HIGH pulse width
TA0
OUT
input LOW pulse width
TA0
OUT
input HIGH pulse width
TA0
OUT
input cycle time
TA0
OUT
in
p
ut hold time
TA0
OUT
input setup time
122
Electrical characteristics (Vcc = 3V)
Under
development
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
ns
ns
ns
t
c(TB)
t
w(TBH)
t
w(TBL)
t
c(TB)
t
w(TBL)
t
w(TBH)
ns
ns
ns
ns
ns
t
c(TB)
t
w(TBH)
t
w(TBL)
ns
ns
ns
t
c(TB)
t
w(TBL)
ns
t
w(TBH)
ns
ns
t
c(TX)
t
w(TXH)
t
w(TXL)
ns
ns
ns
t
c(TX)
t
w(TXL)
ns
t
w(TXH)
ns
ns
t
c(TX)
t
w(TXL)
ns
t
w(TXH)
ParameterSymbol Standard Unit
Min. Max.
ParameterSymbol Standard Unit
Min. Max.
ParameterSymbol Standard Unit
Min. Max.
ParameterSymbol Standard Unit
Min. Max.
ParameterSymbol Standard Unit
Min. Max.
ParameterSymbol Standard Unit
Min. Max.
TXi
INOUT
input LOW pulse width
TXi
INOUT
input HIGH pulse width
TXi
INOUT
input cycle time
TXi
INOUT
input LOW pulse width
TXi
INOUT
input HIGH pulse width
TXi
INOUT
input cycle time
TXi
INOUT
input LOW pulse width
TXi
INOUT
input HIGH pulse width
TXi
INOUT
input cycle time
TBi
IN
input LOW pulse width
TBi
IN
input HIGH pulse width
TBi
IN
input cycle time
TBi
IN
input LOW pulse width
TBi
IN
input HIGH pulse width
TBi
IN
input cycle time
TBi
IN
input LOW pulse width (counted on both edges)
TBi
IN
input HIGH pulse width (counted on both edges)
TBi
IN
input cycle time (counted on both edges)
TBi
IN
input LOW pulse width (counted on one edge)
TBi
IN
input HIGH pulse width (counted on one edge)
TBi
IN
input cycle time (counted on one edge) 150
60
60
160
160
300
600
300
300
600
300
300
150
60
60
600
300
300
300
150
150
Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = 25oC unless otherwise specified)
Table 1.65. Timer B input (counter input in event counter mode)
Table 1.66. Timer B input (pulse period measurement mode)
Table 1.67. Timer B input (pulse width measurement mode)
Table 1.68. Timer X input (counter input in event counter mode)
Table 1.69. Timer X input (gate input in timer mode)
Table 1.70. Timer X input (external trigger input in one-shot timer mode)
VCC = 3V
123
Electrical characteristics (Vcc = 3V)
Under
development
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = 25oC unless otherwise specified)
Table 1.71. Timer X input (pulse period measurement mode)
Table 1.72. Timer X input (pulse width measurement mode)
Table 1.73. Serial I/O
ns
ns
t
c(TX)
t
w(TXH)
t
w(TXL)
ns
ns
ns
t
c(TX)
t
w(TXL)
ns
t
w(TXH)
ns
ns
t
w(INH)
t
w(INL)
ns
ns
ns
ns
ns
ns
ns
t
c(CK)
t
w(CKH)
t
w(CKL)
t
d(C-Q)
t
su(D-C)
t
h(C-Q)
t
h(C-D)
ParameterSymbol Standard Unit
Min. Max.
ParameterSymbol Standard Unit
Min. Max.
ParameterSymbol Standard Unit
Min. Max.
ParameterSymbol Standard Unit
Min. Max.
TXi
INOUT
input LOW pulse width
TXi
INOUT
input HIGH pulse width
TXi
INOUT
input cycle time
TXi
INOUT
input LOW pulse width
TXi
INOUT
input HIGH pulse width
TXi
INOUT
input cycle time
CLK0 input cycle time
CLK0 input HIGH pulse width
CLK0 input LOW pulse width
TxDi hold time
RxDi input setup time
TxDi output delay time
RxDi input hold time
INTi input LOW pulse width
INTi input HIGH pulse width
600
300
300
600
300
300
380
380
300
150
150
0
50
90
160
VCC = 3V
_______
Table 1.74. External interrupt INTi inputs
124
Electrical characteristics (Vcc = 3V)
Under
development
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
t
su(D–C)
TA0
IN
input
TA0
OUT
input
During event counter mode
TBi
IN
input
CLK0
TxDi
RxDi
t
c(TA)
t
w(TAH)
t
w(TAL)
t
c(UP)
t
w(UPH)
t
w(UPL)
t
c(TB)
t
w(TBH)
t
w(TBL)
t
c(CK)
t
w(CKH)
t
w(CKL)
t
w(INL)
t
w(INH)
t
d(C–Q)
t
h(C–D)
t
h(C–Q)
t
h(T
IN
–UP)
t
su(UP–T
IN
)
TA0
IN
input
(When count on falling
edge is selected)
TA0
IN
input
(When count on rising
edge is selected)
TA0
OUT
input
(Up/down input)
INTi input
TXi
INOUT
input
t
c(TX)
t
w(TXH)
t
w(TXL)
VCC = 3V
125
Under
development
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Preliminary
Item
Power supply voltage
Program/erase voltage
Flash memory operation mode
Erase block
division
Program method
Erase method
Program/erase control method
Number of commands
Program/erase count
ROM code protect
Performance
4.0V to 5.5 V (f(X
IN
)=10MHz)
V
PP
=12V ± 5% (f(X
IN
)=10MHz)
Three modes (parallel I/O, standard serial I/O, CPU
rewrite)
See Figure 1.AA.3.
One division (4 Kbytes) (Note 1)
In units of byte
Collective erase
Program/erase control by software command
6 commands
100 times
Parallel I/O mode is supported.
Note: The boot ROM area contains a standard serial I/O mode control program which is stored in it
when shipped from the factory. This area can be erased and programmed in only parallel I/O
mode.
User ROM area
Boot ROM area
V
CC
=5V ± 5% (f(X
IN
)=10MHz)
Table AA-1. Outline Performance of the M30201 (flash memory version)
Outline Performance
Table AA-1 shows the outline performance of the M30201 (flash memory version).
126
Description
Under
development
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Preliminary
Flash Memory
The M30201 (flash memory version) contains the NOR type of flash memory that requires a high-voltage
VPP power supply for program/erase operations, in addition to the VCC power supply for device operation.
For this flash memory, three flash memory modes are available in which to read, program, and erase:
parallel I/O and standard serial I/O modes in which the flash memory can be manipulated using a program-
mer and a CPU rewrite mode in which the flash memory can be manipulated by the Central Processing Unit
(CPU). Each mode is detailed in the pages to follow.
In addition to the ordinary user ROM area to store a microcomputer operation control program, the flash
memory has a boot ROM area that is used to store a program to control rewriting in CPU rewrite and
standard serial I/O modes. This boot ROM area has had a standard serial I/O mode control program stored
in it when shipped from the factory. However, the user can write a rewrite control program in this area that
suits the user’s application system. This boot ROM area can be rewritten in only parallel I/O mode.
Figure AA-3. Block diagram of flash memory version
SFR
RAM
SFR
RAM
SFR
RAM
00000
16
00400
16
YYYYY
16
DF000
16
DFDFF
16
XXXXX
16
FFFFF
16
M30201F6
XXXXX
16
F4000
16
YYYYY
16
00BFF
16
Microcomputer mode Parallel I/O mode CPU rewrite mode
Standard serial I/O mode
Boot ROM
area
(3.5K bytes)
Boot ROM
area
(3.5K bytes)
User ROM
area User ROM
area
User ROM
area
Collective
erasable/
programmable
area
Type No.
Note 1: In CPU rewrite and standard serial I/O modes, the user ROM is the only erasable/programmable area.
Note 2: In parallel I/O mode, the area to be erased/programmed can be selected by the address A17 input.
The user ROM area is selected when this address input is high and the boot ROM area is selected
when this address input is low.
Collective
erasable/
programmable
area
Collective
erasable/
programmable
area
127
Under
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode
Preliminary
CPU Rewrite Mode
In CPU rewrite mode, the on-chip flash memory can be operated on (read, program, or erase) under control
of the Central Processing Unit (CPU). In CPU rewrite mode, the flash memory can be operated on by
reading or writing to the flash memory control register and flash command register. Figure BB-1, Figure BB-
2 show the flash memory control register, and flash command register respectively.
Also, in CPU rewrite mode, the CNVSS pin is used as the V PP power supply pin. Apply the power supply
voltage, VPPH, from an external source to this pin.
In CPU rewrite mode, only the user ROM area shown in Figure AA-3 can be rewritten; the boot ROM area
cannot be rewritten. Make sure the program and block commands are issued for only the user ROM area.
The control program for CPU rewrite mode can be stored in either user ROM or boot ROM area. In the CPU
rewrite mode, because the flash memory cannot be read from the CPU, the rewrite control program must
be transferred to internal RAM before it can be executed.
Flash memory control register 0
Symbol Address When reset
FCON0 03B4
16
00100000
2
WR
b7 b6 b5 b4 b3 b2 b1 b0
CPU rewrite mode
select bit
FCON00
Bit symbol
Bit name Function
RW
0: CPU rewrite mode is invalid
1: CPU rewrite mode is valid
This bit can not write. The value, if
read, turns out to be indeterminate.
Reserved bit
CPU rewrite mode
monitor flag 0: CPU rewrite mode is invalid
1: CPU rewrite mode is valid
Must always be set to "0".
Nothing is assigned. In an attempt to write this bit, write "0". The value,
if read, turns out to be "0".
FCON02
0
A
A
A
A
A
A
Reserved bit
01
Must always be set to "1".
Reserved bit
0
A
A
Must always be set to "0".
Reserved bit
Flash memory control register 1
Symbol Address When reset
FCON1 03B5
16
XXXXXX00
2
WR
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
Bit name Function
RW
0
A
0
Reserved bit
A
Nothing is assigned. In an attempt to write these bits, write "0". The
value, if read, turns out to be indeterminate.
Must always be set to "0".
A
Flash command register
Symbol Address When reset
FCMD 03B616 0016
WR
b7 b6 b5 b4 b3 b2 b1 b0
Writing of software command
<Software command name> <Command code>
•Read command "0016"
•Program command "4016"
•Program verify command "C016"
•Erase command "2016"+"2016"
•Erase verify command "A016"
•Reset command "FF16"+"FF6"
Function RW
A
Figure BB-1. Flash memory control register
Figure BB-2. Flash command register
128
Under
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode
Preliminary
Microcomputer Mode and Boot Mode
The control program for CPU rewrite mode must be written into the user ROM or boot ROM area in
parallel I/O mode beforehand. (If the control program is written into the boot ROM area, the standard
serial I/O mode becomes unusable.)
See Figure AA-3 for details about the boot ROM area.
Normal microcomputer mode is entered when the microcomputer is reset with pulling CNV SS pin low
(VSS). In this case, the CPU starts operating using the control program in the user ROM area.
When the microcomputer is reset by pulling the P52 pin high (VCC), the CNVSS pin high(VPPH), the CPU
starts operating using the control program in the boot ROM area. This mode is called the “boot” mode.
The control program in the boot ROM area can also be used to rewrite the user ROM area.
CPU rewrite mode operation procedure
The internal flash memory can be operated on to program, read, verify, or erase it while being placed on-
board by writing commands from the CPU to the flash memory control register (addresses 03B4 16,
03B516) and flash command register (address 03B616). Note that when in CPU rewrite mode, the boot
ROM area cannot be accessed for program, read, verify, or erase operations. Before this can be accom-
plished, a CPU write control program must be written into the boot ROM area in parallel input/output
mode. The following shows a CPU rewrite mode operation procedure.
<Start procedure (Note 1)>
(1) Apply VPPH to the CNVSS/VPP pin and VCC to the port P52 pin for reset release. Or the user can
jump from the user ROM area to the boot ROM area using the JMP instruction and execute the CPU
write control program. In this case, set the CPU write mode select bit of the flash memory control
register to “1” before applying VPPH to the CNVSS/VPP pin.
(2) After transferring the CPU write control program from the boot ROM area to the internal RAM, jump
to this control program in RAM. (The operations described below are controlled by this program.)
(3) Set the CPU rewrite mode select bit to “1”.
(4) Read the CPU rewrite mode monitor flag to see that the CPU rewrite mode is enabled.
(5) Execute operation on the flash memory by writing software commands to the flash command regis-
ter.
Note 1: In addition to the above, various other operations need to be performed, such as for entering the
data to be written to flash memory from an external source (e.g., serial I/O), initializing the ports, and
writing to the watchdog timer.
<Clearing procedure>
(1) Apply VSS to the CNVSS/VPP pin.
(2) Set the CPU rewrite mode select bit to “0”.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode
Preliminary
Precautions on CPU Rewrite Mode
Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite
mode.
(1) Operation speed
During erase/program mode, set BCLK to one of the following frequencies by changing the divide
ratio:
5 MHz or less when wait bit (bit 7 at address 000516) = 0 (without internal access wait state)
10 MHz or less when wait bit (bit 7 at address 000516) = 1 (with internal access wait state)
(2) Instructions inhibited against use
The instructions listed below cannot be used during CPU rewrite mode because they refer to the
internal data of the flash memory:
UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction
(3) Interrupts inhibited against use
No interrupts can be used that look up the fixed vector table in the flash memory area. Maskable
interrupts may be used by setting the interrupt vector table in a location outside the flash memory
area.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode
Preliminary
Command
Program verify
Read
Program
03B6
16
First bus cycle Second bus cycle
00
16
40
16
C0
16
Write
Write
Write
Program
address
Write
Read
Erase verify A0
16
Write Verify
address Verify
data
Read
Erase 20
16
Write 03B6
16
20
16
Write
Verify
address
Reset FF
16
Write
Mode Address Mode Address Data
(D
0
to D
7
)
Data
(D
0
to D
7
)
03B6
16
03B6
16
03B6
16
03B6
16
03B6
16
Program
data
Verify
data
FF
16
Write 03B6
16
Software Commands
Table BB-1 lists the software commands available with the M30201 (flash memory version).
When CPU rewrite mode is enabled, write software commands to the flash command register to specify
the operation to erase or program.
The content of each software command is explained below.
Table BB-1. List of Software Commands (CPU Rewrite Mode)
Read Command (0016)
The read mode is entered by writing the command code “0016” to the flash command register in the
first bus cycle. When an address to be read is input in one of the bus cycles that follow, the content of
the specified address is read out at the data bus (D0–D7), 8 bits at a time.
The read mode is retained intact until another command is written.
After reset and after the reset command is executed, the read mode is set.
Program Command (4016)
The program mode is entered by writing the command code “4016” to the flash command register in
the first bus cycle. When the user execute an instruction to write byte data to the desired address (e.g.,
STE instruction) in the second bus cycle, the flash memory control circuit executes the program op-
eration. The program operation requires approximately 20 ms. Wait for 20 ms or more before the user
go to the next processing.
During program operation, the watchdog timer remains idle, with the value “7FFF16” set in it.
Note 1: The write operation is not completed immediately by writing a program command once. The
user must always execute a program-verify command after each program command executed. And if
verification fails, the user need to execute the program command repeatedly until the verification
passes. See Figure 1.BB.3 for an example of a programming flowchart.
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CPU Rewrite Mode
Preliminary
Program-verify command (C016)
The program-verify mode is entered by writing the command code “C016” to the flash command
register in the first bus cycle. When the user execute an instruction (e.g., LDE instruction) to read byte
data from the address to be verified (the previously programmed address) in the second bus cycle,
the content that has actually been written to the address is read out from the memory.
The CPU compares this read data with the data that it previously wrote to the address using the
program command. If the compared data do not match, the user need to execute the program and
program-verify operations one more time.
Erase command (2016 + 2016)
The flash memory control circuit executes an erase operation by writing command code “2016” to the
flash command register in the first bus cycle and the same command code to the flash command
register again in the second bus cycle. The erase operation requires approximately 20 ms. Wait for 20
ms or more before the user go to the next processing.
Before this erase command can be performed, all memory locations to be erased must have had data
“0016” written to by using the program and program-verify commands. During erase operation, the
watchdog timer remains idle, with the value “7FFF16 set in it.
Note 1: The erase operation is not completed immediately by writing an erase command once. The
user must always execute an erase-verify command after each erase command executed. And if
verification fails, the user need to execute the erase command repeatedly until the verification passes.
See Figure BB-3 for an example of an erase flowchart.
Erase-verify command (A016)
The erase-verify mode is entered by writing the command code “A016” to the flash command register
in the first bus cycle. When the user execute an instruction to read byte data from the address to be
verified (e.g., LDE instruction) in the second bus cycle, the content of the address is read out.
The CPU must sequentially erase-verify memory contents one address at a time, over the entire area
erased. If any address is encountered whose content is not “FF16” (not erased), the CPU must stop
erase-verify at that point and execute erase and erase-verify operations one more time.
Note 1: If any unerased memory location is encountered during erase-verify operation, be sure to
execute erase and erase-verify operations one more time. In this case, however, the user does not
need to write data “0016” to memory before erasing.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode
Preliminary
Start
Address = first location
Loop counter : X=0
Write program command Write : 40
16
Duration = 20 µs
Duration = 6 µs
X=25 ?
Verify
OK ?
PASS FAIL
FAIL
PASS
YES
PASS
NO
NO
FAIL
Write program data/
address
Loop counter : X=X+1
Write program verify
command
Last
address ?
Next address ?
Write read command Write read command
Verify
OK ?
Write : Program data
Write : C0
16
Write : 00
16
Write:20
16
Duration = 6µs
X=1000 ?
Verify
OK?
PASS FAIL
FAIL
PASS
YES
PASS
NO
NO
FAIL
Duration = 20ms
YES
NO
Start
All bytes =
"00
16
"?
Program all bytes =
"00
16
"
Address = First address
Loop counter X=0
Write erase command
Write erase command
Loop counter X=X+1
Write erase verify
command/address
Verify
OK?
Last
address?
Next address
Write read command Write read command
Write:20
16
Write:A0
16
Write:00
16
Read:
expect value=FF
16
Figure BB-3. Program and erase execution flowchart in the CPU rewrite mode
Program Erase
Reset command (FF16 + FF16)
The reset command is used to stop the program command or the erase command in the middle of
operation. After writing command code “4016” or “2016” twice to the flash command register, write
command code “FF16” to the flash command register in the first bus cycle and the same command
code to the flash command register again in the second bus cycle. The program command or erase
command is disabled, with the flash memory placed in read mode.
133
Appendix Parallel I/O Mode
Preliminary
Under
development
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pin name Signal name I/O Function
V
CC
,V
SS
Power supply input Apply 5 V ± 10 % to the Vcc pin and 0 V to the Vss pin.
CNV
SS
CNV
SS
Apply 12 V ± 5 % to the CNV
SS
pin.
I
RESET Reset input Connect this pin to V
SS
.
I
X
IN
Clock input Connect a ceramic or crystal resonator between the X
IN
and X
OUT
pins.
When entering an externally derived clock, enter it from X
IN
and leave
X
OUT
open.
I
X
OUT
Clock output O
AV
CC
, AV
SS
Analog power supply input
V
REF
Reference voltage input I
Connect AV
SS
to Vss and AVcc to Vcc, respectively.
Connect this pin to V
SS
.
P0
0
to P0
7
Data I/O D
0
to D
7
These are data D
0
–D
7
input/output pins.
These are address A
4
–A
7
input pins.
I
P3
0
to P3
3
P3
4
to P3
5
I
P4
1
This is a OE input pin.
I
P5
0
Address input A
17
P6
4
to P6
7
I/O
Address input A
4
to A
7
Input port P3
OE input
P4
2
, P4
4
, P4
5
Input port P4 IEnter high signals or low signals to these pins.
Input port P6 Enter high signals or low signals to these pins.
I
P7
0
to P7
1
Input port P7 I
CE input This is a CE input pin.
I
P4
3
Enter low signals to these pins.
P4
0
WE input This is a WE input pin.
I
IThis is address A
17
input pin.
P5
1
V
RFY
input IApply V
IH
(5 V) to this pin when V
PP
= V
PPH
(12 V), or V
IL
(0 V) when V
PP
= V
PPL
(5 V).
P5
2
I
Input port P5 Enter low signal to this pin.
P5
3
, P5
4
Input port P5 IEnter high signals or low signals to these pins.
These are address A
0
–A
3
input pins.
I
P6
0
to P6
3
Address input A
0
to A
3
Enter high signals or low signals to these pins.
P1
0
to P1
7
Address input A
8
to A
15
These are address A
8
–A
15
input pins.
I
Description of Pin Function (Flash Memory Parallel I/O Mode)
134
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Preliminary
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
M30201(flash memory version) M5M28F101
V
CC
V
SS
V
CC
V
SS
V
CC
V
SS
Address input
Data I/O
OE input
CE input
P6
0
to P6
3
, P3
0
to P3
3
,
P1
0
to P1
7
, P5
0
P0
0
to P0
7
P4
1
P4
3
A
0
to A
15
, A
17
D
0
to D
7
OE
CE
WE input
V
RFY
input (Note) P4
0
P5
1
WE
Note: The V
RFY
input only selects read-only or read/write mode, and does not have any pin
associated with it on the M5M28F101.
Parallel I/O Mode
The parallel I/O mode is entered by making connections shown in Figures CC-2 and CC-3 and then turning
the VPPH power supply on. In this mode, the M30201 (flash memory version) operates in a manner similar
to the NOR flash memory M5M28F101 from Mitsubishi. Note, however, that there are some differences
with regard to the functions not available with the microcomputer (function of read device identification
code) and matters related to memory capacity.
Table CC-2 shows pin relationship between the M30201 and M5M28F101 in parallel I/O mode.
Table CC-2. Pin relationship in parallel I/O mode
SFR
RAM
SFR
RAM
SFR
RAM
00000
16
00400
16
YYYYY
16
DF000
16
DFDFF
16
XXXXX
16
FFFFF
16
M30201F6
XXXXX
16
F4000
16
YYYYY
16
00BFF
16
Microcomputer mode Parallel I/O mode CPU rewrite mode
Standard serial I/O mode
Boot ROM
area
(3.5K bytes)
Boot ROM
area
(3.5K bytes)
User ROM
area User ROM
area
User ROM
area
Collective
erasable/
programmable
area
Type No.
Note 1: In CPU rewrite and standard serial I/O modes, the user ROM is the only erasable/programmable area.
Note 2: In parallel I/O mode, the area to be erased/programmed can be selected by the address A17 input.
The user ROM area is selected when this address input is high and the boot ROM area is selected
when this address input is low.
Collective
erasable/
programmable
area
Collective
erasable/
programmable
area
Figure CC-1. Block diagram of flash memory version
135
Appendix Parallel I/O Mode
Preliminary
Under
development
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M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
P6
3
/AN
3
P6
2
/AN
2
P6
1
/AN
1
P6
0
/AN
0
V
REF
X
IN
X
OUT
P5
0
/T
X
D
0
/AN
50
P6
7
/AN
7
P6
6
/AN
6
P6
5
/AN
5
P6
4
/AN
4
V
SS
RESET
V
CC
CNV
SS
P5
1
/R
X
D
0
/AN
51
P5
2
/CLK
0
/AN
52
AV
SS
P4
5
/TX2
INOUT
P7
0
/TB0
IN
/X
COUT
P7
1
/TB1
IN
/X
CIN
P5
4
/CK
OUT
/AN
54
P5
3
/CLKS/AN
53
AV
CC
P0
7
/KI
7
P0
6
/KI
6
P0
5
/KI
5
P0
4
/KI
4
P0
3
/KI
3
P0
2
/KI
2
P0
1
/KI
1
P1
0
(LED
0
)
P1
1
(LED
1
)
P1
2
(LED
2
)
P1
3
(LED
3
)
P1
4
(LED
4
)
P1
5
(LED
5
)
P1
6
(LED
6
)
P1
7
(LED
7
)
M30201F6SP
M30201F6TSP
P0
0
/KI
0
P3
0
P3
1
P3
2
P3
3
P3
4
P3
5
P4
0
/TA0
IN
/T
X
D
1
P4
1
/TA0
OUT
P4
2
/R
X
D
1
P4
4
/INT
1
/TX1
INOUT
P4
3
/INT
0
/TX0
INOUT
CE
OE
WE
D0
A1
A3 A2
D1
D2 D3
D4 D5
D6 D7
A8 A9
A10 A11
A13
A14 A15
A4 A5
A12
A6
A0
A17
V
SS
V
CC
A7
V
PPH
Connect oscillator circuit.
V
RFY
Figure CC-2. Pin connection diagram in parallel I/O mode (1)
136
Appendix Parallel I/O Mode
Preliminary
Under
development
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M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Figure CC-3. Pin connection diagram in parallel I/O mode (2)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
56
55
54
53
27
28
X
IN
X
OUT
P5
0
/T
X
D
0
/AN
50
P6
7
/AN
7
V
SS
RESET
V
CC
CNV
SS
P5
1
/R
X
D
0
/AN
51
P5
2
/CLK
0
/AN
52
P4
5
/TX2
INOUT
P7
1
/TB1
IN
/X
CIN
P7
0
/TB0
IN
/X
COUT
P4
1
/TA0
OUT
P4
0
/TA0
IN
/T
X
D
1
P4
2
/R
X
D
1
P5
4
/CK
OUT
/AN
54
P5
3
/CLKS/AN
53
V
REF
P6
0
/AN
0
P6
1
/AN
1
AV
SS
AV
CC
P1
0
(LED
0
)
P1
4
(LED
4
)
M30201F6FP
M30201F6TFP
N.C.
N.C.
N.C.
N.C.
P0
0
/KI
0
P6
2
/AN
2
P6
3
/AN
3
P6
4
/AN
4
P6
5
/AN
5
P6
6
/AN
6
P0
1
/KI
1
P0
2
/KI
2
P0
3
/KI
3
P0
4
/KI
4
P0
5
/KI
5
P0
6
/KI
6
P0
7
/KI
7
P1
1
(LED
1
)
P1
2
(LED
2
)
P1
3
(LED
3
)
P1
5
(LED
5
)
P1
6
(LED
6
)
P1
7
(LED
7
)
P3
0
P3
1
P3
2
P3
3
P3
4
P3
5
P4
4
/INT
1
/TX1
INOUT
P4
3
/INT
0
/TX0
INOUT
A17 D0 D1
D2 D3
D4 D5
D6 D7
A8 A9
A10 A11
A12
A13
A15 A14
A4
A6
A5
A7
V
SS
VCC
CE
OE WE
VRFY
VPPH
Connect oscillator
circuit.
A0
A1 A2
A3
137
Appendix Parallel I/O Mode
Preliminary
Under
development
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Read
only
Read/
Write
Read
Write
Output disabled
Stand by
Read
Output disabled
Stand by
Data output
Hi-Z
Data output
Hi-Z
Data input
V
IL
V
IL
V
IH
V
IL
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IH
V
IH
V
IL
V
IL
V
IL
V
IH
V
IH
V
IH
V
IH
V
IH
Mode Pin name CE OE WE V
RFY
D
0
to D
7
Note: X can be V
IL
or V
IH
.
V
PPH
V
PP
V
PPH
V
PPH
V
PPH
V
PPH
V
PPH
V
PPH
XX
XX Hi-Z
Hi-Z
V
IL
V
IH
V
IL
V
IH
User ROM and Boot ROM Areas
In parallel I/O mode, the user ROM and boot ROM areas shown in Figure CC-1 can be rewritten.
In the boot ROM area, an erase block operation is applied to only one 4 K byte block. The boot ROM area
has had a standard serial I/O mode control program stored in it when shipped from the Mitsubishi factory.
Therefore, using the device in standard serial input/output mode, the user does not need to write to the
boot ROM area.
Functional Outline (Parallel I/O Mode)
In parallel I/O mode, bus operation modes—Read, Output Disable, Standby, and Write—are selected by
_____ _____ _____
the status of the CE, OE, WE, VRFY, and CNVSS input pins.
The contents of erase, program, and other operations are selected by writing a software command. The
data in memory can only be read out by a read after software command input.
Program and erase operations are controlled using software commands.
Table CC-3. Relationship between control signals and bus operation modes
138
Appendix Parallel I/O Mode
Preliminary
Under
development
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The following explains about bus operation modes, software commands, and status register.
Bus Operation Modes
Read-only mode is entered by applying VPPH to the CNVSS pin and a low voltage to the VRFY pin.
Read-only mode has three states: Read, Output Disable, and Standby which are selected by
_____ _____ ______
setting the CE, OE, and WE pins high or low.
Read-write mode is entered by applying VPPH to the CNVSS pin and a high voltage to the VRFY pin.
Read-write mode has four states: Read, Output Disable, Standby, and Write which are selected by
_____ _____ ______
setting the CE, OE, and WE pins high or low.
Read ______ _____ _____
The Read mode is entered by pulling the WE pin high when the CE and OE pins are low. In Read
mode, the data corresponding to each software command entered is output from the data I/O pins
D0–D7.
Output Disable _____ _____ _____
The Output Disable mode is entered by pulling the CE pin low and the WE and OE pins high. Also,
the data I/O pins are placed in the high-impedance state.
Standby _____
The Standby mode is entered by driving the CE pin high. Also, the data I/O pins are placed in the
high-impedance state.
Write
The Write mode is entered by applying VPPH to the CNVSS pin and a high voltage to the VRFY pin
_____ _____ _____
and then pulling the WE pin low when the CE pin is low and OE pin is high. In this mode, the device
accepts the software commands or write data entered from the data I/O pins. A program, erase, or
some other operation is initiated depending on the content of the software command entered here.
_____
The input data such as address is latched at the falling edge of WE pin. The input data such as
_____
software command is latched at the rising edge of WE pin.
139
Appendix Parallel I/O Mode
Preliminary
Under
development
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Command
Program verify
Read
Program
First bus cycle Second bus cycle
0016
4016
C016
Write
Write
Write
Program
address
Write
Read
Erase verify A016
Write Verify
data
Read
Erase 2016
Write 2016
Write
Reset FF16
Write
Mode Address Mode Address Data
(D0 to D7)
Data
(D0 to D7)
xProgram
data
Verify
data
FF16
Write
x
x
x
x
Verify
address
x
x
x
x
Software Commands
Table CC-4 lists the software commands available with the M30201 (flash memory version). By entering
a software command from the data I/O pins (D0–D7) in Write mode, specify the content of the operation,
such as erase or program operation, to be performed.
The following explains the content of each software command.
Table CC-4. Software command list (parallel I/O mode)
Read Command (0016)
The read mode is entered by writing the command code “0016” in the first bus cycle. When an address
to be read is input in one of the bus cycles that follow, the content of the specified address is read out
at the data I/O pins (D0–D7).
The read mode is retained intact until another command is written.
After reset and after the reset command is executed, the read mode is set.
Program Command (4016)
The program mode is entered by writing the command code “4016” in the first bus cycle. When an
address and data to be program is write in the second bus cycle, the flash memory control circuit
executes the program operation. The program operation requires approximately 20 ms. Wait for 20 ms
or more before the user go to the next processing.
Note 1: The write operation is not completed immediately by writing a program command once. The
user must always execute a program-verify command after each program command executed. And if
verification fails, the user need to execute the program command repeatedly until the verification
passes. See Figure CC-4 for an example of a programming flowchart.
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Program-verify command (C016)
The program-verify mode is entered by writing the command code “C016” in the first bus cycle and the
verify data is output from the data I/O pins (D0–D7) in the second bus cycle.
Erase command (2016 + 2016)
The flash memory control circuit executes an erase operation by writing command code “2016” in the
first bus cycle and the same command code again in the second bus cycle. The erase operation
requires approximately 20 ms. Wait for 20 ms or more before the user go to the next processing.
Before this erase command can be performed, all memory locations to be erased must have had data
“0016” written to by using the program and program-verify commands.
Note 1: The erase operation is not completed immediately by writing an erase command once. The
user must always execute an erase-verify command after each erase command executed. And if
verification fails, the user need to execute the erase command repeatedly until the verification passes.
See Figure CC-4 for an example of an erase flowchart.
Erase-verify command (A016)
The erase-verify mode is entered by writing the command code “A016” in the first bus cycle and the
verify data is output from the data I/O pins (D0–D7) in the second bus cycle.
Note 1: If any unerased memory location is encountered during erase-verify operation, be sure to
execute erase and erase-verify operations one more time. In this case, however, the user does not
need to write data “0016” to memory before erasing.
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Start
Address = first location
Loop counter : X=0
Write program command Write : 40
16
Duration = 20 µs
Duration = 6 µs
X=25 ?
Verify
OK ?
PASS FAIL
FAIL
PASS
YES
PASS
NO
NO
FAIL
Write program data/
address
Loop counter : X=X+1
Write program verify
command
Last
address ?
Next address ?
Write read command Write read command
Verify
OK ?
Write : Program data
Write : C0
16
Write : 00
16
Write:20
16
Duration = 6µs
X=1000 ?
Verify
OK?
PASS FAIL
FAIL
PASS
YES
PASS
NO
NO
FAIL
Duration = 20ms
YES
NO
Start
All bytes =
"00
16
"?
Program all bytes =
"00
16
"
Address = First address
Loop counter X=0
Write erase command
Write erase command
Loop counter X=X+1
Write erase verify
command/address
Verify
OK?
Last
address?
Next address
Write read command Write read command
Write:20
16
Write:A0
16
Write:00
16
Read:
expect value=FF
16
Figure CC-4. Program and erase execution flowchart in the CPU rewrite mode
Program Erase
Reset command (FF16 + FF16)
The reset command is used to stop the program command or the erase command in the middle of
operation. After writing command code “4016” or “2016” twice, write command code “FF16” in the first
bus cycle and the same command code again in the second bus cycle. The program command or
erase command is disabled, with the flash memory placed in read mode.
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Figure CC-5. Protect control address
Protect function
In parallel I/O mode, the internal flash memory has the “protect function” available. This function protects
the flash memory contents from being read or rewritten easily.
Depending on the content at the protect control address (FFFFF16) in parallel I/O mode, this function
inhibits the flash memory contents against read or modification. The protect control address (FFFFF16) is
shown in Figure CC-5 . (This address exists in the user ROM area.)
The protect function is enabled by setting one of the two protect set bits to “0”, so that the internal flash
memory contents are inhibited against read or modification. The protect function is disabled by setting
both of the two protect reset bits to “00”, so that the internal flash memory contents can be read or
modified. Once the protect function is set, the user cannot change settings of the protect clear bits while
in parallel I/O mode. Settings of the protect reset bits can only be changed in CPU rewrite mode.
Symbol Address When shipping
ROMCP FFFFF
16
FF
16
Protect control address
Bit name Function
Bit symbol
b7 b6 b5 b4 b3 b2 b1 b0
00: Protect removed
01: Protect set bit effective
10: Protect set bit effective
11: Protect set bit effective
00: Protect enabled
01: Protect enabled
10: Protect enabled
11: Protect disabled
Protect reset bit
Protect set bit
ROMCR
ROMCP
b5 b4
b7 b6
Note 1: When protect is turned on, the flash memory version is protected against readout or modification
in parallel I/O mode.
Note 2: The protect reset bits can be used to turn off protect . However, since these bits cannot be
changed in parallel I/O mode, they need to be rewritten in CPU rewrite mode.
Reserved bit Always set to "1".
1111
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Pin Description
V
CC
,V
SS
Apply 5V ± 10 % to Vcc pin and 0 V to Vss pin.
CNV
SS
Apply 12V ± 5 % to this pin.
RESET Reset input pin. While reset is "L" level, a 20 cycle or longer clock
must be input to XIN pin.
X
IN
Connect a ceramic resonator or crystal oscillator between X
IN
and
X
OUT
pins. To input an externally generated clock, input it to X
IN
pin
and open X
OUT
pin.
X
OUT
AV
CC
, AV
SS
V
REF
Connect AV
SS
to Vss and AVcc to Vcc, respectively.
Enter the reference voltage for AD from this pin.
P0
0
to P0
7
Input "H" or "L" level signal or open.
P1
0
to P1
7
Input "H" or "L" level signal or open.
P3
0
to P3
5
Input "H" or "L" level signal or open.
P4
0
to P4
5
Input "H" or "L" level signal or open.
P5
4
Input "H" or "L" level signal or open.
P5
0
Serial data output pin.
P5
1
P5
2
Serial clock input pin.
P5
3
P6
0
to P6
7
Input "H" or "L" level signal or open.
P7
0
to P7
1
Input "H" or "L" level signal or open.
Name
Power input
CNV
SS
Reset input
Clock input
Clock output
Analog power supply input
Reference voltage input
Input port P0
Input port P1
Input port P3
Input port P4
Input port P5
TxD output
SCLK input
BUSY output
Input port P6
Input port P7
I/O
I
I
I
O
I
I
I
I
I
I
I
I
I
I
O
RxD input Serial data input pin.
OBUSY signal output pin.
Pin functions (Flash memory standard serial I/O mode)
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Appendix Standard Serial I/O Mode
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Figure DD-1. Pin connections for serial I/O mode (1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
P6
3
/AN
3
P6
2
/AN
2
P6
1
/AN
1
P6
0
/AN
0
V
REF
X
IN
X
OUT
P5
0
/T
X
D
0
/AN
50
P6
7
/AN
7
P6
6
/AN
6
P6
5
/AN
5
P6
4
/AN
4
V
SS
RESET
V
CC
CNV
SS
P5
1
/R
X
D
0
/AN
51
P5
2
/CLK
0
/AN
52
AV
SS
P4
5
/TX2
INOUT
P7
0
/TB0
IN
/X
COUT
P7
1
/TB1
IN
/X
CIN
P5
4
/CK
OUT
/AN
54
P5
3
/CLKS/AN
53
AV
CC
P0
7
/KI
7
P0
6
/KI
6
P0
5
/KI
5
P0
4
/KI
4
P0
3
/KI
3
P0
2
/KI
2
P0
1
/KI
1
P1
0
(LED
0
)
P1
1
(LED
1
)
P1
2
(LED
2
)
P1
3
(LED
3
)
P1
4
(LED
4
)
P1
5
(LED
5
)
P1
6
(LED
6
)
P1
7
(LED
7
)
M30201F6SP
M30201F6TSP
P0
0
/KI
0
P3
0
P3
1
P3
2
P3
3
P3
4
P3
5
P4
0
/TA0
IN
/T
X
D
1
P4
1
/TA0
OUT
P4
2
/R
X
D
1
P4
4
/INT
1
/TX1
INOUT
P4
3
/INT
0
/TX0
INOUT
BUSY
SCLK R
X
D
T
X
D
V
SS
V
CC
CNV
SS
V
SS
V
CC
RESET
CNV
SS
V
PP
H
RESET V
SS
V
CC
Mode setup method
Signal Value
Connect oscillator circuit.
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Figure DD-2. Pin connections for serial I/O mode (2)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
56
55
54
53
27
28
XIN
XOUT
P50/TXD0/AN50
P67/AN7
VSS
RESET
VCC
CNVSS
P51/RXD0/AN51
P5
2
/CLK
0
/AN
52
P45/TX2INOUT
P71/TB1IN/XCIN
P70/TB0IN/XCOUT
P4
1
/TA0
OUT
P4
0
/TA0
IN
/T
X
D
1
P4
2
/R
X
D
1
P5
4
/CK
OUT
/AN
54
P5
3
/CLKS/AN
53
V
REF
P6
0
/AN
0
P6
1
/AN
1
AV
SS
AV
CC
P10(LED0)
P1
4
(LED
4
)
M30201F6FP
M30201F6TFP
N.C.
N.C.
N.C.
N.C.
P00/KI0
P6
2
/AN
2
P6
3
/AN
3
P6
4
/AN
4
P6
5
/AN
5
P6
6
/AN
6
P01/KI1
P02/KI2
P03/KI3
P04/KI4
P05/KI5
P06/KI6
P07/KI7
P11(LED1)
P12(LED2)
P13(LED3)
P1
5
(LED
5
)
P1
6
(LED
6
)
P1
7
(LED
7
)
P3
0
P3
1
P3
2
P3
3
P3
4
P3
5
P44/INT1/TX1INOUT
P43/INT0/TX0INOUT
V
SS
V
CC
BUSY
SCLK
RXDTXD
CNVSS
RESET
VSS
VCC
CNVSS VPPH
RESET VSS VCC
Mode setup method
Signal Value
Connect oscillator
circuit.
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Appendix Standard Serial I/O Mode
Preliminary
Standard Serial I/O Mode
The standard serial I/O mode serially inputs and outputs the software commands, addresses and data
necessary for operating (read, program, erase, etc.) the internal flash memory. It uses a purpose-specific
serial programmer.
The standard serial I/O mode differs from the parallel I/O mode in that the CPU controls operations like
rewriting (uses the CPU rewrite mode) in the flash memory or serial input for rewriting data. The standard
serial I/O mode is started by clearing the reset with VPPH at the CNVss pin. (For the normal microprocessor
mode, set CNVss to “L”.)
This control program is written in the boot ROM area when shipped from Mitsubishi Electric. Therefore, if
the boot ROM area is rewritten in the parallel I/O mode, the standard serial I/O mode cannot be used.
Figures DD-1 and DD-2 show the pin connections for the standard serial I/O mode. Serial data I/O uses
three UART0 pins: CLK0, RxD0, and TxD0 and port P53 (BUSY).
The CLK0 pin is the transfer clock input pin and it transfers the external transfer clock. The TxD0 pin outputs
the CMOS signal. The P53 (BUSY) pin outputs an “L” level when reception setup ends and an “H” level
when the reception operation starts. Transmission and reception data is transferred serially in 8-byte
blocks.
In the standard serial I/O mode, only the user ROM area shown in Figure CC-1 can be rewritten, the boot
ROM area cannot.
The standard serial I/O mode has a 7-byte ID code. When the flash memory is not blank and the ID code
does not match the content of the flash memory, the command sent from the programmer is not accepted.
Function Overview (Standard Serial I/O Mode)
In the standard serial I/O mode, software commands, addresses and data are input and output between
the flash memory and an external device (serial programmer, etc.) using a clock synchronized serial I/O
(UART0) and P53. In reception, the software commands, addresses and program data are synchronized
with the rise of the transfer clock input to the CLK0 pin and input into the flash memory via the RxD0 pin.
In transmission, the read data and status are synchronized with the fall of the transfer clock and output to
the outside from the TxD0 pin.
The TxD1 pin is CMOS output. Transmission is in 8-bit blocks and LSB first.
When busy, either during transmission or reception, or while executing an erase operation or program,
the P53 (BUSY) pin is “H” level. Accordingly, do not start the next transmission until the P53 (BUSY) pin is
“L” level.
Also, data in memory and the status register can be read after inputting a software command. It is pos-
sible to check flash memory operating status or whether a program or erase operation ended success-
fully or in error by reading the status register.
Software commands and the status register are explained here following.
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Software Commands
Table DD-1 lists software commands. In the standard serial I/O mode, erase operations, programs and
reading are controlled by transferring software commands via the RxD pin. Software commands are
explained here below.
Table DD-1. Software commands (Standard serial I/O mode)
Control command 2nd byte 3rd byte 4th byte 5th byte 6th byte
1 Page read
2 Page program
3 Erase all unlocked blocks
4 Read status register
5 Clear status register
6 Read lockbit status
7 ID check function
8 Download function
9 Version data output function
14 Boot area output function
Note1: Shading indicates transfer from flash memory microcomputer to serial programmer. All other data is
transferred from the serial programmer to the flash memory microcomputer.
Note2: SRD refers to status register data. SRD1 refers to status register 1 data.
Note3: All commands can be accepted when the flash memory is totally blank.
When ID is
not verificate
Not
acceptable
Not
acceptable
Not
acceptable
Acceptable
Not
acceptable
Not
acceptable
Acceptable
Not
acceptable
Acceptable
Not
acceptable
Version
data output
to 9th byte
Data
output to
259th byte
Data
output to
259th
byte
Data input
to 259th
byte
To ID7
Data
output
Data
input
ID1
To
required
number
of times
Version
data
output
Data
output
Data
output
Data
input
ID size
Data
input
Version
data
output
Data
output
Data
output
Data
input
Lock bit
data
output
Address
(high)
Check-
sum
Version
data
output
Data
output
Address
(high)
Address
(high)
SRD1
output
Address
(high)
Address
(middle)
Size
(high)
Version
data
output
Address
(high)
Address
(middle)
Address
(middle)
D016
SRD
output
Address
(middle)
Address
(low)
Size
(low)
Version
data
output
Address
(middle)
FF16
4116
A716
7016
5016
7116
F516
FA16
FB16
FC16
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Appendix Standard Serial I/O Mode
Preliminary
Page Read Command
This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a
time. Execute the page read command as explained here following.
(1) Send the “FF16” command code in the 1st byte of the transmission.
(2) Send addresses A8 to A15 and A16 to A23 in the 2nd and 3rd bytes of the transmission respec-
tively.
(3) From the 4th byte onward, data (D0–D7) for the page (256 bytes) specified with addresses A8 to
A23 will be output sequentially from the smallest address first in sync with the rise of the clock.
data0 data255
CLK0
RxD0
TxD0
P5
3
(BUSY)
A
8
to
A
15
A
16
to
A
23
FF
16
SRD
output SRD1
output
7016
CLK0
RxD0
TxD0
P53(BUSY)
Figure DD-3. Timing for page read
Read Status Register Command
This command reads status information. When the “7016” command code is sent in the 1st byte of the
transmission, the contents of the status register (SRD) specified in the 2nd byte of the transmission
and the contents of status register 1 (SRD1) specified in the 3rd byte of the transmission are read.
Figure DD-4. Timing for reading the status register
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Figure DD-5. Timing for clearing the status register
Page Program Command
This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a
time. Execute the page program command as explained here following.
(1) Send the “4116” command code in the 1st byte of the transmission.
(2) Send addresses A
8
to A
15
and A
16
to A
23
in the 2nd and 3rd bytes of the transmission respectively.
(3) From the 4th byte onward, as write data (D
0
–D
7
) for the page (256 bytes) specified with addresses
A
8
to A
23
is input sequentially from the smallest address first, that page is automatically written.
When reception setup for the next 256 bytes ends, the P53 (BUSY) signal changes from the “H” to the
“L” level. The result of the page program can be known by reading the status register. For more
information, see the section on the status register.
5016
CLK0
RxD0
TxD0
P53(BUSY)
Clear Status Register Command
This command clears the bits (SR3–SR4) which are set when the status register operation ends in
error. When the “5016” command code is sent in the 1st byte of the transmission, the aforementioned
bits are cleared. When the clear status register operation ends, the P53 (BUSY) signal changes from
the “H” to the “L” level.
A
8
to
A
15
A
16
to
A
23
41
16
data0 data255
CLK0
RxD0
TxD0
P5
3
(BUSY)
Figure DD-6. Timing for the page program
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Appendix Standard Serial I/O Mode
Preliminary
Read Lock Bit Status Command
This command reads the lock bit status of the specified block. Execute the read lock bit status com-
mand as explained here following.
(1) Send the “7116” command code in the 1st byte of the transmission.
(2) Send addresses A8 to A15 and A16 to A23 in the 2nd and 3rd bytes of the transmission respec-
tively.
(3) The lock bit data of the specified block is output in the 4th byte of the transmission. Write the
highest address of the specified block for addresses A8 to A23.
The M30201 (flash memory version) does not have the lock bit, so the read value is always “1”
(block unlock).
A
8
to
A
15
A
16
to
A
23
71
16
DQ6
CLK0
RxD0
TxD0
P5
3
(BUSY)
Figure DD-8. Timing for reading lock bit status
Erase All Unlocked Blocks Command
This command erases the content of all blocks. Execute the erase all unlocked blocks command as
explained here following.
(1) Send the “A716” command code in the 1st byte of the transmission.
(2) Send the verify command code “D016” in the 2nd byte of the transmission. With the verify com-
mand code, the erase operation will start and continue for all blocks in the flash memory.
When block erasing ends, the
P53
(BUSY) signal changes from the “H” to the “L” level. The result of the
erase operation can be known by reading the status register.
A7
16
D0
16
CLK0
RxD0
TxD0
P5
3
(BUSY)
Figure DD-7. Timing for erasing all unlocked blocks
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Appendix Standard Serial I/O Mode
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Download Command
This command downloads a program to the RAM for execution. Execute the download command as
explained here following.
(1) Send the “FA16” command code in the 1st byte of the transmission.
(2) Send the program size in the 2nd and 3rd bytes of the transmission.
(3) Send the check sum in the 4th byte of the transmission. The check sum is added to all data sent
in the 5th byte onward.
(4) The program to execute is sent in the 5th byte onward.
When all data has been transmitted, if the check sum matches, the downloaded program is executed.
The size of the program will vary according to the internal RAM.
FA
16 Program
data Program
data
Data size (high)
Data size (low)
Check
sum
CLK0
RxD0
TxD0
P5
3
(BUSY)
Figure DD-9. Timing for download
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development
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Appendix Standard Serial I/O Mode
Preliminary
Version Information Output Command
This command outputs the version information of the control program stored in the boot area. Execute
the version information output command as explained here following.
(1) Send the “FB16” command code in the 1st byte of the transmission.
(2) The version information will be output from the 2nd byte onward. This data is composed of 8
ASCII code characters.
Figure DD-10. Timing for version information output
Boot Area Output Command
This command outputs the control program stored in the boot area in one page blocks (256 bytes).
Execute the boot area output command as explained here following.
(1) Send the “FC16” command code in the 1st byte of the transmission.
(2) Send addresses A8 to A15 and A16 to A23 in the 2nd and 3rd bytes of the transmission respec-
tively.
(3) From the 4th byte onward, data (D0–D7) for the page (256 bytes) specified with addresses A8 to
A23 will be output sequentially from the smallest address first, in sync with the rise of the clock.
FB
16
'X'
'V' 'E' 'R'
CLK0
RxD0
TxD0
P5
3
(BUSY)
data0 data255
A
8
to
A
15
A
16
to
A
23
FC
16
CLK0
RxD0
TxD0
P5
3
(BUSY)
Figure DD-11. Timing for boot area output
153
Appendix Standard Serial I/O Mode
Preliminary
Under
development
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
ID Check
This command checks the ID code. Execute the boot ID check command as explained here following.
(1) Send the “F516” command code in the 1st byte of the transmission.
(2) Send addresses A0 to A7, A8 to A15 and A16 to A23 of the 1st byte of the ID code in the 2nd, 3rd
and 4th bytes of the transmission respectively.
(3) Send the number of data sets of the ID code in the 5th byte.
(4) The ID code is sent in the 6th byte onward, starting with the 1st byte of the code.
ID size ID1 ID7
F5
16
DF
16
FF
16
0F
16
CLK0
RxD0
TxD0
P5
3
(BUSY)
Figure DD-12. Timing for the ID check
ID Code
When the flash memory is not blank, the ID code sent from the serial programmer and the ID code
written in the flash memory are compared to see if they match. If the codes do not match, the com-
mand sent from the serial programmer is not accepted. An ID code contains 8 bits of data. Area is,
from the 1st byte, addresses 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, and
0FFFF716 . Write a program into the flash memory, which already has the ID code set for these
addresses.
Reset
Watchdog timer vector
Single step vector
Address match vector
BRK instruction vector
Overflow vector
Undefined instruction vector
ID7
ID6
ID5
ID4
ID3
ID2
ID1
DBC vector
0FFFFF
16
to 0FFFFC
16
0FFFFB
16
to 0FFFF8
16
0FFFF7
16
to 0FFFF4
16
0FFFF3
16
to 0FFFF0
16
0FFFEF
16
to 0FFFEC
16
0FFFEB
16
to 0FFFE8
16
0FFFE7
16
to 0FFFE4
16
0FFFE3
16
to 0FFFE0
16
0FFFDF
16
to 0FFFDC
16
4 bytes
Address
Figure DD-13. ID code storage addresses
Under
development
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
154
Appendix Standard Serial I/O Mode
Preliminary
Status Register (SRD)
The status register indicates operating status of the flash memory and status such as whether an erase
operation or a program ended successfully or in error. It can be read by writing the read status register
command (7016). Also, the status register is cleared by writing the clear status register command (5016).
Table DD-2 gives the definition of each status register bit. After clearing the reset, the status register
outputs “8016”.
Table DD-2. Status register (SRD)
Status Bit (SR7)
The status bit indicates the operating status of the flash memory. When power is turned on, “1” (ready)
is set for it. The bit is set to “0” (busy) during an auto write or auto erase operation, but it is set back to
“1” when the operation ends.
Erase Bit (SR5)
The erase bit reports the operating status of the auto erase operation. If an erase error occurs, it is set
to “1”. When the erase status is cleared, it is set to “0”.
Program Bit (SR4)
The program bit reports the operating status of the auto write operation. If a write error occurs, it is set
to “1”. When the program status is cleared, it is set to “0”.
SRD0 bits
SR7 (bit7)
SR6 (bit6)
SR5 (bit5)
SR4 (bit4)
SR3 (bit3)
SR2 (bit2)
SR1 (bit1)
SR0 (bit0)
Status name
Status bit
Reserved
Erase bit
Program bit
Reserved
Reserved
Reserved
Reserved
Definition
"1" "0"
Ready
-
Terminated in error
Terminated in error
-
-
-
-
Busy
-
Terminated normally
Terminated normally
-
-
-
-
155
Appendix Standard Serial I/O Mode
Preliminary
Under
development
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Status Register 1 (SRD1)
Status register 1 indicates the status of serial communications, results from ID checks and results from
check sum comparisons. It can be read after the SRD by writing the read status register command (7016).
Also, status register 1 is cleared by writing the clear status register command (5016).
Table DD-3 gives the definition of each status register 1 bit. “0016” is output when power is turned ON and
the flag status is maintained even after the reset.
Table DD-3. Status register 1 (SRD1)
Boot Update Completed Bit (SR15)
This flag indicates whether the control program was downloaded to the RAM or not, using the down-
load function.
Check Sum Consistency Bit (SR12)
This flag indicates whether the check sum matches or not when a program, is downloaded for execu-
tion using the download function.
ID Check Completed Bits (SR11 and SR10)
These flags indicate the result of ID checks. Some commands cannot be accepted without an ID
check.
Data Reception Time Out (SR9)
This flag indicates when a time out error is generated during data reception. If this flag is attached
during data reception, the received data is discarded and the microcomputer returns to the command
wait state.
SRD1 bits
SR15 (bit7)
SR14 (bit6)
SR13 (bit5)
SR12 (bit4)
SR11 (bit3)
SR10 (bit2)
SR9 (bit1)
SR8 (bit0)
Status name
Boot update completed bit
Reserved
Reserved
Checksum match bit
ID check completed bits
Data receive time out
Reserved
Definition
"1" "0"
Update completed
-
-
Match
00
01
10
11
Not update
-
-
Mismatch
Normal operation
-
Not verified
Verification mismatch
Reserved
Verified
Time out
-
Under
development
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
156
Appendix Standard Serial I/O Mode
Preliminary
Example Circuit Application for The Standard Serial I/O Mode
The below figure shows a circuit application for the standard serial I/O mode. Control pins will vary ac-
cording to programmer, therefore see the programmer manual for more information.
P5
3
(BUSY)
CLK0
R
X
D0
T
X
D0
CNVss
Clock input
P5
3
output
Data input
Data output
M30201 Flash
memory version
(1) Control pins and external circuitry will vary according to programmer. For
more information, see the programmer manual.
(2) In this example, the microprocessor mode and standard serial I/O mode are
switched via a switch.
V
PP
Figure DD-14. Example circuit application for the standard serial I/O mode
keep safety first in your circuit designs !
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MITSUBISHI SEMICONDUCTORS
M30201 Group DATA SHEET REV.D
April First Edition 1998
July Second Edition 1998
February Third Edition 1999
May Fourth Edition 1999
Editioned by
Committee of editing of Mitsubishi Semiconductor DATA SHEET
Published by
Mitsubishi Electric Corp., Kitaitami Works
This book, or parts thereof, may not be reproduced in any form without
permission of Mitsubishi Electric Corporation.
©1999 MITSUBISHI ELECTRIC CORPORATION