ICS843101IAG-100 - Integrated Circuit Systems, Inc.

843101AGI-100 www.icst.com/products/hiperclocks.html REV. A OCTOBER 20, 2005

Integrated

Circuit

Systems, Inc.

ICS843101I-100

FEMTOCLOCKS™ C RYSTAL-TO-LVPECL

100MHZ FREQUENCY MARGINING SYNTHESIZER

PRELIMINARY

GENERAL DESCRIPTION

The ICS843101I-100 is a low phase-noise

frequency margining synthesizer with fre-

quency margining capability and is a member of

the HiPerClockS™ family of high performance

clock solutions from ICS. In the default mode,

the device nominally generates a 100MHz LVPECL output

clock signal from a 24MHz crystal input. There is also a

frequency margining mode available where the device can

be programmed, using the serial interface, to vary the

output frequency up or down from nominal in 2% steps.

The ICS843101I-100 is provided in a 16-pin TSSOP.

FEATURES

• 100MHz nominal LVPECL output

• Selectable crystal oscillator interface designed for 24MHz,

18pF parallel resonant crystal or LVCMOS/LVTTL

single-ended input

• Output frequency can be varied in 2% steps ± from

nominal

• VCO range: 540MHz - 680MHz

• RMS phase jitter @ 100MHz, using a 24MHz crystal

(1.875MHz - 20MHz): 0.55ps (typical)

• Output supply modes

Core/Output

3.3V/3.3V

3.3V/2.5V

2.5V/2.5V

• -40°C to 85°C ambient operating temperature

• Available in both standard and lead-free RoHS-complaint

packages

HiPerClockS™

ICS

PIN ASSIGNMENT

VEE

S_LOAD

S_DATA

S_CLOCK

SEL

VCCA

VCC

MODE

VCCO

VEE

CLK

XTAL_OUT

XTAL_IN

ICS843101I-100

16-Lead TSSOP

4.4mm x 5.0mm x 0.92mm

package body

G Package

Top View

BLOCK DIAGRAM

Phase

Detector

VCO

540 - 680MHz

÷ M

OSC

÷ N

÷ P

Serial Control

Pullup

Pulldown

CLK

SEL

S_CLOCK

S_DATA

S_LOAD

MODE

XTAL_IN

XTAL_OUT

Pulldown

24MHz

The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on

initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications

without notice.

843101AGI-100 www.icst.com/products/hiperclocks.html REV. A OCTOBER 20, 2005

Integrated

Circuit

Systems, Inc.

ICS843101I-100

FEMTOCLOCKS™ C RYSTAL-TO-LVPECL

100MHZ FREQUENCY MARGINING SYNTHESIZER

PRELIMINARY

FUNCTIONAL DESCRIPTION

The ICS843101I-100 features a fully integrated PLL and

therefore requires no external components for setting the

loop bandwidth. A 24MHz fundamental crystal is used as

the input to the on chip oscillator. The output of the oscilla-

tor is fed into the pre-divider. In frequency margining mode,

the 24MHz crystal frequency is divided by 2 and a 12MHz

reference frequency is applied to the phase detector. The

VCO of the PLL operates over a range of 540MHz to

680MHz. The output of the M divider is also applied to the

phase detector.

The default mode for the ICS843101I-100 is 100MHz output

frequency using a 24MHz crystal. The output frequency

can be changed by placing the device into the margining

mode using the mode pin and using the serial interface to

program the M feedback divider. Frequency margining

mode operation occurs when the MODE input is HIGH. The

phase detector and the M divider force the VCO output fre-

quency to be M times the reference frequency by adjusting

the VCO control voltage. Note that for some values of M

(either too high or too low), the PLL will not achieve lock. The

output of the VCO is scaled by an output divider prior to

being sent to the LVPECL output buffer. The divider provides

a 50% output duty cycle. The relationship between the crys-

tal input frequency, the M divider, the VCO frequency and

the output frequency is provided in Table 1. When changing

back from frequency margining mode to nominal mode, the

device will return to the default nominal configuration that

will provide 100MHz output frequency.

Serial operation occurs when S_LOAD is HIGH. Serial data

can be loaded in either the default mode or the frequency

margining mode. The 6-bit shift register is loaded by samp-

ling the S_DATA bits with the rising edge of S_CLOCK.

After shifting in the 6-bit M divider value, S_LOAD is

transitioned from HIGH to LOW which latches the contents

of the shift-register into the M divider control register.

When S_LOAD is LOW, any transitions of S_CLOCK or

S_DATA are ignored.

TABLE 1. FREQUENCY MARGIN FUNCTION TABLE

FIGURE 1. SERIAL LOAD OPERATIONS

Time

SERIAL LOADING

tStH

M5 M4 M3 M2 M1 M0

S_CLOCK

S_DATA

S_LOAD

LATX

)zHM(

rediviD-erP

)P(

ecnerefeR

)zHM(ycneuqerF

kcabdeeF

)M(rediviD

ataD-M

)yraniB(

OCV

)zHM(

tuptuO

)N(redivi

tuptuO

ycneuqerF

)zHM(

egnahC%

422 21541011010456 090.01-

422 21640111012556 290.8-

422 21741111014656 490.6-

422 21840000116756 690.4-

422 21941000118856 890

.2-

422 21050100110066 001edoMlanimoN

422 21151100112166 2010.2

422 21250010114266 4010.4

422 21351010116366 6010.6

422 21450110118466 8010.8

422 21551110110666 0110.0

843101AGI-100 www.icst.com/products/hiperclocks.html REV. A OCTOBER 20, 2005

Integrated

Circuit

Systems, Inc.

ICS843101I-100

FEMTOCLOCKS™ C RYSTAL-TO-LVPECL

100MHZ FREQUENCY MARGINING SYNTHESIZER

PRELIMINARY

TABLE 2. PIN DESCRIPTIONS

TABLE 3. PIN CHARACTERISTICS

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

ecnaticapaCtupnI 4Fp

NWODLLUP

rotsiseRnwodlluPtupnI 15kΩ

PULLUP

rotsiseRnwodlluPtupnI 15kΩ

ρεβμυΝεμαΝεπψΤνοιτπιρχσεΔ

21,1V

rewoP.snipylppusevitageN

2DAOL_StupnInwodlluP .slevelecafretniLTTVL/SOMCVL.tupnilaireSehtfonoitarepoehtslor

tnoC

3ATAD_StupnInwodlluP .KCOLC_SfoegdegnisirehtnodelpmasataD.tupnilairesretsigertfihS

.slevelecafretniLTT

VL/SOMCVL

4KCOLC_StupnInwodlluP ehtnoretsigertfihsehtotnitupniATAD_StatneserpatadlairesnikcolC

.slevelecafr

etniLTTVL/SOMCVL.KCOLC_Sfoegdegnisir

5LEStupnInwodlluP .tupniKLCstceles,HGIHnehW.niptceleS

.slevelecafretni

LTTVL/SOMCVL.stupniLATXstceles,WOLnehW

6EOtupnIpulluP .stuptuoQn/QfognilbasiddnagnilbaneslortnoC.nipelbane

tuptuO

slevelecafretniLTTVL/SOMCVL

ACC

rewoP.nipylppusgolanA

rewoP.nipylppuseroC

01,9 ,NI_LATX

TUO_LATX tupnI ehtsiNI_LATX,tuptuoehtsiTUO_LATX.ecafretnilatsyrctnanoserl

ellaraP

.tupni

11KLCtupnInwodlluP.tupnikcolcLTTVL/SOMCVL

41,31Q,QntupuO.slevelecafretniLCEPVL.riaptuptuolaitner

effiD

51V

OCC

rewoP.nipylppustuptuO

61EDOMtupnInwodlluP .edomgninigramycneuqerf=HGIH.edomtluafed=WOL.nipEDOM

.slevelecafre

tniLTTVL/SOMCVL

:ETON nwodlluPdnapulluP .seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilan

retniotrefer

843101AGI-100 www.icst.com/products/hiperclocks.html REV. A OCTOBER 20, 2005

Integrated

Circuit

Systems, Inc.

ICS843101I-100

FEMTOCLOCKS™ C RYSTAL-TO-LVPECL

100MHZ FREQUENCY MARGINING SYNTHESIZER

PRELIMINARY

TABLE 4D. SERIAL MODE FUNCTION TABLE

TABLE 4A. OE CONTROL INPUT FUNCTION TABLE

TABLE 4B. SEL CONTROL INPUT FUNCTION TABLE

TABLE 4C. MODE CONTROL INPUT FUNCTION TABLE

tupnI

LESecruoSdetceleS

0TUO_LATX,NI_LATX

1KLC

tupnIstuptuO

EOQn,Q

0ZiH

1delbanE

tupnInoitidnoC

edoMQn,Q

0edoMtluafeD

1edoMgninigraMycneuqerF

stupnI snoitidnoC

DAOL_SKCOLC_SATAD_S

LX X .derongierastupnilaireS

H↑ataD .edomtupnilaireS

.KCOLC_Sfoegdegnisirhca

enoATAD_SnoatadhtiwdedaolsiretsigertfihS

↓LX .dehctaleraretsigertfihsehtfostnetnoC

WOL=L:ETON

HGIH=H

eract'n

oD=X

↑noitisnartegdegnisiR=

↓noitisnartegdegnillaF=

843101AGI-100 www.icst.com/products/hiperclocks.html REV. A OCTOBER 20, 2005

Integrated

Circuit

Systems, Inc.

ICS843101I-100

FEMTOCLOCKS™ C RYSTAL-TO-LVPECL

100MHZ FREQUENCY MARGINING SYNTHESIZER

PRELIMINARY

TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C

ABSOLUTE MAXIMUM RATINGS

Supply Voltage, V

CC 4.6V

Inputs, VI-0.5V to VCC + 0.5V

Outputs, IO

Continuous Current 50mA

Surge Current 100mA

Package Thermal Impedance, θJA 89°C/W (0 lfpm)

Storage Temperature, T

STG -65°C to 150°C

NOTE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent damage to the

device. These ratings are stress specifications only. Functional

operation of product at these conditions or any conditions be-

yond those listed in the DC Characteristics or AC Character-

istics is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect product reliability.

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVylppuSeroC 531.33.3564.3V

ACC

egatloVylppuSgolanA 531.33.3564.3V

OCC

egatloVylppuStuptuO 531.33.3564.3V

tnerruCylppuSrewoP 29Am

tnerruCylppuSeroC 87Am

ACC

tnerruCylppuSgolanA 7Am

OCC

tnerruCylppuStuptuO 4Am

TABLE 5B. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%,VCCO = 2.5V±5%, TA = -40°C TO 85°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVylppuSeroC 531.33.3564.3V

ACC

egatloVylppuSgolanA 531.33.3564.3V

OCC

egatloVylppuStuptuO 573.25.2526.2V

tnerruCylppuSrewoP 09Am

tnerruCylppuSeroC 87Am

ACC

tnerruCylppuSgolanA 7Am

OCC

tnerruCylppuStuptuO 4Am

TABLE 5C. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 2.5V±5%, TA = -40°C TO 85°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVylppuSeroC 573.25.2526.2V

ACC

egatloVylppuSgolanA 573.25.2526.2V

OCC

egatloVylppuStuptuO 573.25.2526.2V

tnerruCylppuSrewoP 48Am

tnerruCylppuSeroC 47Am

ACC

tnerruCylppuSgolanA 7Am

OCC

tnerruCylppuStuptuO 3Am

843101AGI-100 www.icst.com/products/hiperclocks.html REV. A OCTOBER 20, 2005

Integrated

Circuit

Systems, Inc.

ICS843101I-100

FEMTOCLOCKS™ C RYSTAL-TO-LVPECL

100MHZ FREQUENCY MARGINING SYNTHESIZER

PRELIMINARY

TABLE 6. CRYSTAL CHARACTERISTICS

TABLE 5D. LVCMOS / LVTTL DC CHARACTERISTICS, TA = -40°C TO 85°C

TABLE 5E. LVPECL DC CHARACTERISTICS, TA = -40°C TO 85°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

1ETON;egatloVhgiHtuptuOV

OCC

4.1-V

OCC

9.0-V

1ETON;egatloVwoLtuptuOV

OCC

0.2-V

OCC

7.1-V

GNIWS

gniwSegatloVtuptuOkaeP-ot-kaeP 6.00.1V

05htiwdetanimretstuptuO:1ETON ΩVot

OCC

.V2-

retemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

noitallicsOfoedoM latnemadnuF

ycneuqerF 42zHM

)RSE(ecnatsiseRs

eireStnelaviuqE 05 Ω

ecnaticapaCtnuhS 7Fp

leveLevirD 001Wµ

.latsyrctnanoserlellarapFp81nagnisudeziretcarahC:ET

TABLE 7. INPUT FREQUENCY CHARACTERISTICS, TA = -40°C TO 85°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

tupnI

ycneuqerF

KLC 42zHM

TUO_LATX/NI_LATX 42zHM

KCOLC_S 05zHM

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVhgiHtupnI V

V3.3=2V

3.0+V

V5.2=7.1V

3.0+V

egatloVwoLtupnI V

V3.3=3.0-8.0V

V5.2=3.0-7.0V

tupnI

tnerruChgiH

,LES,KLC

,KCOLC_S,DAOL_S

EDOM,ATAD_S

564.3=

V526.2ro 051Aµ

EO V

564.3=

V526.2ro 5Aµ

tupnI

tnerruCwoL

,LES,KLC

,KCOLC_S,DAOL_S

EDOM,ATAD_S

,V526.2roV564.3=

V0= 5-Aµ

EO V

,V526.2roV564.3=

V0= 051-Aµ

Δ/t ΔvnoitsisnarTtupnI

etaRllaF/esiR

,LES,EO

,ATAD_S,KCOLC_S

EDOM,DAOL_S

02v/sn

843101AGI-100 www.icst.com/products/hiperclocks.html REV. A OCTOBER 20, 2005

Integrated

Circuit

Systems, Inc.

ICS843101I-100

FEMTOCLOCKS™ C RYSTAL-TO-LVPECL

100MHZ FREQUENCY MARGINING SYNTHESIZER

PRELIMINARY

TABLE 8A. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C

TABLE 8B. AC CHARACTERISTICS, VCC = VCCA = 3.3V±5%,VCCO = 2.5V±5%, TA = -40°C TO 85°C

TABLE 8C. AC CHARACTERISTICS, VCC = VCCA = VCCO = 2.5V±5%, TA = -40°C TO 85°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

TUO

ycneuqerFtuptuO 001zHM

t)Ø(tij1ETON;rettiJesahPSMR WOL=edoM

)zHM02-zHM578.1(,zHM001 55.0sp

emiTllaF/esiRtuptuO%08ot%02574sp

cdoelcyCytuDtuptuO 05%

emiTputeS

otATAD_S

KCOLC_S 01sn

KCOLC_S

DAOL_Sot 01sn

emiTdloH otATAD_S

KCOLC_S 01sn

.latsyrczHM52agnisudeziretcarahC:1ETON

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

TUO

ycneuqerFtuptuO 001zHM

t)Ø(tij1ETON;rettiJesahPSMR WOL=edoM

)zHM02-zHM578.1(,zHM001 55.0sp

emiTllaF/esiRtuptuO%08ot%02244sp

cdoelcyCytuDtuptuO 05%

emiTputeS

otATAD_S

KCOLC_S 01sn

KCOLC_S

DAOL_Sot 01sn

emiTdloH otATAD_S

KCOLC_S 01sn

.latsyrczHM52agnisudeziretcarahC:1ETON

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

TUO

ycneuqerFtuptuO 001zHM

t)Ø(tij1ETON;rettiJesahPSMR WOL=edoM

)zHM02-zHM578.1(,zHM001 55.0sp

emiTllaF/esiRtuptuO%08ot%02504sp

cdoelcyCytuDtuptuO 05%

emiTputeS

otATAD_S

KCOLC_S 01sn

KCOLC_S

DAOL_Sot 01sn

emiTdloH otATAD_S

KCOLC_S 01sn

.latsyrczHM52agnisudeziretcarahC:1ETON

843101AGI-100 www.icst.com/products/hiperclocks.html REV. A OCTOBER 20, 2005

Integrated

Circuit

Systems, Inc.

ICS843101I-100

FEMTOCLOCKS™ C RYSTAL-TO-LVPECL

100MHZ FREQUENCY MARGINING SYNTHESIZER

PRELIMINARY

OFFSET FREQUENCY (HZ)

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-150

-160

-170

-180

-190

100 1k 10k 100k 1M 10M 100M

TYPICAL PHASE NOISE AT 100MHZ (3.3V)

100MHz

RMS Phase Noise Jitter

1.875MHz to 20MHz = 0.55ps (typical)

➤

10 Gigabit Ethernet Filter

Raw Phase Noise Data

Phase Noise Result by adding

10 Gigabit Ethernet Filter to raw data

dBc

NOISE POWER

843101AGI-100 www.icst.com/products/hiperclocks.html REV. A OCTOBER 20, 2005

Integrated

Circuit

Systems, Inc.

ICS843101I-100

FEMTOCLOCKS™ C RYSTAL-TO-LVPECL

100MHZ FREQUENCY MARGINING SYNTHESIZER

PRELIMINARY

PARAMETER MEASUREMENT INFORMATION

tPERIOD

PERIOD

odc = x 100%

2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT

3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT

SCOPE

nQx

LVPECL

-1.3V ± 0.165V

RMS PHASE JITTER

Clock

Outputs 20%

80% 80%

20%

SWING

VCC,

VCCA, VCCO

VEE

OUTPUT DUTY CYCLE/PULSE W IDTH/PERIOD

Phase Noise Mas

Offset Frequency

Phase Noise Plot

RMS Jitter = Area Under the Masked Phase Noise Plot

Noise Power

OUTPUT RISE/FALL T IME

SCOPE

nQx

LVPECL

2.8V±0.04V

-0.5V ± 0.125V

VCC,

VCCA

VEE

VCCO

SCOPE

nQx

LVPECL

-0.5V ± 0.125V

VCC,

VCCA, VCCO

VEE

843101AGI-100 www.icst.com/products/hiperclocks.html REV. A OCTOBER 20, 2005

Integrated

Circuit

Systems, Inc.

ICS843101I-100

FEMTOCLOCKS™ C RYSTAL-TO-LVPECL

100MHZ FREQUENCY MARGINING SYNTHESIZER

PRELIMINARY

APPLICATION INFORMATION

As in any high speed analog circuitry, the power supply pins

are vulnerable to random noise. The ICS843101I-100 pro-

vides separate power supplies to isolate any high switch-

ing noise from the outputs to the internal PLL. VCC, VCCA, and

VCCO should be individually connected to the power supply

plane through vias, and bypass capacitors should be

used for each pin. To achieve optimum jitter performance,

power supply isolation is required. Figure 2 illustrates how

a 10Ω resistor along with a 10µF and a .01μF bypass

capacitor should be connected to each VCCA. The 10Ω resis-

tor can also be replaced by a ferrite bead.

POWER SUPPLY FILTERING TECHNIQUES

FIGURE 2. POWER SUPPLY FILTERING

10Ω

VCCA

10μF

.01μF

3.3V or 2.5V

.01μF

VCC

CRYSTAL INPUT INTERFACE

The ICS843101I-100 has been characterized with 18pF

parallel resonant crystals. The capacitor values shown in

Figure 3 below were determined using a 24MHz, 18pF par-

Figure 3. CRYSTAL INPUt INTERFACE

allel resonant crystal and were chosen to minimize the

ppm error.

27p

18pF Parallel Crystal

27p

XTAL_OUT

XTAL_IN

843101AGI-100 www.icst.com/products/hiperclocks.html REV. A OCTOBER 20, 2005

Integrated

Circuit

Systems, Inc.

ICS843101I-100

FEMTOCLOCKS™ C RYSTAL-TO-LVPECL

100MHZ FREQUENCY MARGINING SYNTHESIZER

PRELIMINARY

TERMINATION FOR 3.3V LVPECL OUTPUT

- 2V

50Ω50Ω

RTT

= 50Ω

FOUT FIN

RTT = Z

((V

+ V

) / (V

– 2)) – 2

3.3V

125Ω125Ω

84Ω84Ω

Zo = 50Ω

FOUT FIN

The clock layout topology shown below is a typical ter-

mination for LVPECL outputs. The two different layouts

mentioned are recommended only as guidelines.

FOUT and nFOUT are low impedance follower outputs

that generate ECL/LVPECL compatible outputs. There-

fore, terminating resistors (DC current path to ground)

or current sources must be used for functionality. These

FIGURE 4B. LVPECL OUTPUT T ERMINATIONFIGURE 4A. LVPECL OUTPUT T ERMINATION

outputs are designed to drive 50Ω transmission lines.

Matched impedance techniques should be used to maxi-

mize operating frequency and minimize signal distor-

tion. Figures 4A and 4B show two different layouts which

are recommended only as guidelines. Other suitable

clock layouts may exist and it would be recommended

that the board designers simulate to guarantee compat-

ibility across all printed circuit and clock component pro-

cess variations.

INPUTS:

CRYSTAL INPUT:

For applications not requiring the use of the crystal oscillator

input, both XTAL_IN and XTAL_OUT can be left floating. Though

not required, but for additional protection, a 1kΩ resistor can be

tied from XTAL_IN to ground.

CLK INPUT:

For applications not requiring the use of the test clock, it can be

left floating. Though not required, but for additional protection, a

1kΩ resistor can be tied from the CLK input to ground.

LVCMOS CONTROL PINS:

All control pins have internal pull-ups or pull-downs; additional

resistance is not required but can be added for additional

protection. A 1kΩ resistor can be used.

RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS

OUTPUTS:

LVPECL OUTPUT

All unused LVPECL outputs can be left floating. We recommend

that there is no trace attached. Both sides of the differential output

pair should either be left floating or terminated.

843101AGI-100 www.icst.com/products/hiperclocks.html REV. A OCTOBER 20, 2005

Integrated

Circuit

Systems, Inc.

ICS843101I-100

FEMTOCLOCKS™ C RYSTAL-TO-LVPECL

100MHZ FREQUENCY MARGINING SYNTHESIZER

PRELIMINARY

TERMINATION FOR 2.5V LVPECL OUTPUT

Figure 5A and Figure 5B show examples of termination for

2.5V LVPECL driver. These terminations are equivalent to

terminating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is

very close to ground level. The R3 in Figure 4B can be

eliminated and the termination is shown in Figure 4C.

FIGURE 5C. 2.5V LVPECL TERMINATION EXAMPLE

FIGURE 5B. 2.5V LVPECL DRIVER T ERMINATION EXAMPLE

FIGURE 5A. 2.5V LVPECL DRIVER T ERMINATION EXAMPLE

62.5

Zo = 50 Ohm

250

2.5V

2,5V LVPECL

Driv er

62.5

250

Zo = 50 Ohm

2.5V

VCC=2.5V

Zo = 50 Ohm

2,5V LVPECL

Driver

VCC=2.5V

2.5V

2,5V LVPECL

Driv er

VCC=2.5V

2.5V

Zo = 50 Ohm

843101AGI-100 www.icst.com/products/hiperclocks.html REV. A OCTOBER 20, 2005

Integrated

Circuit

Systems, Inc.

ICS843101I-100

FEMTOCLOCKS™ C RYSTAL-TO-LVPECL

100MHZ FREQUENCY MARGINING SYNTHESIZER

PRELIMINARY

POWER CONSIDERATIONS

This section provides information on power dissipation and junction temperature for the ICS843101I-100.

Equations and example calculations are also provided.

1. P ower Dissipation.

The total power dissipation for the ICS843101I-100 is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

•Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 92mA = 318.78mW

•Power (outputs)MAX = 30mW/Loaded Output pair

Total Power_MAX (3.63V, with all outputs switching) = 318.78mW + 30mW = 348.78mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the

device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.

The equation for Tj is as follows: Tj = θJA * Pd_total + TA

Tj = Junction Temperature

θJA = Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

TA = Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA

must be used. Assuming a

moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 81.8°C/W per Table 7 below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.349W *81.8°C/W = 113.5°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,

and the type of board (single layer or multi-layer).

θθ

θJA by Velocity (Linear Feet per Minute)

0 200 500

Single-Layer PCB, JEDEC Standard Test Boards 137.1°C/W 118.2°C/W 106.8°C/W

Multi-Layer PCB, JEDEC Standard Test Boards 89.0°C/W 81.8°C/W 78.1°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

TABLE 7. THERMAL RESISTANCE θθ

θθ

θJA FOR 16-PIN TSSOP, FORCED CONVECTION

843101AGI-100 www.icst.com/products/hiperclocks.html REV. A OCTOBER 20, 2005

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ICS843101I-100

FEMTOCLOCKS™ C RYSTAL-TO-LVPECL

100MHZ FREQUENCY MARGINING SYNTHESIZER

PRELIMINARY

3. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load.

LVPECL output driver circuit and termination are shown in Figure 5.

To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination

voltage of V

CCO

- 2V.

• For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V

(VCCO_MAX - VOH_MAX

) = 0.9V

• For logic low, VOUT = VOL_MAX = VCCO_MAX

– 1.7V

(VCCO_MAX - VOL_MAX

) = 1.7V

Pd_H is power dissipation when the output drives high.

Pd_L is the power dissipation when the output drives low.

Pd_H = [(VOH_MAX

– (VCCO_MAX

- 2V))/R

] * (VCCO_MAX

- VOH_MAX) = [(2V - (VCCO_MAX - VOH_MAX

))/R

] * (VCCO_MAX

- VOH_MAX) =

[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW

Pd_L = [(VOL_MAX

– (VCCO_MAX

- 2V))/R

] * (VCCO_MAX

- VOL_MAX) = [(2V - (VCCO_MAX - VOL_MAX

))/R

] * (VCCO_MAX

- VOL_MAX) =

[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW

Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW

FIGURE 5. LVPECL DRIVER CIRCUIT AND T ERMINATION

VOUT

VCCO

VCCO - 2V

843101AGI-100 www.icst.com/products/hiperclocks.html REV. A OCTOBER 20, 2005

Integrated

Circuit

Systems, Inc.

ICS843101I-100

FEMTOCLOCKS™ C RYSTAL-TO-LVPECL

100MHZ FREQUENCY MARGINING SYNTHESIZER

PRELIMINARY

RELIABILITY INFORMATION

TRANSISTOR COUNT

The transistor count for ICS843101I-100 is: 4093

TABLE 9. θJAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP

θθ

θJA by Velocity (Linear Feet per Minute)

0 200 500

Single-Layer PCB, JEDEC Standard Test Boards 137.1°C/W 118.2°C/W 106.8°C/W

Multi-Layer PCB, JEDEC Standard Test Boards 89.0°C/W 81.8°C/W 78.1°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

843101AGI-100 www.icst.com/products/hiperclocks.html REV. A OCTOBER 20, 2005

Integrated

Circuit

Systems, Inc.

ICS843101I-100

FEMTOCLOCKS™ C RYSTAL-TO-LVPECL

100MHZ FREQUENCY MARGINING SYNTHESIZER

PRELIMINARY

PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP

TABLE 10. PACKAGE DIMENSIONS

Reference Document: JEDEC Publication 95, MO-153

LOBMYS sretemilliM

muminiMmumixaM

N61

A--02.1

1A50.051.0

2A08.050.1

b91.003.0

c90.002.0

D09.401.5

ECISAB04.6

1E03.405.4

eCISAB56.0

4.057.0

α°0°8

aaa--01.0

843101AGI-100 www.icst.com/products/hiperclocks.html REV. A OCTOBER 20, 2005

Integrated

Circuit

Systems, Inc.

ICS843101I-100

FEMTOCLOCKS™ C RYSTAL-TO-LVPECL

100MHZ FREQUENCY MARGINING SYNTHESIZER

PRELIMINARY

TABLE 11. ORDERING INFORMATION

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use

or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use

in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not

recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product

for use in life support devices or critical medical instruments.

The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.

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