HD74HC161FPEL - Renesas Electronics

To our custo mers,

Old Company Name in Catalogs and Other Documents

On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology

Corporation, and Renesas Electronics Corpor ation took over all the business of both

companies. Therefore, althoug h the old com pany name remains in this docum ent, it is a valid

Renesas Electronics document. W e appreciate your understanding.

Renesas Electronics website: http://www.renesas.com

April 1st, 2010

Renesas Electronics Corporation

Issued by: Renesas Electronics Corporation (http://www.renesas.com)

Send any inquiries to http://www.renesas.com/inquiry.

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Rev.2.00, Oct 11, 2005 page 1 of 14

HD74HC160/HD74HC161/HD74HC162/

HD74HC163

Synchronous Decade Counter (Direct Clear)

Synchronous 4-bit Binary Counter (Direct Clear)

Synchronous Decade Counter (Synchronous Clear)

Synchronous 4-bit Binary Counter (Synchronous Clear) REJ03D0579-0200

(Previous ADE-205-4 55)

Rev.2.00

Oct 11, 2005

Description

The HD74HC160 and the HD74HC162 are 4 bit decade counters, and the HD74HC161 and the HD74HC163 are 4 bit

binary counters All flip-flops are clocked simultaneously on the low to high to transition (positive edge) of the clock

input waveform.

These counters may be preset usi n g the load input. Presetting of all four flip-flops is synchronous to the risin g edge of

clock. When load is held low co unting is disabled and the data on the A, B, C, and D inputs is lo ad ed into the counter

on the rising edge of clock. If the load input is taken high before the positive edge of clock the count operation will be

unaffected.

All of these counters may be cleared by the utilizing clear input. The clear function on the HD74HC162 and

HD74HC163 counters are synchronous to the clock. That is, the counters are cleared on the positive edge of clock

while the clear input is held low.

The HD74HC160 and HD74HC161 counters are cleared asynchronously. When the clear is taken low the counter is

cleared immediately regardless of the clock.

Two active high enable inputs Enable P and Enable T and a ripple carry output are provided to enable easy cascading of

counters. Both enable inputs must be high to count. The Enable T input also enables the Ripple Carry output. When

enabled, the Ripple Carry outputs a positive pulse when the counter overflows. This pulse is approximately equal in

duration to the high level portion of the QA outputs. The Ripple Carry o utput is fed to successive cascaded stages to

facilitate easy implementation of N-bit counters.

Features

• High Speed Operation: tpd (Clock to Q) = 18 ns typ (CL = 50 pF)

• High O utput Current: Fa nout of 10 LSTTL Loa ds

• Wide Operating Voltage: VCC = 2 to 6 V

• Low Input Current: 1 µA max

• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)

HD74HC160, HD74HC161, HD74HC162, HD74HC163

Rev.2.00, Oct 11, 2005 page 2 of 14

• Ordering Info rmation

Part Name Package Type Package Code

(Previous Code) Package

Abbreviation Taping Abbreviation

(Quantity)

HD74HC160P

HD74HC161P

HD74HC162P

HD74HC163P

DILP-16 pin PRDP0016AE-B

(DP-16FV) P —

HD74HC160FPEL

HD74HC161FPEL

HD74HC162FPEL

HD74HC163FPEL

SOP-16 pin (JEITA) PRSP0016DH-B

(FP-16DAV) FP EL (2,000 pcs/reel)

HD74HC160RPEL

HD74HC162RPEL

HD74HC163RPEL SOP-16 pin (JEDEC) PRSP0016DG-A

(FP-16DNV) RP EL (2,500 pcs/reel)

HD74HC161TELL TSSOP-16 pin PTSP0016JB-A

(TTP-16DAV) T ELL (2,000 pcs/reel)

Note: Please consult the sales office for the above package availability.

Function Table

Inputs Outputs

Clock Clear*1 Load Enable P Enable T Qn

L X X X Reset-clear

H L X X Load input data

H H H H Count

H H L X No count

H H X L No count

H : High level L : Low level X : Irrelevant

Note: 1. 162 and 163 Only-160 and 161 are Asynchronous Clear Devices

Decade Counter Binary Counter

Asynchronous clear HD74HC160 HD74HC161

Synchronous cl ear HD74HC162 HD74HC163

Pin Arrangement

Clear

Clock

Enable P

GND

VCC

Enable T

Load

(Top view)

Ripple

Carry

Ripple

Carry Output

Outputs

Data

Inputs

CLR

Load

HD74HC160, HD74HC161, HD74HC162, HD74HC163

Rev.2.00, Oct 11, 2005 page 3 of 14

Logic Diagram

HD74HC160

Decade Counter with Asynchronous Clear

Ripple

Carry

Output

CLR

Load

Clock

Clear

Enable T

Enable P

CLR

Load

CLR

Load

VCC

CLR

Load

CLR

Load

HD74HC160, HD74HC161, HD74HC162, HD74HC163

Rev.2.00, Oct 11, 2005 page 4 of 14

HD74HC161

4-bit Binary Counter with Asynchronous Clear

Ripple

Carry

Output

CLR

Load

Clock

Clear

Enable T

Enable P

CLR

Load

CLR

Load

CLR

Load

CLR

Load

HD74HC160, HD74HC161, HD74HC162, HD74HC163

Rev.2.00, Oct 11, 2005 page 5 of 14

HD74HC162

Decade Counter with Synchronous Clear

RCO

CLR

LD·CLR

CLR

LD·CLR

CLR

LD·CLR

CLR

LD·CLR

CLR

LD·CLR

CLR

HD74HC160, HD74HC161, HD74HC162, HD74HC163

Rev.2.00, Oct 11, 2005 page 6 of 14

HD74HC163

4-bit Binary Counter with Synchronous Clear

RCO

CLR

LD·CLR

CLR

LD·CLR

CLR

LD·CLR

CLR

LD·CLR

CLR

LD·CLR

CLR

HD74HC160, HD74HC161, HD74HC162, HD74HC163

Rev.2.00, Oct 11, 2005 page 7 of 14

Timing Diagram

HD74HC160/HD74HC162

Sequence illustrated in wavefo rms.

1. Clear outputs to zero.

2. Preset to BCD seven.

3. Count to eight, nine, zero, one, two and three.

4. Inhibit

(Asynchronous)Clear(HC160)

Clear(HC162)

Clock(HC160)

Ripple

Carry

Output

Clear Load Count

0987321

Inhibit

Clock(HC162)

Enable P

Enable T

Load

Data

Inputs

Count

Enables

Outputs

(Synchronous)

HD74HC160, HD74HC161, HD74HC162, HD74HC163

Rev.2.00, Oct 11, 2005 page 8 of 14

HD74HC161/HD74HC163

Sequence illustrated in wavefo rms.

1. Clear outputs to zero.

2. Preset to binary twelve.

3. Count to thirteen, fourteen, fifteen, zero, one and two.

4. Inhibit

(Asynchronous)Clear(HC161)

Clear(HC163)

Clock(HC161)

Ripple

Carry

Output

Clear Load Count

15141312 210

Inhibit

Clock(HC163)

Enable P

Enable T

Load

Data

Inputs

Count

Enables

Outputs

(Synchronous)

HD74HC160, HD74HC161, HD74HC162, HD74HC163

Rev.2.00, Oct 11, 2005 page 9 of 14

Absolute Maximum Ratings

Item Symbol Rating Unit

Supply voltage range VCC –0.5 to +7.0 V

Input voltage VIN –0.5 to VCC + 0.5 V

Output voltage VOUT –0.5 to VCC + 0.5 V

Output current IOUT ±25 mA

DC current drain per VCC, GND ICC, IGND ±50 mA

DC input diode current IIK ±20 mA

DC output diode current IOK ±20 mA

Power dissipation per package PT 500 mW

Storage temperature Tstg –65 to +150 °C

Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of

which may be realized at the same time.

Recommended Operating Conditions

Item Symbol Ratings Unit Conditions

Supply voltage VCC 2 to 6 V

Input / Output voltage VIN, VOUT 0 to VCC V

Operating temperature Ta –40 to 85 °C

0 to 1000 VCC = 2.0 V

0 to 500 VCC = 4.5 V

Input rise / fall time*1 t

r, tf 0 to 400 ns VCC = 6.0 V

Note: 1. This item guarantees maximum limit when one input switches.

Waveform: Refer to test circuit of switching characteristics.

Electrical Characteristics

Ta = 25°C Ta = –40 to+85°C

Item Symbol VCC (V) Min Typ Max Min Max Unit Test Conditions

2.0 1.5 — — 1.5 —

4.5 3.15 — — 3.15 —

VIH

6.0 4.2 — — 4.2 —

2.0 — — 0.5 — 0.5

4.5 — — 1.35 — 1.35

Input voltage

VIL

6.0 — — 1.8 — 1.8

2.0 1.9 2.0 — 1.9 —

4.5 4.4 4.5 — 4.4 —

6.0 5.9 6.0 — 5.9 —

IOH = –20 µA

4.5 4.18 — — 4.13 — IOH = –4 mA

VOH

6.0 5.68 — — 5.63 —

V Vin = VIH or VIL

IOH = –5.2 mA

2.0 — 0.0 0.1 — 0.1

4.5 — 0.0 0.1 — 0.1

6.0 — 0.0 0.1 — 0.1

IOL = 20 µA

4.5 — — 0.26 — 0.33 IOL = 4 mA

Output voltage

VOL

6.0 — — 0.26 — 0.33

V Vin = VIH or VIL

IOL = 5.2 mA

Input current Iin 6.0 — — ±0.1 — ±1.0 µA Vin = VCC or GND

Quiescent su pply

current ICC 6.0 — — 4.0 — 40 µA Vin = VCC or GND, Iout = 0 µA

HD74HC160, HD74HC161, HD74HC162, HD74HC163

Rev.2.00, Oct 11, 2005 page 10 of 14

Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns)

Ta = 25°C Ta = –40 to +85°C

Item Symbol VCC (V) Min Typ Max Min Max Unit Test Conditions

2.0 — — 5 — 4

4.5 — — 25 — 20

Maximum clock

frequency fmax

6.0 — — 29 — 23

MHz

2.0 — — 160 — 200

4.5 — 18 32 — 40

6.0 — — 27 — 34

ns Clock to Q

2.0 — — 225 — 280

4.5 — 23 45 — 56

6.0 — — 38 — 48

ns Clear to Q

(HC160, HC161 only)

2.0 — — 150 — 190

4.5 — 15 30 — 38

6.0 — — 26 — 33

ns Enable T to Ripple Carry

output

2.0 — — 200 — 250

4.5 — 16 40 — 50

Propagation delay

time tPLH, tPHL

6.0 — — 34 — 43

ns Clock to Ripple carry output

2.0 125 — — 156 —

4.5 25 9 — 31 —

6.0 21 — — 26 —

ns Data to Clock

2.0 125 — — 156 —

4.5 25 15 — 31 —

6.0 21 — — 26 —

ns Load to Clock

2.0 125 — — 156 —

4.5 25 — — 31 —

Setup time tsu

6.0 21 — — 26 —

ns Clear to Clock

(HC162, HC163 only)

2.0 0 — — 0 —

4.5 0 –7 — 0 —

Hold time th

6.0 0 — — 0 —

2.0 100 — — 125 —

4.5 20 7 — 25 —

Remo val time trem

6.0 17 — — 21 —

2.0 80 — — 100 —

4.5 16 6 — 20 —

Pulse width tw

6.0 14 — — 17 —

2.0 — — 75 — 95

4.5 — 5 15 — 19

Output rise/fall

time tTLH, tTHL

6.0 — — 13 — 16

Input capacitan ce Cin — — 5 10 — 10 pF

HD74HC160, HD74HC161, HD74HC162, HD74HC163

Rev.2.00, Oct 11, 2005 page 11 of 14

Function Table

Count Enable/Disable

Control Inputs Result at Outputs

Load Enable P Enable T QA to QD Ripple Carry Output

H H H Count

L H H No count

High when QA to QD are maximum

X L H No count High when QA to QD are maximum

X H L No count L

X L L No count L

H : High level L : Low level X : Irrelevant

Test Circuit

C includes the probe and fig capacitance.Note:

Measurement point

HD74HC160, HD74HC161, HD74HC162, HD74HC163

Rev.2.00, Oct 11, 2005 page 12 of 14

Waveforms

Clock

Clear

Load

Clock

, Q

Enable T

Ripple

Carry

Output

Clock

Data

50%

, Q

PHL

PLH

50% 50%

50% 50% 50%

PHL

Clock

Ripple

Carry

Output

50%

PLH

PHL

W(H)

W(L)

PLH

rem

PHL

50%

HD74HC160, HD74HC161, HD74HC162, HD74HC163

Rev.2.00, Oct 11, 2005 page 13 of 14

Package Dimensions

7.62

DP-16FV

RENESAS CodeJEITA Package Code Previous Code

MaxNomMin

Dimension in Millimeters

Symbol

Reference

19.2

6.3

5.06

MASS[Typ.]

1.05g

0.51

0.56

1.30

0.19 0.25 0.31

2.29 2.54 2.79

PRDP0016AE-BP-DIP16-6.3x19.2-2.54

20.32

7.4

0.40 0.48

1.12

2.54

1 8

16 9

e c

0.89

( Ni/Pd/Au plating )

0.635

0.15

1.27

5.80 6.20

0.400.34

10.30

FP-16DNV

RENESAS CodeJEITA Package Code Previous Code

MaxNomMin

Dimension in Millimeters

Symbol

Reference

1.75

1.270.600.40

3.95

0.250.140.10

0.46

0.250.200.15

6.10

0.25

1.08

9.90

0.15g

MASS[Typ.]

P-SOP16-3.95x9.9-1.27 PRSP0016DG-A

Index mark

916

Terminal cross section

( Ni/Pd/Au plating )

Detail F

NOTE)

1. DIMENSIONS"*1 (Nom)"AND"*2"

DO NOT INCLUDE MOLD FLASH.

2. DIMENSION"*3"DOES NOT

INCLUDE TRIM OFFSET.

HD74HC160, HD74HC161, HD74HC162, HD74HC163

Rev.2.00, Oct 11, 2005 page 14 of 14

0.80

0.15

1.27

7.50 8.00

0.400.34

10.5

FP-16DAV

RENESAS CodeJEITA Package Code Previous Code

MaxNomMin

Dimension in Millimeters

Symbol

Reference

2.20

0.900.700.50

5.50

0.200.100.00

0.46

0.250.200.15

7.80

0.12

1.15

10.06

0.24g

MASS[Typ.]

P-SOP16-5.5x10.06-1.27 PRSP0016DH-B

16 9

Index mark

Terminal cross section

( Ni/Pd/Au plating )

Detail F

NOTE)

1. DIMENSIONS"*1 (Nom)"AND"*2"

DO NOT INCLUDE MOLD FLASH.

2. DIMENSION"*3"DOES NOT

INCLUDE TRIM OFFSET.

0.65

0.10

0.65

6.20 6.60

0.200.15

5.3

TTP-16DAV

RENESAS CodeJEITA Package Code Previous Code

MaxNomMin

Dimension in Millimeters

Symbol

Reference

1.10

0.60.50.4

4.40

0.100.070.03

0.25

0.200.150.10

6.40

0.13

1.0

5.0

0.05g

MASS[Typ.]

P-TSSOP16-4.4x5-0.65 PTSP0016JB-A

Index mark

16 9

Terminal cross section

( Ni/Pd/Au plating )

Detail F

NOTE)

1. DIMENSIONS"*1 (Nom)"AND"*2"

DO NOT INCLUDE MOLD FLASH.

2. DIMENSION"*3"DOES NOT

INCLUDE TRIM OFFSET.

Keep safety first in your circuit designs!

1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble

may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.

Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary

circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.

Notes regarding these materials

1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's

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2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,

diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.

3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of

publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is

therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product

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The information described here may contain technical inaccuracies or typographical errors.

Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.

Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor

home page (http://www.renesas.com).

4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to

evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes

no responsibility for any damage, liability or other loss resulting from the information contained herein.

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Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.

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