© Semiconductor Components Industries, LLC, 2010
May, 2010 − Rev. 11
1Publication Order Number:
CAT661/D
CAT661
High Frequency 100 mA
CMOS Charge Pump,
Inverter/Doubler
Description
The CAT661 is a charge−pump voltage converter. It can invert a
positive input voltage to a negative output. Only two external
capacitors are needed. With a guaranteed 100 mA output current
capability, the CAT661 can replace a switching regulator and its
inductor. Lower EMI is achieved due to the absence of an inductor.
In addition, the CAT661 can double a voltage supplied from a
battery or power supply. Inputs from 2.5 V to 5.5 V will yield a
doubled, 5 V to 11 V output.
A Frequency Control pin (BOOST/FC) is provided to select either a
high (typically 135 kHz) or low (25 kHz) internal oscillator frequency,
thus allowing quiescent current vs. capacitor size trade−offs to be made.
The 135 kHz frequency is selected when the FC pin is connected to V+.
The operating frequency can also be adjusted with an external capacitor
at the OSC pin or by driving OSC with an external clock.
Both 8−pin DIP and SO packages are available. For die availability,
contact ON Semiconductor marketing.
The CAT661 can replace the MAX660 and the LTC660 in applications
where higher oscillator frequency and smaller capacitors are needed. In
addition, the CAT661 is pin compatible with the 7660/1044, offering an
easy upgrade for applications with 100 mA loads.
Features
•Converts V+ to V− or V+ to 2V+
•Low Output Resistance, 10 W Max.
•High Power Efficiency
•Selectable Charge Pump Frequency of 25 kHz or 135 kHz;
Optimize Capacitor Size
•Low Quiescent Current
•Pin−compatible to MAX660, LTC660 with Higher Frequency
Operation
•Available in 8−pin SOIC and DIP Packages
•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Applications
•Negative Voltage Generator
•Voltage Doubler
•Voltage Splitter
•Low EMI Power Source
•GaAs FET Biasing
•Lithium Battery Power Supply
•Instrumentation
•LCD Contrast Bias
•Cellular Phones, Pagers
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PIN CONFIGURATION
SOIC−8
V SUFFIX
CASE 751BD
PDIP−8
L SUFFIX
CASE 646AA
(Top View)
V+
OSC
LV
OUT
BOOST/FC
CAP+
GND
CAP−
Device Package Shipping
ORDERING INFORMATION
CAT661EVA SOIC−8
(Pb−Free)
100 / Tube
MARKING DIAGRAMS
CAT661EVA−T3 SOIC−8
(Pb−Free)
3,000 /
Tape & Reel
CAT661ELA PDIP−8
(Pb−Free)
50 / Tube
661ELA 661EVA
661ELA = CAT661ELA
661EVA = CAT661EVA or
660EVA = CAT661EVA−T3
1
CAT661
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2
Typical Application
Figure 1. Voltage Inverter
V+
OSC
LV
OUT
CAT661
+
+
V+
OSC
LV
OUT
C1 C1 CAT661
1 mF to
100 mF
CAP+
GND
CAP−
BOOST/FC
1
2
3
4
8
7
6
5
C2 1 mF to
100 mF
+VIN
1.5 V to 5.5 V
Inverted
Negative
Voltage
Output
8
7
6
5
CAP+
GND
CAP−
BOOST/FC
1
2
3
4
1 mF to
100 mF
VIN = 2.5 V
to 5.5 V
1 mF to
100 mF
C2
Doubled
Positive
Voltage
Output
Figure 2. Positive Voltage Doubler
Table 1. PIN DESCRIPTIONS
Circuit Configuration
Pin Number Name Inverter Mode Doubler Mode
1 Boost/FC Frequency Control for the internal oscillator. With an external
oscillator BOOST/FC has no effect.
Same as inverter.
Boost/FC Oscillator Frequency Oscillator Frequency
Open 25 kHz typical, 10 kHz minimum 40 kHz typical
V+ 135 kHz typical, 80 kHz minimum 135 kHz typical, 40 kHz minimum
2 CAP+ Charge Pump Capacitor. Positive terminal. Same as inverter.
3 GND Power Supply Ground. Power supply. Positive voltage input.
4 CAP−Charge pump capacitor. Negative terminal. Same as inverter.
5 OUT Output for negative voltage. Power supply ground.
6LV Low−Voltage selection pin. When the input voltage is less
than 3 V, connect LV to GND. For input voltages above 3 V,
LV may be connected to GND or left open. If OSC is driven
externally, connect LV to GND.
LV must be tied to OUT for all input
voltages.
7 OSC Oscillator control input. An external capacitor can be connec-
ted to lower the oscillator frequency. An external oscillator
can drive OSC and set the chip operating frequency. The
charge−pump frequency is one−half the frequency at OSC.
Same as inverter. Do not overdrive OSC
in doubling mode. Standard logic levels
will not be suitable. See the applications
section for additional information.
8 V+ Power supply. Positive voltage input. Positive voltage output.
CAT661
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3
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameters Ratings Units
V+ to GND 6 V
Input Voltage (Pins 1, 6 and 7) −0.3 to (V+ + 0.3) V
BOOST/FC and OSC Input Voltage The least negative of (Out − 0.3 V) or
(V+ − 6 V) to (V+ + 0.3 V)
V
Output Short−circuit Duration to GND
(OUT may be shorted to GND for 1 sec without damage but shorting OUT
to V+ should be avoided.)
1 sec.
Continuous Power Dissipation (TA = 70°C)
Plastic DIP
SO
TDFN
730
500
1
mW
mW
W
Storage Temperature −65 to +160 °C
Lead Soldering Temperature (10 sec) 300 °C
ESD Rating − Human Body Model 2000 V
Operating Ambient Temperature Range −40 to +85 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
NOTE: TA = Ambient Temperature
Table 3. ELECTRICAL CHARACTERISTICS (V+ = 5 V, C1 = C2 = 100 mF, Boost/FC = Open, COSC = 0 pF, and Test Circuit is
Figure 3 unless otherwise noted. Temperature is TA = TAMIN to TAMAX unless otherwise noted.)
Parameter Symbol Conditions Min Typ Max Units
Supply Voltage VS Inverter: LV = Open, RL = 1 kW3.0 5.5 V
Inverter: LV = GND, RL = 1 kW1.5 5.5
Doubler: LV = OUT, RL = 1 kW2.5 5.5
Supply Current IS BOOST/FC = open, LV = Open 0.2 0.5 mA
BOOST/FC = V+, LV = Open 1 3
Output Current IOUT OUT is more negative than −4 V 100 mA
Output Resistance RO C1 = C2 = 10 mF
BOOST/FC = V+ (C1, C2 ESR ≤ 0.5 W)
3.5 10 W
C1 = C2 = 100 mF (Note 2) 3.5 10
Oscillator Frequency
(Note 3)
FOSC BOOST/FC = Open 10 25 kHz
BOOST/FC = V+ 80 135
OSC Input Current IOSC BOOST/FC = Open
BOOST/FC = V+
±2
±10
mA
Power Efficiency PE RL = 1 kW connected between V+ and OUT,
TA = 25°C (Doubler)
96 98 %
RL = 500 W connected between GND and OUT,
TA = 25°C (Inverter)
92 96
IL = 100 mA to GND, TA = 25°C (Inverter) 88
Voltage Conversion
Efficiency
VEFF No load, TA = 25°C 99 99.9 %
1. In Figure 3, test circuit electrolytic capacitors C1 and C2 are 100 mF and have 0.2 W maximum ESR. Higher ESR levels may reduce efficiency
and output voltage.
2. The output resistance is a combination of the internal switch resistance and the external capacitor ESR. For maximum voltage and efficiency
keep external capacitor ESR under 0.2 W.
3. FOSC is tested with COSC = 100 pF to minimize test fixture loading. The test is correlated back to COSC = 0 pF to simulate the capacitance
at OSC when the device is inserted into a test socket without an external COSC.
CAT661
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4
Voltage Inverter
Figure 3. Test Circuit Voltage Inverter
CAT661
External
Oscillator
C2
100 mF
+
BOOST/FC V+
OSC
LV
OUT
C1
100 mF
V+1
2
3
4
CAP+
CAP−
GND
8
7
6
5
ISV+
5 V
COSC
RL
IL
VOUT
+
TYPICAL OPERATING CHARACTERISTICS
(Typical characteristic curves are generated using the test circuit in Figure 3. Inverter test conditions are: V+ = 5 V, LV = GND,
BOOST/FC = Open and TA = 25°C unless otherwise indicated. Note that the charge−pump frequency is one−half the oscillator frequency.)
Figure 4. Supply Current vs. Input Voltage Figure 5. Supply Current vs. Temperature
(No Load)
INPUT VOLTAGE (V) TEMPERATURE (°C)
654321
0
200
600
800
1000
1400
1251007550250−25−50
0
50
100
150
200
250
Figure 6. Output Resistance vs. Input Voltage Figure 7. Output Resistance vs. Temperature
(50 W Load)
INPUT VOLTAGE (V) TEMPERATURE (°C)
654321
0
2
4
6
8
10
1251007550250−25−50
2
3
4
5
6
7
8
INPUT CURRENT (mA)
INPUT CURRENT (mA)
OUTPUT RESISTANCE (W)
OUTPUT RESISTANCE (W)
FC = V+
VIN = 5 V
VIN = 3 V
VIN = 2 V
VIN = 2 V
VIN = 3 V
VIN = 5 V
FC = open
400
1200
CAT661
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TYPICAL OPERATING CHARACTERISTICS
Figure 8. Inverted Output Voltage vs. Load,
V+ = 5 V
Figure 9. Output Voltage Drop vs. Load
Current
LOAD CURRENT (mA) LOAD CURRENT (mA)
100806040200
4.0
4.2
4.4
4.6
4.8
5.0
100806040200
0
0.2
0.4
0.6
0.8
1.0
Figure 10. Oscillator Frequency vs. Supply
Voltage
Figure 11. Oscillator Frequency vs. Supply
Voltage
SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)
65431
0
20
30
50
65431
0
40
120
160
200
Figure 12. Supply Current vs. Oscillator
Frequency
OSCILLATOR FREQUENCY (kHz)
1,000100101
10
100
1,000
10,000
INV. OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
FREQUENCY (kHz)
FREQUENCY (kHz)
INPUT CURRENT (mA)
10
40
FC = Open
V+ = 5 V
V+ = 3 V
FC = V+
No Load
Figure 13. Efficiency vs. Load Current
LOAD CURRENT (mA)
1005040100
40
50
70
80
100
EFFICIENCY (%)
2
80
2
60
90
20 30 60 70 80 90
V+ = 5 V
V+ = 3 V
CAT661
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6
Voltage Doubler
Figure 14. Test Circuit Voltage Doubler
CAT661
External
Oscillator
C2
100 μF
10 V
+
BOOST/FC V+
OSC
LV
OUT
V+
5 V
1
2
3
4
8
7
6
5
CAP+
GND
CAP−
C1
100 mF
VOUT
V+
TYPICAL OPERATING CHARACTERISTICS
(Typical characteristic curves are generated using the circuit in Figure 14. Doubler test conditions are:
V+ = 5 V, LV = GND, BOOST/FC = Open and TA = 25°C unless otherwise indicated.)
V+ = 5 V
Figure 15. Supply Current vs. Input Voltage
(No Load)
Figure 16. Output Resistance vs. Input Voltage
INPUT VOLTAGE (V) INPUT VOLTAGE (V)
654320
0
500
1000
1500
2000
3000
654321
0
2
4
6
8
10
Figure 17. Supply Current vs. Oscillator
Frequency
Figure 18. Output Voltage Drop vs. Load
Current
OSCILLATOR FREQUENCY (kHz) LOAD CURRENT (mA)
1,000100101
10
100
1,000
10,000
100806040200
0
0.2
0.4
0.6
0.8
1.0
INPUT CURRENT (mA)
OUTPUT RESISTANCE (W)
INPUT CURRENT (mA)
OUTPUT VOLTAGE (V)
FC = V+
V+ = 3 V
FC = open
2500
1
No Load
CAT661
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7
Application Information
Circuit Description and Operating Theory
The CAT661 switches capacitors to invert or double an
input voltage.
Figure 19 shows a simple switch capacitor circuit. In
position 1 capacitor C1 is charged to voltage V1. The total
charge on C1 is Q1 = C1V1. When the switch moves to
position 2, the input capacitor C1 is discharged to voltage
V2. After discharge, the charge on C1 is Q2 = C1V2.
The charge transferred is:
DQ+Q1 *Q2 +C1 (V1 *V2)
If the switch is cycled “F” times per second, the current
(charge transfer per unit time) is:
I+F DQ+F C1 (V1 *V2)
Rearranging in terms of impedance:
I+(V1 *V2)
(1ńFC1) +V1 *V2
REQ
The 1/FC1 term can be modeled as an equivalent
impedance REQ. A simple equivalent circuit is shown in
Figure 20. This circuit does not include the switch resistance
nor does it include output voltage ripple. It does allow one
to understand the switch−capacitor topology and make
prudent engineering tradeoffs.
For example, power conversion efficiency is set by the
output impedance, which consists of REQ and switch
resistance. As switching frequency is decreased, REQ, the
1/FC1 term, will dominate the output impedance, causing
higher voltage losses and decreased efficiency. As the
frequency is increased quiescent current increases. At high
frequency this current becomes significant and the power
efficiency degrades.
The oscillator is designed to operate where voltage losses
are a minimum. With external 150 mF capacitors, the internal
switch resistances and the Equivalent Series Resistance
(ESR) of the external capacitors determine the effective
output impedance.
A block diagram of the CAT661 is shown in Figure 21.
Figure 19. Switched−Capacitor Building Block Figure 20. Switched−Capacitor Equivalent Circuit
V1
C1
V2 V1 V2
REQ
C2
RLRL
C2
REQ +1
FC1
CAT661
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Oscillator Frequency Control
The switching frequency can be raised, lowered or driven
from an external source. Figure 22 shows a functional
diagram of the oscillator circuit.
The CAT661 oscillator has four control modes:
Table 4.
BOOST/FC
Pin Connection
OSC Pin
Connection
Nominal
Oscillator
Frequency
Open Open 25 kHz
BOOST/FC = V+ Open 135 kHz
Open or
BOOST/FC = V+
External Capacitor −
Open External Clock Frequency of
external clock
If BOOST/FC and OSC are left floating (Open), the
nominal oscillator frequency is 25 kHz. The pump
frequency is one−half the oscillator frequency.
By connecting the BOOST/FC pin to V+, the charge and
discharge currents are increased, and the frequency is
increased by approximately 6 times. Increasing the
frequency will decrease the output impedance and ripple
currents. This can be an advantage at high load currents.
Increasing the frequency raises quiescent current but allows
smaller capacitance values for C1 and C2.
If pin 7, OSC, is loaded with an external capacitor the
frequency is lowered. By using the BOOST/FC pin and an
external capacitor at OSC, the operating frequency can be
set.
Note that the frequency appearing at CAP+ or CAP− is
one−half that of the oscillator.
Driving the CAT661 from an external frequency source
can be easily achieved by driving Pin 7 and leaving the
BOOST pin open, as shown in Figure 22. The output current
from Pin 7 is small, typically 1 mA to 8 mA, so a CMOS can
drive the OSC pin. For 5 V applications, a TTL logic gate can
be used if an external 100 kΩ pull−up resistor is used as
shown in Figure 23.
Figure 21. CAT661 Block Diagram
+
C2
OSC
BOOST/FC
OSC
(7)
GND
(3)
C1
+
(2)
SW2
SW1
VOUT
(5)
(N) = Pin Number
LV
(6)
8x
(1)
f
f
B2
V+
(8)
CLOSED WHEN
V+ > 3.0 V
CAP+
(4)
CAP−
CAT661
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Capacitor Selection
Low ESR capacitors are necessary to minimize voltage
losses, especially at high load currents. The exact values of
C1 and C2 are not critical but low ESR capacitors are
necessary.
The ESR of capacitor C1, the pump capacitor, can have a
pronounced effect on the output. C1 currents are
approximately twice the output current and losses occur on
both the charge and discharge cycle. The ESR effects are
thus multiplied by four. A 0.5 Ω ESR for C1 will have the
same effect as a 2 Ω increase in CAT661 output impedance.
Output voltage ripple is determined by the value of C2 and
the load current. C2 is charged and discharged at a current
roughly equal to the load current. The internal switching
frequency is one−half the oscillator frequency.
VRIPPLE +IOUTń(FOSC C2) )IOUT ESRC2
For example, with a 25 kHz oscillator frequency
(12.5 kHz switching frequency), a 150 mF C2 capacitor with
an ESR of 0.2 Ω and a 100 mA load peak−to−peak ripple
voltage is 45 mV.
Table 5. VRIPPLE vs. FOSC
VRIPPLE (mV) IOUT (mA) FOSC (kHz) C2 (mF) C2 ESR (W)
45 100 25 150 0.2
25 100 135 150 0.2
Figure 22. Oscillator Figure 23. External Clocking
+C2
REQUIRED FOR TTL LOGIC
CAT661
100 k OSC
NC
+
C1
BOOST/FC V+
OSC
LV
OUT
BOOST/FC
(1)
OSC
(7)
~18 pF
I
7.0 I
I
7.0 I
V+
LV
(6)
INPUT
V+
−V+
CAP+
GND
CAP−
1
2
3
4
8
7
6
5
CAT661
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Capacitor Suppliers
The following manufacturers supply low−ESR capacitors:
Table 6. CAPACITOR SUPPLIERS
Manufacturer Capacitor Type Phone WEB Email Comments
AVX/Kyocera TPS/TPS3 843−448−9411 www.avxcorp.com avx@avxcorp.com Tantalum
Vishay/Sprague 595 402−563−6866 www.vishay.com −Aluminum
Sanyo MV−AX, UGX 619−661−6835 www.sanyo.com Svcsales@sanyo.com Aluminum
Nichicon F55 847−843−7500 www.nichicon−us.com −Tantalum
HC/HD Aluminum
Capacitor manufacturers continually introduce new series and offer different package styles. It is recommended that before
a design is finalized capacitor manufacturers should be surveyed for their latest product offerings.
Controlling Loss in CAT661 Applications
There are three primary sources of voltage loss:
1. Output resistance:
VLOSS = ILOAD x ROUT, where ROUT is the
CAT661 output resistance and ILOAD is the load
current.
2. Charge pump (C1) capacitor ESR:
VLOSSC1 ≈ 4 x ESRC1 x ILOAD, where
ESRC1 is the ESR of capacitor C1.
3. Output or reservoir (C2) capacitor ESR:
VLOSSC2 = ESRC2 x ILOAD, where ESRC2 is
the ESR of capacitor C2.
Increasing the value of C2 and/or decreasing its ESR will
reduce noise and ripple.
The effective output impedance of a CAT661 circuit is
approximately:
Rcircuit [Rout 661 )(4 ESRC1) )ESRC2
CAT661
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Typical Applications
Voltage Inversion Positive−to−Negative
The CAT661 easily provides a negative supply voltage from a positive supply in the system. Figure 24 shows a typical circuit.
The LV pin may be left floating for positive input voltages at or above 3.3 V.
Figure 24. Voltage Inverter
+
C2
CAT661
NC
+
C1
BOOST/FC V+
OSC
LV
OUT
1
2
3
4
8
7
6
5
CAP+
CAP−
GND
VIN
1.5 V to 5.5 V
VOUT = −VIN
Positive Voltage Doubler
The voltage doubler circuit shown in Figure 25 gives VOUT = 2 x VIN for input voltages from 2.5 V to 5.5 V.
Figure 25. Voltage Doubler
CAT661
+
BOOST/FC +
2.5 V to 5.5 V
1N5817*
*SCHOTTKY DIODE IS FOR START−UP ONLY
V+
OSC
LV
OUT
C2
150 mF
VOUT = 2VIN
8
7
6
5
1
2
3
4
C1
150 mF
CAP+
CAP−
GND
VIN
CAT661
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Precision Voltage Divider
A precision voltage divider is shown in Figure 26. With load currents under 100 nA, the voltage at pin 2 will be within 0.002%
of V+/2.
Figure 26. Precision Voltage Divider (Load 3 100 nA)
+
+
BOOST/FC V+
OSC
LV
OUT
CAT661
C2
150 mF
C1
150 mF
1
2
3
4
CAP+
CAP−
GND
8
7
6
5
3 V to 11 V
V+
IL ≤ 100 nA
± 0.002%
V)
2
Battery Voltage Splitter
Positive and negative voltages that track each other can be obtained from a battery. Figure 27 shows how a 9 V battery can
provide symmetrical positive and negative voltages equal to one−half the battery voltage.
Figure 27. Battery Splitter
+
CAT661
+
BOOST/FC V+
OSC
LV
OUT
9 V
BATTERY
VBAT
C1
150 mF
3 V ≤ VBAT ≤ 11 V
1
CAP+
CAP−
GND
2
3
4
8
7
6
5
C2
150 mF
*VBAT
2(−4.5 V)
)VBAT
2(4.5 V)
CAT661
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13
Cascade Operation for Higher Negative Voltages
The CAT661 can be cascaded as shown in Figure 28 to generate more negative voltage levels. The output resistance is
approximately the sum of the individual CAT661 output resistance.
VOUT = −N x VIN, where N represents the number of cascaded devices.
Figure 28. Cascading to Increase Output Voltage
+
C2
4
8
5
+
C1
+CAT661
4
8
5
C1N
+
C2
VOUT = −NVIN
3
2
“N”
CAT661
“1”
3
2
+VIN
Parallel Operation
Paralleling CAT661 devices will lower output resistance. As shown in Figure 29, each device requires its own pump
capacitor, C2, but the output reservoir capacitor is shared with all devices. The value of C2 should be increased by a factor of
N, where N is the number of devices.
ROUT +ROUT (of CAT661)
N (NUMBER OF DEVICES)
Figure 29. Reduce Output Resistance BY Paralleling Devices
+
C2
4
8
5
+
C1
+
4
8
5
C1N
CAT661
3
2
“N”
CAT661
“1”
3
2
+VIN
CAT661
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PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
E1 E
A
A1
h
θ
L
c
eb
D
PIN # 1
IDENTIFICATION
TOP VIEW
SIDE VIEW END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
SYMBOL MIN NOM MAX
θ
A
A1
b
c
D
E
E1
e
h
0º 8º
0.10
0.33
0.19
0.25
4.80
5.80
3.80
1.27 BSC
1.75
0.25
0.51
0.25
0.50
5.00
6.20
4.00
L0.40 1.27
1.35
CAT661
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PACKAGE DIMENSIONS
PDIP−8, 300 mils
CASE 646AA−01
ISSUE A
E1
D
A
L
eb
b2
A1
A2
E
eB
c
TOP VIEW
SIDE VIEW END VIEW
PIN # 1
IDENTIFICATION
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-001.
SYMBOL MIN NOM MAX
A
A1
A2
b
b2
c
D
e
E1
L
0.38
2.92
0.36
6.10
1.14
0.20
9.02
2.54 BSC
3.30
5.33
4.95
0.56
7.11
1.78
0.36
10.16
eB 7.87 10.92
E 7.62 8.25
2.92 3.80
3.30
0.46
6.35
1.52
0.25
9.27
7.87
CAT661
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Example of Ordering Information (Note 6)
Prefix Device # Suffix
Company ID
CAT 661
Product Number
661
T3
T: Tape & Reel
3: 3,000 / Reel
Tape & Reel (Note 7)
(Optional)
EVA
Package
ELA: PDIP
EVA: SOIC
4. All packages are RoHS−compliant (Lead−free, Halogen−free).
5. The standard lead finish is Matte−Tin.
6. The device used in the above example is a CAT661EVA−T3 (SOIC, Tape & Reel, 3,000/Reel).
7. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
CAT661/D
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