ESD7561N2T5G - ON SEMICONDUCTOR

February, 2016 − Rev. 0 1Publication Order Number:

ESD7561/D

ESD7561

Ultra-Low Capacitance ESD

Protection

Micro−Packaged Diodes for ESD Protection

The ESD7561 is designed to protect voltage sensitive components

that require ultra−low capacitance from ESD and transient voltage

events. It has industry leading capacitance linearity over voltage

making it ideal for RF applications. This capacitance linearity

combined with the extremely small package and low insertion loss

makes this part well suited for use in antenna line applications for

wireless handsets and terminals.

Features

•Industry Leading Capacitance Linearity Over Voltage

•Ultra−Low Capacitance: 0.3 pF Typ

•Insertion Loss: 0.05 dB at 1 GHz; 0.21 dB at 3 GHz

•Low Leakage: < 1 nA

•Protection for the following IEC Standards:

♦IEC61000−4−2 (ESD): Level 4 ±18 kV Contact

♦IEC61000−4−4 (EFT): 40 A −5/50 ns

♦IEC61000−4−5 (Lightning): 1 A (8/20 ms)

•ISO 10605 (ESD) 330 pF/2 kW ±23 kV Contact

•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

Typical Applications

•RF Signal ESD Protection

•RF Switching, PA, and Antenna ESD Protection

•Near Field Communications

•USB 2.0, USB 3.0

MAXIMUM RATINGS (TA = 25°C unless otherwise noted)

Rating Symbol Value Unit

IEC 61000−4−2 (ESD) (Note 1) ±18 kV

Total Power Dissipation (Note 2) @ TA = 25°C

Thermal Resistance, Junction−to−Ambient °PD°

RqJA 300

400 mW

°C/W

Junction and Storage Temperature Range TJ, Tstg −55 to

+150 °C

Lead Solder Temperature − Maximum

(10 Second Duration) TL260 °C

Stresses exceeding those listed in the Maximum Ratings table may damage the

device. If any of these limits are exceeded, device functionality should not be

assumed, damage may occur and reliability may be af fected.

1. Non−repetitive current pulse at TA = 25°C, per IEC61000−4−2 waveform.

2. Mounted with recommended minimum pad size, DC board FR−4

Device Package Shipping†

ORDERING INFORMATION

www.onsemi.com

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer t o our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

ESD7561N2T5G X2DFN2

(Pb−Free) 8000 / Tape &

Reel

MARKING

DIAGRAM

V = Specific Device Code

M = Date Code

V M

X2DFN2

CASE 714AB

ESD7561

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ELECTRICAL CHARACTERISTICS

(TA = 25°C unless otherwise noted)

Symbol Parameter

IPP Maximum Reverse Peak Pulse Current

VCClamping Voltage @ IPP

VRWM Working Peak Reverse Voltage

IRMaximum Reverse Leakage Current @ VRWM

VBR Breakdown Voltage @ IT

ITTest Current

*See Application Note AND8308/D for detailed explanations of

datasheet parameters. Bi−Directional TVS

IPP

VRWM

VCVBR VRWM VC

VBR

ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)

Parameter Symbol Condition Min Typ Max Unit

Reverse Working Voltage VRWM 16 V

Breakdown Voltage VBR IT = 1 mA (Note 3) 16.5 V

Reverse Leakage Current IRVRWM = 5 V <1 100 nA

Clamping Voltage TLP VCIPP = 8 A (Note 4) 35 V

Clamping Voltage TLP VCIPP = 16 A (Note 4) 39 V

Junction Capacitance CJVR = 0 V, f = 1 MHz

VR = 0 V, f = 1 GHz 0.3

0.3 0.55

0.55 pF

Dynamic Resistance RDYN TLP Pulse 1.05 W

Insertion Loss f = 1 GHz

f = 3 GHz 0.05

0.21 dB

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

3. Breakdown voltage is tested from pin 1 to 2 and pin 2 to 1.

4. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.

TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns.

Figure 1. Typical IV Characteristics Figure 2. Typical CV Characteristics

1.3−03

1.E−04

1.E−05

1.E−06

1.E−07

1.E−08

1.E−09

1.E−10

1.E−11

1.E−12−30 30−20 20−10 100

CURRENT (A)

VOLTAGE (V)

CAPACITANCE (pF)

VOLTAGE (V)

0.8

0.6

0.4

0.2

−18 −15 −12 −9 −6 −3 0 1512963

ESD7561

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TYPICAL CHARACTERISTICS

Figure 3. Typical Insertion Loss

ESD7561N2T5G (SOD882) Figure 4. Typical Capacitance over Frequency

ESD7561N2T5G (SOD882)

1.E+07 1.E+101.E+08 1.E+09

S21 (dB)

FREQUENCY (Hz)

0.5

−0.5

−1

−1.5

−2

−2.5

−3

FREQUENCY (Hz)

CAPACITANCE (pF)

1.E+07 1.E+102.E+09 8.E+096.E+094.E+09

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

ESD7561

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IEC 61000−4−2 Spec.

Level Test Volt-

age (kV)

First Peak

Current

(A) Current at

30 ns (A) Current at

60 ns (A)

1 2 7.5 4 2

2 4 15 8 4

3 6 22.5 12 6

4 8 30 16 8

Ipeak

90%

10%

IEC61000−4−2 W aveform

100%

I @ 30 ns

I @ 60 ns

tP = 0.7 ns to 1 ns

Figure 5. IEC61000−4−2 Spec

Figure 6. Diagram of ESD Clamping Voltage Test Setup

50 W

Cable

TVS Oscilloscope

ESD Gun

The following is taken from Application Note

AND8308/D − Interpretation of Datasheet Parameters

for ESD Devices.

ESD Voltage Clamping

For sensitive circuit elements it is important to limit the

voltage that an IC will be exposed to during an ESD event

to as low a voltage as possible. The ESD clamping voltage

is the voltage drop across the ESD protection diode during

an ESD event per the IEC61000−4−2 waveform. Since the

IEC61000−4−2 was written as a pass/fail spec for larger

systems such as cell phones or laptop computers it is not

clearly defined in the spec how to specify a clamping voltage

at the device level. ON Semiconductor has developed a way

to examine the entire voltage waveform across the ESD

protection diode over the time domain of an ESD pulse in the

form of an oscilloscope screenshot, which can be found on

the datasheets for all ESD protection diodes. For more

information on how ON Semiconductor creates these

screenshots and how to interpret them please refer to

AND8307/D.

ESD7561

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Figure 7. Positive TLP I−V Curve Figure 8. Negative TLP I−V Curve

TLP CURRENT (A)

VC, VOLTAGE (V)

040353051015 2520

TLP CURRENT (A)

VC, VOLTAGE (V)

−25

0 −45−40−35−5 −10 −15 −30

NOTE: TLP parameter: Z0 = 50 W, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns. VIEC is the equivalent voltage

stress level calculated at the secondary peak of the IEC 61000−4−2 waveform at t = 30 ns with 2 A/kV. See TLP description

below for more information.

−20

−15

−10

−5

45 −20 −25

Transmission Line Pulse (TLP) Measurement

Transmission Line Pulse (TLP) provides current versus

voltage (I−V) curves in which each data point is obtained

from a 100 ns long rectangular pulse from a charged

transmission line. A simplified schematic of a typical TLP

system is shown in Figure 9. TLP I−V curves of ESD

protection devices accurately demonstrate the product’s

ESD capability because the 10s of amps current levels and

under 100 ns time scale match those of an ESD event. This

is illustrated in Figure 10 where an 8 kV IEC 61000−4−2

current waveform is compared with TLP current pulses at

8 A and 16 A. A TLP I−V curve shows the voltage at which

the device turns on as well as how well the device clamps

voltage over a range of current levels.

Figure 9. Simplified Schematic of a Typical TLP

System

DUT

Oscilloscope

Attenuator

10 MW

50 W Coax

Cable

50 W Coax

Cable

Figure 10. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms

ESD7561

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PACKAGE DIMENSIONS

X2DFN2 1.0x0.6, 0.65P

CASE 714AB

ISSUE O

ÉÉ

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. EXPOSED COPPER ALLOWED AS SHOWN.

A B

BOTTOM VIEW

0.10 C

TOP VIEW

0.05 C

0.10 C

CSEATING

PLANE

SIDE VIEW

DIM MIN MAX

MILLIMETERS

A0.34 0.40

A1 −−− 0.05

b0.45 0.55

D1.00 BSC

E0.60 BSC

SOLDER FOOTPRINT*

DIMENSIONS: MILLIMETERS

1.20

0.60

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

L0.20 0.30

0.47

RECOMMENDED

PIN 1

INDICATOR

e0.65 BSC

0.05 BC

e/2

2X 2X

NOTE 3

ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.

SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed

at www.onsemi.com/site/pdf/Patent−Marking. pdf. SCILLC reserves the r ight t o make changes without further notice t o any p roducts h erein. S CILLC m akes no warranty, representation

or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and

specifically disclaims any and all l iabilit y, including without limitation special, consequential or i ncident al d amages. “Typical” parameters which m ay b e p r ovided i n SCILLC data sheets

and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each

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USA/Canada

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Phone: 421 33 790 2910

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Phone: 81−3−5817−1050

ESD7561/D

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Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

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