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FEATURES DESCRIPTION
APPLICATIONS
FUNCTIONAL DIAGRAM
1.5 Gbps
223 − 1 PRBS
VCC = 3.3 V
VID = 200 mV, VIC = 1.2 V
Horizontal Scale= 200 ps/div
Vertical Scale=200 mV/div
EYE PATTERNS OF OUTPUTS
OPERATING SIMULTANEOUSLY
MUX
1DE
1A
1B
S0
S1
2A
2B
2DE
1Y
1Z
2Y
2Z
Integrated Termination on SN65LVDT122 Only
OUTPUT 1
OUTPUT 2
110 Ω
110 Ω
SN65LVDS122
SN65LVDT122
SLLS525B – MAY 2002 – REVISED JUNE 2004
1.5-Gbps 2 ×2 LVDS CROSSPOINT SWITCH
•Designed for Signaling Rates
(1)
Up To
The SN65LVDS122 and SN65LVDT122 are1.5 Gbps
crosspoint switches that use low voltage differentialsignaling (LVDS) to achieve signaling rates as high•Total Jitter < 65 ps
as 1.5 Gbps. They are pin-compatible speed up-•Pin-Compatible With SN65LVDS22 and
grades to the SN65LVDS22 and SN65LVDM22. TheSN65LVDM22
internal signal paths maintain differential signaling for•25 mV of Receiver Input Threshold Hysteresis
high speeds and low signal skews. These devicesOver 0-V to 4-V Common-Mode Range
have a 0-V to 4-V common-mode input range thataccepts LVDS, LVPECL, or CML inputs. Two logic•Inputs Electrically Compatible With CML,
pins (S0 and S1) set the internal configuration be-LVPECL and LVDS Signal Levels
tween the differential inputs and outputs. This allows•Propagation Delay Times, 900 ps Maximum
the flexibility to perform the following configurations:•LVDT Integrates 110-ΩTerminating Resistor
2 x 2 crosspoint switch, 2:1 input multiplexer, 1:2splitter or dual repeater/translator within a single•Offered in SOIC and TSSOP
device. Additionally, SN65LVDT122 incorporates a110-Ωtermination resistor for those applicationswhere board space is a premium. Although these•10-G (OC-192) Optical Modules
devices are designed for 1.5 Gbps, some applications•622-MHz Central Office Clock Distribution
at a 2-Gbps data rate can be supported depending onloading and signal quality.•Wireless Basestations•Low Jitter Clock Repeater/Multiplexer
The intended application of this device is ideal forloopback switching for diagnostic routines, fanout•Protection Switching for Serial Backplanes
buffering of clock/data distribution provide protectionin fault-tolerant systems, clock multiplexing in opticalmodules, and for overall signal boosting overextended distances.(1) The signlaing rate of a line is the number of voltage
The SN65LVDS122 and SN65LVDT122 aretransitions that are made per second expressed in the units
characterized for operation from –40°C to 85°C.bps (bits per second).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2002–2004, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
PACKAGE DISSIPATION RATINGS
SN65LVDS122
SN65LVDT122
SLLS525B – MAY 2002 – REVISED JUNE 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the deviceplaced in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PACKAGE TERMINATION RESISTOR PART NUMBER
(1)
SYMBOLIZATION
SOIC No SN65LVDS122D LVDS122SOIC Yes SN65LVDT122D LVDT122TSSOP No SN65LVDS122PW LVDS122TSSOP Yes SN65LVDT122PW LVDT122
(1) Add the suffix R for taped and reeled carrier
over operating free-air temperature range unless otherwise noted
(1)
SN65LVDS122, SN65LVDT122
V
CC
Supply voltage range
(2)
–0.5 V to 4 V(A, B) –0.7 V to 4.3 V|V
A
-V
B
| (LVDT only) 1 VVoltage range
(DE, S0, S1) –0.5 V to 4 V(Y, Z) –0.5 V to 4 VA, B, Y, Z, and GND ±4 kVHuman Body Model
(3)ESD All pins ±2 kVCharged-Device Model
(4)
All pins ±1500 VContinuous power dissipation See Dissipation Rating TableT
stg
Storage temperature range –65°C to 150°CLead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.7.(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
MIN NOM MAX UNIT
V
CC
Supply voltage 3 3.3 3.6 VV
IH
High-level input voltage S0, S1, 1DE, 2DE 2 4 VV
IL
Low-level input voltage S0, S1, 1DE, 2DE 0 0.8 VLVDS 0.1 1|V
ID
| Magnitude of differential input voltage VLVDT 0.1 0.8Input voltage (any combination of common-mode or input signals) 0 4 VT
A
Operating free-air temperature –40 85 °C
T
A
≤25°C DERATING FACTOR
(1)
T
A
= 85°CPACKAGE
POWER RATING ABOVE T
A
= 25°C POWER RATING
PW 712 mW 6.2 mW/°C 340 mWD 1002 mW 8.7 mW/°C 480 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
2
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INPUT ELECTRICAL CHARACTERISTICS
OUTPUT ELECTRICAL CHARACTERISTICS
SN65LVDS122
SN65LVDT122
SLLS525B – MAY 2002 – REVISED JUNE 2004
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
V
IT+
Positive-going differential input voltage threshold See Figure 1 and Table 1 100 mVV
IT-
Negative-going differential input voltage threshold See Figure 1 and Table 1 –100
(2)
mVV
ID(HYS)
Differential input voltage hysteresis (V
IT+
– V
IT-
) 25 mVDE –10 0I
IH
High-level input current V
IH
= 2 µAS0, S1 0 20DE –10 0I
IL
Low-level input current V
IL
= 0.8 V µAS0, S1 20R
L
= 100 Ω80 100I
CC
Supply current mADisabled 35 45V
I
= 0 V or 2.4 V, Other input at 1.2 V –20 20Input current (A or B inputs 'LVDS) µAV
I
= 4 V, Other input at 1.2 V 0 33I
I
V
I
= 0 V or 2.4 V, Other input open –40 40Input current (A or B inputs 'LVDT) µAV
I
= 4 V, Other input open 0 66V
CC
= 1.5 V, V
I
= 0 V or 2.4 V,
–20 20Other input at 1.2 VInput current (A or B inputs 'LVDS) µAV
CC
= 1.5 V, V
I
= 2.4 V or 4 V,
0 33Other input at 1.2 VI
I(OFF)
V
CC
= 1.5 V, V
I
= 0 V or 2.4 V,
–40 40Other input openInput current (A or B inputs 'LVDT) µAV
CC
= 1.5 V, V
I
= 2.4 V or 4 V,
0 66Other input openI
IO
Input offset current (| I
IA
– I
IB
|) 'LVDS V
IA
= V
IB
, 0 ≤V
IA
≤4 V –6 6 µAV
ID
= 300 mV and 500 mV,Termination resistance ('LVDT) 90 110 132V
IC
= 0 V to 2.4 VR
T
ΩV
ID
= 300 mV and 500 mV,Termination resistance ('LVDT with power-off) 90 110 132V
CC
= 1.5 V, V
IC
= 0 V to 2.4 VV
I
= 0.4 sin (4E6πt) + 0.5 V 3Differential input capacitance ('LVDT withC
I
pFpower-off)
Powered down (V
CC
= 1.5 V) 3
(1) All typical values are at 25°C and with a 3.3-V supply.(2) The algebraic convention in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
|V
OD
| Differential output voltage magnitude 247 310 454See Figure 2 mVChange in differential output voltage magnitude between logic∆|V
OD
| –50 50statesV
OC(SS)
Steady-state common-mode output voltage 1.125 1.375 VChange in steady-state common-mode output voltage between∆V
OC(SS)
See Figure 3 –50 50 mVlogic statesV
OC(PP)
Peak-to-peak common-mode output voltage 50 150 mVI
OS
Short-circuit output current V
O(Y)
or V
O(Z)
= 0 V –24 24 mAI
OS(D)
Differential short-circuit output current V
OD
= 0 V –12 12 mAV
OD
= 600 mV –1 1I
OZ
High-impedance output current µAV
O
= 0 V or V
CC
–1 1C
o
Differential output capacitance V
I
= 0.4 sin (4E6πt) + 0.5 V 3 pF
(1) All typical values are at 25°C and with a 3.3-V supply.
3
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TIMING CHARACTERISTICS
SWITCHING CHARACTERISTICS
SN65LVDS122
SN65LVDT122
SLLS525B – MAY 2002 – REVISED JUNE 2004
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
t
SET
Input to select setup time 0 nst
HOLD
Input to select hold time 0.5 nst
SWITCH
Select to switch output 1 2 2.6 ns
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN NOM
(1)
MAX UNIT
t
PLH
Propagation delay time, low-to-high-level output 400 650 900 pst
PHL
Propagation delay time, high-to-low-level output 400 650 900 psSee Figure 4t
r
Differential output signal rise time (20% - 80%) 280 pst
f
Differential output signal fall time (20% - 80%) 280 pst
sk(p)
Pulse skew (|t
PHL
- t
PLH
|)
(2)
10 50 pst
sk(pp)
Part-to-part skew
(3)
V
ID
= 0.2 V 100 pst
jit(per)
Period jitter, rms (1 standard deviation)
(4)
750 MHz clock input
(5)
1 2.2 pst
jit(cc)
Cycle-to-cycle jitter (peak)
(4)
750 MHz clock input
(6)
10 17 pst
jit(pp)
Peak-to-peak jitter
(4)
1.5 Gbps 2
23
–1 PRBS input
(7)
33 65 pst
jit(det)
Deterministic jitter, peak-to-peak
(4)
1.5 Gbps 2
7
–1 PRBS input
(8)
17 50 pst
PHZ
Propagation delay time, high-level-to-high-impedance output See Figure 5 6 8 nst
PLZ
Propagation delay time, low-level-to-high-impedance output See Figure 5 6 8 nst
PZH
Propagation delay time, high-impedance-to-high-level output See Figure 5 4 6 nst
PZL
Propagation delay time, high-impedance-to-low-level output See Figure 5 4 6 nst
sk(o)
Output skew
(9)
15 40 ps
(1) All typical values are at 25°C and with a 3.3-V supply.(2) t
sk(p)
is the magnitude of the time difference between the t
PLH
and t
PHL
of any output of a single device.(3) t
sk(pp)
is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devicesoperate with the same supply voltages, at the same temperature, and have identical packages and test circuits.(4) Jitter is specified by design and characterization. Stimulus jitter has been subtracted.(5) Input voltage = V
ID
= 200 mV, 50% duty cycle at 750 MHz, t
r
= t
f
= 50 ps (20% to 80%), measured over 1000 samples.(6) Input voltage = V
ID
= 200 mV, 50% duty cycle at 750 MHz, t
r
= t
f
= 50 ps (20% to 80%).(7) Input voltage = V
ID
= 200 mV, 2
23
–1 PRBS pattern at 1.5 Gbps, t
r
= t
f
= 50 ps (20% to 80%), measured over 200 k samples.(8) Input voltage = V
ID
= 200 mV, 2
7
–1 PRBS pattern at 1.5 Gbps, t
r
= t
f
= 50 ps (20% to 80%).(9) Output skew is the magnitude of the time delay difference between the outputs of a single device with all inputs tied together.
4
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PIN ASSIGNMENT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1B
1A
S0
1DE
S1
2A
2B
GND
VCC
VCC
1Y
1Z
2DE
2Z
2Y
GND
D OR PW PACKAGE
(TOP VIEW)
1Y / 1Z1A / 1B
2A / 2B 2Y / 2Z
2DE
1DE
1Y / 1Z1A / 1B
2A / 2B 2Y / 2Z
2DE
1DE
1Y / 1Z
1A / 1B
2A / 2B 2Y / 2Z
2DE
1DE
1Y / 1Z1A / 1B
2A / 2B 2Y / 2Z
2DE
1DE
SN65LVDS122
SN65LVDT122
SLLS525B – MAY 2002 – REVISED JUNE 2004
Circuit Function Table
INPUTS
(1)
OUTPUTS
(1)
LOGIC DIAGRAM1V
ID
2V
ID
S1 S0 1DE 2DE 1V
OD
2V
OD
X X X X L L Z Z> 100 mV X L L H L H Z< -100 mV X L L H L L Z< -100 mV X L L H H L L> 100 mV X L L H H H H> 100 mV X L L L H Z H< -100 mV X L L L H Z L> 100 mV X H L H L H Z< -100 mV X H L H L L Z< -100 mV < -100 mV H L H H L L< -100 mV > 100 mV H L H H L H> 100 mV < -100 mV H L H H H L> 100 mV > 100 mV H L H H H HX > 100 mV H L L H Z HX < -100 mV H L L H Z LX > 100 mV L H H L H ZX < -100 mV L H H L L ZX < -100 mV L H H H L LX > 100 mV L H H H H HX > 100 mV L H L H Z HX < -100 mV L H L H Z LX > 100 mV H H H L H ZX < -100 mV H H H L L Z< -100 mV < -100 mV H H H H L L< -100 mV > 100 mV H H H H H L> 100 mV < -100 mV H H H H L H> 100 mV > 100 mV H H H H H H> 100 mV X H H L H Z H< -100 mV X H H L H Z L
(1) H = high level, L = low level, Z = high impedance, X = don't care
5
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PARAMETER MEASUREMENT INFORMATION
VOD 100 Ω
Y
Z
3.74 kΩ
3.74 kΩ_
+0 V ≤ Vtest ≤ 2.4 V
VOC
49.9 Ω ±1%
Y
1 pF
VOC(PP) VOC(SS)
VOC
≈ 1.4 V
B
A
≈ 1 V
49.9 Ω ±1%
Z
A
B
VID
1.4 V
1 V
tPLH
0.4 V
-0.4 V
VIA
VIB
VID
80%
tPHL
20%
tftr
VOD 0 V
0 V
Y
Z
A
B1 pF 100 Ω
VIB
VIA VID VOD
SN65LVDS122
SN65LVDT122
SLLS525B – MAY 2002 – REVISED JUNE 2004
Figure 1. Voltage and Current Definitions
Figure 2. Differential Output Voltage (V
OD
) Test Circuit
NOTE: All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤0.25 ns, pulse repetition rate(PRR) = 0.5 Mpps, pulse width = 500 ±10 ns; R
L
= 100 Ω; C
L
includes instrumentation and fixture capacitance within0,06 mm of the D.U.T.; the measurement of V
OC(PP)
is made on test equipment with a –3-dB bandwidth of at least300 MHz.
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
NOTE: All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤0.25 ns, pulse repetition rate(PRR) = 0.5 Mpps, pulse width = 500 ±10 ns. C
L
includes instrumentation and fixture capacitance within 0,06 mm ofthe D.U.T.
Figure 4. Timing Test Circuit and Waveforms
6
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1.2 V
Y
Z
A
B
1 pF
49.9 Ω ±1%
49.9 Ω ±1%
1 V or 1.4 V DE
VOY or VOZ
VOZ or VOY
3 V
1.5 V
0 V
≅ 1.4 V
1.25 V
1.2 V
1.2 V
1.15 V
tPZH tPHZ
≅ 1 V
tPZL tPLZ
1.2 V
DE
t(SET) t(HOLD)
t(SWITCH)
INPUT 1
OUTPUT1
AB
C D
A B C D
INPUT 2
SEL 0/1
SN65LVDS122
SN65LVDT122
SLLS525B – MAY 2002 – REVISED JUNE 2004
PARAMETER MEASUREMENT INFORMATION (continued)
NOTE: All input pulses are supplied by a generator having the following characteristics: t
r
or t
f
≤1 ns, pulse repetition rate(PRR) = 0.5 Mpps, pulse width = 500 ±10 ns. C
L
includes instrumentation and fixture capacitance within 0,06 mm ofthe D.U.T.
Figure 5. Enable and Disable Time Circuit and Definitions
Figure 6. Example Switch, Setup, and Hold Times
7
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SN65LVDS122
SN65LVDT122
SLLS525B – MAY 2002 – REVISED JUNE 2004
PARAMETER MEASUREMENT INFORMATION (continued)t
(SET)
and t
(HOLD)
times specify that data must be in a stable state before and after multiplex control switches.
Table 1. Receiver Input Voltage Threshold Test
APPLIED RESULTING DIFFERENTIAL RESULTING COMMON-
OUTPUT
(1)VOLTAGES INPUT VOLTAGE MODE INPUT VOLTAGE
V
IA
V
IB
V
ID
V
IC
1.25 V 1.15 V 100 mV 1.2 V H1.15 V 1.25 V –100 mV 1.2 V L4.0 V 3.9 V 100 mV 3.95 V H3.9 V 4. 0 V –100 mV 3.95 V L0.1 V 0.0 V 100 mV 0.05 V H0.0 V 0.1 V –100 mV 0.05 V L1.7 V 0.7 V 1000 mV 1.2 V H0.7 V 1.7 V –1000 mV 1.2 V L4.0 V 3.0 V 1000 mV 3.5 V H3.0 V 4.0 V –1000 mV 3.5 V L1.0 V 0.0 V 1000 mV 0.5 V H0.0 V 1.0 V –1000 mV 0.5 V L
(1) H = high level, L = low level
8
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EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
VCC VCC
A B
INPUT LVDS122
VCC
Y Z
OUTPUT LVDS122
VCC VCC
VCC
300 kΩ
DE1, DE2 400 Ω
VCC
300 kΩ
400 ΩS0, S1
7 V 7 V
7 V 7 V
7 V
7 V
SN65LVDS122
SN65LVDT122
SLLS525B – MAY 2002 – REVISED JUNE 2004
9
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TYPICAL CHARACTERISTICS
0 1 2 3 4 5
VIC − Common-Mode Input Voltage − V
700
500
Differential Propagation Delay − ps
800
1000
900
600
VCC = 3.3 V
TA = 25°C
VID= 200 mV
f = 150 MHz
tPHL
tPLH
50
100
250
300
350
0 500 1000 1500 2000
− Differential Output Voltage − mV
f − Frequency − MHz
VO
VCC = 3.3 V
TA = 25°C
VIC = 1.2 V
VID= 200 mV
Input = Clock
0
200
150
400
300
100
500
600
800
700
200
TA − Free Air Temperature − °C
−40 −20 0 20 40 60 80 100
0
Differential Propagation Delay − ps
VCC = 3.3 V
VID = 200 mV
f = 150 MHz
tPHL
tPLH
0 200 400 600 800
f − Frequency − MHz
10
0
Peak-To-Peak Jitter − ps
15
25
20
5
30 VCC = 3.3 V
TA = 25°C
VIC = 400 mV
Input = Clock
VID = 0.5 V
VID = 0.3 V
VID = 0.8 V
0 400 800 1200 1600
Data Rate − Mbps
20
0
Peak-To-Peak Jitter − ps
30
50
40
10
60 VCC = 3.3 V
TA = 25°C
VIC = 400 mV
Input = PRBS 223 −1
VID = 0.3 V
VID = 0.5 V
VID = 0.8 V
0 200 400 600 800
f − Frequency − MHz
10
0
Peak-To-Peak Jitter − ps
15
25
20
5
30 VCC = 3.3 V
TA = 25°C
VIC = 1.2 V
Input = Clock
VID = 0.5 V VID = 0.8 V
VID = 0.3 V
0 400 800 1200 1600
Data Rate − Mbps
20
0
Peak-To-Peak Jitter − ps
30
50
40
10
60 VCC = 3.3 V
TA = 25°C
VIC = 1.2 V
Input = PRBS 223 −1
VID = 0.5 V
VID = 0.8 V
VID = 0.3 V
0 200 400 600 800
f − Frequency − MHz
10
0
Peak-To-Peak Jitter − ps
15
25
20
5
30 VCC = 3.3 V
TA = 25°C
VIC = 2.8 V
Input = Clock
VID = 0.5 V
VID = 0.3 V
VID = 0.8 V
0 400 800 1200 1600
Data Rate − Mbps
20
0
Peak-To-Peak Jitter − ps
30
50
40
10
60
VCC = 3.3 V
TA = 25°C
VIC = 2.8 V
Input = PRBS 223 −1
VID = 0.3 V
VID = 0.8 V
VID = 0.5 V
SN65LVDS122
SN65LVDT122
SLLS525B – MAY 2002 – REVISED JUNE 2004
DIFFERENTIAL OUTPUT DIFFERENTIAL PROPAGATION DIFFERENTIAL PROPAGATIONVOLTAGE DELAY DELAYvs vs vsFREQUENCY COMMON-MODE INPUT VOLTAGE TEMPERATURE
Figure 7. Figure 8. Figure 9.
PEAK-TO-PEAK JITTER PEAK-TO-PEAK JITTER PEAK-TO-PEAK JITTERvs vs vsFREQUENCY DATA RATE FREQUENCY
Figure 10. Figure 11. Figure 12.
PEAK-TO-PEAK JITTER PEAK-TO-PEAK JITTER PEAK-TO-PEAK JITTERvs vs vsDATA RATE FREQUENCY DATA RATE
Figure 13. Figure 14. Figure 15.
10
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0 500 1500 2000 2500
Data Rate − Mbps
20
0
Peak-To-Peak Jitter − ps
30
50
40
10
60
1000 3000 3500
80
70
90
100 VCC = 3.3 V
TA = 25°C
VIC = 1.2 V
|VID |= 200 m V
Input = PRBS 223 −1
TA − Free Air Temperature − °C
20
0−40 −20 0 20 40
Peak-To-Peak Jitter - ps
30
50
60 80 100
40
10
VCC = 3.3 V
TA = 25°C
VIC = 1.2 V
VID= 200 mV
Input = 1.5 Gpbs, PRBS 223 −1
LVPECL-to-LVDS
Horizontal Scale= 200 ps/div
VCC = 3.3 V
TA = 25°C
VID= 200 mV
LVPECL-to-LVDS
Horizontal Scale= 100 ps/div
VCC = 3.3 V
TA = 25°C
VID= 200 mV
SN65LVDS122
SN65LVDT122
SLLS525B – MAY 2002 – REVISED JUNE 2004
TYPICAL CHARACTERISTICS (continued)
PEAK-TO-PEAK JITTER PEAK-TO-PEAK JITTERvs vsTEMPERATURE DATA RATE
Figure 16. Figure 17.
LVDS122 LVDS122622 Mbps, 2
23
– 1 PRBS 1.5 Gbps, 2
23
– 1 PRBS
Figure 18. Figure 19.
11
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LVDS-to-LVDS
Horizontal Scale= 200 ps/div
VCC = 3.3 V
TA = 25°C
VID= 200 mV
LVDS-to-LVDS
Horizontal Scale= 100 ps/div
VCC = 3.3 V
TA = 25°C
VID= 200 mV
Pattern
Generator
Oscilloscope
EVM
Power Supply 1 +
−
Power Supply 2 +
−
VCC
EVM
GND
DUT
GND
1.22 V
3.3 V
Matched
Cables
SMA to SMA
Matched
Cables
SMA to SMA
J2
J7
J6
J5
J4
J3 J1
100 Ω
50 Ω50 Ω
DUT
SN65LVDS122
SN65LVDT122
SLLS525B – MAY 2002 – REVISED JUNE 2004
TYPICAL CHARACTERISTICS (continued)
LVDS122 LVDS122622 Mbps, 2
23
– 1 PRBS 1.5 Gbps, 2
23
– 1 PRBS
Figure 20. Figure 21.
Figure 22. Jitter Setup Connections for SN65LVDS122
12
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APPLICATION INFORMATION
TYPICAL APPLICATION CIRCUITS (ECL, PECL, LVDS, etc.)
3.3 V or 5 V SN65LVDS122
3.3 V
50 Ω
50 Ω
A
B
50 Ω 50 Ω
VTT
VTT = VCC −2 V
ECL
3.3 V SN65LVDS122
3.3 V
50 Ω
50 Ω
A
B
50 Ω
CML
50 Ω
3.3 V
3.3 V
3.3 V SN65LVDS122
3.3 V
50 Ω A
B
50 Ω
ECL
VTT VTT = VCC −2 V
1.5 kΩ1.1 kΩ
VCC
3.3 V or 5 V SN65LVDS122
3.3 V
50 Ω
50 Ω
A
B
100 Ω
LVDS
SN65LVDS122
SN65LVDT122
SLLS525B – MAY 2002 – REVISED JUNE 2004
Figure 23. Low-Voltage Positive Emitter-Coupled Logic (LVPECL)
Figure 24. Current-Mode Logic (CML)
Figure 25. Single-Ended (LVPECL)
Figure 26. Low-Voltage Differential Signaling (LVDS)
13
PACKAGE OPTION ADDENDUM
www.ti.com 28-Aug-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN65LVDS122D ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
SN65LVDS122DG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
SN65LVDS122DR ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
SN65LVDS122DRG4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
SN65LVDS122PW ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
SN65LVDS122PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
SN65LVDS122PWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
SN65LVDS122PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
SN65LVDT122D ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
SN65LVDT122DG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
SN65LVDT122PW ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
SN65LVDT122PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Request Free Samples
SN65LVDT122PWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
SN65LVDT122PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com 28-Aug-2010
Addendum-Page 2
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN65LVDS122DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN65LVDS122PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN65LVDT122PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65LVDS122DR SOIC D 16 2500 367.0 367.0 38.0
SN65LVDS122PWR TSSOP PW 16 2000 367.0 367.0 35.0
SN65LVDT122PWR TSSOP PW 16 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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