REG103UA-A/2K5 - Texas Instruments

DMOS

500mA Low-Dropout Regulator

FEATURES

● NEW DMOS TOPOLOGY:

Ultra Low Dropout Voltage:

115mV Typ at 500mA and 3.3V Output

Output Capacitor NOT Required for Stability

●FAST TRANSIENT RESPONSE

●

VERY LOW NOISE:

Vrms

●HIGH ACCURACY: ±2% max

●HIGH EFFICIENCY:

GND

= 1mA at I

OUT

= 500mA

Not Enabled: IGND = 0.5µA

● 2.5V, 2.7V, 3.0V, 3.3V, 5.0V, AND ADJUSTABLE

OUTPUT VERSIONS

●FOLDBACK CURRENT LIMIT

● THERMAL PROTECTION

● OUTPUT VOLTAGE ERROR INDICATOR(1)

● SMALL SURFACE-MOUNT PACKAGES:

SOT223-5, DDPAK-5, SO-8

APPLICATIONS

● PORTABLE COMMUNICATION DEVICES

● BATTERY-POWERED EQUIPMENT

● PERSONAL DIGITAL ASSISTANTS

● MODEMS

● BAR-CODE SCANNERS

●BACKUP POWER SUPPLIES

DESCRIPTION

The REG103 is a family of low-noise, low-dropout, linear

regulators with low ground pin current. Its new DMOS

topology provides significant improvement over previous

designs, including low-dropout voltage (only 115mV typ at

full load), and better transient performance. In addition, no

output capacitor is required for stability, unlike conventional

low-dropout regulators that are difficult to compensate and

require expensive low ESR capacitors greater than 1µF.

Typical ground pin current is only 1mA (at IOUT = 500mA)

and drops to 0.5µA in not enabled mode. Unlike regulators

with PNP pass devices, quiescent current remains relatively

constant over load variations and under dropout conditions.

The REG103 has very low output noise (typically 33µVrms

for VOUT = 3.3V with CNR = 0.01µF), making it ideal for use

in portable communications equipment. On-chip trimming

results in high output voltage accuracy. Accuracy is main-

tained over temperature, line, and load variations. Key

parameters are tested over the specified temperature range

(–40°C to +85°C).

The SO-8 version of the REG103 has an ERROR pin that

provides a power good flag, indicating the regulator is in

regulation. The REG103 is well protected—internal cir-

cuitry provides a current limit that protects the load from

damage. Thermal protection circuitry keeps the chip from

being damaged by excessive temperature. In addition to the

SO-8 package, the REG103 is also available in the DDPAK

and the SOT223-5.

REG103

(Fixed Voltage

Versions)

ENABLE

Gnd

0.1µFCOUT(2)

+VOUT

VIN

NR = Noise Reduction

ERROR(1) ERROR1)

REG103-A

Gnd

ENABLE

0.1µF

+COUT(2)

VOUT

VIN

Adj

REG103

SBVS010D – JANUARY 2000 – REVISED SEPTEMBER 2005

www.ti.com

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

NOTE: (1) SO-8 Package Only. (2) Optional.

REG103

2SBVS010D

ABSOLUTE MAXIMUM RATINGS(1)

Supply Input Voltage, VIN .......................................................–0.3V to 16V

Enable Input Voltage, VEN ....................................................... –0.3V to VIN

Feedback Voltage, VFB ........................................................ –0.3V to 6.0V

NR Pin Voltage, VNR .............................................................–0.3V to 6.0V

Error Flag Output .....................................................................–0.3V to 6V

Error Flag Current ............................................................................... 2mA

Output Short-Circuit Duration ......................................................Indefinite

Operating Temperature Range ....................................... –55°C to +125°C

Storage Temperature Range .......................................... –65°C to +150°C

Junction Temperature ..................................................... –55°C to +150°C

Lead Temperature (soldering, 3s, SO-8, SOT, and DDPAK) ........ +240°C

ESD Rating: HBM (VOUT to GND) ..................................................... 1.5kV

HBM (All other pins)........................................................ 2kV

CDM.............................................................................. 500V

NOTE: (1) Stresses above these ratings may cause permanent damage.

Exposure to absolute maximum conditions for extended periods may degrade

device reliability.

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas

Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper han-

dling and installation procedures can cause damage.

ESD damage can range from subtle performance degrada-

tion to complete device failure. Precision integrated circuits

may be more susceptible to damage because very small

parametric changes could cause the device not to meet its

published specifications.

PIN CONFIGURATIONS

Top View

VOUT

NR/Adjust(1)

GND

VIN

ERROR

ENABLE

SO-8

NOTE: (1) For REG103A-A: voltage setting resistor pin.

All other models: noise reduction capacitor pin.

GND

ENABLE

VIN

NR/Adjust(1)

12345

DDPAK-5 SOT223-5

(U Package)

(F Package) (G Package)

Tab is GND

ENABLE

NR/Adjust(1)

GNDVIN

12345

VOUT

PACKAGE/ORDERING INFORMATION(1)

PRODUCT VOUT

REG103xx-

yyyy/zzz

XX is package designator.

YYYY is typical output voltage (5 = 5.0V, 2.85 = 2.85V, A = Adjustable).

ZZZ is package quantity.

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com.

REG103 3

SBVS010D

ELECTRICAL CHARACTERISTICS

Boldface limits apply over the specified temperature range, TJ = –40°C to +85°C.

At TJ = +25°C, VIN = VOUT + 1V (VOUT = 3.0V for REG103-A), VENABLE = 2V, IOUT = 10mA, CNR = 0.01µF, and COUT = 0.1µF(1), unless otherwise noted.

REG103GA, UA, FA

PARAMETER CONDITION MIN TYP MAX UNITS

OUTPUT VOLTAGE

Output Voltage Range VOUT

REG103-2.5 2.5 V

REG103-2.7 2.7 V

REG103-3.0 3.0 V

REG103-3.3 3.3 V

REG103-5 5V

REG103-A VREF 5.5 V

Reference Voltage VREF 1.295 V

Adjust Pin Current IADJ 0.2 1 µA

Accuracy ±0.5 ±2%

TJ = –40°C to +85°C±2.8 %

vs Temperature dVOUT/dT TJ = –40°C to +85°C70ppm/°C

vs Line and Load

IOUT = 10mA to 500mA, VIN = (VOUT + 0.7V) to 15V

±0.5 ±2.5 %

TJ = –40°C to +85°CV

IN = (VOUT + 0.9V) to 15V ±3.5 %

DC DROPOUT VOLTAGE(2, 3) VDROP IOUT = 10mA 3 25 mV

For all models except 5V IOUT = 500mA 115 200 mV

For 5V model IOUT = 500mA 160 250 mV

For all models except 5V IOUT = 500mA 230 mV

TJ = –40°C to +85°C

For 5V models IOUT = 500mA 280 mV

TJ = –40°C to +85°C

VOLTAGE NOISE

f = 10Hz to 100kHz Vn

Without CNR (all models) CNR = 0, COUT = 0 30µVrms/V • VOUT µVrms

With CNR (all fixed voltage models) CNR = 0.01µF, COUT = 10µF10µVrms/V • VOUT µVrms

OUTPUT CURRENT

Current Limit(4) ICL 550 700 950 mA

TJ = –40°C to +85°C500 1000 mA

RIPPLE REJECTION

f = 120Hz 65 dB

ENABLE CONTROL

VENABLE HIGH (output enabled) VENABLE 2V

IN V

VENABLE LOW (output disabled) –0.2 0.5 V

IENABLE HIGH (output enabled) IENABLE VENABLE = 2V to VIN, VIN = 2.1V to 6.5(5) 1 100 nA

IENABLE LOW (output disabled) VENABLE = 0V to 0.5V 2 100 nA

Output Disable Time 50 µs

Output Enable Soft Start Time 1.5 ms

ERROR FLAG(6)

Current,

Logic HIGH (open drain)—Normal Operation

VIN = VERROR = VOUT + 1V 0.1 10 µA

Voltage,

Logic LOW—On Error

Sinking 500µA 0.2 0.4 V

THERMAL SHUTDOWN

Junction Temperature

Shutdown 150 °C

Reset from Shutdown 130 °C

GROUND PIN CURRENT

Ground Pin Current IGND IOUT = 10mA 0.5 0.7 mA

IOUT = 500mA 1 1.3 mA

ENABLE Pin LOW VENABLE ≤ 0.5V 0.5 µA

INPUT VOLTAGE VIN

Operating Input Voltage Range(7) 2.1 15 V

Specified Input Voltage Range VIN > 2.7V VOUT + 0.7 15 V

TJ = –40°C to +85°CV

IN > 2.9V VOUT + 0.9 15 V

TEMPERATURE RANGE

Specified Range TJ–40 +85 °C

Operating Range –55 +125 °C

Storage Range –65 +150 °C

Thermal Resistance

DDPAK-5 Surface-Mount

JC Junction-to-Case 4 °C/W

SO-8 Surface-Mount

JA Junction-to-Ambient 150 °C/W

SOT223-5 Surface-Mount

JC Junction-to-Case 15 °C/W

NOTES: (1) The REG103 does not require a minimum output capacitor for stability. However, transient response can be improved with proper capacitor selection.

(2) Dropout voltage is defined as the input voltage minus the output voltage that produces a 2% change in the output voltage from the value at VIN = VOUT + 1V at

fixed load.

(3) Not applicable for VOUT less than 2.7V.

(4) Current limit is the output current that produces a 10% change in output voltage from VIN = VOUT + 1V and IOUT = 10mA.

(5) For VIN > 6.5V, see typical characteristic

VENABLE vs IENABLE

(6) Logic low indicates out-of-regulation condition by approximately 10%, or thermal shutdown.

(7) The REG103 no longer regulates when VIN < VOUT + VDROP (MAX). In drop-out or when the input voltage is between 2.7V and 2.1V, the impedance from VIN to

VOUT is typically less than 1Ω at TJ = +25°C. See typical characteristic.

REG103

4SBVS010D

TYPICAL CHARACTERISTICS

For all models, at TJ = +25°C and VENABLE = 2V, unless otherwise noted.

1000 200 300 400 500

0.5

–0.5

–1.0

–1.5

Output Voltage Change (%)

OUT

(mA)

OUTPUT VOLTAGE CHANGE vs I

OUT

= V

OUT

+ 1V, Output Voltage % Change

Referred to I

OUT

= 10mA at +25°C)

= –55°C

= +25°C

= +125°C

1000 200 300 400 500

180

160

140

120

100

DC Dropout Voltage (mV)

Output Current (mA)

DC DROPOUT VOLTAGE vs OUTPUT CURRENT

= –55°C

= +25°C

= +125°C

–75 –25–50 250 50 75 100 125

0.1

0.5

–0.5

–1

–1.5

Output Voltage Change (%)

Temperature (°C)

OUTPUT VOLTAGE vs TEMPERATURE

(Output Voltage % Change Referred to

OUT

= 10mA at +25°C)

= 10mA

= 100mA

= 500mA

–75 –25–50 250 50 75 100 125

160

120

DC Dropout Voltage (mV)

Temperature (°C)

DC DROPOUT VOLTAGE vs TEMPERATURE

= 10mA

= 100mA

= 500mA

–75 –25–50 250 50 75 100 125

0.5

0.4

0.3

0.2

0.1

Output Voltage Change (%)

Temperature (°C)

LINE REGULATION vs TEMPERATURE

= V

OUT

+ 1V to V

= 15V )

= 10mA

= 100mA

0246 108

0.5

–0.5

–1.0

–1.5

Output Voltage Change (%)

Input Voltage Above V

OUT

OUTPUT VOLTAGE CHANGE vs V

(Output Voltage % Change Referred

to V

= V

OUT

+ 1V at I

OUT

= 10mA)

= 10mA

= 100mA

= 500mA

REG103 5

SBVS010D

TYPICAL CHARACTERISTICS (Cont.)

For all models, at TJ = +25°C and VENABLE = 2V, unless otherwise noted.

–75 –25–50 250 50 10075 125

0.5

0.4

0.3

0.2

0.1

Output Voltage Change (%)

Temperature (°C)

LOAD REGULATION vs TEMPERATURE

= V

OUT

+ 1V and 10mA < I

OUT

< 500mA)

10 100 1000 10000 100,000

0.1

0.01

Noise Density (µV/√Hz)

Frequency (Hz)

OUTPUT NOISE DENSITY

CNR = 0

COUT = 0

CNR = 0.01µF

COUT = 10µF

LOAD TRANSIENT RESPONSE

200mV/div200mV/div

500mA

10mA

OUT

10µs/div

REG103-3.3

= 4.3V C

OUT

= 0

OUT

= 10µF

LINE TRANSIENT RESPONSE

50mV/div50mV/div

VIN

VOUT

50µs/div

REG103-3.3

Load = 100mA

COUT = 0

COUT = 10µF

LOAD TRANSIENT RESPONSE

200mV/div200mV/div

500mA

10mA

IOUT

VOUT

10µs/div

COUT = 0

COUT = 10µF

REG103-Adj.

OUT

= 3.3V, V

= 4.3V, C

= 0.01µF

LINE TRANSIENT RESPONSE

50mV/div50mV/div

VIN

VOUT

50µs/div

REG103-Adj.

OUT

= 3.3V, C

= 0.01µF, I

OUT

= 100mA

COUT = 0

COUT = 10µF

REG103

6SBVS010D

TYPICAL CHARACTERISTICS (Cont.)

For all models, at TJ = +25°C and VENABLE = 2V, unless otherwise noted.

–75 –25–50 250 50 75 100 125

1.2

1.1

0.9

0.8

0.7

0.6

0.5

0.4

IGND (mA)

Temperature (°C)

GROUND PIN CURRENT vs TEMPERATURE

= 10mA

= 100mA

= 500mA

–75 –50 –25 0 25 50 75 100 125

2.5

1.5

0.5

GND

(µA)

Temperature (°C)

GROUND PIN CURRENT, NOT ENABLED

vs TEMPERATURE

ENABLE

= 0V

–75 –50 –25 0 25 50 75 100 125

730

720

710

700

690

680

670

660

650

640

630

Current Limit (mA)

Temperature (°C)

CURRENT LIMIT vs TEMPERATURE

OUT

= V

OUT-NOMINAL

• 0.90

OUT

= 1V

–20–40 0 40 80 120–60 20 60 100 140

0.28

0.26

0.24

0.22

0.20

0.18

0.16

0.14

Adjust Pin Current (µA)

Temperature (°C)

ADJUST

vs TEMPERATURE

REG103-A

1 10 100 1000

1.2

1.1

0.9

0.8

0.7

0.6

0.5

0.4

IGND (mA)

IOUT (mA)

GROUND PIN CURRENT vs IOUT

10 100 1000 10000 100000

Ripple Rejection (dB)

Frequency (Hz)

RIPPLE REJECTION vs FREQUENCY

COUT = 10µF

COUT = 0

REG103 7

SBVS010D

TYPICAL CHARACTERISTICS (Cont.)

For all models, at TJ = +25°C and VENABLE = 2V, unless otherwise noted.

OUTPUT VOLTAGE DRIFT HISTOGRAM

Percent of Units (%)

VOUT Drift (ppm/°C)

40 45 50 55 60 65 70 75 80 85 90

OUTPUT VOLTAGE ACCURACY HISTOGRAM

Percent of Units (%)

Error (%)

–1–0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1

0 100 200 300 400 500

Ripple Rejection (dB)

Load Current (mA)

RIPPLE REJECTION vs IOUT

VRIPPLE = 3Vp-p, f = 120Hz

SOFT START

OUT

ENABLE

1V/div

0250µs/div

No Load

LOAD

= 6.8Ω

OUTPUT DISABLE TIME

OUT

VENABLE

1V/div

010µs/div

No Load

RLOAD = 6.8Ω

RLOAD = 330

REG103

8SBVS010D

BASIC OPERATION

The REG103 series is a family of LDO (Low Drop-Out)

linear regulators. The family includes five fixed output

versions (2.5V to 5.0V) and an adjustable output version. An

internal DMOS power device provides low dropout regula-

tion with near constant ground pin current (largely indepen-

dent of load and drop-out conditions) and very fast line and

load transient response. All versions include internal current

limit and thermal shutdown circuitry.

Figure 1 shows the basic circuit connections for the fixed

voltage models. Figure 2 gives the connections for the

adjustable output version (REG103A) and example resistor

values for some commonly used output voltages. Values for

other voltages can be calculated from the equation shown in

Figure 2. The SO-8 package provides two pins each for VIN

and VOUT. Both sets of pins MUST be used and connected

adjacent to the device.

FIGURE 1. Fixed Voltage Nominal Circuit for REG103.

REG103

ENABLE

OUT

0.1µF

0.01µF

ERROR

Gnd NR

In Out

Optional

None of the versions require an output capacitor for regula-

tor stability. The REG103 will accept any output capacitor

type less than 1µF. For capacitance values larger than 1µF,

the effective ESR should be greater than 0.1Ω. This mini-

mum ESR value includes parasitics such as printed circuit

board traces, solder joints, and sockets. A minimum 0.1µF

low ESR capacitor connected to the input supply voltage is

recommended.

INTERNAL CURRENT LIMIT

The REG103 internal current limit has a typical value of

700mA. A fold-back feature limits the short-circuit current

to a typical short-circuit value of 40mA. This circuit will

protect the regulator from damage under all load conditions.

A typical characteristic of VOUT versus IOUT is given in

Figure 3a.

Care should be taken in high current applications to avoid

ground currents flowing in the circuit board traces causing

voltage drops between points on the circuit. If voltage drops

occur on the circuit board ground that causes the load ground

voltage to be much lower than the ground voltage seen by

the ground pin on the REG103, the foldback current may

approach zero and the REG103 may not start up. In these

types of applications, a large value resistor can be placed

between VIN and VOUT to help “boost” up the output of the

REG103 during start-up, see Figure 3b. The value for the

“boost” resistor should be chosen so that the current through

the “boost” resistor is less than the minimum load current:

RBOOST > (VIN – VOUT)/ILOAD. Typically, a good value for a

“boost” resistor is 5kΩ.

FIGURE 2. Adjustable Voltage Circuit for REG103A.

OUT

= (1 + R

) • 1.295V

Pin numbers for SO-8 package.

REG103

0.1µF

Gnd

OUT

0.01µFC

OUT

Adj

ADJ

Load

ERRORENABLE

To reduce current through divider, increase resistor

values (see table at right).

As the impedance of the resistor divider increases,

ADJ

(~200nA) may introduce an error.

improves noise and transient response.

OUT

(V) R

(Ω)

(1)

(Ω)

(1)

1.295 Short Open

2.5 12.1k 13k

1.21k 1.3k

3 16.9k 13k

1.69k 1.3k

3.3 20k 13k

2.0k 1.3k

5 37.4k 13k

3.74k 1.3k

NOTE: (1) Resistors are standard 1% values.

EXAMPLE RESISTOR VALUES

Optional

REG103 9

SBVS010D

0 2 4 6 8 10 12 14 16

100

0.1

0.01

0.001

Enable Current (µA)

Enable Voltage

FIGURE 5. ENABLE Pin Current versus Applied Voltage.

REG103

ERROR

+5V

10kΩ

Pull-up

3 ENABLE

SO-8 Package

Only

Open

Drain

µP

FIGURE 6. ERROR Pin Typical Fault-Monitoring Circuit.

ENABLE

The ENABLE pin allows the regulator to be turned on and

off. This pin is active HIGH and compatible with standard

TTL-CMOS levels. Inputs below 0.5V (max) turn the regu-

lator off and all circuitry is disabled. Under this condition,

ground pin current drops to approximately 0.5µA. When not

used, the ENABLE pin may be connected to VIN.

Internal to the part, the ENABLE pin is connected to an

input resistor-zener diode circuit, as shown in Figure 4,

creating a nonlinear input impedance. The ENABLE Pin

Current versus Applied Voltage relationship is shown in

Figure 5. When the ENABLE pin is connected to a voltage

greater than 10V, a series resistor may be used to limit the

current.

ENABLE

= 10V

175kΩ

FIGURE 4. ENABLE Pin Equivalent Input Circuit.

FIGURE 3. Foldback Current Limit and Boost Circuit.

0 100 200 300 400 500 600 700 800

3.5

2.5

1.5

0.5

Output Voltage (V)

Output Current (mA)

REG103

0.1µF

Gnd

BOOST

OUT

+0.1µF

(1)

Load

(1) Optional.

(a) Foldback Current Limit of the REG103-3.3 at 25°C.

(b) Foldback Current Boost Circuit.

ERROR FLAG

The error indication pin, only available on the SO-8 package

version, provides a fault indication out-of-regulation condi-

tion. During a fault condition, ERROR is pulled LOW by an

open drain output device. The pin voltage, in the fault state,

is typically less than 0.2V at 500µA.

A fault condition is indicated when the output voltage differs

(either above or below) from the specified value by approxi-

mately 10%. Figure 6 shows a typical fault-monitoring

application.

OUTPUT NOISE

A precision band-gap reference is used for the internal

reference voltage, VREF, for the REG103. This reference is

the dominant noise source within the REG103. It generates

approximately 45µVrms in the 10Hz to 100kHz bandwidth

at the reference output. The regulator control loop gains up

the reference noise, so that the noise voltage of the regulator

is approximately given by:

V Vrms RR

RVrms V

NOUT

REF

=µ +=µ •45 245

REG103

10 SBVS010D

Since the value of V

REF

is 1.295V, this relationship reduces to:

VVrms

N OUT

=µ•35

Connecting a capacitor, CNR, from the Noise-Reduction

(NR) pin to ground, can reduce the output noise voltage.

Adding CNR, as shown in Figure 7, forms a low-pass filter

for the voltage reference. For CNR = 10nF, the total noise in

the 10Hz to 100kHz bandwidth is reduced by approximately

a factor of 3.5, as shown in Figure 8.

FIGURE 7. Block Diagram.

Over Current

Over Temp

Protection

REF

(1.295V)

Low Noise

Charge Pump

DMOS

Output

NOTE: R

and R

are internal

on fixed output versions.

OUT

Adj

(Adjustable

Versions)

(fixed output

versions only)

ENABLE

REG103

ERROR

(optional)

FIGURE 8. Output Noise versus Noise-Reduction Capacitor.

0.001 0.01 0.1 1

Output Noise Voltage

(µV

RMS

10Hz - 100kHz)

(µF)

OUT

= 0

OUT

= 10µF

FIGURE 9. Output Noise Density on Adjustable Versions.

10010 1000 10000 100000

10.0

1.0

0.1

nV/√Hz

Frequency

COUT = 0, CFB = 0

COUT = 0, CFB = 0.01µF

COUT = 10µF, CFB = 0.01µF

The REG103 adjustable version does not have the noise-

reduction pin available, however, the adjust pin is the sum-

ming junction of the error amplifier. A capacitor, CFB,

connected from the output to the adjust pin will reduce both

the output noise and the peak error from a load transient.

Figure 9 shows improved output noise performance for two

capacitor combinations.

The REG103 utilizes an internal charge pump to develop an

internal supply voltage sufficient to drive the gate of the

DMOS pass element above VIN. The charge-pump switch-

ing noise (nominal switching frequency = 2MHz) is not

measurable at the output of the regulator.

DROP-OUT VOLTAGE

The REG103 uses an N-channel DMOS as the “pass”

element. When the input voltage is within a few hundred

millivolts of the output voltage, the DMOS device behaves

like a resistor. Therefore, for low values of VIN to VOUT, the

regulator’s input-to-output resistance is the RdsON of the

DMOS pass element (typically 230mΩ). For static (DC)

loads, the REG103 will typically maintain regulation down

to VIN to VOUT voltage drop of 115mV at full-rated output

current. In Figure 10, the bottom line (DC dropout) shows

the minimum VIN to VOUT voltage drop required to prevent

drop-out under DC load conditions.

REG103 11

SBVS010D

FIGURE 11. Maximum Power Dissipation versus Ambient

Temperature for the Various Packages and

PCB Heat Sink Configurations.

Power Dissipation (W)

0 25 50 75 100 150125

Ambient Temperature (°C)

CONDITIONS

CONDITION PACKAGE PCB AREA JA

1 DDPAK 4in2 Top Side Only 27°C/W

2 SOT-223 4in2 Top Side Only 53°C/W

3 DDPAK None 65°C/W

4 SOT-223 0.5in2 Top Side Only 110°C/W

5 SO-8 None 150°C/W

For large step changes in load current, the REG103 requires

a larger voltage drop across it to avoid degraded transient

response. The boundary of this “transient drop-out” region is

shown as the top line in Figure 10. Values of V

to V

OUT

voltage drop above this line insure normal transient response.

250

200

150

100

Drop-Out Voltage (mV)

0 100 200 300 400 500

IOUT (mA)

REG103–3.3 at 25°C

Transient

FIGURE 10. Transient and DC Dropout.

In the transient dropout region between “DC” and “Tran-

sient”, transient response recovery time increases. The time

required to recover from a load transient is a function of both

the magnitude and rate of the step change in load current and

the available “headroom” VIN to VOUT voltage drop. Under

worst-case conditions (full-scale load change with VIN to

VOUT voltage drop close to DC dropout levels), the REG103

can take several hundred microseconds to re-enter the speci-

fied window of regulation.

TRANSIENT RESPONSE

The REG103 response to transient line and load conditions

improves at lower output voltages. The addition of a capaci-

tor (nominal value 10nF) from the output pin to ground may

improve the transient response. In the adjustable version, the

addition of a capacitor, CFB (nominal value 10nF), from the

output to the adjust pin will also improve the transient

response.

THERMAL PROTECTION

Power dissipated within the REG103 will cause the junction

temperature to rise. The REG103 has thermal shutdown

circuitry that protects the regulator from damage. The ther-

mal protection circuitry disables the output when the junc-

tion temperature reaches approximately 150°C, allowing the

device to cool. When the junction temperature cools to

approximately 130°C, the output circuitry is again enabled.

Depending on various conditions, the thermal protection

circuit may cycle on and off. This limits the dissipation of

the regulator, but may have an undesirable effect on the load.

Any tendency to activate the thermal protection circuit

indicates excessive power dissipation or an inadequate heat

sink. For reliable operation, junction temperature should be

limited to 125°C, maximum. To estimate the margin of

safety in a complete design (including heat sink), increase

the ambient temperature until the thermal protection is

triggered. Use worst-case loads and signal conditions. For

good reliability, thermal protection should trigger more than

35°C above the maximum expected ambient condition of

your application. This produces a worst-case junction tem-

perature of 125°C at the highest expected ambient tempera-

ture and worst-case load.

The internal protection circuitry of the REG103 has been

designed to protect against overload conditions. It was not

intended to replace proper heat sinking. Continuously run-

ning the REG103 into thermal shutdown will degrade reli-

ability.

POWER DISSIPATION

The REG103 is available in three different package configu-

rations. The ability to remove heat from the die is different

for each package type and, therefore, presents different

considerations in the printed circuit board (PCB) layout. The

PCB area around the device that is free of other components

moves the heat from the device to the ambient air. While it

is difficult to impossible to quantify all of the variables in a

thermal design of this type, performance data for several

configurations are shown in Figure 11. In all cases, the PCB

copper area is bare copper, free of solder-resist mask, and

not solder plated. All examples are for 1-ounce copper.

Using heavier copper will increase the effectiveness in

moving the heat from the device. In those examples where

there is copper on both sides of the PCB, no connection has

been provided between the two sides. The addition of plated

through holes will improve the heat sink effectiveness.

REG103

12 SBVS010D

Power dissipation depends on input voltage and load condi-

tions. Power dissipation is equal to the product of the

average output current times the voltage across the output

element, VIN to VOUT voltage drop.

PVV I

D IN OUT OUT AVG

=•(– )

()

Power dissipation can be minimized by using the lowest

possible input voltage necessary to assure the required

output voltage.

REGULATOR MOUNTING

The tab of both packages is electrically connected to ground.

For best thermal performance, the tab of the DDPAK sur-

face-mount version should be soldered directly to a circuit-

board copper area. Increasing the copper area improves heat

dissipation. Figure 12 shows typical thermal resistance from

junction to ambient as a function of the copper area for the

DDPAK.

Although the tabs of the DDPAK and the SOT-223 are

electrically grounded, they are not intended to carry any

current. The copper pad that acts as a heat sink should be

isolated from the rest of the circuit to prevent current flow

through the device from the tab to the ground pin. Solder pad

footprint recommendations for the various REG103 devices

are presented in the Application Bulletin “Solder Pad Rec-

ommendations for Surface-Mount Devices” (SBFA015),

available from the Texas Instruments web site (www.ti.com).

FIGURE 12. Thermal Resistance versus PCB Area for the Five-Lead DDPAK.

FIGURE 13. Thermal Resistance versus PCB Area for the Five-Lead SOT-223.

0012345

Copper Area (Inches2)

REG103

Surface-Mount Package

1 oz. copper

Circuit-Board Copper Area

REG103

DDPAK Surface-Mount Package

THERMAL RESISTANCE vs PCB COPPER AREA

Thermal Resistance, JA (°C/W)

THERMAL RESISTANCE vs PCB COPPER AREA

180

160

140

120

100

Thermal Resistance, JA (°C/W)

012345

Copper Area (Inches2)

Circuit-Board Copper Area

REG103

SOT-223 Surface-Mount Package

REG103

Surface-Mount Package

1 oz. copper

PACKAGE OPTION ADDENDUM

www.ti.com 17-Aug-2012

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

REG103FA-2.5 OBSOLETE DDPAK/

TO-263 KTT 5 TBD Call TI Call TI

REG103FA-2.5/500 NRND DDPAK/

TO-263 KTT 5 500 Green (RoHS

& no Sb/Br) CU SN Level-2-260C-1 YEAR

REG103FA-2.5/500G3 ACTIVE DDPAK/

TO-263 KTT 5 500 Green (RoHS

& no Sb/Br) CU SN Level-2-260C-1 YEAR

REG103FA-2.5KTTT ACTIVE DDPAK/

TO-263 KTT 5 50 Green (RoHS

& no Sb/Br) CU SN Level-2-260C-1 YEAR

REG103FA-2.5KTTTG3 ACTIVE DDPAK/

TO-263 KTT 5 50 Green (RoHS

& no Sb/Br) CU SN Level-2-260C-1 YEAR

REG103FA-2.7 OBSOLETE DDPAK/

TO-263 KTT 5 TBD Call TI Call TI

REG103FA-3.3 OBSOLETE DDPAK/

TO-263 KTT 5 TBD Call TI Call TI

REG103FA-3.3/500 NRND DDPAK/

TO-263 KTT 5 500 Green (RoHS

& no Sb/Br) CU SN Level-2-260C-1 YEAR

REG103FA-3.3/500G3 ACTIVE DDPAK/

TO-263 KTT 5 500 Green (RoHS

& no Sb/Br) CU SN Level-2-260C-1 YEAR

REG103FA-3.3KTTT ACTIVE DDPAK/

TO-263 KTT 5 50 Green (RoHS

& no Sb/Br) CU SN Level-2-260C-1 YEAR

REG103FA-3.3KTTTG3 ACTIVE DDPAK/

TO-263 KTT 5 50 Green (RoHS

& no Sb/Br) CU SN Level-2-260C-1 YEAR

REG103FA-5 OBSOLETE DDPAK/

TO-263 KTT 5 TBD Call TI Call TI

REG103FA-5/500 NRND DDPAK/

TO-263 KTT 5 TBD Call TI Call TI

REG103FA-5/500G3 ACTIVE DDPAK/

TO-263 KTT 5 TBD Call TI Call TI

REG103FA-5KTTT ACTIVE DDPAK/

TO-263 KTT 5 50 Green (RoHS

& no Sb/Br) CU SN Level-2-260C-1 YEAR

REG103FA-5KTTTG3 ACTIVE DDPAK/

TO-263 KTT 5 50 Green (RoHS

& no Sb/Br) CU SN Level-2-260C-1 YEAR

REG103FA-A OBSOLETE DDPAK/

TO-263 KTT 5 TBD Call TI Call TI

PACKAGE OPTION ADDENDUM

www.ti.com 17-Aug-2012

Addendum-Page 2

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

REG103FA-A/500 NRND DDPAK/

TO-263 KTT 5 500 Green (RoHS

& no Sb/Br) CU SN Level-2-260C-1 YEAR

REG103FA-A/500E3 ACTIVE DDPAK/

TO-263 KTT 5 TBD Call TI Call TI

REG103FA-A/500G3 ACTIVE DDPAK/

TO-263 KTT 5 500 Green (RoHS

& no Sb/Br) CU SN Level-2-260C-1 YEAR

REG103FA-AKTTT ACTIVE DDPAK/

TO-263 KTT 5 50 Green (RoHS

& no Sb/Br) CU SN Level-2-260C-1 YEAR

REG103FA-AKTTTG3 ACTIVE DDPAK/

TO-263 KTT 5 50 Green (RoHS

& no Sb/Br) CU SN Level-2-260C-1 YEAR

REG103GA-2.5 ACTIVE SOT-223 DCQ 6 78 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

REG103GA-2.5/2K5 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

REG103GA-2.5/2K5G4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

REG103GA-2.5G4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

REG103GA-2.7 NRND SOT-223 DCQ 6 78 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

REG103GA-2.7G4 NRND SOT-223 DCQ 6 78 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

REG103GA-3 NRND SOT-223 DCQ 6 78 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

REG103GA-3.3 ACTIVE SOT-223 DCQ 6 78 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

REG103GA-3.3/2K5 NRND SOT-223 DCQ 6 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

REG103GA-3.3/2K5G4 NRND SOT-223 DCQ 6 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

REG103GA-3.3G4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

REG103GA-3G4 NRND SOT-223 DCQ 6 78 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

REG103GA-5 ACTIVE SOT-223 DCQ 6 78 Green (RoHS

& no Sb/Br) CU SN Level-2-260C-1 YEAR

PACKAGE OPTION ADDENDUM

www.ti.com 17-Aug-2012

Addendum-Page 3

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

REG103GA-5/2K5 NRND SOT-223 DCQ 6 2500 Green (RoHS

& no Sb/Br) CU SN Level-2-260C-1 YEAR

REG103GA-5/2K5G4 NRND SOT-223 DCQ 6 2500 Green (RoHS

& no Sb/Br) CU SN Level-2-260C-1 YEAR

REG103GA-5G4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS

& no Sb/Br) CU SN Level-2-260C-1 YEAR

REG103GA-A ACTIVE SOT-223 DCQ 6 78 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

REG103GA-A/2K5 NRND SOT-223 DCQ 6 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

REG103GA-A/2K5G4 NRND SOT-223 DCQ 6 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

REG103GA-AG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

REG103UA-2.5 ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

REG103UA-2.5/2K5 ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

REG103UA-2.5/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

REG103UA-2.5G4 ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

REG103UA-2.7 NRND SOIC D 8 TBD Call TI Call TI

REG103UA-2.7G4 NRND SOIC D 8 TBD Call TI Call TI

REG103UA-3 NRND SOIC D 8 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

REG103UA-3.3 ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

REG103UA-3.3/2K5 NRND SOIC D 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

REG103UA-3.3/2K5G4 NRND SOIC D 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

REG103UA-3.3G4 ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

REG103UA-3G4 NRND SOIC D 8 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

PACKAGE OPTION ADDENDUM

www.ti.com 17-Aug-2012

Addendum-Page 4

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

REG103UA-5 ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

REG103UA-5/2K5 NRND SOIC D 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

REG103UA-5/2K5G4 NRND SOIC D 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

REG103UA-5G4 ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

REG103UA-A ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

REG103UA-A/2K5 NRND SOIC D 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

REG103UA-A/2K5G4 NRND SOIC D 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

REG103UA-AG4 ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

PACKAGE OPTION ADDENDUM

www.ti.com 17-Aug-2012

Addendum-Page 5

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

REG103FA-2.5/500 DDPAK/

TO-263 KTT 5 500 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2

REG103FA-2.5KTTT DDPAK/

TO-263 KTT 5 50 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2

REG103FA-3.3/500 DDPAK/

TO-263 KTT 5 500 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2

REG103FA-3.3KTTT DDPAK/

TO-263 KTT 5 50 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2

REG103FA-5KTTT DDPAK/

TO-263 KTT 5 50 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2

REG103FA-A/500 DDPAK/

TO-263 KTT 5 500 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2

REG103FA-AKTTT DDPAK/

TO-263 KTT 5 50 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2

REG103GA-2.5/2K5 SOT-223 DCQ 6 2500 330.0 12.4 6.8 7.3 1.88 8.0 12.0 Q3

REG103GA-3.3/2K5 SOT-223 DCQ 6 2500 330.0 12.4 6.8 7.3 1.88 8.0 12.0 Q3

REG103GA-5/2K5 SOT-223 DCQ 6 2500 330.0 12.4 6.8 7.3 1.88 8.0 12.0 Q3

REG103GA-A/2K5 SOT-223 DCQ 6 2500 330.0 12.4 6.8 7.3 1.88 8.0 12.0 Q3

REG103UA-2.5/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

REG103UA-3.3/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 17-Aug-2012

Pack Materials-Page 1

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

REG103UA-5/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

REG103UA-A/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

REG103FA-2.5/500 DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0

REG103FA-2.5KTTT DDPAK/TO-263 KTT 5 50 367.0 367.0 45.0

REG103FA-3.3/500 DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0

REG103FA-3.3KTTT DDPAK/TO-263 KTT 5 50 367.0 367.0 45.0

REG103FA-5KTTT DDPAK/TO-263 KTT 5 50 367.0 367.0 45.0

REG103FA-A/500 DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0

REG103FA-AKTTT DDPAK/TO-263 KTT 5 50 367.0 367.0 45.0

REG103GA-2.5/2K5 SOT-223 DCQ 6 2500 358.0 335.0 35.0

REG103GA-3.3/2K5 SOT-223 DCQ 6 2500 358.0 335.0 35.0

REG103GA-5/2K5 SOT-223 DCQ 6 2500 358.0 335.0 35.0

REG103GA-A/2K5 SOT-223 DCQ 6 2500 358.0 335.0 35.0

REG103UA-2.5/2K5 SOIC D 8 2500 367.0 367.0 35.0

REG103UA-3.3/2K5 SOIC D 8 2500 367.0 367.0 35.0

REG103UA-5/2K5 SOIC D 8 2500 367.0 367.0 35.0

REG103UA-A/2K5 SOIC D 8 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 17-Aug-2012

Pack Materials-Page 2

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