LM49101, LM49101TMEVAL
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LM49101 Mono Class AB Audio Subsystem with a True
Ground Headphone Amplifier and Earpiece Switch
Check for Samples: LM49101,LM49101TMEVAL
1FEATURES APPLICATIONS
2• Differential Mono Input and Stereo Single- • Portable Electronic Devices
Ended Input • Mobile Phones
• Separate Earpiece (Receiver) Differential Input • PDAs
• Analog Switch for a Separate Earpiece Path DESCRIPTION
• 32-Step Digital Volume Control (-80 to +18dB) The LM49101 is a fully integrated audio subsystem
• Three Independent Volume Channels (Left, with a mono power amplifier capable of delivering
Right, Mono) 540mW of continuous average power into an 8ΩBTL
• Separate Headphone Volume Control speaker load with 1% THD+N using a 3.3V supply.
The LM49101 includes a separate stereo headphone
• Flexible Output for Speaker and Headphone amplifier that can deliver 44mW per channel into 32Ω
Output loads using a 2.75V supply.
• True Ground Headphone Amplifier Eliminates
Large DC Blocking Capacitors Reducing PCB The LM49101 has four input channels. A pair of
single-ended inputs and a fully differential input
Space and Cost channel with volume control and amplification stages.
• Hardware Reset Function Additionally, a bypass differential input is available
• RF Immunity Topology that connects directly to the mono speaker outputs
• “Click and Pop” Suppression Circuitry through an analog switch without any amplification or
volume control stages. The LM49101 features a
• Thermal Shutdown Protection 32–step digital volume control on the input stage and
• Micro-Power Shutdown an 8–step digital volume control on the headphone
• I2C Control Interface output stage.
• Available in Space-Saving DSBGA Package The digital volume control and output modes,
programmed through a two-wire I2C compatible
KEY SPECIFICATIONS interface, allows flexibility in routing and mixing audio
channels.
• Supply Voltage (VDDLS): 2.7V ≤VDDLS ≤5.5V The LM49101 is designed for cellular phones, PDAs,
• Supply Voltage (VDDHP): 1.8V ≤VDDHP ≤2.9V and other portable handheld applications. The high
• I2C Supply Voltage: 1.7V ≤I2CVDD ≤5.5V level of integration minimizes external components.
• Output Power, VDDLS = 5V, VDDHP = 2.75V, 1% The True Ground headphone amplifier eliminates the
THD+N physically large DC blocking output capacitors
reducing required board space and reducing cost.
– RL= 8ΩSpeaker 1.3W (Typ)
– RL= 32ΩHeadphone 45mW (Typ)
• Output Power VDDLS = 3.3V, VDDHP = 2.75V,
1% THD+N
– RL= 8ΩSpeaker 540W (Typ)
– RL= 32ΩHeadphone 40mW (Typ)
• PSRR: VDD = 3.3V, 217Hz Ripple, Mono In:
90dB (Typ)
• Shutdown Power Supply Current: 0.01μA (Typ)
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2009–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LM49101, LM49101TMEVAL
SNAS475A –MARCH 2009–REVISED APRIL 2013
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Typical Application
Figure 1. Typical Audio Application Circuit
Connection Diagram
Top View
Figure 2. 25 Bump DSBGA Package
See Package Number YFQ0025BCA
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Table 1. Bump Descriptions
Bump Name Pin Function Type
A1 CPGND Charge pump ground terminal Ground
A2 VSSCP Negative charge pump power supply Power Output
A3 HPR Right headphone output Analog Output
A4 VDDHP Headphone amplifier power supply Power Input
A5 MIN+ Positive input pin for the mono, differential input Analog Input
B1 C1N Negative terminal of the charge pump flying capacitor Analog Output
B2 C1P Positive terminal of the charge pump flying capacitor Analog Output
B3 HPL Left headphone output Analog Output
B4 HPGND Headphone signal ground Ground
B5 MIN- Negative input pin for the mono, differential input Analog Input
C1 VDDCP Charge pump power supply Power Input
C2 SDA I2C data Digital Input
C3 GND Ground Ground
C4 RIN Single-ended input for the right channel Analog Input
C5 LIN Single-ended input for the left channel Analog Input
D1 BYPASS_IN- Earpiece negative input, bypass volume control and amplifier Analog Input
D2 I2CVDD I2C power supply Power Input
D3 SCL I2C clock Digital Input
Hardware reset function, active low. When pin is low (<0.6V) the
LM49101 goes into shutdown mode and will remain in shutdown
D4 HW RESET Digital Input
mode until pin goes to logic high (>1.6V) and is activated by I2C
control. When reset all registers are set to the default value of 0.
D5 BYPASS_IN+ Earpiece positive input, bypass volume control and amplifier Analog Input
E1 MONO+ Positive loudspeaker output Analog Output
E2 VDDLS Main power supply Power Input
E3 GND Ground Ground
E4 MONO- Negative loudspeaker output Analog Output
E5 BIAS Half-supply bias, capacitor bypassed Analog Output
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Absolute Maximum Ratings(1)(2)(3)(4)
Supply Voltage (Loudspeaker, VDDLS) 6.0V
Supply Voltage (Headphone, VDDHP) 3.0V
Storage Temperature −65°C to +150°C
Voltage at Any Input Pin GND −0.3 to VDD LS + 0.3
Power Dissipation(5) Internally Limited
ESD Rating(6) 2000V
ESD Rating(7) 200V
Junction Temperature (TJMAX) 150°C
Vapor Phase (60sec.) 215°C
Soldering Information Infrared (15sec.) 220°C
Thermal Resistance θJA(8) 51°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified
(2) The Electrical Characteristics tables list specified specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(3) See AN-1112 “Micro SMD Wafer Level Chip Scale Package" ().
(4) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(5) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX,θJA, and the ambient temperature,
TA. The maximum allowable power dissipation is PDMAX = (TJMAX - TA) / θJA or the number given in Absolute Maximum Ratings,
whichever
(6) Human body model, applicable std. JESD22-A114C.
(7) Machine model, applicable std. JESD22-A115-A.
(8) The given θJA is for an LM49101 mounted on a demonstration board.
Operating Ratings
Temperature Range (TMIN ≤TA≤TMAX)−40°C ≤TA≤85°C
Supply Voltage (VDDLS) 2.7V ≤VDDLS ≤5.5V
1.8V ≤VDDHP ≤2.9V
Supply Voltage (VDDHP) VDDHP ≤VDDLS
Supply Voltage (VDDCP) VDDCP = VDD HP
1.7V ≤I2CVDD ≤5.5V
Supply Voltage (I2CVDD)I2CVDD ≤VDDLS
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Electrical Characteristics VDDLS = 3.3V, VDDHP = 2.75V(1)(2)
The following specifications apply for VDDLS = 3.3V, VDDHP = 2.75V, TA= 25°C, all volume controls set to 0dB, unless
otherwise specified. LS = Loudspeaker, HP = Headphone, EP = Earpiece. LM49101 Units
Parameter Test Conditions (Limits)
Typ(3) Limits(4)
VIN = 0, No Load
EP Receiver 0.03 0.045 mA (max)
(Output Mode Bit EP Bypass = 1)
LS only (Mode 1), GAMP_SD = 0
VDDLS 2.5 4.2 mA (max)
VDDHP 0 mA
LS only (Mode 1), GAMP_SD = 1
VDDLS 2 mA
VDDHP 0 mA
HP only (Mode 8), GAMP_SD = 0
IDD Quiescent Power Supply Current VDDLS 1.6 2.0 mA (max)
VDDHP 3.1 4.5 mA (max)
VDDLS +VDDHP 6.45 mA (max)
HP only (Mode 8), GAMP_SD = 1
VDDLS 2.8 mA
VDDHP 3.3 mA
LS+HP (Mode 10), GAMP_SD = 0
VDDLS 2.8 3.8 mA (max)
VDDHP 3.1 4.5 mA (max)
VDDLS +VDDHP 8 mA (max)
ISD Shutdown Current Power_On = 0 0.01 2 µA (max)
VIN = 0V, Mode 10
VOS Output Offset Voltage LS output, RL= 8ΩBTL 2.5 22 mV (max)
HP output, RL= 32ΩSE 0.5 5 mV (max)
LS output, Mode 1, RL= 8ΩBTL 540 480 mW (min)
THD+N = 1%, f = 1kHz, LS_Gain = 6dB
POOutput Power HP output, Mode 8, RL= 32ΩSE 44 40 mW (min)
THD+N = 1%, f = 1kHz
LS output, f = 1kHz, RL= 8ΩBTL 0.065 %
PO= 250mW, Mode 1, LS_Gain = 6dB
THD+N Total Harmonic Distortion + Noise HP output, f = 1kHz, RL= 32ΩSE 0.015 %
PO= 20mW, Mode 8
LS output, f = 1kHz, Mode 1
VREF = VOUT (1%THD+N) 105 dB
Vol. Gain & LS_GAIN = 0dB
A-Wtg, LIN & RIN AC terminated
SNR Signal-to-Noise Ratio HP output, f = 1kHz, Mode 8
VREF = VOUT (1%THD+N) 100 dB
Vol. Gain = 0dB, A-weighted
LIN & RIN AC terminated
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified
(2) The Electrical Characteristics tables list specified specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(3) Typical values represent most likely parametric norms at TA= +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not ensured.
(4) Datasheet min/max specification limits are specified by test or statistical analysis.
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Electrical Characteristics VDDLS = 3.3V, VDDHP = 2.75V(1)(2) (continued)
The following specifications apply for VDDLS = 3.3V, VDDHP = 2.75V, TA= 25°C, all volume controls set to 0dB, unless
otherwise specified. LS = Loudspeaker, HP = Headphone, EP = Earpiece. LM49101 Units
Parameter Test Conditions (Limits)
Typ(3) Limits(4)
VRIPPLE on VDDLS = 200mVPP, fRIPPLE = 217Hz, CB= 2.2μF
All inputs AC terminated to GND, output referred
LS: Mode 1, 5, 9, 13, RL= 8ΩBTL 90 dB (max)
PSRR Power Supply Rejection Ratio LS: Mode 2, 6, 10 ,14, RL= 8ΩBTL 75 dB (max)
HP: Mode 4, 5, 6, 7, RL= 32ΩSE 85 dB (max)
HP: Mode 8, 9, 10, 11, RL= 32ΩSE 81 dB (max)
f = 217Hz, VCM = 1VP-P
CMRR Common-Mode Rejection Ratio LS: RL= 8ΩBTL, Mode 1 60 dB
HP: RL= 32ΩSE, Mode 4 60 dB
HP PO= 20mW
XTALK Crosstalk 72 dB
f = 1kHz, Mode 8 10 KΩ(min)
Maximum Gain setting 12.5 15 KΩ(max)
ZIN MIN, LIN, and RIN Input Impedance 90 KΩ(min)
Maximum Attenuation setting 110 130 KΩ(max)
RON On Resistance Analog Switch On 3.4 Ω
Maximum Gain 18 dB
VOL Digital Volume Control Range Maximum Attenuation –80 dB
VOL Volume Control Step Size Error ±0.02 dB
CB= 2.2μF, HP, Normal Turn-On Mode 30 ms
TWU Wake-Up Time from Shutdown CB= 2.2μF, HP, Fast Turn-On Mode 15 ms
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Electrical Characteristics VDDLS = 5.0V, VDDHP = 2.75V(1)(2)
The following specifications apply for VDDLS = 5.0V, VDDHP = 2.75V, TA= 25°C, all volume controls set to 0dB, unless
otherwise specified. LS = Loudspeaker, HP = Headphone, EP = Earpiece. LM49101 Units
Parameter Test Conditions (Limits)
Typ(3) Limits(4)
VIN = 0, No Load
EP Receiver 0.05 0.07 mA (max)
(Output Mode Bit EP Bypass = 1)
LS only (Mode 1), GAMP_SD = 0 mA (max)
VDDLS 2.9 4.4 mA
VDDHP 0
LS only (Mode 1), GAMP_SD = 1
VDDLS 2.1 mA
VDDHP 0 mA
HP only (Mode 8), GAMP_SD = 0
IDD Quiescent Power Supply Current VDDLS 1.8 2.15 mA (max)
VDDHP 3.1 4.5 mA (max)
VDDLS+VDDHP 6.6 mA (max)
HP only (Mode 8), GAMP_SD = 1
VDDLS 1.3 mA
VDDHP 3.1 mA
LS+HP only (Mode 10), GAMP_SD = 0
VDDLS 3 4.1 mA (max)
VDDHP 3.1 4.5 mA (max)
VDDLS+VDDHP 8.35 mA (max)
ISD Shutdown Current Power_On = 0 0.01 2 µA (max)
VIN = 0V, Mode 10
VOS Output Offset Voltage LS output, RL= 8ΩBTL 2.5 22 mV (max)
HP output, RL= 32ΩSE 0.5 5 mV (max)
LS output, Mode 1, RL= 8ΩBTL 1.3 W
THD+N = 1%, f = 1kHz, LS_Gain = 6dB
POOutput Power HP output, Mode 8, RL= 32ΩSE 45 mW
THD+N = 1%, f = 1kHz
LS output, f = 1kHz, RL= 8ΩBTL 0.055 %
PO= 600mW, Mode 1, LS_Gain = 6dB
THD+N Total Harmonic Distortion + Noise HP output, f = 1kHz, RL= 32ΩSE 0.015 %
PO= 20mW, Mode 8
LS output, f = 1kHz, Mode 1
VREF = VOUT (1%THD+N) 108 dB
Vol. Gain & LS_GAIN = 0dB
A-Wtg, LIN & RIN AC terminated
SNR Signal-to-Noise Ratio HP output, f = 1kHz, Mode 8
VREF = VOUT (1%THD+N) 100 dB
Vol. Gain = 0dB, A-weighted
LIN & RIN AC terminated
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified
(2) The Electrical Characteristics tables list specified specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(3) Typical values represent most likely parametric norms at TA= +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not ensured.
(4) Datasheet min/max specification limits are specified by test or statistical analysis.
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Electrical Characteristics VDDLS = 5.0V, VDDHP = 2.75V(1)(2) (continued)
The following specifications apply for VDDLS = 5.0V, VDDHP = 2.75V, TA= 25°C, all volume controls set to 0dB, unless
otherwise specified. LS = Loudspeaker, HP = Headphone, EP = Earpiece. LM49101 Units
Parameter Test Conditions (Limits)
Typ(3) Limits(4)
VRIPPLE on VDDLS = 200mVPP, fRIPPLE = 217Hz, CB= 2.2μF
All inputs AC terminated to GND, output referred
LS: Mode 1, 5, 9, 13, RL= 8ΩBTL 90 dB
PSRR Power Supply Rejection Ratio LS: Mode 2, 6, 10, 14, RL= 8ΩBTL 74 dB
HP: Mode 4, 5, 6, 7, RL= 32ΩSE 84 dB
HP: Mode 8, 9, 10, 11, RL= 32ΩSE 79 dB
f = 217Hz, VCM = 1VP-P
CMRR Common-Mode Rejection Ratio LS: RL= 8ΩBTL, Mode 1 60 dB
HP: RL= 32ΩSE, Mode 4 60 dB
XTALK Crosstalk HP PO= 20mW, f = 1kHz, Mode 8 72 dB
10 KΩ(min)
Maximum Gain setting 12.5 15 KΩ(max)
ZIN MIN, LIN, and RIN Input Impedance 90 KΩ(min)
Maximum Attenuation setting 110 130 KΩ(max)
RON On Resistance Analog Switch On 2 Ω
Maximum Gain 18 dB
VOL Digital Volume Control Range Maximum Attenuation –80 dB
VOL Volume Control Step Size Error ±0.02 dB
CB= 2.2μF, HP, Normal Turn-On Mode 30 ms
TWU Wake-Up Time from Shutdown CB= 2.2μF, HP, Fast Turn-On Mode 15 ms
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I2C Interface 2.2V ≤I2C_VDD ≤5.5V(1)(2)
The following specifications apply for VDDLS = 5.0V and 3.3V, 2.2V ≤I2C_VDD ≤5.5V, TA= 25°C, unless otherwise specified.
LM49101 Units
Parameter Test Conditions (Limits)
Typ(3) Limits(4)(5)
t1I2C Clock Period 2.5 µs (min)
t2I2C Data Setup Time 100 ns (min)
t3I2C Data Stable Time 0 ns (min)
t4Start Condition Time 100 ns (min)
t5Stop Condition Time 100 ns (min)
t6I2C Data Hold Time 100 ns (min)
VIH I2C Input Voltage High 0.7xI2CVDD V (min)
VIL I2C Input Voltage Low 0.3xI2CVDD V (max)
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified
(2) The Electrical Characteristics tables list specified specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(3) Human body model, applicable std. JESD22-A114C.
(4) Datasheet min/max specification limits are specified by test or statistical analysis.
(5) Refer to the I2C timing diagram, Figure 39.
I2C Interface 1.7V ≤I2C_VDD ≤2.2V(1)(2)
The following specifications apply for VDDLS = 5.0V and 3.3V, TA= 25°C, 1.7V ≤I2C_VDD ≤2.2V, unless otherwise specified.
LM49101 Units
Parameter Test Conditions (Limits)
Typ(3) Limits(4)(5)
t1I2C Clock Period 2.5 µs (min)
t2I2C Data Setup Time 250 ns (min)
t3I2C Data Stable Time 0 ns (min)
t4Start Condition Time 250 ns (min)
t5Stop Condition Time 250 ns (min)
t6I2C Data Hold Time 250 ns (min)
VIH I2C Input Voltage High 0.7xI2CVDD V (min)
VIL I2C Input Voltage Low 0.3xI2CVDD V (max)
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified
(2) The Electrical Characteristics tables list specified specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(3) Typical values represent most likely parametric norms at TA= +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not ensured.
(4) Datasheet min/max specification limits are specified by test or statistical analysis.
(5) Refer to the I2C timing diagram, Figure 39.
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Typical Performance Characteristics
THD+N vs Frequency THD+N vs Frequency
VDDLS = 3.3V, RL= 8ΩBTL, PO= 250mW VDDLS = 3.3V, RL= 8ΩBTL, PO= 250mW
Mode 1 (Mono), 80kHz BW Mode 2 (Left + Right), 80kHz BW
Figure 3. Figure 4.
THD+N vs Frequency THD+N vs Frequency
VDDLS = 3.3V, VDDHP = 1.8V, RL= 32ΩSE, VDDLS = 3.3V, VDDHP = 1.8V, RL= 32ΩSE,
PO= 5mW/Ch, Mode 4 (Mono), 80kHz BW PO= 5mW/Ch, Mode 8 (Left/Right ), 80kHz BW
Figure 5. Figure 6.
THD+N vs Frequency THD+N vs Frequency
VDDLS = 3.3V, VDDHP = 1.8V, RL= 8ΩBTL, RL= 32ΩSE, VDDLS = 3.3V, VDDHP = 1.8V, RL= 8ΩBTL, RL= 32ΩSE,
PO= 250mW BTL, PO= 5mW/Ch SE, Mode 5 (Mono) PO= 250mW BTL, PO= 5mW/Ch SE, Mode 10 (L/R)
LS (EP Mode) = 0, 80kHz BW LS (EP Mode) = 0, 80kHz BW
Figure 7. Figure 8.
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20 20k
FREQUENCY (Hz)
0.001
10
THD + N (%)
10k1k100
0.010
0.1
1
20
20 20k
FREQUENCY (Hz)
0.001
10
THD + N (%)
10k1k100
0.010
0.1
1
20
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Typical Performance Characteristics (continued)
THD+N vs Frequency THD+N vs Frequency
VDDLS = 5V, RL= 8ΩBTL, PO= 600mW, VDDLS = 5V, RL= 8ΩBTL, PO= 600mW,
Mode 1 (Mono), 80kHz BW Mode 2 (Let + Right), 80kHz BW
Figure 9. Figure 10.
THD+N vs Frequency THD+N vs Frequency
VDDLS = 5V, VDDHP = 2.75V, RL= 32ΩSE, VDDLS = 5V, VDDHP = 2.75V, RL= 32ΩSE,
PO= 20mW/Ch, Mode 4 (Mono), 80kHz BW PO= 20mW/Ch, Mode 8 (Left/Right), 80kHz BW
Figure 11. Figure 12.
THD+N vs Frequency THD+N vs Frequency
VDDLS = 5V, VDDHP = 2.75V, RL= 8ΩBTL, RL= 32ΩSE, VDDLS = 5V, VDDHP = 2.75V, RL= 8ΩBTL, RL= 32ΩSE,
PO= 600mW BTL, PO= 20mW/Ch SE, Mode 5 (Mono) PO= 600mW BTL, PO= 20mW/Ch SE, Mode 10 (L/R)
LS (EP Mode) = 0, 80kHz BW LS (EP Mode) = 0, 80kHz BW
Figure 13. Figure 14.
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0.05
0.2
THD+N (%)
OUTPUT POWER (W)
2
1
10
10m
1m
0.5
2
5
0.1
0.02
0.01 100m 1
3.3V
5V
0.05
0.01
THD+N (%)
OUTPUT POWER (W)
60m
1
10
10m
1m
0.5
2
5
0.1
0.02
0.001 5m 20m
2m
0.2
0.005
0.002
1.8V
2.75V
0.05
0.01
THD+N (%)
OUTPUT POWER (W)
60m
1
10
10m
1m
0.5
2
5
0.1
0.02
0.001 5m 20m
2m
0.2
0.005
0.002
1.8V
2.75V
THD+N (%)
OUTPUT POWER (W)
60m
10m
1m 5m 20m
1.8V
2.75V
2m
0.05
0.01
1
10
0.5
2
5
0.1
0.02
0.001
0.2
0.005
0.002
0.05
0.2
THD+N (%)
OUTPUT POWER (W)
2
1
10
10m
1m
0.5
2
5
0.1
0.02
0.01 100m 1
3.3V
5V
0.05
0.2
THD+N (%)
OUTPUT POWER (W)
2
1
10
10m
1m
0.5
2
5
0.1
0.02
0.01 100m 1
3.3V
5V
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Typical Performance Characteristics (continued)
THD+N vs Output Power THD+N vs Output Power
VDDLS = 3.3V & 5V, f = 1kHz, RL= 8ΩBTL VDDLS = 3.3V & 5V, f = 1kHz, RL= 8ΩBTL
Mode 1 (Mono), 80kHz BW Mode 2 (Left + Right), 80kHz BW
Figure 15. Figure 16.
THD+N vs Output Power THD+N vs Output Power
VDDLS = 3.3V, VDDHP = 1.8V & 2.75V, f = 1kHz, VDDLS = 3.3V, VDDHP = 1.8V & 2.75V, f = 1kHz,
RL= 32ΩSE, Mode 4 (Mono), 80kHz BW RL= 32ΩSE, Mode 8 (Left/Right), 80kHz BW
Figure 17. Figure 18.
THD+N vs Output Power THD+N vs Output Power
VDDLS = 3.3V & 5V, VDDHP = 2.75V, f = 1kHz, VDDLS = 3.3V, VDDHP = 1.8V & 2.75V, f = 1kHz,
RL= 8ΩBTL, Mode 5 (Mono), 80kHz BW RL= 32ΩSE, Mode 10 (Left/Right), 80kHz BW
Figure 19. Figure 20.
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Typical Performance Characteristics (continued)
PSRR vs Frequency PSRR vs Frequency
VDDLS = 3.3V, VRIPPLELS = 200mVPP, RL= 8ΩBTL, VDDLS = 3.3V, VRIPPLELS = 200mVPP, RL= 8ΩBTL,
Mode 1 (Mono), 80kHz BW Mode 2 (Left + Right), 80kHz BW
Figure 21. Figure 22.
PSRR vs Frequency PSRR vs Frequency
VDDLS = 5V, VRIPPLELS = 200mVPP, RL= 8ΩBTL, VDDLS = 5V, VRIPPLELS = 200mVPP, RL= 8ΩBTL,
Mode 1 (Mono), 80kHz BW Mode 2 (Left + Right), 80kHz BW
Figure 23. Figure 24.
PSRR vs Frequency PSRR vs Frequency
VDDLS = 3.3V, VDDHP = 1.8V, VRIPPLEHP = 200mVPP, VDDLS = 3.3V, VDDHP = 1.8V, VRIPPLEHP = 200mVPP,
RL= 32ΩSE, Mode 4 (Mono), 80kHz BW RL= 32ΩSE, Mode 8 (Left/Right), 80kHz BW
Figure 25. Figure 26.
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-50
-30
CHANNEL SEPARATION (dB)
FREQUENCY (Hz)
1k20
-10
10k50 2k
-20
0
-40
-60
-70
5k
-100
-90
-80
20k200100 500
-50
-30
CHANNEL SEPARATION (dB)
FREQUENCY (Hz)
1k20
-10
10k50 2k
-20
0
-40
-60
-70
5k
-100
-90
-80
20k200100 500
POWER DISSIPATION (mW)
OUTPUT POWER (mW)
0400
200
0
100
600 800200
700
500
400
600
300
1000 1200
5V
3.3V
-50
-30
POWER SUPPLY REJECTION RATIO (dB)
FREQUENCY (Hz)
1k20
-10
10k50 2k
-20
0
-40
-60
-70
5k
-100
-90
-80
20k200100 500
-50
-30
POWER SUPPLY REJECTION RATIO (dB)
FREQUENCY (Hz)
1k20
-10
10k50 2k
-20
0
-40
-60
-70
5k
-100
-90
-80
20k200100 500
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Typical Performance Characteristics (continued)
PSRR vs Frequency PSRR vs Frequency
VDDLS = 3.3V, VDDHP = 2.75V, VRIPPLEHP = 200mVPP, VDDLS = 3.3V, VDDHP = 2.75V, VRIPPLEHP = 200mVPP,
RL= 32ΩSE, Mode 4 (Mono), 80kHz BW RL= 32ΩSE, Mode 8 (Left/Right), 80kHz BW
Figure 27. Figure 28.
Power Dissipation vs Output Power Power Dissipation vs Output Power
VDDLS = 3.3V & 5V, VDDHP = 2.75V, RL= 8ΩBTL, VDDLS = 5V, VDDHP = 1.8V & 2.75V, RL= 32ΩSE,
Mode 3 (Mono + Left + Right), 80kHz BW Mode 12 (Mono + Left/ Right), 80kHz BW
Figure 29. Figure 30.
Crosstalk vs Frequency Crosstalk vs Frequency
VDDLS = 3.3V, VDDHP = 1.8V, VIN = 1VPP, VDDLS = 3.3V, VDDHP = 2.75V, VIN = 1VPP,
RL= 32ΩSE, Mode 8 (Left/Right), 80kHz BW RL= 32ΩSE, Mode 8 (Left/Right), 80kHz BW
Figure 31. Figure 32.
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2000
OUTPUT POWER (mW)
POWER SUPPLY VOLTAGE (V)
60 1 5
03
24
1000
500
1500
2500
THD+N = 10%
THD+N = 1%
50
OUTPUT POWER (mW)
POWER SUPPLY VOLTAGE (V)
3.50 0.5 2.5
01.5
12
30
20
40
60
3
10
THD+N = 10%
THD+N = 1%
POWER SUPPLY CURRENT (mA)
POWER SUPPLY VOLTAGE (V)
3
04
4.5
3
6
0
1
2
12
0.5
1.5
2.5
3.5
5
4.0 EP_mode = 0
EP_mode = 1
POWER SUPPLY CURRENT (mA)
POWER SUPPLY VOLTAGE (V)
3
01.5
3.5
3
3.5
0
1
2
1 2
0.5
1.5
2.5
0.5
HPR_SD = 0
HPR_SD = 1
2.5
POWER SUPPLY CURRENT (mA)
POWER SUPPLY VOLTAGE (V)
3
04
4
3
6
0
1
2
12
0.5
1.5
2.5
3.5
5
Gain_SD = 0
EP_mode = 0
Gain_SD = 0
EP_mode = 1
Gain_SD = 1
EP_mode = 0
Gain_SD = 1
EP_mode = 1
POWER SUPPLY CURRENT (mA)
POWER SUPPLY VOLTAGE (V)
3
04
4
3
6
0
1
2
12
0.5
1.5
2.5
3.5
5
Gain_SD = 0
EP_mode = 0
Gain_SD = 0
EP_mode = 1
Gain_SD = 1
EP_mode = 0
Gain_SD = 1
EP_mode = 1
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Typical Performance Characteristics (continued)
Supply Current vs Supply Voltage (VDDLS) Supply Current vs Supply Voltage (VDDLS)
VDDHP = 2.75V, No Load, Gain_SD = 0 & 1 VDDHP = 2.75V, No Load, Gain_SD = 0 & 1
LS (EP_Mode) = 0 & 1, Mode 1 LS (EP_Mode) = 0 & 1, Mode 2
Figure 33. Figure 34.
Supply Current vs Supply Voltage (VDDHP) Supply Current vs Supply Voltage (VDDLS)
VDDLS = 3.3V, No Load, Gain_SD = 0 or 1 VDDHP = 2.75V, No Load, Gain_SD = 0 or 1
HPR_SD = 0 & 1, Modes 4, 8, 15 LS (EP_Mode) = 0 & 1, Mode 15
Figure 35. Figure 36.
Output Power vs Supply Voltage (VDDLS) Output Power vs Supply Voltage (VDDHP)
VDDHP = 2.75V, RL= 8ΩBTL, Mode 1 VDDLS = 3.3V, RL= 32ΩSE, Mode 4
Figure 37. Figure 38.
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SCL SP
START condition STOP condition
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APPLICATION INFORMATION
I2C COMPATIBLE INTERFACE
The LM49101 is controlled through an I2C compatible serial interface that consists of a serial data line (SDA) and
a serial clock (SCL). The clock line is uni-directional. The data line is bi-directional (open drain). The LM49101
and the master can communicate at clock rates up to 400kHz. Figure 39 shows the I2C interface timing diagram.
Data on the SDA line must be stable during the HIGH period of SCL. The LM49101 is a transmit/receive slave-
only device, reliant upon the master to generate the SCL signal. Each transmission sequence is framed by a
START condition and a STOP condition (Figure 40). Each data word, device address and data, transmitted over
the bus is 8 bits long and is always followed by an acknowledge pulse (Figure 41). The LM49101 device address
is 11111000.
I2C INTERFACE POWER SUPPLY PIN (I2CVDD)
The LM49101's I2C interface is powered up through the I2CVDD pin. The LM49101's I2C interface operates at a
voltage level set by the I2CVDD pin which can be set independent to that of the main power supply pin VDDLS.
This is ideal whenever logic levels for the I2C interface are dictated by a microcontroller or microprocessor that is
operating at a lower supply voltage than the VDDLS voltage.
I2C BUS FORMAT
The I2C bus format is shown in Figure 41. The START signal, the transition of SDA from HIGH to LOW while
SCL is HIGH, is generated, alerting all devices on the bus that a device address is being written to the bus.
The 7-bit device address is written to the bus, most significant bit (MSB) first, followed by the R/W bit. R/W = 0
indicates the master is writing to the slave device, R/W = 1 indicates the master wants to read data from the
slave device. Set R/W = 0; the LM49101 is a WRITE-ONLY device and will not respond to the R/W = 1. The data
is latched in on the rising edge of the clock. Each address bit must be stable while SCL is HIGH. After the last
address bit is transmitted, the master device releases SDA, during which time, an acknowledge clock pulse is
generated by the slave device. If the LM49101 receives the correct address, the device pulls the SDA line low,
generating an acknowledge bit (ACK).
Once the master device registers the ACK bit, the 8-bit register data word is sent. Each data bit should be stable
while SCL is HIGH. After the 8-bit register data word is sent, the LM49101 sends another ACK bit. Following the
acknowledgement of the register data word, the master issues a STOP bit, allowing SDA to go high while SCL is
high.
Figure 39. I2C Timing Diagram
Figure 40. Start and Stop Diagram
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SCL
SDA STOPMSB REGISTER DATA LSB ACK
R/W
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Figure 41. Start and Stop Diagram
Table 2. Chip Address
A7 A6 A5 A4 A3 A2 A1 A0
Chip Address 1 1 1 1 1 0 0 0
Table 3. Control Registers(1)
Register D7 D6 D5 D4 D3 D2 D1 D0
LS
General Control 0 0 1 GAMP_SD(2) 0 Turn_On _Time(4) Power_On(5)
(EP_Mode)(3)
EP
Output Mode Control 0 1 HPR_SD(6) Mode_ Control(7)
Bypass(6)
Output Gain Control 1 0 0 Input_Mute(8) LS_Gain(9) HP_Gain(10)
Mono Input Volume Mono_Vol(11)
1 0 1
Control
Left Input Volume Left_Vol(11)
1 1 0
Control
Right Input Volume Right_Vol(11)
1 1 1
Control
(1) All registers default to 0 on initial power-up.
(2) GAMP_SD: Is used to shut down gain amplifiers not in use and reduce current consumption. See Table 4.
(3) LS (EP_Mode): Loudspeaker power amplifier bias current reduction. See Table 4.
(4) Turn_On_Time: Reduces the turn on time for faster activation. See Table 4.
(5) Power_On: Master Power on bit. See Table 4.
(6) EP Bypass: Earpiece bypass mode to allow BYPASS inputs to drive speaker outputs. See Table 5.
(7) Mode_Control: Sets the output mode. See Table 5.
(8) Input Mute: Controls muting of the inputs except the BYPASS inputs. See Table 6.
(9) LS_Gain: Sets the gain of the loudspeaker amplifier to 0dB or 6dB. See Table 6.
(10) HP_Gain: Sets the headphone amplifier output gain. See Table 6.
(11) Mono_Vol/Left_Vol/Right_Vol: Sets the input volume for Mono, Left and Right inputs. See Table 7.
Table 4. General Control Register
Bit Name Value Description
This bit is a master shutdown control bit and sets the device to be on or off.
Value Status
0 Power_On 0 Master power off, device disable.
1 Master power on, device enable.
This bit sets the turn on time of the device.
Value Status
1 Turn_On_Time 0 Normal Turn-on time
1 Fast Turn-on time
This bit enables EP Mode reducing loudspeaker output stage bias current by 500μA.
Value Status
3 LS (EP Mode) 0 Normal loudspeaker power amplifier operation.
Enables EP Mode reducing loudspeaker output stage bias current by
1500μA.
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Table 4. General Control Register (continued)
Bit Name Value Description
This bit is used to reduce IDD by shutting down gain amplifiers not in use.
0 Normal operation of all gain amplifiers.
4 GAMP_SD Disables the input gain amplifiers that are not in use to reduce current
1from VDDLS. Recommended for Output Modes 1, 2, 4, 5, 8, 10.
Table 5. Output Mode Control Register(1)
Bits Field Description
3:0 Mode_Control These bits determine how the input signals are mixed and routed to the outputs.
D3 D2 D1 D0
Headphone Loudspeaker
D3D2D1D0Mode Left Headphone Right Headphone
0000 0 SD SD SD
0001 1 SD SD GMx M
0010 2 SD SD 2 x (GLx L + GRx R)
2 x (GLx L + GRx R)
0011 3 SD SD + GMx M
0100 4 GMx M/2 GMx M/2 SD
0101 5 GMx M/2 GMx M/2 GMx M
0110 6 GMx M/2 GMx M/2 2 x (GLx L + GRx R)
2 x (GLx L + GRx R)
0111 7 GMx M/2 GMx M/2 + GMx M
1000 8 GLx L GRx R SD
1001 9 GLx L GRx R GMx M
1010 10 GLx L GRx R 2 x (GLx L + GRx R)
2 x (GLx L + GRx R)
1011 11 GLx L GRx R + GMx M
GLx L + GMx GRx R + GMx
1100 12 SD
M/2 M/2
GLx L + GMx GRx R + GMx
1101 13 GMx M
M/2 M/2
GLx L + GMx GRx R + GMx
1110 14 2 x (GLx L + GRx R)
M/2 M/2
GLx L + GMx GRx R + GMx 2 x (GLx L + GRx R)
1111 15 M/2 M/2 + GMx M
This bit sets the headphone amplifiers to normal mode or mono mode.
Value Status
4 HPR_SD 0 Normal stereo headphone operation.
1 Disable right headphone output.
This bit is used to control the analog switch to have the BYPASS inputs drive the loudspeaker outputs.
Value Status
5 EP Bypass 0 Normal output mode operation with analog switch off.
Loudspeaker and headphone amplifiers go into shutdown mode and Bypass (Receiver) path enable
1with the analog switch on.
(1) M : MIN, Mono differential input
L : LIN, Left single-ended input
R : RIN, Right single-ended input
SD : Shutdown
GM: Mono_Vol setting determined by the Mono Input Volume Control register, See Table 7.
GL: Left_Vol setting determined by the Left Input Volume Control register, See Table 7.
GR: Right_Vol setting determined by the Right Input Volume Control register, See Table 7.
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Table 6. Output Gain Control Register
Bits Field Description
These bits set the gain of the headphone output amplifiers.
Value Gain (dB)
000 0
001 –1.2
010 –2.5
2:0 HP_GAIN 011 –4.0
100 –6.0
101 –8.5
110 –12
111 –18
This bit sets the loudspeaker output amplifier gain.
Value Status
3 LS_GAIN 0 Loudspeaker output amplifier gain is set to 0dB.
1 Loudspeaker output amplifier gain is set to 6dB.
This bit will set all the inputs except the BYPASS inputs to be in Mute mode.
Value Status
0 Normal operation of all inputs.
4 INPUT MUTE Mutes all inputs except BYPASS with over 80dB of attenuation
with out adjusting the volume settings. This bit can be used to
1 mute the inputs to eliminate noise or transients from other
systems and ICs. See INPUT MUTE BIT for a detailed
explanation.
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Table 7. Input Volume Control Registers
Bits Fields Description
4:0 Mono_Vol These bits set the input volume for each input volume register listed.
Right_Vol Volume Step Value Gain (dB)
Left_Vol 1 00000 –80.0
2 00001 –46.5
3 00010 –40.5
4 00011 –34.5
5 00100 –30.0
6 00101 –27.0
7 00110 –24.0
8 00111 –21.0
9 01000 –18.0
10 01001 –15.0
11 01010 –13.5
12 01011 –12.0
13 01100 –10.5
14 01101 –9.0
15 01110 –7.5
16 01111 –6.0
17 10000 –4.5
18 10001 –3.0
19 10010 –1.5
20 10011 0.0
21 10100 1.5
22 10101 3.0
23 10110 4.5
24 10111 6.0
25 11000 7.5
26 11001 9.0
27 11010 10.5
28 11011 12.0
29 11100 13.5
30 11101 15.0
31 11110 16.5
32 11111 18.0
HW RESET FUNCTION
The LM49101 can be globally reset without using the I2C controls. When the HW RESET pin is set to a logic low
the LM49101 will enter into shutdown, the mode control bits of the Output Mode Control register, volume control
registers and Power_On bits will be set to the default value of zero. The other bits will retain their values. The
LM49101 cannot be activated until the HW RESET pin is set to a logic high voltage. When the HW RESET is set
to a logic high then the I2C controls can activate and set the register control bits.
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GAMP_SD BIT
The GAMP_SD bit allows for reduced power consumption. When set to '1' the gain amplifiers on unused inputs
will be shutdown saving approximately 0.4mA per input in shutdown. For example, in Mode 1 only the mono
inputs are in use. Setting GAMP_SD to '1' will shut down the gain amplifiers for the left and right inputs reducing
current draw from the VDDLS supply by approximately 0.8mA. The GAMP_SD bit does not need to be set each
time when changing modes as the LM49101 will automatically activate and deactivate the needed inputs based
on the mode selected.
When operating with GAMP_SD set to '1', a transient may be observed on the outputs when changing modes.
During power up, the LM49101 uses a start up sequence to eliminate any pops and clicks on the outputs. The
volume control circuitry is powered up first followed by the other internal circuitry with the output amplifiers being
powered up last. If a mode change requires a gain amplifier to turn on then a potential transient may be created
that is amplified on the already active outputs. To eliminate unwanted noise on the outputs the Power_On bit
should be used to turn off the LM49101 before changing modes, perform a mode change, then turn the LM49101
back on. This procedure will cause the LM49101 to follow the start up sequence.
LS (EP_MODE) BIT
The LS (EP_Mode) bit selects the amount of bias current in the loudspeaker amplifier. Setting the LS (EP_Mode)
bit to a '1' will reduce the amount of current from the VDDLS supply by approximately 0.5mA. The THD
performance of the loudspeaker amplifier will be reduced as a result of lower bias current. See the performance
graphs in Typical Performance Characteristics.
TURN_ON_TIME BIT
The Turn_On_Time bit determines the delay time from the Power_On bit set to '1' and the internal circuits ready.
For input capacitor values up to 0.47μF the Turn_On_Time bit can be set to fast mode by setting the bit to a '1'.
When the input capacitor values are larger than 0.47μF then the Turn_On_Time bit should be set to '0' for normal
turn-on time and higher delay. This allows sufficient time to charge the input capacitors to the ½ VDDLS bias
voltage.
POWER_ON BIT
The Power_On bit is the master control bit to activate or deactivate the LM49101. All registers can be loaded
independent of the Power_On bit setting as long as the IC is powered correctly. Cycling the Power_On bit does
not change the values of any registers nor return all bits to the default power on value of zero. The Power_On bit
only determines whether the IC is on or off.
EP BYPASS BIT
The EP Bypass bit is used to set the LM49101 to earpiece mode. When this bit is set the analog switch is
activated and the rest of the IC blocks except for the I2C circuitry will go into shutdown for minimal current
consumption.
HPR_SD BIT
The HPR_SD bit will deactivate the right headphone output amplifier. This bit is provided to reduce power
consumption when only one headphone output is needed.
MODE_CONTROL BITS
The LM49101 includes a comprehensive mixer multiplexer controlled through the I2C interface. The
mixer/multiplexer allows any input combination to appear on any output of LM49101. Multiple input paths can be
selected simultaneously. Under these conditions, the selected inputs are mixed together and output on the
selected channel. Table 5 shows how the input signals are mixed together for each possible input selection.
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INPUT MUTE BIT
The Input Mute bit will mute all inputs except the Bypass inputs when set to a '1'. This allows complete and quick
mute of the Mono, Left, and Right inputs without changing the Volume Control registers or HP_Gain bits. The
volume and HP_Gain bits retain their values when the Input Mute is enabled or disabled.
The Input Mute bit can be used to mute all the inputs when other chips in a system, such as the baseband IC,
create transients causing unwanted noise on the outputs of the LM49101. This added feature eliminates the
need for power cycling the LM49101.
LS_GAIN BIT
The loudspeaker amplifier can have an additional gain of 0dB or 6dB by using the LS_Gain bit. The Mono input
has 6dB of attenuation before the volume control (see Figure 1) while the Left and Right inputs do not. The
LS_Gain bit is used to account for the different attenuation levels for each input and to achieve maximum output
power. To obtain maximum output power on the loudspeaker outputs, the LS_Gain bit should be se to '1' for
Modes 1, 5, 9, 13.
HP_GAIN BITS
The headphone outputs have an additional, single volume control set by the three HP_Gain bits in the Output
Gain Control register. The HP_Gain volume setting controls the output level for both the left and the right
headphone outputs.
VOLUME CONTROL BITS
The LM49101 has three independent 32-step volume controls, one for each of the inputs. The five bits of the
Volume Control registers sets the volume for the specified input channel.
SHUTDOWN FUNCTION
The LM49101 features the following shutdown controls.
Bit D4 (GAMP_SD) of the GENERAL CONTROL register controls the gain amplifiers. When GAMP_SD = 1, it
disables the gain amplifiers that are not in use. For example, in Modes 1, 4 and 5, the Mono inputs are in use, so
the Left and Right input gain amplifiers are disabled, causing the IDD to be minimized.
Bit D0 (Power_On) of the GENERAL CONTROL register is the global shutdown control for the entire device. Set
Power_On = 0 for normal operation. Power_On = 1 overrides any other shutdown control bit.
DIFFERENTIAL AMPLIFIER EXPLANATION
The LM49101 features a differential input stage, which offers improved noise rejection compared to a single-
ended input amplifier. Because a differential input amplifier amplifies the difference between the two input
signals, any component common to both signals is cancelled. An additional benefit of the differential input
structure is the possible elimination of the DC input blocking capacitors. Since the DC component is common to
both inputs, and thus cancelled by the amplifier, the LM49101 can be used without input coupling capacitors
when configured with a differential input signal.
BRIDGE CONFIGURATION EXPLAINED
By driving the load differentially through the MONO outputs, an amplifier configuration commonly referred to as
“bridged mode” is established. Bridged mode operation is different from the classical single-ended amplifier
configuration where one side of the load is connected to ground.
A bridge amplifier design has a few distinct advantages over the single-ended configuration, as it provides
differential drive to the load, thus doubling output swing for a specified supply voltage. Four times the output
power is possible as compared to a single-ended amplifier under the same conditions. This increase in attainable
output power assumes that the amplifier is not current limited or clipped.
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A bridge configuration, such as the one used in LM49101, also creates a second advantage over single-ended
amplifiers. Since the differential outputs are biased at half-supply, no net DC voltage exists across the load. This
eliminates the need for an output coupling capacitor which is required in a single supply, single-ended amplifier
configuration. Without an output coupling capacitor, the half-supply bias across the load would result in both
increased internal IC power dissipation and also possible loudspeaker damage.
POWER DISSIPATION
Power dissipation is a major concern when designing a successful amplifier, whether the amplifier is bridged or
single-ended. A direct consequence of the increased power delivered to the load by a bridge amplifier is an
increase in internal power dissipation. The power dissipation of the LM49101 varies with the mode selected. The
maximum power dissipation occurs in modes where all inputs and outputs are active (Modes 6, 7, 8, 9, 10, 11,
13, 14, 15). The power dissipation is dominated by the Class AB amplifier. The maximum power dissipation for a
given application can be derived from the power dissipation graphs or from Equation 1.
PDMAX = 4*(VDD)2/(2π2RL) (1)
It is critical that the maximum junction temperature (TJMAX) of 150°C is not exceeded. TJMAX can be determined
from the power derating curves by using PDMAX and the PC board foil area. By adding additional copper foil, the
thermal resistance of the application can be reduced from the free air value, resulting in higher PDMAX. Additional
copper foil can be added to any of the leads connected to the LM49101. It is especially effective when connected
to VDD, GND, and the output pins. Refer to Demonstration Board for an example of good heat sinking. If TJMAX
still exceeds 150°C, then additional changes must be made. These changes can include reduced supply voltage,
higher load impedance, or reduced ambient temperature. Internal power dissipation is a function of output power.
Refer to the Typical Performance Characteristics curves for power dissipation information for different output
powers and output loading.
POWER SUPPLY BYPASSING
As with any amplifier, proper supply bypassing is critical for low noise performance and high power supply
rejection. The capacitor location on both the bypass and power supply pins should be as close to the device as
possible. Typical applications employ a 5V regulator with 10µF tantalum or electrolytic capacitor and a ceramic
bypass capacitor which aid in supply stability. This does not eliminate the need for bypassing the supply nodes of
the LM49101. The selection of a bypass capacitor, especially CB, is dependent upon PSRR requirements, click
and pop performance, system cost, and size constraints.
GROUND REFERENCED HEADPHONE AMPLIFIER
The LM49101 features a low noise inverting charge pump that generates an internal negative supply voltage.
This allows the headphone outputs to be biased about GND instead of a nominal DC voltage, like traditional
headphone amplifiers. Because there is no DC component, the large DC blocking capacitors (typically 220μF)
are not necessary. The coupling capacitors are replaced by two small ceramic charge pump capacitors, saving
board space and cost. Eliminating the output coupling capacitors also improves low frequency response. In
traditional headphone amplifiers, the headphone impedance and the output capacitor from a high-pass filter that
not only blocks the DC component of the output, but also attenuates low frequencies, impacting the bass
response. Because the LM49101 does not require the output coupling capacitors, the low frequency response of
the device is not degraded by external components. In addition to eliminating the output coupling capacitors, the
ground referenced output nearly doubles the available dynamic range of the LM49101 headphone amplifiers
when compared to a traditional headphone amplifier operating from the same supply voltage.
HEADPHONE & CHARGE PUMP SUPPLY VOLTAGE (VDDHP & VDDCP)
The headphone outputs are centered at ground by using dual supply voltages for the headphone amplifier. The
positive power supply is set by the voltage on the VDDHP pin while the negative supply is created with an internal
charge pump. The negative supply voltage is equal in magnitude but opposite in voltage to the voltage on the
VDDCP pin.
INPUT CAPACITOR SELECTION
Input capacitors may be required for some applications, or when the audio source is single-ended. Input
capacitors block the DC component of the audio signal, eliminating any conflict between the DC component of
the audio source and the bias voltage of the LM49101. The input capacitors create a high-pass filter with the
input resistors RIN. The -3dB point of the high-pass filter is found using Equation 2 below.
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f = 1 / 2πRINCIN (Hz) (2)
Where the value of RIN is given in Electrical Characteristics VDDLS = 3.3V, VDDHP = 2.75V and Electrical
Characteristics VDDLS = 5.0V, VDDHP = 2.75V as ZIN.
When the LM49101 is using a single-ended source, power supply noise on the ground is seen as an input signal.
Setting the high-pass filter point above the power supply noise frequencies, 217Hz in a GSM phone, for example,
filters out the noise such that it is not amplified and heard on the output. Capacitors with a tolerance of 10% or
better are recommended for impedance matching and improved CMRR and PSRR.
CHARGE PUMP FLYING CAPACITOR (C1)
The flying capacitor (C1), see Figure 1, affects the load regulation and output impedance of the charge pump. A
C1value that is too low results in a loss of current drive, leading to a loss of amplifier headroom. A higher valued
C1improves load regulation and lowers charge pump output impedance to an extent. Above 2.2μF, the RDS(ON)
of the charge pump switches and the ESR of C1and Cs3 dominate the output impedance. A lower value capacitor
can be used in systems with low maximum output power requirements.
CHARGE PUMP HOLD CAPACITOR (CS3)
The value and ESR of the hold capacitor Cs3 directly affects the ripple on VSSCP. Increasing the value of Cs3
reduces output ripple. Decreasing the ESR of Cs3 reduces both output ripple and charge pump output
impedance. A lower value capacitor can be used in systems with low maximum output power requirements.
SELECTION OF INPUT RESISTORS
The Bypass_In inputs connect to the loudspeaker output through an FET switch when EP Bypass is active (see
Figure 42). Because THD through this path is mainly dominated by the switch impedance variation, adding input
resistors (R3and R4in Figure 42) will help reduce impedance effects resulting in improved THD. For example, a
change in the switch impedance from 2Ωto 3Ωis a 67% change in impedance. If 10Ωinput resistors are used
then the impedance change is from 12Ωto 13Ω, only 7.7% impedance variation. The analog switch impedance is
typically 2Ωto 3.4Ω. The switch impedance change is a result of heating and the increase in RDS(ON) of the FETs.
The value of the input resistors must be balanced against the amount of output current and the load impedance
on the loudspeaker outputs. A higher value input resistor reduces the effects of switch impedance variation but
also causes voltage drop and reduced power to the load on the loudspeaker outputs.
The current through the FET switch should not exceed 500mA or die heating may cause thermal shut down
activation and potential IC damage.
MINIMUM POWER OPERATION
The LM49101 has several options to reduce power consumption and is designed to conserve power when
possible. When a speaker only mode is selected the headphone sections are shutdown and the current drawn
from the VDDHP/VDDCP power supply will be zero. When a headphone mode is selected the current drawn from
the VDDLS supply is also reduced by shutting down unused circuitry. See the various Supply Current vs Supply
Voltage graphs in Typical Performance Characteristics.
To reduce power consumption further, the additional control bits GAMP_SD, LS (EP Mode), and HPR_SD are
provided. When low power consumption is more important than the THD performance of the loudspeaker the LS
(EP_mode) bit should be set to '1' saving approximately 0.5mA from the VDDLS supply. The GAMP_SD bit
should be set on to save approximately 0.4mA for each input shut down. For modes where only the mono input
is used, up to 0.8mA can be saved from the VDDLS supply. Also, the HPR_SD bit can be used to shut down the
right headphone channel reducing power consumption when only one amplifier headphone output is needed.
Additionally, the supply voltages for the different VDD pins (VDDLS, VDDHP, and VDDCP) can be set to the
minimum needed values to obtain the output power levels required by the design. By reducing the supply voltage
the total power consumption will be reduced.
For best system efficiency, a DC-DC converter (buck) can be used to power the VDDHP and VDDCP voltages
from the VDDLS supply instead of a linear regulator. DC-DC converters achieve much higher efficiency (> 90%)
than even a low dropout regulator (LDO).
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SNAS475A –MARCH 2009–REVISED APRIL 2013
Demo Board Circuit
Figure 42. Demo Board Circuit
Demonstration Board
The demonstration board (see Figure 42) has connection and jumper options to be powered partially from the
USB bus or from external power supplies. Additional options are to power the I2C logic and loudspeaker amplifier
(VDDLS) from a single power supply or separate power supplies. The headphone amplifier and charge pump can
also be powered from the same supply as long as the voltage limits for each power supply are not exceeded,
although the option is not built into the board. See Operating Ratings for each supply's range limit. When
powered from the USB bus the I2CVDD will be set to 3.3V and the VDDLS will be set to 5V. Jumper headers J13
and J12 must be set accordingly. If a single power supply for I2CVDD and VDDLS is desired then header J5should
be used with a jumper added to header J11 to connect I2CVDD to the external supply voltage connected to J5(see
Figure 42).
Connection headers J1and J2are provided along with the stereo headphone jack J4for easily connection and
monitoring of the headphone outputs.
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LM49101 DSBGA Demo Board Views
Figure 43. Composite View Figure 44. Silk Screen
Figure 45. Top Layer Figure 46. Internal Layer 1
Figure 47. Internal Layer 2 Figure 48. Bottom Layer
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SNAS475A –MARCH 2009–REVISED APRIL 2013
LM49101 Reference Demo Board Bill Of Materials
Table 8. Bill Of Materials
Designator Vlaue Tolerance Part Description Comment
R1, R25.1kΩ5% 1/10W, 0603 Resistors
R3, R410Ω1% 1/10W, 0603 Resistors
R5100kΩ5% 1/10W, 0805 Resistor
CIN1, CIN2 1μF 10% 1206, X7R Ceramic Capacitor
CIN3, CIN4
CS1, CS4 2.2μF 10% Size A, Tantalum Capacitor
CS5, CB
CS2 0.1μF 10% 0805, 16V, X7R Ceramic Capacitor
CS3, C12.2μF 10% 0603, 10V, X7R Ceramic Capacitor
U1LM49101TM
J1, J2, J3
J5, J7, J80.100" 1x2 header, vertical mount Input, Output, VDD, GND
J9, J10, J14
J11, J12, J13 0.100" 1x3 header, vertical mount VDD Selects, VDD, I2CVDD, GND
J616 pin header I2C Connector
J4Headphone Jack
SW1 Momentary Push Switch RESET function
PCB Layout Guidelines
This section provides practical guidelines for mixed signal PCB layout that involves various digital/analog power
and ground traces. Designers should note that these are only "rule-of-thumb" recommendations and the actual
results will depend heavily on the final layout.
General Mixed Signal Layout Recommendations
SINGLE-POINT POWER AND GROUND CONNECTIONS
The analog power traces should be connected to the digital traces through a single point (link). A "Pi-filter" can
be helpful in minimizing high frequency noise coupling between the analog and digital sections. It is further
recommended to put digital and analog power traces over the corresponding digital and analog ground traces to
minimize noise coupling.
PLACEMENT OF DIGITAL AND ANALOG COMPONENTS
All digital components and high-speed digital signals traces should be located as far away as possible from
analog components and circuit traces.
AVOIDING TYPICAL DESIGN AND LAYOUT PROBLEMS
Avoid ground loops or running digital and analog traces parallel to each other (side-by-side) on the same PCB
layer. When traces must cross over each other do it at 90 degrees. Running digital and analog traces at 90
degrees to each other from the top to the bottom side as much as possible will minimize capacitive noise
coupling and cross talk.
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Revision History
Rev Date Description
0.01 10/18/08 Initial released.
A 04/08/13 Changed layout of National Data Sheet to TI format.
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PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Top-Side Markings
(4)
Samples
LM49101TM/NOPB ACTIVE DSBGA YFQ 25 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 GL4
LM49101TMX/NOPB ACTIVE DSBGA YFQ 25 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 GL4
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM49101TM/NOPB DSBGA YFQ 25 250 178.0 8.4 2.18 2.18 0.76 4.0 8.0 Q1
LM49101TMX/NOPB DSBGA YFQ 25 3000 178.0 8.4 2.18 2.18 0.76 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Apr-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM49101TM/NOPB DSBGA YFQ 25 250 210.0 185.0 35.0
LM49101TMX/NOPB DSBGA YFQ 25 3000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Apr-2013
Pack Materials-Page 2
MECHANICAL DATA
YFQ0025xxx
www.ti.com
TMD25XXX (Rev C)
A
. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
NOTES:
4215084/A 12/12
D
0.600
±0.075
E
D: Max =
E: Max =
2.082 mm, Min =
2.076 mm, Min =
2.022 mm
2.016 mm
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