MX25L2026E MX25L2026E DATASHEET P/N: PM1580 1 REV. 1.2, FEB. 10, 2012 MX25L2026E Contents FEATURES................................................................................................................................................................... 4 GENERAL DESCRIPTION.......................................................................................................................................... 5 PIN CONFIGURATIONS............................................................................................................................................... 5 PIN DESCRIPTION....................................................................................................................................................... 5 BLOCK DIAGRAM........................................................................................................................................................ 6 MEMORY ORGANIZATION.......................................................................................................................................... 7 Table 1. Memory Organization.............................................................................................................................. 7 DEVICE OPERATION................................................................................................................................................... 8 Figure 1. Serial Peripheral Interface Modes Supported........................................................................................ 8 DATA PROTECTION..................................................................................................................................................... 9 Table 2. Protected Area Sizes............................................................................................................................... 9 HOLD FEATURE......................................................................................................................................................... 10 Figure 2. Hold Condition Operation . .................................................................................................................. 10 Table 3. COMMAND DEFINITION...................................................................................................................... 11 COMMAND DESCRIPTION........................................................................................................................................ 12 (1) Write Enable (WREN).................................................................................................................................... 12 (2) Write Disable (WRDI)..................................................................................................................................... 12 (3) Read Status Register (RDSR)....................................................................................................................... 13 (4) Write Status Register (WRSR)....................................................................................................................... 14 Table 4. Protection Modes................................................................................................................................... 14 (5) Read Data Bytes (READ).............................................................................................................................. 15 (6) Read Data Bytes at Higher Speed (FAST_READ)........................................................................................ 15 (7) Dual Output Mode (DREAD).......................................................................................................................... 15 (8) Sector Erase (SE).......................................................................................................................................... 15 (9) Block Erase (BE)............................................................................................................................................ 16 (10) Chip Erase (CE)........................................................................................................................................... 16 (11) Page Program (PP)...................................................................................................................................... 16 (12) Deep Power-down (DP)............................................................................................................................... 17 (13) Release from Deep Power-down (RDP), Read Electronic Signature (RES) .............................................. 17 (14) Read Identification (RDID)........................................................................................................................... 18 (15) Read Electronic Manufacturer ID & Device ID (REMS)............................................................................... 18 Table 5. ID Definitions......................................................................................................................................... 18 (15) Read SFDP Mode (RDSFDP)...................................................................................................................... 19 Read Serial Flash Discoverable Parameter (RDSFDP) Sequence..................................................................... 19 Table a. Signature and Parameter Identification Data Values ............................................................................ 20 Table b. Parameter Table (0): JEDEC Flash Parameter Tables.......................................................................... 21 Table c. Parameter Table (1): Macronix Flash Parameter Tables........................................................................ 23 POWER-ON STATE.................................................................................................................................................... 25 ELECTRICAL SPECIFICATIONS............................................................................................................................... 26 ABSOLUTE MAXIMUM RATINGS...................................................................................................................... 26 P/N: PM1580 2 REV. 1.2, FEB. 10, 2012 MX25L2026E Figure 3. Maximum Negative Overshoot Waveform........................................................................................... 26 CAPACITANCE TA = 25C, f = 1.0 MHz.............................................................................................................. 26 Figure 4. Maximum Positive Overshoot Waveform............................................................................................. 26 Figure 5. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL............................................................... 27 Figure 6. OUTPUT LOADING............................................................................................................................ 27 Table 6. DC CHARACTERISTICS (Temperature = -40C to 85C, VCC = 2.7V ~ 3.6V) .................................. 28 Table 7. AC CHARACTERISTICS (Temperature = -40C to 85C, VCC = 2.7V ~ 3.6V) .................................. 29 Table 8. Power-Up Timing................................................................................................................................... 30 Timing Analysis......................................................................................................................................................... 31 Figure 7. Serial Input Timing............................................................................................................................... 31 Figure 8. Output Timing....................................................................................................................................... 31 Figure 9. Hold Timing.......................................................................................................................................... 32 Figure 10. WP# Disable Setup and Hold Timing during WRSR when SRWD=1................................................ 32 Figure 11. Write Enable (WREN) Sequence (Command 06).............................................................................. 33 Figure 12. Write Disable (WRDI) Sequence (Command 04)............................................................................... 33 Figure 13. Read Status Register (RDSR) Sequence (Command 05)................................................................. 33 Figure 14. Write Status Register (WRSR) Sequence (Command 01)................................................................ 34 Figure 15. Read Data Bytes (READ) Sequence (Command 03)....................................................................... 34 Figure 16. Read at Higher Speed (FAST_READ) Sequence (Command 0B).................................................... 35 Figure 17. Dual Output Read Mode Sequence (Command 3B).......................................................................... 35 Figure 18. Sector Erase (SE) Sequence (Command 20)................................................................................... 36 Figure 19. Block Erase (BE) Sequence (Command 52 or D8)........................................................................... 36 Figure 20. Chip Erase (CE) Sequence (Command 60 or C7)............................................................................ 36 Figure 21. Page Program (PP) Sequence (Command 02)................................................................................. 37 Figure 22. Deep Power-down (DP) Sequence (Command B9).......................................................................... 37 Figure 23. Read Electronic Signature (RES) Sequence (Command AB)........................................................... 38 Figure 24. Release from Deep Power-down (RDP) Sequence (Command AB)................................................ 38 Figure 25. Read Identification (RDID) Sequence (Command 9F)....................................................................... 39 Figure 26. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90)............................... 39 Figure 27. Power-up Timing................................................................................................................................ 40 OPERATING CONDITIONS........................................................................................................................................ 41 Figure 28. AC Timing at Device Power-Up.......................................................................................................... 41 Figure 29. Power-Down Sequence..................................................................................................................... 42 ERASE AND PROGRAMMING PERFORMANCE..................................................................................................... 43 DATA RETENTION .................................................................................................................................................... 43 LATCH-UP CHARACTERISTICS............................................................................................................................... 43 ORDERING INFORMATION....................................................................................................................................... 44 PART NAME DESCRIPTION...................................................................................................................................... 45 PACKAGE INFORMATION......................................................................................................................................... 46 REVISION HISTORY ................................................................................................................................................. 47 P/N: PM1580 3 REV. 1.2, FEB. 10, 2012 MX25L2026E 2M-BIT [x 1/x 2] CMOS SERIAL FLASH FEATURES GENERAL * Serial Peripheral Interface compatible -- Mode 0 and Mode 3 * 2,097,152 x 1 bit structure or 1,048,576 x 2 bits (Dual Output mode) structure * 64 Equal Sectors with 4K byte each - Any Sector can be erased individually * 4 Equal Blocks with 64K byte each - Any Block can be erased individually * Single Power Supply Operation - 2.7 to 3.6 volt for read, erase, and program operations * Latch-up protected to 100mA from -1V to Vcc +1V PERFORMANCE * High Performance - Fast access time: 86MHz serial clock - Serial clock of Dual Output mode: 80MHz - Fast program time: 1.4ms(typ.) and 5ms(max.)/page - Byte program time: 9us - Fast erase time: 60ms(typ.)/sector (4K-byte per sector) ; 0.7s(typ.)/block (64K-byte per block) * Low Power Consumption - Low active read current: 12mA(max.) at 86MHz and 4mA(max.) at 33MHz - Low active programming current: 20mA (max.) - Low active erase current: 20mA (max.) - Low standby current: 25uA (max.) - Deep power-down mode 5uA (typ.) * Minimum 100,000 erase/program cycles * 20 years data retention SOFTWARE FEATURES * Input Data Format - 1-byte Command code * Block Lock protection - The BP0~BP1 status bit defines the size of the area to be software protected against Program and Erase instructions * Auto Erase and Auto Program Algorithm - Automatically erases and verifies data at selected sector - Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths (Any page to be programed should have page in the erased state first) * Status Register Feature * Electronic Identification - JEDEC 2-byte Device ID - RES command, 1-byte Device ID * Support Serial Flash Discoverable Parameters (SFDP) mode HARDWARE FEATURES * PACKAGE - 8-pin SOP (150mil) - All devices are RoHS Compliant P/N: PM1580 4 REV. 1.2, FEB. 10, 2012 MX25L2026E GENERAL DESCRIPTION The device features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The four bus signals are a clock input (SCLK), a serial data input (SI), a serial data output (SO), and a chip select (CS#). Serial access to the device is enabled by CS# input. When it is in Dual Output read mode, the SI and SO pins become SIO0 and SIO1 pins for data output. The device provides sequential read operation on whole chip. After program/erase command is issued, auto program/erase algorithms which program/erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page basis, or word basis for erase command is executes on sector, or block, or whole chip basis. To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit. When the device is not in operation and CS# is high, it is put in standby mode. The device utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles. PIN DESCRIPTION PIN CONFIGURATIONS 8-PIN SOP (150mil) CS# SO/SIO1 WP# GND P/N: PM1580 1 2 3 4 8 7 6 5 SYMBOL DESCRIPTION CS# Chip Select Serial Data Input (for 1 x I/O) / Serial Data SI/SIO0 Input & Output (for Dual Output mode) Serial Data Output (for 1 x I/O) / Serial SO/SIO1 Data Output (for Dual Output mode) SCLK Clock Input WP# Write Protection Hold, to pause the device without HOLD# deselecting the device VCC + 3.3V Power Supply GND Ground VCC HOLD# SCLK SI/SIO0 5 REV. 1.2, FEB. 10, 2012 MX25L2026E BLOCK DIAGRAM X-Decoder Address Generator Memory Array Page Buffer SI Data Register Y-Decoder SRAM Buffer CS# Mode Logic State Machine Sense Amplifier Output Buffer HV Generator SO SCLK P/N: PM1580 Clock Generator 6 REV. 1.2, FEB. 10, 2012 MX25L2026E MEMORY ORGANIZATION Table 1. Memory Organization Block 3 2 1 0 P/N: PM1580 Sector 63 : 48 47 : 32 31 : 16 15 : 3 2 1 0 Address Range 03F000h 03FFFFh : : 030000h 030FFFh 02F000h 02FFFFh : : 020000h 020FFFh 01F000h 01FFFFh : : 010000h 010FFFh 00F000h 00FFFFh : : 003000h 003FFFh 002000h 002FFFh 001000h 001FFFh 000000h 000FFFh 7 REV. 1.2, FEB. 10, 2012 MX25L2026E DEVICE OPERATION 1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation. 2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z. The CS# falling time needs to follow tCHCL spec. 3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until next CS# rising edge. The CS# rising time needs to follow tCLCH spec. 4. Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK. The difference of serial peripheral interface mode 0 and mode 3 is shown as Figure 1. 5. For the following instructions: RDID, RDSR, READ, FAST_READ, RDSFDP, DREAD, RES and REMS the shifted-in instruction sequence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE, BE, CE, PP, RDP and DP the CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglected and not affect the current operation of Write Status Register, Program, Erase. Figure 1. Serial Peripheral Interface Modes Supported CPOL CPHA shift out shift in (Serial mode 0) 0 0 SCLK (Serial mode 3) 1 1 SCLK SI MSB SO MSB Note: CPOL indicates clock polarity of serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which serial mode is supported. P/N: PM1580 8 REV. 1.2, FEB. 10, 2012 MX25L2026E DATA PROTECTION The device is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the standby mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise. * Valid command length checking: The command length will be checked whether it is at byte base and completed on byte boundary. * Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before other command to change data. The WEL bit will return to reset stage under following situation: - Power-up - Write Disable (WRDI) command completion - Write Status Register (WRSR) command completion - Page Program (PP) command completion - Sector Erase (SE) command completion - Block Erase (BE) command completion - Chip Erase (CE) command completion * Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from writing all commands except Release from deep power down mode command (RDP) and Read Electronic Signature command (RES). * Software Protection Mode (SPM): by using BP0-BP1 bits to set the part of Flash protected from data change. * Hardware Protection Mode (HPM): by using WP# going low to protect the BP0-BP1 bits and SRWD bit from data change. Table 2. Protected Area Sizes BP1 0 0 1 1 P/N: PM1580 Status bit BP0 0 1 0 1 Protect level 2Mb 0 (none) 1 (1 block) 2 (2 blocks) 3 (All) None Block 3 Block 2-3 All 9 REV. 1.2, FEB. 10, 2012 MX25L2026E HOLD FEATURE HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the operation of write status register, programming, or erasing in progress. The operation of HOLD requires Chip Select(CS#) keeping low and starts on falling edge of HOLD# pin signal while Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not start until Serial Clock signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Serial Clock(SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not end until Serial Clock being low), see Figure 2. Figure 2. Hold Condition Operation SCLK HOLD# Hold Condition (standard use) Hold Condition (non-standard use) The Serial Data Output (SO) is high impedance, both Serial Data Input (SI) and Serial Clock (SCLK) are don't care during the HOLD operation. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and CS# must be at low. P/N: PM1580 10 REV. 1.2, FEB. 10, 2012 MX25L2026E Table 3. COMMAND DEFINITION COMMAND (byte) 1st 2nd 3rd 4th 5th Action WREN (write Enable) 06 Hex sets the (WEL) write enable latch bit WRSR WRDI (write status (write disable) register) 04 Hex 01 Hex RDID (read identification) RDSR (read status register) 9F Hex 05 Hex reset the to write new output the (WEL) write status register manufacturer enable latch ID and 2-byte bit device ID to read out the status register READ (read data) Fast Read (fast read data) 03 Hex AD1 AD2 AD3 0B Hex AD1 AD2 AD3 Dummy n bytes read n bytes read out until CS# out until CS# goes high goes high REMS (Read DREAD RES SE Electronic (Double BE CE (Read (Sector Manufacturer Output Mode (Block Erase) (Chip Erase) Electronic ID) Erase) & Device ID) command) 5A Hex AB Hex 90 Hex 3B Hex 20 Hex 52 or D8 Hex 60 or C7 Hex AD1 x x AD1 AD1 AD1 AD2 x x AD2 AD2 AD2 AD3 x ADD(1) AD3 AD3 AD3 Dummy Dummy Read SFDP to read out Output the n bytes read to erase the to erase the to erase mode 1-byte Device manufacturer out by Dual selected selected whole chip ID ID and device Output until sector block ID CS# goes high COMMAND RDSFDP (byte) (Read SFDP) 1st 2nd 3rd 4th 5th Action COMMAND (byte) 1st 2nd 3rd 4th 5th Action PP (Page Program) 02 Hex AD1 AD2 AD3 to program the selected page B9 Hex RDP (Release from Deep Power-down) AB Hex enters deep power down mode release from deep power down mode DP (Deep Power Down) (1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first. (2) It is not recommended to adopt any other code which is not in the above command definition table. P/N: PM1580 11 REV. 1.2, FEB. 10, 2012 MX25L2026E COMMAND DESCRIPTION (1) Write Enable (WREN) The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, SE, BE, CE, and WRSR, which are intended to change the device content, should be set every time after the WREN instruction setting the WEL bit. The sequence is shown as Figure 11. (2) Write Disable (WRDI) The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit. The sequence is shown as Figure 12. The WEL bit is reset by following situations: - Power-up - Write Disable (WRDI) instruction completion - Write Status Register (WRSR) instruction completion - Page Program (PP) instruction completion - Sector Erase (SE) instruction completion - Block Erase (BE) instruction completion - Chip Erase (CE) instruction completion P/N: PM1580 12 REV. 1.2, FEB. 10, 2012 MX25L2026E (3) Read Status Register (RDSR) The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP) bit before sending a new instruction when a program, erase, or write status register operation is in progress. The sequence is shown as Figure 13. The definition of the status register bits is as below: WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/ erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction. BP1, BP0 bits. The Block Protect (BP1, BP0) bits, volatile bits, indicate the protected area(as defined in table 2) of the device to against the program/erase instruction without hardware protection mode being set. To write the Block Protect (BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase (BE) and Chip Erase(CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be executed) SRWD bit. The Status Register Write Disable (SRWD) bit, volatile bit, is operated together with Write Protection (WP#) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and WP# pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP1, BP0) are read only. bit 7 bit 6 bit 5 bit 4 SRWD Status Register Write Protect 0 0 0 1= status register write disable (note 2) 0 0 0 bit 3 bit 2 bit 1 bit 0 BP1 BP0 (the level (the level WEL (write WIP (write in of protected of protected enable latch) progress bit) block) block) 1=write 1=write enable operation (note 1) (note 1) 0=not write 0=not in write enable operation Note: 1. See the table "Protected Area Sizes". The BP0 & BP1 default value are "1" (protected) 2. The SRWD default value is "0" P/N: PM1580 13 REV. 1.2, FEB. 10, 2012 MX25L2026E (4) Write Status Register (WRSR) The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP1, BP0) bits to define the protected area of memory (as shown in table 2). The WRSR also can set or reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#) pin signal. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is entered. The sequence is shown as Figure 14. The WRSR instruction has no effect on b6, b5, b4, b1, b0 of the status register. The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset. Table 4. Protection Modes Mode Software protection mode (SPM) Hardware protection mode (HPM) Status register condition WP# and SRWD bit status Memory Status register can be written in (WEL bit is set to "1") and the SRWD, BP1-BP0 bits can be changed WP#=1 and SRWD bit=0, or WP#=0 and SRWD bit=0, or WP#=1 and SRWD=1 The protected area cannot be program or erase. The SRWD, BP1-BP0 of status register bits cannot be changed WP#=0, SRWD bit=1 The protected area cannot be program or erase. Note: 1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 2. As the above table showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM). Software Protected Mode (SPM): - When SRWD bit=0, no matter WP# is low or high, the WREN instruction may set the WEL bit and can change the values of SRWD, BP1, BP0. The protected area, which is defined by BP1, BP0, is at software protected mode (SPM). - When SRWD bit=1 and WP# is high, the WREN instruction may set the WEL bit can change the values of SRWD, BP1, BP0. The protected area, which is defined by BP1, BP0, is at software protected mode (SPM). Note: If SRWD bit=1 but WP# is low, it is impossible to write the Status Register even if the WEL bit has previously been set. It is rejected to write the Status Register and not be executed. Hardware Protected Mode (HPM): - When SRWD bit=1, and then WP# is low (or WP# is low before SRWD bit=1), it enters the hardware protected mode (HPM). The data of the protected area is protected by software protected mode by BP1, BP0 and hardware protected mode by the WP# to against data modification. Note: to exit the hardware protected mode requires WP# driving high once the hardware protected mode is entered. If the WP# pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via BP1, BP0. P/N: PM1580 14 REV. 1.2, FEB. 10, 2012 MX25L2026E (5) Read Data Bytes (READ) The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence is shown as Figure 15. (6) Read Data Bytes at Higher Speed (FAST_READ) The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence is shown as Figure 16. While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. (7) Dual Output Mode (DREAD) The DREAD instruction enable double throughput of Serial Flash in read mode. The address is latched on rising edge of SCLK, and data of every two bits(interleave on 1I/2O pins) shift out on the falling edge of SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single DREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing DREAD instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit. The sequence is shown as Figure 17. While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. The DREAD only perform read operation. Program/Erase /Read ID/Read status....operation do not support DREAD throughputs. (8) Sector Erase (SE) The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any address of the sector (see table 1) is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. Address bits [Am-A12] (Am is the most significant address) select the sector address. P/N: PM1580 15 REV. 1.2, FEB. 10, 2012 MX25L2026E The sequence is shown as Figure 18. The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the page. (9) Block Erase (BE) The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE). Any address of the block (see table 1) is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence is shown as Figure 19. The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP1, BP0 bits, the Block Erase (BE) instruction will not be executed on the page. (10) Chip Erase (CE) The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). Any address of the sector (see table 1) is a valid address for Chip Erase (CE) instruction. The CS# must go high exactly at the byte boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence is shown as Figure 20. The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip is protected by BP1, BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only executed when BP1, BP0 all set to "0". (11) Page Program (PP) The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device programs only the last 256 data bytes sent to the device. If the entire 256 data bytes are going to be programmed, A7A0 (The eight least significant address bits) should be set to 0. If the eight least significant address bits (A7-A0) are not all 0, all transmitted data going beyond the end of the current page are programmed from the start address of the same page (from the address A7-A0 are all 0). If more than 256 bytes are sent to the device, the data of the last 256-byte is programmed at the request page and previous data will be disregarded. If less than 256 bytes are sent to the device, the data is programmed at the requested address of the page without effect on other address of the same page. P/N: PM1580 16 REV. 1.2, FEB. 10, 2012 MX25L2026E The sequence is shown as Figure 21. The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte boundary( the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed. The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP1, BP0 bits, the Page Program (PP) instruction will not be executed. (12) Deep Power-down (DP) The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to entering the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not active and all Write/Program/Erase instruction are ignored. When CS# goes high, it's only in standby mode not deep power-down mode. It's different from Standby mode. The sequence is shown as Figure 22. Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP) and Read Electronic Signature (RES) instruction. (RES instruction to allow the ID been read out). When Powerdown, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay of tDP is required before entering the Deep Power-down mode and reducing the current to ISB2. (13) Release from Deep Power-down (RDP), Read Electronic Signature (RES) The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip Select (CS#) must remain High for at least tRES2(max), as specified in Table 7. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new deisng, please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/ write cycle in progress. The sequence is shown as Figure 23 and Figure 24. The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction. P/N: PM1580 17 REV. 1.2, FEB. 10, 2012 MX25L2026E The RDP instruction is for releasing from Deep Power Down Mode. (14) Read Identification (RDID) The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The Macronix Manufacturer ID and Device ID are listed as table of "ID Definitions". The sequence is shown as Figure 25. While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage. (15) Read Electronic Manufacturer ID & Device ID (REMS) The REMS instruction is an alternative to the Release from Power-down/Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID. The REMS instruction is very similar to the Release from Power-down/Device ID instruction. The instruction is initiated by driving the CS# pin low and shift the instruction code "90h" followed by two dummy bytes and one bytes address (A7~A0). After which, the Manufacturer ID for Macronix (C2h) and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure 26. The Device ID values are listed in Table 5. ID Definitions. If the one-byte address is initially set to 01h, then the device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high. Table 5. ID Definitions Command Type RDID Command RES Command REMS Command P/N: PM1580 MX25L2026E memory type 20 electronic ID 11 manufacturer ID C2 manufacturer ID C2 18 memory density 12 device ID 11 REV. 1.2, FEB. 10, 2012 MX25L2026E (15) Read SFDP Mode (RDSFDP) The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on CFI. The sequence of issuing RDSFDP instruction is CS# goes lowsend RDSFDP instruction (5Ah)send 3 address bytes on SI pinsend 1 dummy byte on SI pinread SFDP code on SOto end RDSFDP operation can use CS# to high at any time during data out. SFDP is a standard of JEDEC. JESD216. v1.0. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Command SI SO 24 BIT ADDRESS 23 22 21 5Ah 3 2 1 0 High-Z CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Cycle SI 7 6 5 4 3 2 1 0 DATA OUT 2 DATA OUT 1 SO 7 6 5 3 2 1 0 7 MSB MSB P/N: PM1580 4 19 6 5 4 3 2 1 0 7 MSB REV. 1.2, FEB. 10, 2012 MX25L2026E Table a. Signature and Parameter Identification Data Values Description SFDP Signature Comment Fixed: 50444653h Add (h) DW Add Data (h/b) (Byte) (Bit) (Note1) 00h 07:00 53h Data (h) 53h 01h 15:08 46h 46h 02h 23:16 44h 44h 03h 31:24 50h 50h SFDP Minor Revision Number Start from 00h 04h 07:00 00h 00h SFDP Major Revision Number Start from 01h 05h 15:08 01h 01h Number of Parameter Headers Start from 01h 06h 23:16 01h 01h 07h 31:24 FFh FFh 00h: it indicates a JEDEC specified header. 08h 07:00 00h 00h Start from 00h 09h 15:08 00h 00h Start from 01h 0Ah 23:16 01h 01h How many DWORDs in the Parameter table 0Bh 31:24 09h 09h 0Ch 07:00 30h 30h 0Dh 15:08 00h 00h 0Eh 23:16 00h 00h 0Fh 31:24 FFh FFh it indicates Macronix manufacturer ID 10h 07:00 C2h C2h Start from 00h 11h 15:08 00h 00h Start from 01h 12h 23:16 01h 01h How many DWORDs in the Parameter table 13h 31:24 04h 04h 14h 07:00 60h 60h 15h 15:08 00h 00h 16h 23:16 00h 00h 17h 31:24 FFh FFh Unused ID number (JEDEC) Parameter Table Minor Revision Number Parameter Table Major Revision Number Parameter Table Length (in double word) Parameter Table Pointer (PTP) First address of JEDEC Flash Parameter table Unused ID number (Macronix manufacturer ID) Parameter Table Minor Revision Number Parameter Table Major Revision Number Parameter Table Length (in double word) Parameter Table Pointer (PTP) First address of Macronix Flash Parameter table Unused P/N: PM1580 20 REV. 1.2, FEB. 10, 2012 MX25L2026E Table b. Parameter Table (0): JEDEC Flash Parameter Tables Description Comment Block/Sector Erase sizes 00: Reserved, 01: 4KB erase, 10: Reserved, 11: not suport 4KB erase Write Granularity Write Enable Instruction Requested for Writing to Volatile Status Registers Add (h) DW Add Data (h/b) (Byte) (Bit) (Note1) 01:00 01b 0: 1Byte, 1: 64Byte or larger 02 1b 0: Nonvolatitle status bit 1: Volatitle status bit (BP status register bit) 03 1b 30h 0: use 50h opcode, 1: use 06h opcode Write Enable Opcode Select for Note: If target flash status register is Writing to Volatile Status Registers nonvolatile, then bits 3 and 4 must be set to 00b. Contains 111b and can never be Unused changed 4KB Erase Opcode 31h FDh 04 1b 07:05 111b 15:08 20h 16 1b 18:17 00b 19 0b 20 0b (1-1-2) Fast Read (Note2) 0=not support 1=support Address Bytes Number used in addressing flash array Double Transfer Rate (DTR) Clocking 00: 3Byte only, 01: 3 or 4Byte, 10: 4Byte only, 11: Reserved (1-2-2) Fast Read 0=not support 1=support (1-4-4) Fast Read 0=not support 1=support 21 0b (1-1-4) Fast Read 0=not support 1=support 22 0b 23 1b 33h 31:24 FFh 37h:34h 31:00 0=not support 1=support 32h Unused Unused Flash Memory Density (1-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy states (Note3) Clocks) not support (1-4-4) Fast Read Number of 000b: Mode Bits not support Mode Bits (Note4) 38h (1-4-4) Fast Read Opcode 39h (1-1-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (1-1-4) Fast Read Number of 000b: Mode Bits not support Mode Bits 3Ah (1-1-4) Fast Read Opcode 3Bh P/N: PM1580 21 Data (h) 20h 81h FFh 001FFFFFh 04:00 0 0000b 07:05 000b 15:08 FFh 20:16 0 0000b 23:21 000b 31:24 FFh 00h FFh 00h FFh REV. 1.2, FEB. 10, 2012 MX25L2026E Description Comment (1-1-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (1-1-2) Fast Read Number of 000b: Mode Bits not support Mode Bits Add (h) DW Add Data (h/b) (Byte) (Bit) (Note1) 3Ch (1-1-2) Fast Read Opcode 3Dh (1-2-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (1-2-2) Fast Read Number of 000b: Mode Bits not support Mode Bits 3Eh (1-2-2) Fast Read Opcode 3Fh (2-2-2) Fast Read 0=not support 1=support Unused (4-4-4) Fast Read 0=not support 1=support 40h Unused 04:00 0 1000b 07:05 000b 15:08 3Bh 20:16 0 0000b 23:21 000b 31:24 FFh 00 0b 03:01 111b 04 0b 07:05 111b Data (h) 08h 3Bh 00h FFh EEh Unused 43h:41h 31:08 0xFFh 0xFFh Unused 45h:44h 15:00 0xFFh 0xFFh 20:16 0 000b 23:21 000b (2-2-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (2-2-2) Fast Read Number of 000b: Mode Bits not support Mode Bits 46h (2-2-2) Fast Read Opcode 47h 31:24 FFh FFh 49h:48h 15:00 0xFFh 0xFFh 20:16 0 0000b 23:21 000b Unused 00h (4-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy states Clocks) not support (4-4-4) Fast Read Number of 000b: Mode Bits not support Mode Bits 4Ah (4-4-4) Fast Read Opcode 4Bh 31:24 FFh FFh 4Ch 07:00 0Ch 0Ch 4Dh 15:08 20h 20h 4Eh 23:16 10h 10h 4Fh 31:24 D8h D8h 50h 07:00 00h 00h 51h 15:08 FFh FFh 52h 23:16 00h 00h 53h 31:24 FFh FFh Sector Type 1 Size Sector/block size = 2^N bytes (Note5) 0x00b: this sector type doesn't exist Sector Type 1 erase Opcode Sector Type 2 Size Sector/block size = 2^N bytes 0x00b: this sector type doesn't exist Sector Type 2 erase Opcode Sector Type 3 Size Sector/block size = 2^N bytes 0x00b: this sector type doesn't exist Sector Type 3 erase Opcode Sector Type 4 Size Sector/block size = 2^N bytes 0x00b: this sector type doesn't exist Sector Type 4 erase Opcode P/N: PM1580 22 00h REV. 1.2, FEB. 10, 2012 MX25L2026E Table c. Parameter Table (1): Macronix Flash Parameter Tables Description Comment Add (h) DW Add Data (h/b) (Byte) (Bit) (Note1) Data (h) Vcc Supply Maximum Voltage 2000h=2.000V 2700h=2.700V 3600h=3.600V 61h:60h 07:00 15:08 00h 36h 00h 36h Vcc Supply Minimum Voltage 1650h=1.650V 2250h=2.250V 2350h=2.350V 2700h=2.700V 63h:62h 23:16 31:24 00h 27h 00h 27h HW Reset# pin 0=not support 1=support 00 0b HW Hold# pin 0=not support 1=support 01 1b Deep Power Down Mode 0=not support 1=support 02 1b SW Reset 0=not support 1=support 03 0b SW Reset Opcode Reset Enable (66h) should be issued 65h:64h before Reset command 11:04 1111 1111b (FFh) Program Suspend/Resume 0=not support 1=support 12 0b Erase Suspend/Resume 0=not support 1=support 13 0b 14 1b 15 0b 66h 23:16 FFh FFh 67h 31:24 FFh FFh Unused Wrap-Around Read mode 0=not support 1=support Wrap-Around Read mode Opcode Wrap-Around Read data length 08h:support 8B wrap-around read 16h:8B&16B 32h:8B&16B&32B 64h:8B&16B&32B&64B Individual block lock 0=not support 1=support 00 0b Individual block lock bit (Volatile/Nonvolatile) 0=Volatile 1=Nonvolatile 01 1b 09:02 1111 1111b 10 1b 11 1b Individual block lock Opcode 4FF6h Individual block lock Volatile protect bit default protect status 0=protect 1=unprotect Secured OTP 0=not support 1=support Read Lock 0=not support 1=support 12 0b Permanent Lock 0=not support 1=support 13 0b Unused 15:14 11b Unused 31:16 0xFFh 0xFFh 31:00 0xFFh 0xFFh Unused P/N: PM1580 6Bh:68h 6Fh:6Ch 23 CFFEh REV. 1.2, FEB. 10, 2012 MX25L2026E Note 1: h/b is hexadecimal or binary. Note 2: (x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the opcode (x), address (y), and data (z). At the present time, the only valid Read SFDP instruction modes are: (1-1-1), (2-2-2), and (4-4-4) Note 3: Wait States is required dummy clock cycles after the address bits or optional mode bits. Note 4: Mode Bits is optional control bits that follow the address bits. These bits are driven by the system controller if they are specified. (eg,read performance enhance toggling bits) Note 5: 4KB=2^0Ch,32KB=2^0Fh,64KB=2^10h Note 6: 0xFFh means all data is blank ("1b"). P/N: PM1580 24 REV. 1.2, FEB. 10, 2012 MX25L2026E POWER-ON STATE The device is at below states when power-up: - Standby mode ( please note it is not deep power-down mode) - Write Enable Latch (WEL) bit is reset The device must not be selected during power-up and power-down stage unless the VCC achieves below correct level: - VCC minimum at power-up stage and then after a delay of tVSL - GND at power-down Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level. An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change during power up state. For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not guaranteed. The write, read, erase, and program command should be sent after the below time delay: - tVSL after VCC reached VCC minimum level The device can accept read command after VCC reached VCC minimum and a time delay of tVSL. Please refer to the figure of "power-up timing". Note: - To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended. (generally around 0.1uF) P/N: PM1580 25 REV. 1.2, FEB. 10, 2012 MX25L2026E ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS RATING Ambient Operating Temperature Storage Temperature Applied Input Voltage Applied Output Voltage VCC to Ground Potential VALUE -40C to 85C -55C to 125C -0.5V to 4.6V -0.5V to 4.6V -0.5V to 4.6V Industrial (I) grade Notes: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. 2. Specifications contained within the following tables are subject to change. 3. During voltage transitions, all pins may overshoot to 4.6V or -0.5V for period up to 20ns. 4. All input and output pins may overshoot to VCC+0.5V while VCC+0.5V is smaller than or equal to 4.6V. Figure 4. Maximum Positive Overshoot Waveform Figure 3. Maximum Negative Overshoot Waveform 20ns 4.6V 0V 3.6V -0.5V 20ns CAPACITANCE TA = 25C, f = 1.0 MHz Symbol CIN COUT P/N: PM1580 Parameter Input Capacitance Output Capacitance Min. Typ. Max. 6 8 26 Unit pF pF Conditions VIN = 0V VOUT = 0V REV. 1.2, FEB. 10, 2012 MX25L2026E Figure 5. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL Input timing reference level 0.8VCC 0.7VCC 0.3VCC 0.2VCC Output timing reference level AC Measurement Level 0.5VCC Note: Input pulse rise and fall time are <5ns Figure 6. OUTPUT LOADING DEVICE UNDER TEST 2.7K ohm CL 6.2K ohm +3.3V DIODES=IN3064 OR EQUIVALENT CL=30pF Including jig capacitance P/N: PM1580 27 REV. 1.2, FEB. 10, 2012 MX25L2026E Table 6. DC CHARACTERISTICS (Temperature = -40C to 85C, VCC = 2.7V ~ 3.6V) Symbol Parameter Notes Min. Typ. Max. Units ILI Input Load Current 1 2 uA ILO Output Leakage Current 1 2 uA ISB1 VCC Standby Current 1 25 uA ISB2 Deep Power-down Current 10 uA 12 mA 12 mA 4 mA 20 mA 15 mA 1 15 mA 1 20 mA 0.3VCC VCC+0.4 0.4 V V V V 2.5 V ICC1 ICC2 ICC3 ICC4 ICC5 VIL VIH VOL VOH VWI VCC Read VCC Program Current (PP) VCC Write Status Register (WRSR) Current VCC Sector Erase Current (SE) VCC Chip Erase Current (CE) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Low VCC Write Inhibit Voltage 5 1 1 -0.5 0.7VCC VCC-0.2 3 2.1 2.3 Test Conditions VCC = VCC Max VIN = VCC or GND VCC = VCC Max VOUT = VCC or GND VIN = VCC or GND CS# = VCC VIN = VCC or GND CS# = VCC f=86MHz SCLK=0.1VCC/0.9VCC, SO=Open f=66MHz SCLK=0.1VCC/0.9VCC, SO=Open f=33MHz SCLK=0.1VCC/0.9VCC, SO=Open Program in Progress CS# = VCC Program status register in progress, CS#=VCC Erase in Progress, CS#=VCC Erase in Progress, CS#=VCC IOL = 1.6mA IOH = -100uA Notes: 1. Typical values at VCC = 3.3V, T = 25C. These currents are valid for all product versions (package and speeds). 2. Typical value is calculated by simulation. 3. Not 100% tested. P/N: PM1580 28 REV. 1.2, FEB. 10, 2012 MX25L2026E Table 7. AC CHARACTERISTICS (Temperature = -40C to 85C, VCC = 2.7V ~ 3.6V) Symbol Alt. fSCLK fC fRSCLK fTSCLK fR fT tCH(1) tCLH tCL(1) tCLL tCLCH(2) tCHCL(2) tSLCH tCSS tCHSL tDVCH tDSU tCHDX tDH tCHSH tSHCH tSHSL tCSH tSHQZ(2) tDIS tCLQV tV tCLQX tHLCH tCHHH tHHCH tCHHL tHHQX(2) tHLQZ(2) tWHSL(4) tSHWL(4) tDP(2) tHO tRES1(2) tRES2(2) tW tBP tPP tSE tBE tCE tLZ tHZ Parameter Clock Frequency for the following instructions: FAST_READ, RDSFDP, PP, SE, BE, CE, DP, RES, RDP, WREN, WRDI, RDID, RDSR, WRSR Clock Frequency for READ instructions Clock Frequency for DREAD instructions @33MHz Clock High Time @86MHz @33MHz Clock Low Time @86MHz Clock Rise Time (3) (peak to peak) Clock Fall Time (3) (peak to peak) CS# Active Setup Time (relative to SCLK) CS# Not Active Hold Time (relative to SCLK) Data In Setup Time Data In Hold Time CS# Active Hold Time (relative to SCLK) CS# Not Active Setup Time (relative to SCLK) Read CS# Deselect Time Write Output Disable Time 30pF Clock Low to Output Valid 15pF Output Hold Time HOLD# Setup Time (relative to SCLK) HOLD# Hold Time (relative to SCLK) HOLD Setup Time (relative to SCLK) HOLD Hold Time (relative to SCLK) HOLD to Output Low-Z HOLD# to Output High-Z Write Protect Setup Time Write Protect Hold Time CS# High to Deep Power-down Mode CS# High to Standby Mode without Electronic Signature Read CS# High to Standby Mode with Electronic Signature Read Write Status Register Cycle Time Byte-Program Page Program Cycle Time Sector Erase Cycle Time Block Erase Cycle Time Chip Erase Cycle Time Min. Typ. Max. Unit DC 86 MHz DC DC 13 5.5 13 5.5 0.1 0.1 7 7 2 5 7 7 15 40 33 80 10 MHz MHz ns ns ns ns V/ns V/ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns us 8.8 us 8.8 us 15 300 5 300 2 3.8 ms us ms ms s s 6 8 6 0 5 5 5 5 6 6 20 100 5 9 1.4 60 0.7 1.8 Note: 1. tCH + tCL must be greater than or equal to 1/f (fC or fR). 2. Value guaranteed by characterization, not 100% tested in production. 3. Expressed as a slew-rate. 4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1. 5. Test condition is shown as Figure 5 & 6. 6. The CS# rising time needs to follow tCLCH spec and CS# falling time needs to follow tCHCL spec. P/N: PM1580 29 REV. 1.2, FEB. 10, 2012 MX25L2026E Table 8. Power-Up Timing Symbol tVSL(1) Parameter VCC(min) to CS# low Min. 200 Max. Unit us Note: 1. The parameter is characterized only. INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). P/N: PM1580 30 REV. 1.2, FEB. 10, 2012 MX25L2026E Timing Analysis Figure 7. Serial Input Timing tSHSL CS# tCHSL tSLCH tCHSH tSHCH SCLK tDVCH tCHCL tCHDX tCLCH LSB MSB SI High-Z SO Figure 8. Output Timing CS# tCH SCLK tCLQV tCL tCLQV tSHQZ tCLQX LSB SO SI P/N: PM1580 ADDR.LSB IN 31 REV. 1.2, FEB. 10, 2012 MX25L2026E Figure 9. Hold Timing CS# tHLCH tHHCH tCHHL SCLK tCHHH tHLQZ tHHQX SO tCLHS tCLHH HOLD# * SI is "don't care" during HOLD operation. Figure 10. WP# Disable Setup and Hold Timing during WRSR when SRWD=1 WP# tSHWL tWHSL CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK 01 SI SO P/N: PM1580 High-Z 32 REV. 1.2, FEB. 10, 2012 MX25L2026E Figure 11. Write Enable (WREN) Sequence (Command 06) CS# 1 0 2 3 4 5 6 7 SCLK Command SI 06 High-Z SO Figure 12. Write Disable (WRDI) Sequence (Command 04) CS# 1 0 2 3 4 5 6 7 SCLK Command SI 04 High-Z SO Figure 13. Read Status Register (RDSR) Sequence (Command 05) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK command 05 SI Status Register Out High-Z SO 7 6 5 3 2 1 0 7 6 5 4 3 2 1 0 7 MSB MSB P/N: PM1580 4 Status Register Out 33 REV. 1.2, FEB. 10, 2012 MX25L2026E Figure 14. Write Status Register (WRSR) Sequence (Command 01) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK command SI Status Register In 01 7 5 4 3 2 1 0 MSB High-Z SO 6 Figure 15. Read Data Bytes (READ) Sequence (Command 03) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCLK command SI 03 24-Bit Address 23 22 21 3 2 1 0 MSB Data Out 1 High-Z 7 SO 6 5 4 3 2 Data Out 2 1 0 7 MSB P/N: PM1580 34 REV. 1.2, FEB. 10, 2012 MX25L2026E Figure 16. Read at Higher Speed (FAST_READ) Sequence (Command 0B) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Command SI 24 BIT ADDRESS 23 22 21 0B 3 2 1 0 High-Z SO CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Byte 7 SI 6 5 4 3 2 1 0 DATA OUT 2 DATA OUT 1 7 SO 6 5 4 3 2 1 0 7 6 5 4 3 2 MSB MSB 1 0 7 MSB Figure 17. Dual Output Read Mode Sequence (Command 3B) CS# 0 1 2 3 4 5 6 7 8 9 10 11 39 40 41 42 43 30 31 32 SCLK 8 Bit Instruction SI/SO0 SO/SO1 P/N: PM1580 3B(hex) 24 BIT Address address bit23, bit22, bit21...bit0 High Impedance 8 dummy cycle dummy Data Output data bit6, bit4, bit2...bit0, bit6, bit4.... data bit7, bit5, bit3...bit1, bit7, bit5.... 35 REV. 1.2, FEB. 10, 2012 MX25L2026E Figure 18. Sector Erase (SE) Sequence (Command 20) CS# 0 1 2 3 4 5 6 7 8 9 29 30 31 SCLK 24 Bit Address Command SI 23 22 20 2 1 0 MSB Note: SE command is 20(hex). Figure 19. Block Erase (BE) Sequence (Command 52 or D8) CS# 0 1 2 3 4 5 6 7 8 9 29 30 31 SCLK Command SI 24 Bit Address 23 22 52 or D8 2 1 0 MSB Note: BE command is 52 or D8(hex). Figure 20. Chip Erase (CE) Sequence (Command 60 or C7) CS# 0 1 2 3 4 5 6 7 SCLK Command SI 60 or C7 Note: CE command is 60(hex) or C7(hex). P/N: PM1580 36 REV. 1.2, FEB. 10, 2012 MX25L2026E Figure 21. Page Program (PP) Sequence (Command 02) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCLK 1 0 7 6 5 3 2 1 0 2079 2 2078 3 2077 23 22 21 02 SI Data Byte 1 2076 24-Bit Address 2075 Command 4 1 0 MSB MSB 2074 2073 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2072 CS# SCLK Data Byte 2 SI 7 6 5 4 3 Data Byte 3 2 1 0 MSB 7 6 5 4 3 2 Data Byte 256 1 0 MSB 7 6 5 4 3 2 MSB Figure 22. Deep Power-down (DP) Sequence (Command B9) CS# 0 1 2 3 4 5 6 tDP 7 SCLK Command SI B9 Stand-by Mode P/N: PM1580 37 Deep Power-down Mode REV. 1.2, FEB. 10, 2012 MX25L2026E Figure 23. Read Electronic Signature (RES) Sequence (Command AB) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 SCLK Command SI tRES2 3 Dummy Bytes 23 22 21 AB 3 2 1 0 MSB Electronic Signature Out High-Z 7 SO 6 5 4 3 2 1 0 MSB Deep Power-down Mode Stand-by Mode Figure 24. Release from Deep Power-down (RDP) Sequence (Command AB) CS# 0 1 2 3 4 5 6 tRES1 7 SCLK Command SI SO AB High-Z Deep Power-down Mode P/N: PM1580 38 Stand-by Mode REV. 1.2, FEB. 10, 2012 MX25L2026E Figure 25. Read Identification (RDID) Sequence (Command 9F) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 28 29 30 31 SCLK Command SI 9F Manufacturer Identification High-Z SO 7 6 5 3 2 1 Device Identification 0 15 14 13 MSB 3 2 1 0 MSB Figure 26. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90) CS# 0 1 2 3 4 5 6 7 8 9 10 SCLK Command SI 2 Dummy Bytes 15 14 13 90 3 2 1 0 High-Z SO CS# 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK ADD (1) SI 7 6 5 4 3 2 1 0 Manufacturer ID SO X 7 6 5 4 3 2 1 Device ID 0 7 6 5 4 3 2 MSB MSB 1 0 7 MSB Notes: (1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first. P/N: PM1580 39 REV. 1.2, FEB. 10, 2012 MX25L2026E Figure 27. Power-up Timing VCC VCC(max) Chip Selection is Not Allowed VCC(min) tVSL Device is fully accessible time P/N: PM1580 40 REV. 1.2, FEB. 10, 2012 MX25L2026E OPERATING CONDITIONS At Device Power-Up and Power-Down AC timing illustrated in Figure 28 and Figure 29 are the supply voltages and the control signals at device power-up and power-down. If the timing in the figures is ignored, the device will not operate correctly. During power-up and power down, CS# needs to follow the voltage applied on VCC to keep the device not be selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL. Figure 28. AC Timing at Device Power-Up VCC VCC(min) GND tVR tSHSL CS# tSLCH tCHSL tSHCH tCHSH SCLK tDVCH tCHCL tCHDX LSB IN MSB IN SI High Impedance SO Symbol tVR tCLCH Parameter VCC Rise Time Notes 1 Min. 0.5 Max. 500000 Unit us/V Notes : 1. Sampled, not 100% tested. 2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to "AC CHARACTERISTICS" table. P/N: PM1580 41 REV. 1.2, FEB. 10, 2012 MX25L2026E Figure 29. Power-Down Sequence During power down, CS# needs to follow the voltage drop on VCC to avoid mis-operation. VCC CS# SCLK P/N: PM1580 42 REV. 1.2, FEB. 10, 2012 MX25L2026E ERASE AND PROGRAMMING PERFORMANCE Parameter Write Status Register Cycle Time Sector erase Time Block erase Time Chip Erase Time Byte Program Time (via page program command) Page Program Time Erase/Program Cycle Min. Typ. (1) 5 60 0.7 1.8 9 1.4 Max. (2) 15 300 2 3.8 300 5 Unit ms ms s s us ms cycles 100,000 Note: 1. Typical program and erase time assumes the following conditions: 25C, 3.3V, and checker board pattern. 2. Under worst conditions of 85C and 2.7V. 3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming command. DATA RETENTION Parameter Condition Min. Data retention 55C 20 Max. Unit years LATCH-UP CHARACTERISTICS Input Voltage with respect to GND on all power pins, SI, CS# Input Voltage with respect to GND on SO Current Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time. P/N: PM1580 43 Min. -1.0V -1.0V -100mA Max. 2 VCCmax VCC + 1.0V +100mA REV. 1.2, FEB. 10, 2012 MX25L2026E ORDERING INFORMATION PART NO. CLOCK (MHz) MX25L2026EM1I-12G 86 P/N: PM1580 OPERATING STANDBY Temperature CURRENT(mA) CURRENT(uA) 12 10 44 -40~85C Package Remark 8-SOP (150mil) RoHS Compliant REV. 1.2, FEB. 10, 2012 MX25L2026E PART NAME DESCRIPTION MX 25 L 2026E M1 I 12 G OPTION: G: RoHS Compliant SPEED: 12: 86MHz TEMPERATURE RANGE: I: Industrial (-40C to 85C) PACKAGE: M1: 150mil 8-SOP DENSITY & MODE: 2026E: 2Mb TYPE: L: 3V DEVICE: 25: Serial Flash P/N: PM1580 45 REV. 1.2, FEB. 10, 2012 MX25L2026E PACKAGE INFORMATION P/N: PM1580 46 REV. 1.2, FEB. 10, 2012 MX25L2026E REVISION HISTORY Revision No. Description 0.01 1. Renamed from MX25L2025E to MX25L2026E 2. Modified "Initial Delivery State" description 3. Modified OTP Capable data from 1 to 0 0.02 1. Revised Vcc Supply Minimum Voltage Address Bits 2. Changed wording from DMC to SFDP 3. Changed title from "Advanced Information" to "Preliminary" 4. Corrected Part Name Description 5. Corrected Max. Write Status Register Cycle Time 6. Revised SFDP sequence description 1.0 1. Removed Preliminary 2. Removed SFDP sequence description & content table 3. Modified Write Status Register Cycle Time 4. Removed Write Status Register Cycle Time in notes 5. Added Sector Erase Time : 300ms (max.) 1.1 1. Added CS# rising and falling time description 2. Corrected RDID description 3. Modified tVSL from 10us(min.) to 200us(min.) 4. Modified description for RoHS compliance 1.2 1. Added Read SFDP (RDSFDP) Mode P/N: PM1580 47 Page Date All APR/27/2010 P27 P21 P21 MAY/19/2010 P4,8,11,19 P4 P42 P40 P19 P4 JUL/06/2010 P4,8,11,19 P23,37 P23,37 P23,37 P8,23 JAN/12/2011 P18 P24 P4,38,39 P4,8,11, FEB/10/2012 P19~24,29 REV. 1.2, FEB. 10, 2012 MX25L2026E Except for customized products which has been expressly identified in the applicable agreement, Macronix's products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. In the event Macronix products are used in contradicted to their target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualified for its actual use in accordance with the applicable laws and regulations; and Macronix as well as it's suppliers and/or distributors shall be released from any and all liability arisen therefrom. Copyright(c) Macronix International Co., Ltd. 2010~2012. All rights reserved, including the trademarks and tradename thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, Nbit, NBiit, Macronix NBit, eLiteFlash, XtraROM, Phines, KH Logo, BE-SONOS, KSMC, Kingtech, MXSMIO, Macronix vEE, Macronix MAP, Rich Audio, Rich Book, Rich TV, and FitCAM. The names and brands of other companies are for identification purposes only and may be claimed as the property of the respective companies. For the contact and order information, please visit Macronix's Web site at: http://www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. 48