WAMIL STANDARD PRODUCTS $44233 A-Law Asynchronous Codec February 1993 Features Exceeds AT&T D3, CCITT G.711, G.712, and G.733 Specifications * Available with A-Law Signal Companders Input Op Amp for Gain Adjustment and Anti-aliasing Filtering * Asynchronous Operation for 2048/1544/1536 kHz PCM Data Rates * Auto-Zero Circuitry Requires No External Components Energy Saving Power Down Mode Single Chip Codecs With Filters The $44233 is a high quality monolithic CMOS Codec suitable for use in telephone central offices and PBXs. This codec provides the interface between the analog signals of the subscriber loop and the digital signals of the PCM high ways in telephone switching systems. This codec contains band-limiting filters, the A/D and D/A conversion circuits, and the PCM encoder/decoder. The $44233 conforms to European A-Law signal companding characteristics. Functional Block Diagram Pin Configuration Veg (5) 5002 PCM C-R cos our Au O>| opcurt Firen|t-P-F-/4-P-F.[ | CODER | Ch 6 ve td | een cat [_]2 15{"] pcm Tero i i CO | ouT ee A2 ae tome ee | eo Me SEEAATOR [=== 22S { RCV. CLOCK ! AGND([_]4 $44233 13| ] DGND a ee 4 (TRIMMING) Aon [| 5 12 [[] TX.SYNc ; V L,I! (N.c.) [| 6 11 |] RCV.SYNC a | DECODER }<+O PCM, U HI | Yoo [_] 7 10 ["] TX.cLock hou |<} LPF. PCM [_|8 9 |] Rcv.cLock r++ 4 Von Vss_ AGNOD DGND 81$44233 A-Law Asynchronous Codec AMI Z STANDARD PRODUCTS Single Chip Codecs With Filters February 1993 Pin Function Description Pin Name Number Function Ain GA1 GA2 AGNnD Aout NC Deno PD PCMourt Vss PCMin TX.CLK RCV.CLK RCV.SYNC TX.SYNC 1 2 3 13 14 15 16 10 11 12 These three pins make up the basic analog input section. Ajy is the Analog Input pin and GA1/GA2 are the Gain Adjustment and Gain Adjustment feedback pins. The maximum input to the analog section is +Vper and the minimum input is -V_ee where Vp_r is approximately 2 to 3 volts. The operational amplifier may be tied directly to provide a unity gain input or it may be configured for negative feedback to facilitate system calibration. When configured for negative feedback, the load on the op amp should be less than 100pF with approximately 10K to 20K ohms of resistance. Analog Ground should be separate from digital ground in order to minimize crosstalk and noise. Analog Out is the smoothed output from the low pass filter after it has been decoded from the PCM input. For minimum distortion, pin 5 should be loaded with at least 3K ohms and no more than 100pF. No connect. Positive supply voltage. Normally +5 volts. Digital Ground reference point for digital input signals. Normally connected to ground. Power Down Mode. The power down mode will be activated when this TTL compatible input is held low even if the SYNC lines continue to strobe. The chip will also power down if the SYNCs stop strobing. The strobes can be either high, low, or floating, but as long as they are static, the power mode is in effect. PCM out is the output of the PCM encoder filtering and the A-D conversion. This is a LS-TTL compatible open-drain output. It is active only during transmission of digital PCM output for 8 bit periods of the transmit clock signal following a positive edge on the transmit SYNC input. Data is clocked out by the positive edge of the transmit clock. This pin should have a pull up to Vop of approximately 500 ohms, although only one 500 ohm resistor is required for eight codecs. Negative supply voltage. Normally -5 volts. This is a TTL compatible input for supplying digital PCM data to the codec decoder for con- version into analog form. The PCM data is clocked in by the negative edge of the receive (RCV) clock. TX.CLK/Transmit clock, RCV.CLK/Receive Clock Any one of three different clock frequencies (1.536 MHz, 1.544 MHz, and 2.048 MHz) will be accepted by this pin. The input clock frequency will automatically be divided down to provide all the necessary internal clocks. The TX.CLK shifts PCM data out of the coder on the positive going edge and the RCV.CLK shifts PCM data into the decoder on the negative going edges after receiving a positive edge on the TX.SYNC or RCV.SYNC input respectively. RCV.SYNC/Receive Sync, TX.SYNC/Transmit Sync These TTL compatible pulse inputs (typ. 8kHz) are used for analog sampling and for initiating the clocking of PCM output from the coder and initiating the clocking of PCM input data into the decoder. The width of these signals is not critical. An internal bit counter generates the necessary timing for PCM output and input. 82IWAMI $44233 A-Law Asynchronous Codec STANDARD PRODUCTS February 1993 Single Chip Codecs With Filters Absolute Maximum Rating Item DD ss Rating oO .3 to -55C to 125 0. emperature nput nput Electrical Characteristics 1) Static Characteristics (Vpp = 5 + 0.25V, Veg = -5 = 0.25V, Voc = 5 + 0.25V, Ta = 0 70C) < Vin < pp +0.3 ss -0.3V < IN< Yop +0.3V Symbol os Descriptions Min. sae Unit Note/Conditions lbp 7 Vpp Current (Open) 5.5 10 mA Iss 16 Vss Current (Open) -10 -4.5 mA lopst 7 Vop Current (Standby) 0.3 1.0 mA Isgst 16 Vsg Current (Standby) -0.2 mA 0 =0. A 128, Leak Current 19. io HA vu = oe , 10.0 vA | Vpp = VM = 5.25V IPL 11,12 | Pull Up Current -100 0.0 pA lbL 15 Leak Current 10.0 vA | Vpp = VM = 5.25V Caine 1,2 | Analog Input Capacitance 10 pF | at 1MHz Vbias = OV CDin 8,9,10, | input Capacitance 10 pF jat 1MHz Vbias = OV 11,12,14 RoutTa 5 Aout Resistance 1 10 Q Route 3 GA2 Resistance 1 10 Q2 Vasw GA2 Output Swing -3.0 3.0 VJ RL = 10k VoFFIN Analog Offset Input -500 -500 mV j|Note 1 VoreG GA2 Offset Output -50 50 mV |Note 1 VoFFA Aout Offset Output -50 50 mV |PCMin = +0-Code CDout 15 PCMout Capacitance 15.0 pF {at 1MHz Vbias = OV Voi 15 PCMogurt Low Voltage 0.4 Vo | RL = 5002 + Io, = 0.8mMA Vou 15 PCMout High Voltage Vec-0.3 Vo floy = - 150pA Vin 10,11, | Digital Input High Voltage 20 Vv 9,12,14 Vit 10,11, | Digital Input Low Voltage 08 Vv 9,12,14 NOTE: 1. Analog Input Amplifier Gain = 0dB (GA1 is connected to GA2) 83$44233 A-Law Asynchronous Codec MAMI STANDARD PRODUCTS Single Chip Codecs With Filters February 1993 2) Dynamic Characteristics (Vpp = 5 + 0.25V, Vgg = -5 + 0.25V, Voc = 5 + 0.25V, Ta = 0 - 70C) Specifications Symbol Descriptions Min. Typ. Max. Unit Notes FS Synchronization Rate 8 kHz FC PCM Bit Clock Rate 1536/1544/2048 kHz twe Clock Pulse Width 200 ns twsH SYNC Pulse High Width 200 ns twsL SYNC Pulse Low Width 8 us t, Logic Input Rise Time 50 ns ts Logic Input Fall Time 50 ns tacs Previous Clock to SYNC Delay 40 100 ns Note 1 tes Clock to SYNC Delay 100 ns Note 1,3 teal Clock to PCMysg Delay 170 ns Note 1,2,4 tea Clock to PCMoyr Delay 180 ns Note 1,2,5 teu PCMiwn Setup Time 65 ns Note 1 tha PCMin Hold Time 120 ns Note 1 tsa Sync to PCMysp Delay 170 ns Note 1,2,4 Notes: 1. t,, t of digital input or clock is assumed 5ns for timing measurement. 2. PCMoyt LOAD CONDITION: 500Q 165 pF + two LS-TTL Equivalent (Ij, = 0.8mA, ly = -150A) Threshold Level (Voy = 2.4V, Vo, = 0.4) 3. Positive value shows SYNC delay from Clock. 4. tog, teg are specified by Clock or SYNC, which has slower rise time. 5. teg Specification is valid for the data exept MSB. 3) System Related Characteristics - S44233 A-Law Codec (Vpp = 5 + 0.25V, Vsg = -5 + 0.25V, Voc = 5 + 0.25V, Ta = 0- 70C, Input Amplifier Gain = OdB, GA2 Load = 10KQ, Agyz Load = 600Q) Specifications Symbol Descriptions Test Conditions Min. Typ. | Max. Unit Notes SDA Signal to Dist. 820Hz tone -45dBm0 24 dB p-wogt (Ato A) -40 30 dB -30 to+3 35 dB NOTE 1 SNA Signal to Dist. Noise -55 dBm0 14 dB (Ato A) -40 29 dB -34 34 dB -27 to -6 36 dB -3 28 dB SDX Signal to Dist. 820Hz tone -45 dBm0 26 dB p-wgt (Ato D) -40 31 dB -30 to +3 36 dB NOTE 1 84AMI IZ STANDARD PRODUCTS February 1993 $44233 A-Law Asynchronous Codec Single Chip Codecs With Filters 3) System Related Characteristics S44233 A-Law Codec (Vpp = 5 + 0.25V, Vsg = -5 + 0.25V, Vec = 5 + 0.25V, Ta = 0 - 70C, Input Amplifier Gain = 0dB, GA2 Load = 10KQ, Apyt Load = 6002) Specifications Symbol Descriptions Test Conditions Min. Typ. | Max. Unit Notes SNX Signal to Dist. Noise -55 dBm0 15 dB (Ato D) -40 30 dB -34 35 dB -27 to -6 37 dB SDR Signal to Dist. 820Hz tone -45 dBm0 25 dB p-wgt (D to A) -40 30 dB -30 to +3 35 dB NOTE 1 SNR Signal to Dist. Noise -55 dBm0 15 dB (D to A) -40 30 dB -34 35 dB -27 to -6 37 dB GTA Gain Track 820Hz tone -55 to-50dBm0 | -1.0 1.0 dB (Ato A) -50 to -40 -0.5 0.5 dB -40 to +3 -0.4 0.3 dB NOTE 1 GNA Gain Track Noise -60 to -55 dBm0 -0.8 0.8 dB (Ato A) -55 to -10 -0.4 0.4 dB GTX Gain Track 820Hz tone -55 to-50dBm0 |_ -0.8 0.8 dB (Ato D) -50 to -40 -0.4 0.4 dB -40 to +3 -0.2 0.2 dB NOTE 1 GNX Gain Track Noise -60 to -55 dBm0 -0.6 0.6 dB (Ato D) -55 to -40 -0.4 0.4 dB -40 to -10 -0.2 0.2 dB GTR Gain Track 820Hz tone -55 to-50 dBm0 |_ -0.8 0.8 dB (D to A) -50 to -40 -0.4 0.4 dB -40 to +3 -0.2 0.2 dB NOTE 1 GNR Gain Track Noise -60 to -55 dBm0 -0.4 0.4 dB (D to A) -55 to -40 -0.2 0.2 dB FRX Freq. Response Relative to 0.06kKHzZ 24 (Ato D) (Loss) 820Hz 0.2 0.0 2.0 0.3 to3 -0.15 0.15 OdBmo 3.18 0.15 oe5 | 98 | NOTE 3.4 0.0 0.8 3.78 6.5 FRR Freq. Response Relative to 0 to 3kHz -0.15 0.15 (D to A) (Loss) 820Hz 3.18 -0.15 0.65 OdBmo 3.4 0.0 og | 9B | NOTE 3.78 6.5 AlL Analog Input Level | 820Hz OdBmo 25C nom. PS. 1.217 | 1.231 | 1.246 Vrms | NOTE 1 AOL Analog Output 820Hz OdBm0 25C nom. PS. 1.217 | 1.231 | 1.246 Vrms | NOTE 1 Level NOTE 1: Total variation of GAIN including the initial fluctuation temperature variation and power supply dependence (0-70C, Vpp/Vsg = + 5V +) 85$44233 A-Law Asynchronous Codec WAMIL STANDARD PRODUCTS Single Chip Codecs With Filters February 1993 3) System Related Characteristics S44233 A-Law Codec (Vpp = 5 + 0.25V, Vsg = -5 + 0.25V, Vec = 5 + 0.25V, Ta, = 0 - 70C, Input Amplifier Gain = 0dB, GA2 Load = 10K, Agyy Load = 6002) Specifications Symbol Descriptions Test Conditions Min. Typ. | Max. Unit Notes AT AIL, AOL Variation | Relative to 25C nominal PS. +20 ppm/C with temp. AP AIL, AOL Variation | 25C, Supplies +5% + 0.01 dB with PS. ALS GAIN Variation AtoD INITIAL -0.2 0.2 dB over Temp. P.S. DtoA AIP Peak Analog Input 3.0 Vv AOP Peak Analog 2.5 Vv Output PDL Propagation Delay | AtoA OdBmo 450 480 us DD Delay Distortion AtoA 0.5 to 0.6kHz 1.4 rel. OdBmoO 0.6 to 1.0 0.7 ms to 1.0 to2.6 0.2 min. 2.6 to 2.8 1.4 delay PSRR PSRR AtoA +5V +100mV op 30 jinsBand =| -sv.+100mV op | 9 a ICNA Idle Ch. Noise AtoA Ain = Aanp -70 | dBmoP | A-Law ICNX Idle Ch. Noise AtoD Ain = AGnp -72 dBmoP | A-Law ICNR Idle Ch. Noise DtoA PCM, y=+0- -78 dBmoP |; A-Law CODE IM1 Intermodulation Ato A (2a-b) a;0.47kHz, -4 dBmO -38 dBmo b;0.32, -4 IM2 Intermodulation Ato A (a-b) a;1.02kHz, -4 dBm0o -52 dBmo b;0.05, -23 ICS Single Freq. Noise | AtoA 8,16,24,32, -50 dBmo AIn = Aanb 40kHz DIS Discrimination AtoA 4.6 to 30 dB OdBmo 200kHz XTKA Ain to Aout 1020Hz OdBmo -65 dB Crosstalk XTKD PCM, to PCMoyt | 1020HZ OdBm0 -65 dB 86WAMIL $44233 A-Law Asynchronous Codec February 1993 Single Chip Codecs With Filters $44233 Timing Chart ty twsh ty | 1 | XSYNC XCLOCK RSYNC RCLOCK >| > _ 2.0 A- [-F _Lo__y f= === PCMin DON'T CARE 0.8 - +| -\.--__~\.---~- tu Js ty 87$44233 A-Law Asynchronous Codec AMI Z STANDARD PRODUCTS Single Chip Codecs With Filters Codecs Bridge the Analog/Digital Worlds Single chip CMOS Codec Combos, with their A/D and D/A converters and all the necessary analog filtering, are a powerful tool for the systems designer. Typically, codecs have three major uses. The traditional use of a codec is as a gateway between the analog subscriber loop and the digital pathways of a central telephone office. In the newer digital PBXs, the single chip codec is found in the telephone handset itself and thus is the key in bringing out the power of voice/data integration to the latest PBX generation. The third major application of codecs is in smart instrumentation where digital signal processing is required, and the codec replaces separate A/D and D/A converters and associated filters. Operation PCM to Analog (Receive Section)}The PCM data is shifted into the decoders input buffer register once every sampling period. Once the PCM data has been shifted into the decoder register, a charge proportional to the received PCM data word value appears on the decoders capacitor array. A sample and hold circuit integrates to the charge value and holds that value for the rest of the sampling period. Then a low pass switched capacitor filter smooth the signal and performs loss equalization to compensate for the sin x/x distortion due to the sample and hold operation. The low pass filters output is then buffered and available for driving electronic hybrids directly. Analog to PCM (Transmit Section)The analog input signal is placed on the uncommitted op amps terminals. The op amp allows for input gain adjustment, if necessary, to either OdB or the systems 0 level. The op amp also acts as a 2nd order analog anti-aliasing filter by bandlimiting the input to less than half of the sampling frequency per the Nyquist Rate Theorem. To meet CCITT G.712 specifications, the analog signal is filtered by a cosine filter, a 6th order low pass filter, and the high pass filter before being sampled. The sampling is performed by a capacitor array at a rate of 8kKHz and the value fed into the encoder. From the encoder the 8-bit PCM data is clocked out by the shift clock. Lastly, an auto-zero loop (without any external capacitor) provides cancellation of any DC offset by integrating the sign bit of the PCM data and feeding it back to the non- inverting input of the comparator, and a sign bit fixation circuitry reduces idle channel noise during quiet periods. 88 February 1993 Timing RequirementsThe 8kHz transmit and receive sampling strobes need not be exactly 8 bit periods wide. The codec has an internal bit counter that counts the number of data bits shifted and forces the PCM output into a high impedance state after the 8th bit has been shifted out. This allows the strobe signal to have any duty cycle as long as its repetition rate is 8kHz and the shift clock is synchronized to it and the clock rate is either 1.536MHz, 1.544MHz, or 2.048MHz. Note that all internal clocks for the switched capacitor filters and timing conversions are automatically derived; no external control signal for clock selection is required. Power Down Circuitry-The codec can be powered in two ways. The most direct power down command is to force the PD (pin 14) mode select low. This will shut down the chip regardless of the strobes. The second way is to stop strobing with the SYNC (pin 11) input. The SYNC can be held high, low, or floating, as long as its state is not changed. After the chip has been shut down, the PCMoyr is locked into a high impedance state and the Aout is connected to Agnp to avoid output noise to the system. A-Law Characteristics-Compression (refer to figure 1) allows more channels to be multiplexed on a given transmission media by reducing the bandwidth of each individual channel. Figure 2 shows the A-Law companding transfer function used in telephony to convert the speakers analog voice signal into PCM. Figure 3 shows the expansion transfer function used to convert the digital PCM signal back into an analog signal for the end telephone user to hear. Response CharacteristicsFigure 4 shows the very flat (less than + .25dB) response of a typical S44233 receiver filter, while figure 5 shows the very flat response of a typical $44233 transmit filter. Figure 6 shows the gain tracking curve of a typical S44233 codec, and figure 7 shows the signal to distortion ratio of a typical $44233 codec. Together the flat filter response, excellent gain tracking, and low distortion make the S44233 an excellent choice for telephonys demanding quality needs.WAMIL $44233 A-Law Asynchronous Codec STANDARD PRODUCTS February 1993 Single Chip Codecs With Filters Figure 1 QUANTIZING LEVELS ZL STRONG SIGNAL WEAK SIGNAL en 1 WITHOUT A COMPANDER 2 WITH A COMPANDER 89AMI STANDARD PRODUCTS $44233 A-Law Asynchronous Codec Y Single Chip Codecs With Filters February 1993 Figure 2: The A-Law A/D Companding Transfer Function 10100701 F- 10110101 F- 19000101 10010101 11100101 |- 41110101 11000101 11016101 (41111111] (01111111) 01010101 ___> 01000101 [- DIGITAL OUTPUTS 01110101 [- 01100101 |- 00010101 F 00000101 ;- 00110101 F- 00100101 |- ANALOG INPUT (V) Figure 3: The A-Law D/A Companding Transfer Function ANALOG INPUT (V) Ss = 60100101 60110101 00000101 00010101 01100101 01110101 01000101 F- 11000107 11110101 11100101 10010101 10000101 10110101 10100101 | 01010101 (09111111) 111114411] 11010101 DIGITAL INPUTS (b) DECODER 90AMI STANDARD PRODUCTS $44233 A-Law Asynchronous Codec February 1993 Single Chip Codecs With Filters Figure 4 Figure 5 1.00 1.00 FREQUENCY RESPONSE RCV FREQUENCY RESPONSE TX | 0.75 }--- S44Z34A 0.75 5442344 Vaar8V Vue SV Waar Ve SV aah; _ 0.50 0.50 3 2 | | 0.25 - 0.25 T / 9.00 / 1.00 \__ Lo | | 02 F 3 02 1 2 3 FREQUENCY (kHz) FREQUENCY (kHz) Figure 6 Figure 7 os | % os GAIN oe | . SMMZ344A - - SIGNAL TO DISTORTION VearSV Vase SV . . A. \ TR, @ }- wea vey poh, Y| 04 A Tres I | : 0.2 Vu 2 3s V g 0.6 PAL yah prony fo 2 - = 02 2 / 3 3 Fo) 4 0.4 / 20 06 / 0.8 Be 58 ~40 wv -20 10 0 69 ) 40 30 -20 10 9 3 INPUT LEVEL (dBm0) INPUT LEVEL (48mo) 91