Am27LV512 65,536 x 8-Bit CMOS Low Voltage, One Time Programmable Memory cl Advanced Micro Devices DISTINCTIVE CHARACTERISTICS @ 3.3V+0.3 V Vcc read operation High performance at 3.3 V Vcc 200 ns maximum access time @ Low power consumption 90 u.W maximum standby power ~ 25 A maximum standby current 54 mW maximum power at 5 MHz 15 mA maximum current at 5 MHz No data retention power @ Industry standard packaging 32-pin PLCC 32-pin Plastic DIP @ Program voltage 12.75 + 0.25 V Latch-up protected to 100 mA from -1 V to Vcc +1V B Flashrite programming 10 us typical byte-program Less than 1 second typical chip program @ Advanced CMOS memory technology Low cost single transistor memory cell GENERAL DESCRIPTION The Am27LV512 device is a low voltage, low power, CMOS 64K x 8 One Time Programmable (OTP) non- volatile memory. Maximum power consumption in standby mode is 90 UW. If the device is constantly accessed at 5 MHz, then maximum power consumption increases to 54 mW. These power ratings are significantly lower than typical EPROM devices. Since power consumption is proportional to voltage squared, 3.3 V devices typically consume at least 57% less power than 5.0 V devices. The Am27LV512 typically draws 10 mA of current ena- bling 200 ns read operations. Typical power consump- tion under these conditions equals 33 mW. This high performance, low voltage device is ideal for BIOS stor- age in portable computing applications and control code storage in portable digital cellular phone applications. Low voltage CMOS designs require less operating power and hence dramatically increases the usable op- erating life of battery powered systems. The Am27LV512 is packaged in standard 32-pin PLCC and Plastic DIP packages. It is designed to be pro- grammed in standard EPROM programmers. The highest degree of latch-up protection is achieved with AMD's proprietary non-epi process. Latch-up pro- tection is provided for stresses up to 100 milliamps on address and data pins from 1 V to Vcc+1 V. The Am27LV512 is byte programmable using 10 us pro- gramming pulses in accordance with AMDs Flashrite programming algorithm. The typical room temperature programming time of the Am27LV512 is less than one second. M Data Outputs BLOCK DIAGRA ata Outpu oe V ls =H ttttttt Oo Vep Output Enable]__. OE" Chip Enable ce and + Output Buffers! PGMeL_Prog Logic = Y = Ts1__Decoder [-te{ Y-Gating Loe Ao-Ais > > Address . Inputs ) * x s | 524,288-Bit ; Decoder Cell Matrix : p 08140-001A This document contains information on a product under development at Advanced Micro Devices, Inc. The Information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication #: 16358 Rev. A Amendment 0 issue Date: July 1992 3-3al AMD PRELIMINARY PRODUCT SELECTOR GUIDE Family Part No. Am27LV512 Ordering Part No: +0.3 V Vcc Tolerance -200 -250 -300 Max Access Time (ns) 200 250 300 CE (E) Access (ns) 200 250 300 OE (G) Access (ns) 75 100 100 CONNECTION DIAGRAMS DIP PLCC Vep (11 32 0) Vcc ne (2 31 {] Pam (P) Aus (3 30 1] Nc Aw 4 29] At A7 0 5 28 i] A13 Ac [J 6 27 [ Ae As 7 26 [] Ao ws 251] An As []9 241] OE(G) Ao [] 10 23D Ato Ai 11 22 cE Aoi12 210 par Dao [J 13 20 [] Das Dai [14 19 1] Das DQe2 [15 18 L] Das 16358A-001B vss {] 16 171] Das 11561-002B Note: Pin 1 is marked for orientation. LOGIC SYMBOL 16 Ao- Ais 8 DQo- DQ7 KP) +P] CE ~-P} OE (G) #>| Pm (P) 11561-004A 3-4 Am27LV512 Data SheetPRELIMINARY AMD A ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The ordering number (Valid Combination) is formed by a combination of these elements: AM27LV512 -200 J Le OPTIONAL PROCESSING Blank = Standard processing TEMPERATURE RANGE C = Commercial (0 to +70C) PACKAGE TYPE J = 32-Pin Rectangular Plastic Leaded Chip Carrier (PL 032) P = 32-Pin Plastic DIP (PD 032) SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER/DESCRIPTION Am27LV512 512K (64K x 8-Bit) CMOS OTP Memory Valid Combinations Valid Combinations _ Valid Combinations list configurations planned to Am27LV512-200 be supported in volume for this device. Consult Am27LV512-250 Jc, PC the local AMD sales office to confirm availability of Am27LV512-300 specific valid combinations and to check on newly released combinations. One Time Programmable EPROM Products 3-5at AMD PRELIMINARY PIN DESCRIPTION Ao Ais Address Inputs for memory locations. DQo- DQ; Data Inputs during memory program cycles. Internal latches hold data during program cycles. Data Outputs during memory read cycles. CE (E) The Chip Enable active low input activates the chips control logic and input buffers. Chip Enable high will deselect the device and operates the chip in stand-by mode. OE (G) The Output Enable active low input gates the outputs of the device through the data buffers during memory read cycles. PGM (P) The Program Enable active low input controls the pro- gram function of the memory array. Vpp Power supply for programming. Vcc Power supply for device operation. (Read: Vcc =3.3 V+0.3 V, Program: Vec = 5.0 V + 10%) Vss Ground NC No Connect-corresponding pin is not connected inter- nally to the die. BASIC PRINCIPLES The Am27LV512 supports programming operations us- ing a fixed 12.75 + .25 V power supply. Read Only Memory Without high Vep voltage, the Am27LV512 functions as a read only memory and operates like a standard EPROM. The control inputs still manage traditional read, standby, output disable, and Auto select modes. Programming These devices are programmable on standard PROM programmer equipment. Please contact Advanced Micro Devices for PROM pro- grammer information. FUNCTIONAL DESCRIPTION Description Of User Modes Table 1. Am27LV512 User Bus Operations Operation cE OE WE VP P (E) (G) | (W) | (Note 1)| Ao Ao vo Read VIL Vit xX VePL Ao Ag Dout Standby Vin Xx xX VPPL Xx Xx HIGH Z Read-Only | Output Disable Vit Vin Vin VpeL Xx X HIGH Z Auto-select Manufacturer Vit Vie Vin VepL Vir Vio CODE Code (Note 2)} (01H) Auto-select Device Code Vit Vit Vin VpPL Vin Vip CODE (Note 2)} (26H) Legend: X= Don't care, where Dont Care is either ViLor Vin levels, Ver = Vpp < Vcc + 2 V, See DC Characteristics for voltage levels of Vppu, 0 V < An <Vcc + 2 V, (normal CMOS input levels, where n = 0 or 9). Notes: 1. VppL may be grounded, connected with a resistor to ground, or < Vcc +2.0V. VePH is the programming voltage specified for the device. Refer to the DC characteristics. When Vpp = VepL, memory contents can be read but not written. 2. 11.5< Vins 13.0 V, Voc = 5.0 Vt 10%. 3-6 Am27LV512 Data SheetPRELIMINARY AMD at READ ONLY MODE Veco =3.3V+0.3V Read The Am27LV512 functions as a read only memory. The Am27LV512 has two contro! functions. Both must be satisfied in order to output data. CE controls power to the device. This pin should be used for specific device se- lection. OE controls the device outputs and should be used to gate data to the output pins if a device is se- lected. Address access time tacc is equal to the delay from sta- ble addresses to valid output data. The chip enable ac- cess time tce is the delay from stable addresses and stable CE to valid data at the output pins. The output en- able access time is the delay from the falling edge of OE to valid data at the output pins (assuming the addresses have been stable at least tacc toe). Standby Mode The Am27LV512 has one standby mode. The CMOS standby mode (CE input held at Vcc + 0.5 V), con- sumes less than 25 A of current. When in the standby mode the outputs are in a high impedance state, inde- pendent of the OE input. If the device is deselected during programming, or pro- gram verification, the device will draw active current un- til the operation is terminated. Output Disable Output from the device is disabled when OE is at a logic high level. When disabled, output pins are in a high im- pedance state. Auto Select The Am27LV512 can be programmed in a standard PROM programmer. The Auto select mode allows the reading out of a binary code from the device that will identify its manufacturer and type. This mode is intended for the purpose of auto- matically matching the device to be programmed with its corresponding programming algorithm. Programming In A PROM Programmer To activate this mode, the programming equipment must force Vip (11.5 V to 13.0 V) on address Ag. Two identifier bytes may then be sequenced from the device outputs by toggling address Ao from Vit to Vin. All other address lines must be held at Vi_, and Ver must be less than or equal to Vcc + 2.0 V while using this Auto select mode. Byte 0 (Ao = Vit) represents the manufacturer code and byte 1 (Ao = Vin) the device identifier code. For the Am27LV512 these two bytes are given in the table below. All identifiers for manufacturer and device codes will exhibit odd parity with the MSB (DQ7) defined as the parity bit. Table 2. Am27LV512 Auto Select Code Code Type Ao | (HEX)| DQ7 | DQs | DQs | DQs | DQs | DQ2 | DQ: | DQo Manufacturer Code Vit 01 0 0 0 0 0 0 0 1 Device Code Vin 26 0 0 1 0 0 1 1 0 One Time Programmable EPROM Products 3-7EN amp PRELIMINARY ABSOLUTE MAXIMUM RATINGS Storage Temperature . Plastic Packages ............ 65C to +125C Ambient Temperature with Power Applied ........... 55C to + 126C Voltage with Respect To Ground All pins except Ag and Vep(Note 1) ...... 2.0Vt07.0V Vcc (Note 1) 2.6... eee eee eee eee -2.0Vt0o7.0V Ag (Note 2)...........0-.0000- -2.0V to 14.0V Vpp (Note 2)... 0.2.00. ee eee eee -2.0V to 14.0V Output Short Circuit Current (Note 3) ...... 200 mA Notes: 1. Minimum DC voltage on input or I/O pins is0.5 V. During voltage transitions, inputs may overshoot Vss to -2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins is Vcc + 0.5 V. During voltage transitions, outputs may overshoot to Vcc + 2.0 V for periods up to 20 ns. 2. Minimum DC input voltage on Ag and Vep pins is -0.5V. During voltage transitions, Ag and Vpp may overshoot Vss to -2.0 V for periods of up to 20 ns. Maximum DC in- put voltage on Ag and Vpp is +13.5 V which may over- shoot to 14.0 V for periods up to 20 ns. 3. No more than one output shorted at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under Absolute Maximum Rat- ings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. Exposure of the device to absolute maximum rating conditions for ex- tended periods may affect device reliability. OPERATING RANGES Commercial (C) Devices Case Temperature (Tc).......... 0C to +70C Vcc Supply Voltage Vecfor Am27LV512 .......... +3.0 V to +3.6V Veep Supply Voltage Program and Verify .......... 4125 Vto+13V Operating ranges define those limits between which the func- tionality of the device is guaranteed. 3-8 Am27LV512 Data SheetPRELIMINARY AMD a MAXIMUM OVERSHOOT Maximum Negative Input Overshoot 20nS 20nS -5V -2.0V 20 nS 11561-009B Maximum Negative Overshoot Waveform Maximum Positive Input Overshoot 20 nS Vcc +2.0V Vcc + 0.5 V KKKXXX XXX XXX 2.0V (IVAN 20 nS 20 nS 11561-010A Maximum Positive Overshoot Waveform Maximum Vpp Overshoot 20 nS 14.0V Voc +0.5V 20nS 20 nS 11561-011A Maximum Vpp Overshoot Waveform One Time Programmable EPROM Products 3-9al AMD PRELIMINARY DC CHARACTERISTICS-CMOS COMPATIBLE Parameter Symbol Parameter Description Test Conditions Min. Max. | Unit lu Input Leakage Current Vcc = Vcc Max., +1.0 |] pA Vin = Vcc or Vss ILo Output Leakage Current Vcc = Vcc Max., +1.0 |] pA Vout = Vcc or Vss Iccs Vcc Standby Current Vcc = Vcc Max. 25 pA CE=Vcc +0.3V Ices Vcc Active Read Current Voc = Vec Max.,CE = Vi, OE = Vin 15 mA lout = 0 mA, at 5 MHz Icc2 Vcc Programming Current CE=ViL 30 mA Programming in Progress IPPs Vee Standby Current Vpp = VpPL +1.0 | pA Vit Input Low Voltage 0.5 0.6 Vv Vin Input High Voltage 2.0 Veco Vv +05 VoL Output Low Voltage lo. =1mA 0.3 Vv Vcc = Vcc Min. Vou Output High Voltage lo = 100 pA, Vcc = Vcc Min. Vcc Vv -0.3 Vip Ag Auto Select Voltage Ag = Vio 41.5 13.0 Vv lip Ag Auto Select Current Ag = Vip Max. 35 pA Vcc = Vcc Max. VPPL Vpp during Read-Only 0.0 Vcc Vv Operations +2.0 VPPH Vpp during Read/Write 12.5 13.0 Vv Operations Notes: 1. Caution: the Am27LV512 must not be removed from (or inserted into) a socket when Vcc or Vpp is applied. 2. Icc1 is tested with OE = Vin to simulate open outputs. 3. Maximum active power usage is the sum of Icc and lpr. 3-10 Am27LV512 Data SheetPRELIMINARY AMD & PIN CAPACITANCE Parameter Symbol Parameter Description Test Conditions Typ. | Max. | Unit Cin Input Capacitance Vin=0 8 10 pF Court Output Capacitance Vout = 0 8 12 pF Cinz Vpp Input Capacitance Ver = 0 8 12 pF Notes: 1. Sampled, not 100% tested. 2. Test conditions Ta = 25C, f = 1.0 MHz. SWITCHING CHARACTERISTICS over operating range unless otherwise specified AC CHARACTERISTICS-Read Only Operation (Notes 1- 2) Parameter Symbols Am27LV512 JEDEC] Standard | Parameter Description -200 -250 -300 Unit tavav tac Read Cycle Time Min. 200 250 300 ns Max. teLav tce Chip Enable Min. Access Time Max. 200 250 300 ns tavav tacc Address Min. Access Time Max. 200 250 300 ns tetav toe Output Enable Min. Access Time Max. 75 100 100 ns teLax tz Chip Enabie to Min. 0 0 0 ns Output in Low Z Max. teHaz tor Chip Disable to Min. Output in High Z Max. 35 35 35 ns taLax toiz Output Enable to Min. 0 0 0 ns Output in Low Z Max. taHaz tor Output Disable to Min. Output in High Z Max. 35 35 35 ns taxax tou Output Hold from first of Min. 0 0 0 ns Address, CE, or OE Change | Max. tvcs Vcc Set-up Time to Min. 50 50 50 ys Valid Read Max. Notes: 1. Output Load: 1 TTL gate and CL = 100 pF, input Rise and Fall Times: < 10 ns, Input Pulse levels: 0.45 to 2.4 V, Timing Measurement Reference Level - Inputs: 0.6 V and 2 V Outputs: 1.5 V 2. tvcs is guaranteed by design not tested. One Time Programmable EPROM Products 3-11Zt amp PRELIMINARY Device and Outputs Data Power-up, Standby Address Selection Enabled Valid Standby, Power-down a Addresses \ Addresses Stable tavav (tac) - _ I NO =~ tEHQZ (toF) a, TWHGL -p| tGHaz (toF) LE J 5 WE (W) >| tatav(toe) je [* teLav (tce) tacav (toz) < taxax (toH) A teLax (tLz) HighZ fe _tvcs ~~ High Z Data (DQ) 4 ( Output Valid Dy) ) f? tavov (tacc) 4} 3.3V Vcc . \ OV 11561-013C AC Waveforms for Read Operations 3-12 Am27LV512 Data SheetPRELIMINARY AMD & SWITCHING TEST CIRCUIT 2.7 kQ Device Under Test +5V Diodes = IN3064 or Equivalent = = = 411561-012A CL = 100 pF including jig capacitance SWITCHING TEST WAVEFORMS 2.4V 2.0V TEST POINTS 1.5V 0.6 V 0.45 V INPUT OUTPUT All Devices AC Testing: Inputs are driven at 2.4 V fora logic 1 and 0.45 V for a logic O. Input pulse rise and fall times are < 10 ns. 16357 A-002B One Time Programmable EPROM Products 3-1321 amp PRELIMINARY ERASE AND PROGRAMMING PERFORMANCE Limits Parameter Min. | Typ. | Max. | Unit Comments Chip Programming Time 1 12 Ss Excludes system-level overhead (Note 1) Note: 1. 25C, 12.75 V Vep LATCHUP CHARACTERISTICS Min. Max. Input Voltage with respect to Vss on all pins except I/O pins (Including As and Ver) -1.0V 13.5V Input Voltage with respect to Vss on all pins I/O pins -1.0V Vec + 1.0 V Current 100 mA +100 mA Includes all pins except Vcc. Test conditions: Vcc = 5.0 V, one pin at a time. 3-14 Am27LV512 Data SheetPRELIMINARY Amp ot PHYSICAL DIMENSIONS* PD 032 1.640 1.680 So dt no eee eo , a 4 530 ) 580 1 4 -090 $$ a a * 005 065 ios 600 018 * e05 060 140 LU 225 | { | .008 J _ 015 f } | 630 t | , 700 Op O14 _ Pea 022 12416B PL 032 042 .048 .050 (+ REF | 042 ores Coe cri rr) .056 [oe] ON C ' qj q il Q ql 388 C Hl 1 026 595 C 032 547 C H f 553 q n Q i O i SST ooo .009 487 015 "15 425 -095 485 140 495 , 06971C *For reference only. All dimensions are measured in inches, unless otherwise noted. BSC is an ANSI standard for Basic Space Centering. One Time Programmable EPROM Products 3-15