500 MHz, Linear-in-dB VGA
with AGC Detector
AD8367
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
FEATURES
Broad-range analog variable gain: −2.5 dB to +42.5 dB
3 dB cutoff frequency of 500 MHz
Gain up and gain down modes
Linear-in-dB, scaled 20 mV/dB
Resistive ground referenced input
Nominal ZIN = 200 Ω
On-chip, square-law detector
Single-supply operation: 2.7 V to 5.5 V
APPLICATIONS
Cellular base stations
Broadband access
Power amplifier control loops
Complete, linear IF AGC amplifiers
High speed data I/O
FUNCTIONAL BLOCK DIAGRAM
02710-001
V
PSI
12
V
PSO
11
ENBL
2
DETO
6
GAIN
5
MODE
4
ICOM
14
ICOM
1
INPT
3
ICOM
7
DECL
9
HPFL
13
VOUT
10
OCOM
8
9-STAGE ATTENUATOR BY 5dB
GAUSSIAN INTERPOLATOR
BIAS
SQUARE
LAW
DETECTOR
g
m
CELLS
AD8367
Figure 1.
GENERAL DESCRIPTION
The AD8367 is a high performance 45 dB variable gain
amplifier with linear-in-dB gain control for use from low
frequencies up to several hundred megahertz. The range,
flatness, and accuracy of the gain response are achieved using
Analog Devices’ X-AMP® architecture, the most recent in a
series of powerful proprietary concepts for variable gain
applications, which far surpasses what can be achieved using
competing techniques.
The input is applied to a 9-stage, 200 Ω resistive ladder network.
Each stage has 5 dB of loss, giving a total attenuation of 45 dB.
At maximum gain, the first tap is selected; at progressively
lower gains, the tap moves smoothly and continuously toward
higher attenuation values. The attenuator is followed by a
42.5 dB fixed gain feedback amplifier—essentially an
operational amplifier with a gain bandwidth product of
100 GHz—and is very linear, even at high frequencies. The
output third order intercept is +20 dBV at 100 MHz (+27 dBm,
re 200 Ω), measured at an output level of 1 V p-p with VS = 5 V.
The analog gain-control input is scaled at 20 mV/dB and runs
from 50 mV to 950 mV. This corresponds to a gain of −2.5 dB
to +42.5 dB, respectively, when the gain up mode is selected and
+42.5 dB to −2.5 dB, respectively, when gain down mode is
selected. The gain down, or inverse, mode must be selected
when operating in AGC in which an integrated square-law
detector with an internal setpoint is used to level the output to
354 mV rms, regardless of the crest factor of the output signal.
A single external capacitor sets up the loop averaging time.
The AD8367 can be powered on or off by a voltage applied to
the ENBL pin. When this voltage is at a logic LO, the total
power dissipation drops to the milliwatt range. For a logic HI,
the chip powers up rapidly to its normal quiescent current of
26 mA at 25°C. The AD8367 is available in a 14-lead TSSOP
package for the industrial temperature range of −40°C to +85°C.
AD8367
Rev. A | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 11
Input Attenuator and Gain Control ......................................... 11
Input and Output Interfaces...................................................... 11
Power and Voltage Metrics........................................................ 12
Noise and Distortion.................................................................. 12
Output Centering ....................................................................... 12
RMS Detection ........................................................................... 13
Applications..................................................................................... 14
Input and Output Matching...................................................... 14
VGA Operation .......................................................................... 15
Modulated Gain Mode .............................................................. 15
AGC Operation .......................................................................... 15
Modifying the AGC Setpoint.................................................... 16
Evaluation Board ........................................................................ 19
Characterization Setup and Methods...................................... 20
Outline Dimensions ....................................................................... 21
Ordering Guide .......................................................................... 21
REVISION HISTORY
7/05—Rev. 0 to Rev. A
Changes to Format .............................................................Universal
Changes to General Description .................................................... 1
Changes to Table 1............................................................................ 3
Changes to Table 3............................................................................ 6
Changes to Figure 8.......................................................................... 7
Changes to Figure 9, Figure 12, and Figure 14 ............................. 8
Changes to Input and Output Interfaces Section....................... 11
Changes to Output Centering Section and Figure 31................ 12
Changes to RMS Detection Section ............................................. 13
Changes to Figure 32, Table 4, and Table 5 ................................. 14
Changes to Figure 33, Figure 34, and
AGC Operation Section................................................................. 15
Changes to the Modifying the AGC Set Point Section.............. 16
Changes to Figure 38...................................................................... 17
Changes to Figure 42...................................................................... 19
Changes to Table 7.......................................................................... 20
Moved Table 7 to Page ................................................................... 20
Moved Characterization Setup and Methods Section to Page . 20
Moved Figure 45 to Page ............................................................... 20
Changes to Ordering Guide .......................................................... 21
Updated Outline Dimensions....................................................... 21
10/01—Revision 0: Initial Version
AD8367
Rev. A | Page 3 of 24
SPECIFICATIONS
VS = 5 V, TA = 25°C, system impedance ZO = 200 Ω, VMODE = 5 V, f = 10 MHz, unless otherwise noted.
Table 1.
Parameter Conditions Min Typ Max Unit
OVERALL FUNCTION
Frequency Range LF 500 MHz
GAIN Range 45 dB
INPUT STAGE Pins INPT and ICOM
Maximum Input To avoid input overload 700 mV p-p
Input Resistance From INPT to ICOM 175 200 225 Ω
GAIN CONTROL INTERFACE Pin GAIN
Scaling Factor VMODE = 5 V, 50 mV ≤ VGAIN ≤ 950 mV +20 mV/dB
V
MODE = 0 V, 50 mV ≤ VGAIN ≤ 950 mV −20 mV/dB
Gain Law Conformance 100 mV ≤ VGAIN ≤ 900 mV ±0.2 dB
Maximum Gain VGAIN = 0.95 V +42.5 dB
Minimum Gain VGAIN = 0.05 V −2.5 dB
VGAIN Step Response From 0 dB to 30 dB 300 ns
From 30 dB to 0 dB 300 ns
Small Signal Bandwidth VGAIN = 0.5 V 5 MHz
OUTPUT STAGE Pin VOUT
Maximum Output Voltage Swing RL = 1 kΩ 4.3 V p-p
R
L = 200 Ω 3.5 V p-p
Output Source Resistance Series resistance of output buffer 50 Ω
Output Centering Voltage1 V
S/2 V
SQUARE LAW DETECTOR Pin DETO
Output Set Point 354 mV rms
AGC Small Signal Response Time CAGC = 100 pF, 6 dB gain step 1 μs
POWER INTERFACE Pins VPSI, VPSO, ICOM, and OCOM
Supply Voltage 2.7 5.5 V
Total Supply Current ENBL high, maximum gain, RL = 200 Ω
(includes load current)
26 30 mA
Disable Current vs. Temperature ENBL low 1.3 1.6 mA
−40°C ≤ TA ≤ +85°C 1.8 mA
MODE CONTROL INTERFACE Pin MODE
Mode LO Threshold Device in negative slope mode of operation 1.2 V
Mode HI Threshold Device in positive slope mode of operation 1.4 V
ENABLE INTERFACE Pin ENBL
Enable Threshold 2.5 V
Enable Response Time Time delay following LO to HI transition until
device meets full specifications.
1.5 μs
Enable Input Bias Current ENBL at 5 V 27 μA
ENBL at 0 V 32 nA
f = 70 MHz
Gain Maximum gain +42.5 dB
Minimum gain −3.7 dB
Gain Scaling Factor 19.9 mV/dB
Gain Intercept −5.6 dB
Noise Figure Maximum gain 6.2 dB
Output IP3 f1 = 70 MHz, f2 = 71 MHz, VGAIN = 0.5 V 36.5 dBm
29.5 dBV rms
Output 1 dB Compression Point VGAIN = 0.5 V 8.5 dBm
1.5 dBV rms
AD8367
Rev. A | Page 4 of 24
Parameter Conditions Min Typ Max Unit
f = 140 MHz
Gain Maximum gain +43.5 dB
Minimum gain −3.6 dB
Gain Scaling Factor 19.7 mV/dB
Gain Intercept −5.3 dB
Noise Figure Maximum gain 7.4 dB
Output IP3 f1 = 140 MHz, f2 = 141 MHz, VGAIN = 0.5 V 32.7 dBm
25.7 dBV rms
Output 1 dB Compression Point VGAIN = 0.5 V 8.4 dBm
1.4 dBV rms
f = 190 MHz
Gain Maximum gain +43.5 dB
Minimum gain −3.8 dB
Gain Scaling Factor 19.6 mV/dB
Gain Intercept −5.3 dB
Noise Figure Maximum gain 7.5 dB
Output IP3 f1 = 190 MHz, f2 = 191 MHz, VGAIN = 0.5 V 30.9 dBm
23.9 dBV rms
Output 1 dB Compression Point VGAIN = 0.5 V 8.4 dBm
1.4 dBV rms
f = 240 MHz
Gain Maximum gain +43 dB
Minimum gain −4.1 dB
Gain Scaling Factor 19.7 mV/dB
Gain Intercept −5.2 dB
Noise Figure Maximum gain 7.6 dB
Output IP3 f1 = 240 MHz, f2 = 241 MHz, VGAIN = 0.5 V 29.2 dBm
22.2 dBV rms
Output 1 dB Compression Point VGAIN = 0.5 V 8.1 dBm
1.1 dBV rms
1 The output dc centering voltage is normally set at VS/2 and can be adjusted by applying a voltage to DECL.
AD8367
Rev. A | Page 5 of 24
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage VPSO, VPSI 5.5 V
ENBL Voltage VS + 200 mV
MODE Select Voltage VS + 200 mV
VGAIN Control Voltage 1.2 V
Input Voltage ±600 mV
Internal Power Dissipation 250 mW
θJA 150°C/W
Maximum Junction Temperature 125°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature Range
(Soldering 60 sec)
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD8367
Rev. A | Page 6 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
02710-002
AD8367
TOP VIEW
(Not to Scale)
ICOM
1
ICOM
14
ENBL
2
HPFL
13
INPT
3
VPSI
12
MODE
4
VPSO
11
GAIN
5
VOUT
10
DETO
6
DECL
9
ICOM
7
OCOM
8
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1, 7, 14 ICOM Signal Common. Connect to low impedance ground.
2 ENBL A HI Activates the Device.
3 INPT Signal Input. 200 Ω to ground.
4 MODE Gain Direction Control. HI for positive slope; LO for negative slope.
5 GAIN Gain Control Voltage Input.
6 DETO Detector Output. Provides output current for RSSI function and AGC control.
8 OCOM Power Common. Connect to low impedance ground.
9 DECL Output Centering Loop Decoupling Pin.
10 VOUT Signal Output. To be externally ac-coupled to load.
11 VPSO Positive Supply Voltage. 2.7 V to 5.5 V. VPSI and VPSO are tied together internally with back-to-back
PN junctions. They should be tied together externally and properly bypassed.
12 VPSI Positive Supply Voltage. 2.7 V to 5.5 V.
13 HPFL High-Pass Filter Connection. A capacitor to ground sets the corner frequency of the output offset control loop.
AD8367
Rev. A | Page 7 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, TA = 25°C, system impedance ZO = 200 Ω, VMODE = 5 V, unless otherwise noted.
50
–10
0
10
20
30
40
10 100 1000
02710-003
FREQUENCY (MHz)
GAIN (dB)
1V
0.9V
0.8V
0.7V
0.6V
0.5V
0.4V
0.3V
0.2V
0.1V
Figure 3. Gain vs. Frequency for Values of VGAIN
45
40
35
30
25
20
15
10
5
0
–50 1.00.90.80.70.60.50.40.30.20.1
02710-004
VGAIN (V)
GAIN (dB)
MODE = 5V
10MHz
70MHz
140MHz
240MHz
MODE = 0V
10MHz
70MHz
140MHz
240MHz
Figure 4. Gain vs. VGAIN (Mode LO and Mode HI)
45
40
35
30
25
20
15
10
5
0
–5
2.0
1.6
1.2
0.8
0.4
0
–0.4
–0.8
–1.2
–1.6
–2.0
0 1.00.90.80.70.60.50.40.30.20.1
02710-005
V
GAIN
(V)
GAIN (dB)
LINEARITY ERROR (dB)
–40°C
+25°C
+85°C
Figure 5. Gain Conformance at 70 MHz for T = −40°C, +25°C, and +85°C
10
9
8
7
6
5
470 25023021019017015013011090
02710-006
FREQUENCY (MHz)
NOISE FIGURE (dB)
–40°C
+25°C
+85°C
`
Figure 6. NF (re 200 Ω) vs. Frequency at Maximum Gain
60
50
40
30
20
10
00 1.00.90.80.70.60.50.40.30.20.1
02710-007
V
GAIN
(V)
NOISE FIGURE (dB)
Figure 7. NF (re 200 Ω) vs. VGAIN at 70 MHz
40
35
30
25
20
15
10
5
00 1.00.90.80.70.60.50.40.30.20.1
02710-008
V
GAIN
(V)
OIP3 (dBm)
70MHz
140MHz
240MHz
10MHz
Figure 8. OIP3 vs. VGAIN
AD8367
Rev. A | Page 8 of 24
40
35
30
25
20
15
10
33
28
23
18
13
8
3
10 1000100
02710-009
FREQUENCY (MHz)
OIP3 (dBm re 200Ω)
OIP3 (dBV rms)
Figure 9. OIP3 vs. Frequency for VGAIN = 500 mV
4
2
0
–2
–4
–6
–8
11
9
7
5
3
1
–1
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
02710-010
V
GAIN
(V)
OUTPUT 1dB COMPRESSION (dBV rms)
OUTPUT 1dB COMPRESSION (dBm re 200
Ω
)
200MHz
140MHz
70MHz
10MHz
Figure 10. Output P1dB vs. VGAIN
5
–5
–4
–3
–2
–1
0
1
2
3
4
12
2
3
4
5
6
7
8
9
10
11
10 100 1000
02710-011
FREQUENCY (MHz)
OUTPUT 1dB COMPRESSION (dBV rms)
OUTPUT 1dB COMPRESSION (dBm re 200
Ω
)
Figure 11. Output P1dB vs. Frequency at VGAIN = 500 mV
0
–80
–70
–60
–50
–40
–30
–20
–10
0 1.00.90.80.70.60.50.40.30.20.1
02710-012
V
GAIN
(V)
OUTPUT IMD3 (dBc)
240MHz
140MHz
10MHz
70MHz
Figure 12. IMD3 vs. Gain (VOUT = 1 V p-p Composite)
4
–8
–6
–4
–2
0
2
11
9
7
5
3
1
–1
2.5 5.55.04.54.03.53.0
02710-013
V
S
(V)
OUTPUT 1dB COMPRESSION (dBV rms)
OUTPUT 1dB COMPRESSION (dBm re 200
Ω
)
Figure 13. Output Compression Point vs. Supply Voltage at 70 MHz,
VGAIN = 500 mV
40
35
30
25
20
15
10
5
0
33
–7
–2
3
8
13
18
23
28
2.5 5.55.04.54.03.53.0
02710-014
V
S
(V)
OUTPUT IP3 (dBm re 200
Ω
)
OUTPUT IP3 (dBV rms)
Figure 14. Output Third-Order Intercept vs. Supply Voltage at 70 MHz,
VGAIN = 500 mV
AD8367
Rev. A | Page 9 of 24
250
0
50
100
150
200
0
–120
–95
–73
–47
–25
0 500400300200100
02710-015
FREQUENCY (MHz)
RESISTANCE (
Ω
)
SERIES REACTANCE (
Ω
)
Figure 15. Input Resistance and Series Reactance vs. Frequency
at VGAIN = 500 mV
02710-016
0180
30
330
60
90
270
300
120
240
150
210 300mV
500mV
700mV
Figure 16. Input Reflection Coefficient vs.
Frequency from 10 MHz to 500 MHz for Multiple Values of VGAIN
70
40
45
50
55
60
65
20
15
–10
–5
0
5
10
0 500400300200100
02710-017
FREQUENCY (MHz)
RESISTANCE (
Ω
)
SERIES REACTANCE (
Ω
)
Figure 17. Output Resistance and Series Reactance vs.
Frequency at VGAIN = 500 mV
02710-018
0180
30
330
60
90
270
300
120
240
150
210
300mV
500mV
700mV
Figure 18. Output Reflection Coefficient vs. Frequency from
10 MHz to 500 MHz for Multiple Values of VGAIN
0.5
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
02710-019
TIME (200ns/DIV)
V (V)
V
GAIN
V
OUT
Figure 19. AGA Time Domain Response (3 dB Steps)
25
0
5
10
15
20
0.1 100k10k1k100101
02710-020
FREQUENCY (kHz)
GAIN (dB)
100pF
1nF
NO CAP
10pF
10nF
Figure 20. Gain vs. Frequency for Multiple Values of
HPFL Capacitor at VGAIN = 500 mV
AD8367
Rev. A | Page 10 of 24
140MHz
10MHz
70MHz
240MHz
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
2.0
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
–60 –50 –40 –30 –20 –10 0
02710-021
INPUT LEVEL (dBV rms)
RSSI (V)
LINEARITY ERROR (dB)
10MHz
70MHz
140MHz
240MHz
Figure 21. AGC RSSI (Voltage on DETO Pin) vs. Input Power at 10 MHz,
70 MHz, 140 MHz, and 240 MHz
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
2.0
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
–60 –50 –40 –30 –20 –10 0
02710-022
INPUT LEVEL (dBV rms)
RSSI (V)
LINEARITY ERROR (dB)
+85°C+25°C
–40°C
+25°C
–40°C
+85°C
Figure 22. AGC RSSI (Voltage on DETO Pin) vs.
Input Power over Temperature at 70 MHz
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
2.5
2.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
–60 –50 –40 –30 –20 –10 0
02710-023
INPUT LEVEL (dBV rms)
RSSI (V)
LINEARITY ERROR (dB)
16QAM
IS95FWD
256QAM
WCDMA
64QAM SINE
Figure 23. AGC RSSI (Voltage on DETO Pin) vs. Input Power
for Various Modulation Schemes
0.8
V
AGC
V
OUT
0.7
0.6
0.5
0.4
–2
–5
–1
–5
01
–5
2
–5
02710-024
TIME (Seconds)
V (V)
C
AGC
= 100pF
Figure 24. AGC Time Domain Response (3 dB Step)
19.0097 19.7297 19.9097 20.0897 20.2697
02710-025
GAIN SCALING (mV/dB)
Figure 25. Gain Scaling Distribution at 70 MHz
–6.4 –6.2 –6.0 –5.8 –5.6 –5.4 –5.2 –5.0 –4.8
02710-026
INTERCEPT (dB)
Figure 26. Gain Intercept Distribution at 70 MHz
AD8367
Rev. A | Page 11 of 24
THEORY OF OPERATION
The AD8367 is a variable gain, single-ended, IF amplifier based
on Analog Devices’ patented X-AMP architecture. It offers
accurate gain control with a 45 dB span and a 3 dB bandwidth
of 500 MHz. It can be configured as a traditional VGA with
50 dB/V gain scaling or as an AGC amplifier by using the built
in rms detector. Figure 27 is a simplified block diagram of the
amplifier. The main signal path consists of a voltage controlled
0 dB to 45 dB variable attenuator followed by a 42.5 dB fixed
gain amplifier. The AD8367 is designed to operate optimally in
a 200 Ω impedance system.
02710-027
GAIN
INPT
ATTENUATOR LADDER
200Ω
GAIN INTERPOLATOR
g
m
g
m
g
m
g
m
0dB –5dB –10dB –45dB V
OUT
–42.5dB
INTEGRATOR OUTPUT
BUFFER
VOUT
Figure 27. Simplified Architecture
INPUT ATTENUATOR AND GAIN CONTROL
The variable attenuator consists of a 200 Ω single-ended
resistive ladder that comprises of nine 5 dB sections and an
interpolator that selects the attenuation factor. Each tap point
down the ladder network further attenuates the input signal
by a fixed decibel factor. Gain control is achieved by sensing
different tap points with variable transconductance stages.
Based on the gain control voltage, an interpolator selects which
stage(s) are active. For example, if only the first stage is active,
the 0 dB tap point is sensed; if the last stage is active, the 45 dB
tap point is sensed. Attenuation levels that fall between tap
points are achieved by having neighboring gm stages active
simultaneously, creating a weighted average of the discrete
tap point attenuations. In this way, a smooth, monotonic
attenuation function is synthesized, that is, linear-in-dB
with a very precise scaling.
The gain of the AD8367 can be an increasing or decreasing
function of the control voltage, VGAIN, depending on whether
the MODE pin is pulled up to the positive supply or down to
ground. When the MODE pin is high, the gain increases with
VGAIN, as shown in Figure 28. The ideal linear-in-dB scaled
transfer function is given by
Gain (dB) = 50 × VGAIN − 5 (1)
where VGAIN is expressed in volts.
Equation 1 contains the gain scaling factor of 50 dB/V (20
mV/dB) and the gain intercept of −5 dB, which represents the
extrapolated gain for VGAIN = 0 V. The gain ranges from −2.5 dB
to +42.5 dB for VGAIN ranging from 50 mV to 950 mV. The
deviation from Equation 1, that is, the gain conformance error,
is also illustrated in Figure 28. The ripples in the error are a
result of the interpolation action between
tap points. The AD8367 provides better than ±0.5 dB of
conformance error over >40 dB gain range at 200 MHz
and ±1 dB at 400 MHz.
44
40
36
32
28
24
20
16
12
8
4
0
–4
2.0
–2.4
–2.0
–1.6
–1.2
–0.8
–0.4
0
0.4
0.8
1.2
1.6
0 1.00.90.80.70.60.50.40.30.20.1
02710-028
V
GAIN
(V)
GAIN (dB)
LINEARITY ERROR (dB)
HI MODE
LO MODE
50dB/V
GAIN
SLOPE
Figure 28. The gain function can be either an increasing or decreasing
function of VGAIN, depending on the MODE pin.
The gain is a decreasing function of VGAIN when the MODE pin
is low. Figure 28 also illustrates this mode, which is described by
Gain (dB) = 45 − 50 × VGAIN (2)
This gain mode is required in AGC applications using the built-
in, square-law level detector.
INPUT AND OUTPUT INTERFACES
The AD8367 was designed to operate best in a 200 Ω imped-
ance system. Its gain range, conformance law, noise, and
distortion assume that 200 Ω source and load impedances
are used. Interfacing the AD8367 to other common impedances
(from 50 Ω used at radio frequencies to 1 kΩ presented by data
converters) can be accomplished using resistive or reactive
passive networks, whose design depends on specific system
requirements, such as bandwidth, return loss, noise figure,
and absolute gain range.
The input impedance of the AD8367 is nominally 200 Ω,
determined by the resistive ladder network. This presents a
200 Ω dc resistance to ground, and, in cases where an elevated
signal potential is used, ac coupling is necessary. The input
signal level must not exceed 700 mV p-p to avoid overloading
the input stage. The output impedance is determined by an
internal 50 Ω damping resistor, as shown in Figure 29. Despite
the fact that the output impedance is 50 Ω, the AD8367 should
still be presented with a load of 200 Ω. This implies that the
load is mismatched, but doing so preserves the distortion
performance of the amplifier.
AD8367
Rev. A | Page 12 of 24
02710-029
50ΩV
OUT
V
B1
V
B2
FROM
INTEGRATOR
Figure 29. A 50 Ω resistor is added to the
output to prevent package resonance.
POWER AND VOLTAGE METRICS
Although power is the traditional metric used in the analysis
of cascaded systems, most active circuit blocks fundamentally
respond to voltage. The relationship between power and voltage
is defined by the impedance level. When input and output
impedance levels are the same, power gain and voltage gain
are identical. However, when impedance levels change between
input and output, they differ. Thus, one must be very careful to
use the appropriate gain for system chain analyses. Quantities
such as OIP3 are quoted in dBV rms as well as dBm referenced
to 200 Ω. The dBV rms unit is defined as decibels relative to
1 V rms. In a 200 Ω environment, the conversion from dBV rms
to dBm requires the addition of 7 dB to the dBV rms value. For
example, a 2 dBV rms level corresponds to 9 dBm.
NOISE AND DISTORTION
Since the AD8367 consists of a passive variable attenuator
followed by a fixed gain amplifier, the noise and distortion
characteristics as a function of the gain voltage are easily
predicted. The input-referred noise increases in proportion to
the attenuation level. Figure 30 shows noise figure, NF, as a
function of VGAIN for the MODE pin pulled high. The minimum
NF of 7.5 dB occurs at maximum gain and increases 1 dB for
every 1 dB reduction in gain. In receiver applications, the
minimum NF should occur at the maximum gain where the
received signal presumably is weak. At higher levels, a lower
gain is needed, and the increased NF becomes less important.
The input-referred distortion varies in a similar manner to the
noise. Figure 30 illustrates how the third-order intercept point
at the input, IIP3, behaves as a function of VGAIN. The highest
IIP3 of 20 dBV rms (27 dBm re 200 Ω) occurs at minimum
gain. The IIP3 then decreases 1 dB for every 1 dB increase in
gain. At lower levels, a degraded IIP3 is acceptable. Overall, the
dynamic range, represented by the difference between IIP3 and
NF, remains reasonably constant as a function of gain. The
output distortion and compression are essentially independent
of the gain. At low gains, when the input level is high, input
overload can occur, causing premature distortion.
60
–30
–20
–10
00
10
20
30
40
50
60
–30
–20
–10
10
20
30
40
50
0 1.00.90.80.70.60.50.40.30.20.1
02710-030
V
GAIN
(V)
IIP3 (dBV)
NF (dB)
NF
IIP3
Figure 30. Noise Figure and Input Third-Order Intercept vs.
Gain (RSOURCE = 200 Ω)
OUTPUT CENTERING
To maximize the ac swing at the output of the AD8367, the
output level is centered midway between ground and the supply.
This is achieved when the DECL pin is bypassed to ground via a
shunt capacitor. The loop acts to suppress deviations from the
reference at outputs below its corner frequency while not affect-
ing signals above it, as shown in Figure 31. The maximum
corner frequency with no external capacitor is 500 kHz. The
corner frequency can be lowered arbitrarily by adding an
external capacitor, CHP:
0.02(nF)
10
(kHz) +
=
HP
HP C
f (3)
A 100 Ω in series with the CHP capacitor is recommended to
de-Q the resonant tank that is formed by the bond-wire
inductance and CHP. Failure to insert this capacitor can
potentially cause oscillations at higher frequencies at high
gain settings.
02710-031
MAIN
AMPLIFIER
g
m
VOUT
FROM
INPUT
HPFL
C
HP
R
HP
V
MID
DECL
A
V
= 1
Figure 31. The dc output level is centered to midsupply by a control loop
whose corner frequency is determined by CHP.
AD8367
Rev. A | Page 13 of 24
RMS DETECTION
The AD8367 contains a square-law detector that senses
the output signal and compares it to a calibrated setpoint of
354 mV rms, which corresponds to a 1 V p-p sine wave. This
setpoint is internally set and cannot be modified to change the
AGC setpoint and the resulting VOUT level without using
additional external components. This is described in the
Modifying the AGC Setpoint section.
Any difference between the output and setpoint generates
a current that is integrated by an external capacitor, CAGC,
connected from the DETO pin to ground, to provide an AGC
control voltage. There is also an internal 5 pF capacitor on the
DETO pin.
The resulting voltage is used as an AGC bias. For this
application, the MODE pin is pulled low and the DETO pin is
tied to the GAIN pin. The output signal level is then regulated
to 354 mV rms. The AGC bias represents a calibrated rms
measure of the received signal strength (RSSI). Since in AGC
mode the output signal is forced to the 354 mV rms setpoint
(−9.02 dBV rms), Equation 2 can be recast to express the
strength of the received signal, VIN-RMS, in terms of the AGC
bias VDETO.
VIN − RMS (dBV rms) = 54.02 + 50 × VDETO (4)
where −54.02 dBV rms = −45 dB − 9.02 dBV rms.
For small changes in input signal level, VDETO responds with a
characteristic single-pole time constant, τAGC, which is
proportional to CAGC.
τAGC (μs) = 10 × CAGC (nf) (5)
where the internal 5 pF capacitor is lumped with the external
capacitor to give CAGC.
AD8367
Rev. A | Page 14 of 24
APPLICATIONS
The AD8367 can be configured either as a VGA whose gain
is controlled externally through the GAIN pin or as an AGC
amplifier, using a supply voltage of 2.7 V to 5.5 V. The supply
to the VPSO and VPSI pins should be decoupled using a low
inductance, 0.1 μF surface-mount, ceramic capacitor as close
as possible to the device. Additional supply decoupling can
be provided by a small series resistor. A 10 nF capacitor from
Pin DECL to Pin OCOM is recommended to decouple the
output reference voltage.
INPUT AND OUTPUT MATCHING
The AD8367 is designed to operate in a 200 Ω impedance
system. The output amplifier is a low output impedance voltage
buffer with a 50 Ω damping resistor to desensitize it from load
reactance and parasitics. The quoted performance includes the
voltage division between the 50 Ω resistor and the 200 Ω load.
The AD8367 can be reactively matched to an impedance other
than 200 Ω by using traditional step-up and step down
matching networks or high quality transformers. Table 4 lists
the 50 Ω S-parameters for the AD8367 at a VGAIN = 750 mV.
Figure 32 illustrates an example where the AD8367 is matched
to 50 Ω at 140 MHz. As shown in the Smith Chart, the input
matching network shifts the input impedance from ZIN to 50 Ω
with an insertion loss of <2 dB over a 5 MHz bandwidth. For
the output network, the 50 Ω load is made to present 200 Ω to
the AD8367 output. Table 5 provides the component values
required for 50 Ω matching at several frequencies of interest.
When added loss and noise can be tolerated, a resistive pad can
be used to provide broadband, near-matched impedances at the
device terminals and the terminations.
Minimum-loss, L-pad networks are used on the evaluation
board (see Figure 45) to allow easy interfacing to standard
50 Ω test equipment. Each pad introduces an 11.5 dB power
loss (5.5 dB voltage loss).
1
0.3333
–0.3333
–1
–3
3
0.3333 1 3
Z
IN
R
SOURCE
SERIES L SHUNT C
02710-032
Z
IN
Z
IN
XS
IN
100nH
Z
LOAD
Z
OUT
XS
OUT
13pF
C
AC
0.1μF
R
SOURCE
50Ω
R
LOAD
50Ω
XP
OUT
120nH
V
S
XP
IN
8.2pF AD8367
f
C
= 140MHz, Z
IN
= 197 – j34.2, R
SOURCE
= 50Ω
Figure 32. Reactive Matching Example for f = 140 MHz
Table 4. S-Parameters for 200 Ω System for VS = 5 V and VGAIN = 0.75 V
Frequency (MHz) S11 S21 S12 S22
10 0.04 ∠ −43.8° 41.1 ∠ 178.8° 0.0003 ∠ 76.1° 0.56 ∠ −179.3°
70 0.09 ∠ −81.5° 43.6 ∠ 163.4° 0.0002 ∠ 63.7° 0.55 ∠ +176.1°
140 0.17 ∠ −103.4° 48.0 ∠ 141.4° 0.0009 ∠ 130.8° 0.56 ∠ +170.2°
190 0.21 ∠ −111.7° 47.5 ∠ 124.0° 0.0017 ∠ 96.8° 0.54 ∠ +166.5°
240 0.26 ∠ −103.8° 48.3 ∠ 107.6° 0.0018 ∠ 113.5° 0.48 ∠ +164.6°
Table 5. Reactive Matching Components for a 50 Ω System where RSOURCE = 50 Ω, RLOAD = 50 Ω
Frequency (MHz) XSIN XPIN (pF) XSOUT (pF) XPOUT
10 1.5 μH 120 180 1.8 μH
70 220 nH 15 27 270 nH
140 100 nH 8.2 13 120 nH
190 82 nH 2.7 10 100 nH
240 68 nH 1.5 7 82 nH
AD8367
Rev. A | Page 15 of 24
VGA OPERATION
The AD8367 is a general-purpose VGA suitable for use in a
wide variety of applications where voltage control of gain is
needed. While having a 500 MHz bandwidth, its use is not
limited to high frequency signal processing. Its accurate,
temperature- and supply-stable linear-in-dB scaling is
valuable wherever it is important to have a more dependable
response to the control voltage than is usually offered by VGAs
of this sort. For example, there is no preclusion to its use in
speech-bandwidth systems.
Figure 33 shows the basic connections. The CHP capacitor at
Pin HPFL can be used to alter the high-pass corner frequency of
the signal path and is associated with the offset control loop that
eliminates the inherent variation in the internal dc balance of the
signal path as the gain is varied (offset ripple). This frequency
should be chosen to be about a decade below the lowest frequency
component of the signal. If made much lower than necessary, the
offset loop is not able to track the variations that occur when there
are rapid changes in VGAIN. The control of offset is important even
when the output is ac-coupled because of the potential reduction of
the upper and lower voltage range at this pin.
However, in many applications these components are
unnecessary because an internal network provides a default
high-pass corner of about 500 kHz. For CHP = 1 nF, the
modified corner is at ~10 kHz; it scales downward with
increasing capacitance. Figure 20 shows representative
response curves for the indicated component values.
02710-033
AD8367
ICOM
1
ICOM
14
ENBL
2
HPFL
13
INPT
3
VPSI
12
MODE
4
VPSO
11
GAIN
5
VOUT
10
DETO
6
DECL
9
ICOM
7
OCOM
8
V
GAIN
VOUT
V
IN
C5
10nF
C1
1μF
C4
0.1μF
C
HP
10nF R
HP
100Ω
R6
4.7ΩR5
4.7Ω
V
P
C3
0.1μF
C2
0.1μF
Figure 33. Basic Connections for Voltage Controlled Gain Mode
MODULATED GAIN MODE
The AD8367 can be used as a means of modulating the signal
level. Keep in mind, however, that the gain is a nonlinear
(exponential) function of VGAIN; thus, it is not suitable for
normal amplitude-modulation functions. The small signal
bandwidth of the gain interface is ~5 MHz, and the slew rate
is of the order of ±500 dB/μs. During gain slewing from close
to minimum to maximum gain (or vice versa), the internal
interpolation processes in an X-AMP-based VGA rapidly
scan the full range of gain values. The gain and offset ripple
associated with this process can cause transient disturbances
in the output. Therefore, it is inadvisable to use high amplitude
pulse drives with rise and fall times below 200 ns.
AGC OPERATION
The AD8367 can be used as an AGC amplifier, as shown in
Figure 34. For this application, the accurate internal, square-law
detector is employed. The output of this detector is a current
that varies in polarity, depending on whether the rms value of
the output is greater or less than its internally-determined
setpoint of 354 mV rms. This is 1 V p-p for sine-wave signals,
but the peak amplitude for other signals, such as Gaussian
noise, or those carrying complex modulation, is invariably
somewhat greater. However, for all waveforms having a crest
factor of <5, and when using a supply voltage of 4.5 V to 5.5 V,
the rms value is correctly measured and delivered at VOUT.
When using lower supplies, the rms value of VOUT is unaffected
(the setpoint is determined by a band gap reference), but the
peak crest factor capacity is reduced.
The gain pin is connected to the base of a transistor internally
and thus requires only 1 μA of current drive. The output of the
detector is delivered to Pin DETO. The detector can source up
to 60 μA and can sink up to 11 μA. For a sine-wave output
signal, and under conditions where the AGC loop is settled, the
detector output also takes the form of a sine-wave, but at twice
the frequency and having a mean value of 0. If the input to the
amplifier increases, the mean of this current also increases and
charges the external loop filter capacitor, CAGC, toward more
positive voltages. Conversely, a reduction in VOUT below the
setpoint of 354 mV rms causes this voltage to fall toward
ground. The capacitor voltage is the AGC bias; this can be
used as a received signal strength indicator (RSSI) output
and is scaled exactly as VGAIN, that is, 20 mV/dB.
02710-034
AD8367
ICOM
1
ICOM
14
ENBL
2
HPFL
13
INPT
3
VPSI
12
MODE
4
VPSO
11
GAIN
5
VOUT
10
DETO
6
DECL
9
ICOM
7
OCOM
8
V
AGC
VOUT
V
IN
C5
10nF
C
AGC
0.1μF
C1
1μF
C4
0.1μF
C
HP
10nF R
HP
100Ω
R6
4.7ΩR5
4.7Ω
V
P
C3
0.1μF
C2
0.1μF
Figure 34. Basic Connections for AGC Operation
A valuable feature of using a square law detector is that the
RSSI voltage is a true reflection of signal power and can be
converted to an absolute power measurement for any given
source impedance. The AD8367 can thus be employed as a
true-power meter, or decibel-reading ac voltmeter, as distinct
from its basic amplifier function.
The AGC mode of operation requires that the correct gain
direction is chosen. Specifically, the gain must fall as VAGC
increases to restore the needed balance against the setpoint.
Therefore, the MODE pin must be pulled low. This accurate
leveling function is shown in Figure 35, where the rms output is
AD8367
Rev. A | Page 16 of 24
held to within 0.1 dB of the setpoint for >35 dB range of
input levels.
The dynamics of this loop are controlled by CAGC acting in
conjunction with an on-chip equivalent resistance, RAGC, of
10 kΩ which form an effective time-constant TAGC = RAGC CAGC.
The loop thus operates as a single-pole system with a loop
bandwidth of 1/(2π TAGC). Because the gain control function is
linear in decibels, this bandwidth is independent of the absolute
signal level. Figure 36 illustrates the loop dynamics for a 30 dB
change in input signal level with CAGC = 100 pF.
–1.2
–2.2
–2.1
–2.0
–1.9
–1.8
–1.7
–1.6
–1.5
–1.4
–1.3
–50 –40 –30 –20 –10 0 10
02710-035
PIN (dBm re 200Ω)
POUT (dBm re 200
Ω
)
Figure 35. Leveling Accuracy of the AGC Function
1.0 V
AGC
V
OUT
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
0 5 10 15 20 25 30 35 40
02710-036
TIME (μs)
V
ACG
(V); V
OUT
(arb)
Figure 36. AGC Response to a 32 dB Step in Input Level (f = 50 MHz)
It is important to understand that RAGC does not act as if in
shunt with CAGC. Rather, the error-correction process is that of a
true integrator, to guarantee an output that is exactly equal in
rms amplitude to the specified setpoint. For large changes in
input level, the integrating action of this loop is most apparent.
The slew rate of VAGC is determined by the peak output current
from the detector and the capacitor. Thus, for a representative
value of CAGC = 3 nF, this rate is about 20 V rms or 10 dB/μs,
while the small-signal bandwidth is 1 kHz.
Most AGC loops incorporating a true error-integrating
technique have a common weakness. When driven from an
increasingly larger signal, the AGC bias increases to reduce the
gain. However, eventually the gain falls to its minimum value,
for which further increase in this bias has no effect on the gain.
That is, the voltage on the loop capacitor is forced progressively
higher because the detector output is a current, and the AGC
bias is its integral. Consequently, there is always a precipitous
increase in this bias voltage when the input to the AD8367
exceeds that value that overdrives the detector, and because the
minimum gain is −2.5 dB, that happens for all inputs 2.5 dB
greater than the setpoint of ~350 mV rms. If possible, the user
should ensure that this limitation is preserved, preferably with a
guard-band of 5 dB to 10 dB below overload
In some cases, if driven into AGC overload, the AD8367
requires unusually long times to recover; that is, the voltage
at DETO remains at an abnormally high value and the gain is at
its lowest value. To avoid this situation, it is recommended that
a clamp be placed on the DETO pin, as shown in Figure 37.
02710-037
AD8367
1 14
2 13
3 12
MODE
4 11
GAIN
5 10
DETO
6 9
ICOM
7 8
RB
RA
C
AGC
0.1μF
V
AGC
Q1
2N2907
0.5V
+V
S
Figure 37. External Clamp to Prevent AGC Overload.
The resistive divider network, RA and RB, should be designed
such that the base of Q1 is driven to 0.5 V.
MODIFYING THE AGC SETPOINT
If an AGC setpoint other than the internal one is desired, an
external detector must be used. Figure 38 shows a method
that uses an external true-rms detector and error integrator to
operate the AD8367 as a closed-loop AGC system with a user-
settable operating level.
The AD8361 (U2) produces a dc output level that is
proportional to the rms value of its input, taken as a sample
of the AD8367 (U1) output. This dc voltage is compared to
an externally-supplied setpoint voltage, and the difference is
integrated by the AD820 (U3) to form the gain control voltage
that is applied to the GAIN input of the AD8367 through the
divider composed of R4 and R5. This divider is included in
order to minimize overload recovery time of the loop by having
the integrator saturate at a point that only slightly overdrives the
gain control input of the AD8367. The scale factor at VAGC is
influenced by the values of R4 and R5; for the values shown, the
factor is 86 mV/dB.
AD8367
Rev. A | Page 17 of 24
0
2710-038
VOUT
10
DECL
9
OCOM
8
C5
10nF
GAIN
5
DETO
6
ICOM
7
V
g
R5
10kΩ
AD8367
U1
ICOM
1
ICOM
14
ENBL
2
HPFL
13
INPT
3
VPSI
12
MODE
4
VPSO
11
INPUT
J1 10nF
R6
57.6Ω
C
HP
10nF R
HP
100Ω
V
AGC
AD820
U3 2
3
6
4
7V
SET
5V
0.1μF
R3
82kΩ20pF
C1
3.3nF
AD8361
U2
PWDN
4
COMM
5
RFIN
3
FLTR
6
IREF
2
VRMS
7
VPOS
1
SREF
8
R2
150kΩ
R4
33kΩ
R1
200kΩ
10nF
10nF
0.1μF
2.2
Ω
12kΩ
C2
0.27μF
Vrms
V
OUT
INTO A
200Ω LOAD
5V
Figure 38. Example of Using an External Detector to Form an AGC Loop
Note that in this circuit the AD8367’s MODE pin must be
pulled high to obtain correct feedback polarity because the
integrator inverts the polarity of the feedback signal.
The relationship between the setpoint voltage and the rms
output voltage of the AD8367 is
(
)
7.5225
225
×
+
×=
−
R1
VV SETRMSOUT (6)
where 225 is the input resistance of the AD8361 and 7.5 is its
conversion gain. For R1 = 200 Ω, this reduces to VOUT –RMS = VSET
× 0.25.
Capacitor C2 sets the averaging time for the rms detector. This
should be made long enough to provide sufficient smoothing of
the detector’s output in the presence of the modulation on the
RF signal. A level fluctuation of less than 1 dB (<5% to 10%) p-p
at the AD8361’s output is a reasonable value. A considerably
longer time constant needlessly lowers the AGC bandwidth,
while a short time constant can degrade the accuracy of the
true-rms measurement process. Components C1, R2, and R3
set the control loop’s bandwidth and stability. The maximum
stable loop bandwidth is limited by the rms detector’s averaging
time constant as previously discussed.
For an input signal consisting of a 4.096 MS/s QPSK modulated
carrier, the relationship between VSET and the output power for
this setup is shown in Figure 39. The exponential shape reflects
the linear-in-magnitude response of the AD8361. The adjacent
channel power ratio (ACPR) as a function of output power is
illustrated in Figure 40. The minima occur where the distortion
and integrated noise powers cross over.
The component values shown in Figure 38 were chosen for a
64-QAM signal at 500 kS/s at a carrier frequency of 150 MHz.
The response time of the loop as shown is roughly 5 ms for
an abrupt input level change of 40 dB. Figure 41 shows the
dynamic performance of the loop with a step-modulated
CW signal applied to the input for a VSET of about 1 V.
For a linear-in-dB response, detectors such as the AD8318 or
the AD8362 can be used in place of the AD8361.
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
–20 1050–5–10–15
02710-039
V
SET
(V)
10MHz
380MHz
POUT (dBm INTO 200Ω)
Figure 39. AGC Setpoint Voltage vs. Output Power
(QPSK: 4.096 MS/s; α = 0.22; 1 User)
AD8367
Rev. A | Page 18 of 24
380MHz
140MHz
10MHz
70MHz
–20
–60
–55
–50
–45
–40
–35
–30
–25
–20 –15 –10 –5 0 5 10
02710-041
ACPR (dBc)
POUT (dBm INTO 200Ω)
Figure 40. ACPR vs. Output Power for QPSK Waveform
(QPSK: 4.096 MS/s; α = 0.22; 1 User)
1.0
–2.0
–1.5
–1.0
–0.5
0
0.5
0 0.005 0.010 0.015 0.020 0.025 0.030 0.035
V
g
0.040
02710-040
TIME (Seconds)
Vg (V); V
OUT
(arb)
V
OUT
Figure 41. AGC Dynamic Response: 8367 AGC with an External Detector
Table 6. Suggested Component Values for External AGC Detector Circuit
Modulation Type Rate Sys/s C1 (μF) C2 (μF) R2 (kΩ) R3 (kΩ)
QPSK 1.23 M 0.0022 0.033 150 62
QPSK 4 M 0.0022 0.015 150 39
π/4 DQPSK 24.3 K 0.033 0.68 150 51
64 QAM 100 K 0.015 1.5 150 51
64 QAM 500 K 0.0068 0.33 150 62
64 QAM 4 M 0.0022 0.068 150 100
AD8367
Rev. A | Page 19 of 24
EVALUATION BOARD
Figure 42 shows the schematic of the AD8367 evaluation board. The board is powered by a single supply of 2.7 V to 5.5 V.
02710-042
AD8367
ICOM
1
ICOM
14
ENBL
2
HPFL
13
INPT
3
VPSI
12
MODE
4
VPSO
11
GAIN
5
VOUT
10
DETO
6
DECL
9
ICOM
7
OCOM
8
INPUT
J1
C5
10nF
C
AGC
0.1μF
C1
1μF
C
HP
10nF R
HP
100Ω
R6
4.7ΩR5
4.7Ω
V
P
TP1
C4
0.1μF
C3
0.1μF
C2
0.1μF
SW1
SW2
TP3
MODE
LK1
TP4
GAIN
R1
57.6Ω
R2
174Ω
R4
174Ω
R7
10kΩ
R1
57.6Ω
OUTPUT
J2
Figure 42. Evaluation Board Schematic
02710-043
02710-044
Figure 43. Layout of Component Side Figure 44. Silkscreen of Component Side
AD8367
Rev. A | Page 20 of 24
Table 7 details the various configuration options of the evaluation board.
Table 7. Evaluation Board Configuration Options
Component Function Default Condition
TP1, TP2 Supply and Ground Vector Pins. Not Applicable
TP3, TP4 Mode and Gain Vector Pins. Not Applicable
SW1 VGA/AGC Select: Used to select VGA (Position A) or AGC (Position B) mode of
operation. SW2 must be set for Position A for AGC mode of operation.
SW1 = A
SW2 MODE Select. Used to select positive or negative VGA slope. Set to Position B for an
increasing gain with VGAIN, Position A for decreasing gain law.
SW2 = B
LK1 Device Enable. When LK1 is installed, the ENBL pin is connected to the positive supply
and the AD8367 is in operating mode.
LK1 = Installed
R1, R2 Input Interface. R1 and R2 are used to provide an L-pad impedance-transforming
network. The broadband matching network transforms a 50 Ω source to match a
200 Ω load with 11.5 dB of insertion loss.
R1 = 57.6 Ω (Size 0603)
R2 = 174 Ω (Size 0603)
R3, R4, C4 Output Interface. R3 and R4 are used to transform a 50 Ω load termination to look like
a 200 Ω load with 11.5 dB of insertion loss. The ac coupling capacitor, C4, can be
increased to obtain a lower high-pass corner frequency.
R3 = 57.6 Ω (Size 0603)
R4 = 174 Ω (Size 0603)
C4 = 0.1 μF (Size 0603)
C1, C2, C3, R5, R6 Power Supply Decoupling. The nominal supply decoupling consists of a 1 μF capacitor
to ground, a 4.7 Ω series resistor, and a 0.1 μF capacitor to ground. The same
decoupling network should be used on both the VPSI and VPSO supply lines.
C1 = 1 μF (Size 0603)
R5 = R6 = 4.7 Ω (Size 0805)
C2 = C3 = 0.1 μF (Size 0603)
C5 Internal Supply Decoupling. Capacitor C5 provides midsupply decoupling. C5 = 10 nF (Size 0603)
CHP Filter Capacitor. HPFL capacitor, sets the high-pass corner frequency. CHP = 0.01 μF (Size 0805)
RHP = 0 Ω (Size 0603)
CAGC AGC Filter Capacitor. Capacitor, CAGC, sets closed-loop AGC response time. CAGC = 0.1 μF (Size 0805)
R7 Mode Pull-Up Resistor. R7 = 10 kΩ (Size 0805)
RHP High-Pass Filter Resistor. RHP = 100 Ω (Size)
CHARACTERIZATION SETUP AND METHODS
Minimum-loss, L-pad matching networks were used to
interface standard 50 Ω. A test equipment to the 200 Ω input
impedance during the characterization process. Using a 57.6 Ω
shunt resistor followed by a 174 Ω series resistor provides a
broadband match between the 50 Ω test equipment and the
200 Ω device impedance, as illustrated in Figure 45. The
insertion loss of this network is 11.5 dB.
02710-045
57.6Ω
174Ω
57.6Ω
174Ω
AD8367
Figure 45. Characterization Test Setup
AD8367
Rev. A | Page 21 of 24
OUTLINE DIMENSIONS
4.50
4.40
4.30
14 8
71
6.40
BSC
PIN 1
5.10
5.00
4.90
0.65
BSC
SEATING
PLANE
0.15
0.05 0.30
0.19
1.20
MAX
1.05
1.00
0.80 0.20
0.09 8°
0°
0.75
0.60
0.45
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153AB-1
Figure 46. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimension shown millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD8367ARU −40°C to +85°C 14-Lead TSSOP, Tube RU-14
AD8367ARU-REEL-7 −40°C to +85°C 14-Lead TSSOP, 7" Tape and Reel RU-14
AD8367ARUZ1−40°C to +85°C 14-Lead TSSOP, Tube RU-14
AD8367ARUZ-RL71−40°C to +85°C 14-Lead TSSOP, 7" Tape and Reel RU-14
AD8367-EVAL Evaluation Board
1 Z = Pb-free part.
AD8367
Rev. A | Page 22 of 24
NOTES
AD8367
Rev. A | Page 23 of 24
NOTES
AD8367
Rev. A | Page 24 of 24
NOTES
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C02710–0–7/05(A)
