MAX1224ETC+T - Maxim Integrated

General Description

The MAX1224/MAX1225 low-power, high-speed, serial-

output, 12-bit, analog-to-digital converters (ADCs) oper-

ate at up to 1.5Msps. These devices feature true-differen-

tial inputs, offering better noise immunity, distortion

improvements, and a wider dynamic range over single-

ended inputs. A standard SPI™/QSPI™/MICROWIRE™

interface provides the clock necessary for conversion.

These devices easily interface with standard digital signal

processor (DSP) synchronous serial interfaces.

The MAX1224/MAX1225 operate from a single +2.7V to

+3.6V supply voltage and require an external reference.

The MAX1224 has a unipolar analog input, while the

MAX1225 has a bipolar analog input. These devices fea-

ture a partial power-down mode and a full power-down

mode for use between conversions, which lower the sup-

ply current to 1mA (typ) and 1µA (max), respectively. Also

featured is a separate power-supply input (VL), which

allows direct interfacing to +1.8V to VDD digital logic. The

fast conversion speed, low-power dissipation, good AC

performance, and DC accuracy (±1.5 LSB INL) make the

MAX1224/MAX1225 ideal for industrial process control,

motor control, and base-station applications.

The MAX1224/MAX1225 come in a 12-pin TQFN pack-

age, and are available in the extended (-40°C to +85°C)

temperature range.

Applications

Data Acquisition Communications

Bill Validation Portable Instruments

Motor Control

Features

♦1.5Msps Sampling Rate

♦Only 18mW (typ) Power Dissipation

♦Only 1µA (max) Shutdown Current

♦High-Speed, SPI-Compatible, 3-Wire Serial Interface

♦69dB S/(N + D) at 525kHz Input Frequency

♦Internal True-Differential Track/Hold (T/H)

♦External Reference

♦No Pipeline Delays

♦Small 12-Pin TQFN Package

MAX1224/MAX1225

1.5Msps, Single-Supply, Low-Power,

True-Differential, 12-Bit ADCs

________________________________________________________________

Maxim Integrated Products

AIN+

N.C.

SCLK

N.C.

GND

2REF

7RGND

CNVST

DOUT

MAX1224

MAX1225

AIN-

VDD

TQFN

TOP VIEW

PART TEMP RANGE PIN-

PACKAGE INPUT

MAX1224ETC+T -40°C to +85°C 12 TQFN Unipolar

MAX1225ETC+T -40°C to +85°C 12 TQFN Bipolar

Pin Configuration

Ordering Information

MAX1224

MAX1225

DOUT

AIN+

REF

4.7μF

10μF10μF

+2.7V TO +3.6V

0.01μF

+1.8V TO VDD

AIN-

REF

VDD

DIFFERENTIAL

INPUT

VOLTAGE

RGND

GND

CNVST

SCLK

μC/DSP

Typical Operating Circuit

19-3271; Rev 1; 4/09

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

SPI/QSPI are trademarks of Motorola, Inc.

MICROWIRE is a trademark of National Semiconductor Corp.

Denotes a lead(Pb)-free/RoHS-compliant package.

T = Tape and reel.

MAX1224/MAX1225

1.5Msps, Single-Supply, Low-Power,

True-Differential, 12-Bit ADCs

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VDD = +2.7V to +3.6V, VL= VDD, VREF = 2.048V, fSCLK = 24.0MHz, 50% duty cycle, TA= -40°C to +85°C, unless otherwise noted.

Typical values are at VDD = 3V and TA= +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

VDD to GND..............................................................-0.3V to +6V

VLto GND ................-0.3V to the lower of (VDD + 0.3V) and +6V

Digital Inputs

to GND .................-0.3V to the lower of (VDD + 0.3V) and +6V

Digital Output

to GND....................-0.3V to the lower of (VL+ 0.3V) and +6V

Analog Inputs and

REF to GND..........-0.3V to the lower of (VDD + 0.3V) and +6V

RGND to GND .......................................................-0.3V to +0.3V

Maximum Current into Any Pin............................................50mA

Continuous Power Dissipation (TA= +70°C)

12-Pin TQFN (derate 16.9mW/°C above +70°C) ......1349mW

Operating Temperature Range

MAX122_ ETC.................................................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-60°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DC ACCURACY

Resolution 12 Bits

Relative Accuracy INL (Note 1) -1.5 +1.5 LSB

Differential Nonlinearity DNL Guaranteed no missing codes (Note 2) -1.0 +1.5 LSB

Offset Error ±8.0 LSB

Offset-Error Temperature

Coefficient ±1 ppm/°C

Gain Error Offset nulled ±6.0 LSB

Gain Temperature Coefficient ±2 ppm/°C

DYNAMIC SPECIFICATIONS (fIN = 525kHz sine wave, VIN = VREF, unless otherwise noted.)

Signal-to-Noise Plus Distortion SINAD 66 69 dB

Total Harmonic Distortion THD Up to the 5th harmonic -80 -76 dB

Spurious-Free Dynamic Range SFDR -83 -76 dB

Intermodulation Distortion IMD fIN1 = 250kHz, fIN2 = 300kHz -78 dB

Full-Power Bandwidth -3dB point 15 MHz

Full-Linear Bandwidth S/(N + D) > 68dB, single ended 1.2 MHz

CONVERSION RATE

Minimum Conversion Time tCONV (Note 3) 0.667 μs

Maximum Throughput Rate 1.5 Msps

Minimum Throughput Rate (Note 4) 10 ksp s

Track-and-Hold Acquisition Time tACQ (Note 5) 125 ns

Aperture Delay 5 ns

Aperture Jitter (Note 6) 30 ps

External Clock Frequency fSCLK (Note 7) 24.0 MHz

MAX1224/MAX1225

1.5Msps, Single-Supply, Low-Power,

True-Differential, 12-Bit ADCs

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(VDD = +2.7V to +3.6V, VL= VDD, VREF = 2.048V, fSCLK = 24.0MHz, 50% duty cycle, TA= -40°C to +85°C, unless otherwise noted.

Typical values are at VDD = 3V and TA= +25°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

ANALOG INPUTS (AIN+, AIN-)

AIN+ - AIN-, MAX1224 0 VREF

Differential Input Voltage Range VIN AIN+ - AIN-, MAX1225 -VREF / 2 +VREF / 2 V

Absolute Input Voltage Range 0 VDD V

DC Leakage Current ±1 μA

Input Capacitance Per input pin 16 pF

Input Current (Average) Time averaged at maximum throughput rate 50 μA

REFERENCE INPUT (REF)

REF Input Voltage Range VREF 1.0 VDD +

50mV V

Input Capacitance 20 pF

DC Leakage Current ±1 μA

Input Current (Average) Time averaged at maximum throughput rate 200 μA

DIGITAL INPUTS (SCLK, CNVST)

Input-Voltage Low VIL 0.3 x VL V

Input-Voltage High VIH 0.7 x VL V

Input Leakage Current IIL 0.05 ±10 μA

DIGITAL OUTPUT (DOUT)

Output Load Capacitance COUT For stated timing performance 30 pF

Output-Voltage Low VOL I

SINK = 5mA, VL 1.8V 0.4 V

Output-Voltage High VOH I

SOURCE = 1mA, VL 1.8V VL - 0.5V V

Output Leakage Current IOL Output high impedance ±0.2 ±10 μA

POWER REQUIREMENTS

Analog Supply Voltage VDD 2.7 3.6 V

Digital Supply Voltage VL 1.8 VDD V

Static, fSCLK = 24.0MHz 5 7

Static, no SCLK 4 5

Analog Supply Current,

Normal Mode IDD

Operational, 1.5Msps 6 8

fSCLK = 24.0MHz 1

Analog Supply Current,

Partial Power-Down Mode IDD No SCLK 1

fSCLK = 24.0MHz 1

Analog Supply Current,

Full Power-Down Mode IDD No SCLK 0.3 1 μA

Operational, full-scale input at 1.5Msps 0.3 1

Static, fSCLK = 24.0MHz 0.15 0.5

Partial/full power-down mode,

fSCLK = 24.0MHz 0.1 0.3

Digital Supply Current (Note 8)

Static, no SCLK, all modes 0.1 1 μA

Positive-Supply Rejection PSR Full-scale input, 3V +20%, -10% ±0.2 ±3.0 mV

MAX1224/MAX1225

1.5Msps, Single-Supply, Low-Power,

True-Differential, 12-Bit ADCs

4 _______________________________________________________________________________________

Note 1: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and the offset

error have been nulled.

Note 2: No missing codes over temperature.

Note 3: Conversion time is defined as the number of clock cycles (16) multiplied by the clock period.

Note 4: At sample rates below 10ksps, the input full-linear bandwidth is reduced to 5kHz.

Note 5: The listed value of three SCLK cycles is given for full-speed continuous conversions. Acquisition time begins on the 14th ris-

ing edge of SCLK and terminates on the next falling edge of CNVST. The IC idles in acquisition mode between conversions.

Note 6: Undersampling at the maximum signal bandwidth requires the minimum jitter spec for SINAD performance.

Note 7: 1.5Msps operation guaranteed for VL> 2.7V. See the

Typical Operating Characteristics

section for recommended sampling

speeds for VL< 2.7V.

Note 8: Digital supply current is measured with the VIH level equal to VL, and the VIL level equal to GND.

TIMING CHARACTERISTICS

(VDD = +2.7V to +3.6V, VL= VDD, VREF = 2.048V, fSCLK = 24.0MHz, 50% duty cycle, TA= -40°C to +85°C, unless otherwise noted.

Typical values are at VDD = 3V and TA= +25°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

VL = 2.7V to VDD 18.7

SCLK Pulse-Width High tCH VL = 1.8V to VDD, minimum recommended

(Note 7) 22.5 ns

VL = 2.7V to VDD 18.7

SCLK Pulse-Width Low tCL VL = 1.8V to VDD, minimum recommended

(Note 7) 22.5 ns

CL = 30pF, VL = 2.7V to VDD 17

SCLK Rise to DOUT Transition tDOUT CL = 30pF, VL = 1.8V to VDD 24

DOUT Remains Valid After SCLK

Rise tDHOLD V

L = 1.8V to VDD 4 ns

CNVST Fall to SCLK Fall tSETUP V

L = 1.8V to VDD 10 ns

CNVST Pulse Width tCSW V

L = 1.8V to VDD 20 ns

Power-Up Time; Full Power-Down tPWR-UP 2 ms

Restart Time; Partial Power-Down tRCV 16 Cycles

CNVST

SCLK

DOUT

tDHOLD

tDOUT

tSETUP

tCSW

tCL tCH

Figure 1. Detailed Serial-Interface Timing

GND

6kΩCL

DOUT DOUT

GND

a) HIGH-Z TO VOH, VOL TO VOH,

AND VOH TO HIGH-Z

b) HIGH-Z TO VOL, VOH TO VOL,

AND VOL TO HIGH-Z

6kΩ

Figure 2. Load Circuits for Enable/Disable Times

MAX1224/MAX1225

1.5Msps, Single-Supply, Low-Power,

True-Differential, 12-Bit ADCs

_______________________________________________________________________________________

Typical Operating Characteristics

(VDD = +3V, VL= VDD, VREF = 2.048V, fSCLK = 24MHz, fSAMPLE = 1.5Msps, TA= -40°C to +85°C, unless otherwise noted. Typical

values are measured at TA= +25°C)

MAXIMUM RECOMMENDED fSCLK vs. VL

MAX1224/25 toc01

VL (V)

fSCLK (MHz)

3.33.02.72.42.1

1.8 3.6

INTEGRAL NONLINEARITY

vs. DIGITAL OUTPUT CODE (MAX1224)

MAX1224/25 toc02

DIGITAL OUTPUT CODE

INL (LSB)

307220481024

-0.75

-0.50

-0.25

0.25

0.50

0.75

1.00

-1.00

0 4096

INTEGRAL NONLINEARITY

vs. DIGITAL OUTPUT CODE (MAX1225)

MAX1224/25 toc03

DIGITAL OUTPUT CODE

INL (LSB)

10240-1024

-0.75

-0.50

-0.25

0.25

0.50

0.75

1.00

-1.00

-2048 2048

DIFFERENTIAL NONLINEARITY

vs. DIGITAL OUTPUT CODE (MAX1224)

MAX1224/25 toc04

DIGITAL OUTPUT CODE

DNL (LSB)

307220481024

-0.75

-0.50

-0.25

0.25

0.50

0.75

1.00

-1.00

0 4096

DIFFERENTIAL NONLINEARITY

vs. DIGITAL OUTPUT CODE (MAX1225)

MAX1224/25 toc05

DIGITAL OUTPUT CODE

DNL (LSB)

10240-1024

-0.75

-0.50

-0.25

0.25

0.50

0.75

1.00

-1.00

-2048 2048

OFFSET ERROR

vs. TEMPERATURE (MAX1224)

MAX1224/25 toc06

TEMPERATURE (°C)

OFFSET ERROR (LSB)

603510-15

-3

-2

-1

-4

-40 85

OFFSET ERROR

vs. TEMPERATURE (MAX1225)

MAX1224/25 toc07

TEMPERATURE (°C)

OFFSET ERROR (LSB)

603510-15

-1

-2

-40 85

GAIN ERROR

vs. TEMPERATURE (MAX1224)

MAX1224/25 toc08

TEMPERATURE (°C)

GAIN ERROR (LSB)

603510-15

-1

-2

-40 85

GAIN ERROR

vs. TEMPERATURE (MAX1225)

MAX1224/25 toc09

TEMPERATURE (°C)

GAIN ERROR (LSB)

603510-15

-1

-2

-40 85

Typical Operating Characteristics (continued)

(VDD = +3V, VL= VDD, VREF = 2.048V, fSCLK = 24MHz, fSAMPLE = 1.5Msps, TA= -40°C to +85°C, unless otherwise noted. Typical

values are measured at TA= +25°C)

MAX1224/MAX1225

1.5Msps, Single-Supply, Low-Power,

True-Differential, 12-Bit ADCs

6 _______________________________________________________________________________________

DYNAMIC PERFORMANCE

vs. INPUT FREQUENCY (MAX1224)

MAX1224/25 toc10

ANALOG INPUT FREQUENCY (kHz)

DYNAMIC PERFORMANCE (dB)

400300200

69.25

69.50

69.75

70.00

69.00

100 500

SNR

SINAD

DYNAMIC PERFORMANCE

vs. INPUT FREQUENCY (MAX1225)

MAX1224/25 toc11

ANALOG INPUT FREQUENCY (kHz)

DYNAMIC PERFORMANCE (dB)

400300200

68.75

69.00

69.25

69.50

68.50

100 500

SNR

SINAD

THD vs. INPUT FREQUENCY

MAX1224/25 toc12

ANALOG INPUT FREQUENCY (kHz)

THD (dB)

400300200

-90

-88

-86

-84

-82

-92

100 500

MAX1224

MAX1225

SFDR vs. INPUT FREQUENCY

MAX1224/25 toc13

ANALOG INPUT FREQUENCY (kHz)

SFDR (dB)

400300200

100 500

MAX1225

MAX1224

FFT PLOT (MAX1224)

MAX1224/25 toc14

ANALOG INPUT FREQUENCY (kHz)

AMPLITUDE (dB)

625500375250125

-120

-100

-80

-60

-40

-20

-140

0 750

fIN = 500kHz

SINAD = 69.4dB

SNR = 69.6dB

THD = -83.9dB

SFDR = 84.3dB

FFT PLOT (MAX1225)

MAX1224/25 toc15

ANALOG INPUT FREQUENCY (kHz)

AMPLITUDE (dB)

625500375250125

-120

-100

-80

-60

-40

-20

-140

0 750

fIN = 500kHz

SINAD = 69.2dB

SNR = 69.3dB

THD = -90.5dB

SFDR = 88.15dB

MAX1224/MAX1225

TOTAL HARMONIC DISTORTION

vs. SOURCE IMPEDANCE

MAX1224/25 toc16

SOURCE IMPEDANCE (Ω)

THD (dB)

100

-90

-80

-70

-60

-50

-100

10 1000

fIN = 500kHz

fIN = 100kHz

TWO-TONE IMD PLOT (MAX1224)

MAX1224/25 toc17

ANALOG INPUT FREQUENCY (kHz)

AMPLITUDE (dB)

625500375250125

-120

-100

-80

-60

-40

-20

-140

0 750

fIN1 = 250.102kHz

fIN2 = 299.966kHz

IMD = -88.4dB

fIN1 fIN2

TWO-TONE IMD PLOT (MAX1225)

MAX1224/25 toc18

ANALOG INPUT FREQUENCY (kHz)

AMPLITUDE (dB)

625500375250125

-120

-100

-80

-60

-40

-20

-140

0 750

fIN1 = 250.102kHz

fIN2 = 299.966kHz

IMD = -85.2dB

fIN1 fIN2

1.5Msps, Single-Supply, Low-Power,

True-Differential, 12-Bit ADCs

_______________________________________________________________________________________

VDD/VL FULL POWER-DOWN

SUPPLY CURRENT vs. TEMPERATURE

MAX1224/25 toc19

TEMPERATURE (°C)

VDD/VL SUPPLY CURRENT (μA)

603510-15

0.2

0.4

0.6

0.8

1.0

-40 85

VDD, fSCLK = 24MHz

VDD, NO SCLK

VL, NO SCLK

VL PARTIAL/FULL POWER-DOWN

SUPPLY CURRENT vs. TEMPERATURE

MAX1224/25 toc20

TEMPERATURE (°C)

VL SUPPLY CURRENT (μA)

603510-15

100

-40 85

VL = 3V, fSCLK = 24MHz

VL = 1.8V, fSCLK = 24MHz

VDD SUPPLY CURRENT vs. TEMPERATURE

MAX1224/25 toc21

TEMPERATURE (°C)

VDD SUPPLY CURRENT (mA)

603510-15

-40 85

CONVERSION

PARTIAL POWER-DOWN

Typical Operating Characteristics (continued)

(VDD = +3V, VL= VDD, VREF = 2.048V, fSCLK = 24MHz, fSAMPLE = 1.5Msps, TA= -40°C to +85°C, unless otherwise noted. Typical

values are measured at TA= +25°C)

MAX1224/MAX1225

1.5Msps, Single-Supply, Low-Power,

True-Differential, 12-Bit ADCs

8 _______________________________________________________________________________________

Pin Description

PIN NAME FUNCTION

1 AIN- Negative Analog Input

2 REF External Reference Voltage Input. VREF sets the analog input range. Bypass REF with a 0.01µF

capacitor and a 4.7µF capacitor to RGND.

3 RGND Reference Ground. Connect RGND to GND.

DD Positive Analog Supply Voltage (+2.7V to +3.6V). Bypass VDD with a 0.01µF capacitor and a 10µF

capacitor to GND.

5, 11 N.C. No Connection

6 GND Ground. GND is internally connected to EP.

LPositive Logic Supply Voltage (1.8V to VDD). Bypass VL with a 0.01µF capacitor and a 10µF capacitor

to GND.

8 DOUT Serial Data Output. Data is clocked out on the rising edge of SCLK.

9 CNVST Convert Start. Forcing CNVST high prepares the part for a conversion. Conversion begins on the

falling edge of CNVST. The sampling instant is defined by the falling edge of CNVST.

10 SCLK Serial Clock Input. Clocks data out of the serial interface. SCLK also sets the conversion speed.

12 AIN+ Positive Analog Input

— EP Exposed Paddle. EP is internally connected to GND.

Typical Operating Characteristics (continued)

(VDD = +3V, VL= VDD, VREF = 2.048V, fSCLK = 24MHz, fSAMPLE = 1.5Msps, TA= -40°C to +85°C, unless otherwise noted. Typical

values are measured at TA= +25°C)

VDD SUPPLY CURRENT

vs. CONVERSION RATE

MAX1224/25 toc22

fSAMPLE (kHz)

VDD SUPPLY CURRENT (mA)

12501000750500250

0 1500

VL SUPPLY CURRENT vs. TEMPERATURE

MAX1224/25 toc23

TEMPERATURE (°C)

VL SUPPLY CURRENT (mA)

603510-15

0.2

0.3

0.5

0.4

0.1

-40 85

CONVERSION, VL = 1.8V

CONVERSION, VL = 3V

VL SUPPLY CURRENT

vs. CONVERSION RATE

MAX1224/25 toc24

fSAMPLE (kHz)

VL SUPPLY CURRENT (μA)

1250100750500250

100

150

200

250

0 1500

VL = 3V

VL = 1.8V

MAX1224/MAX1225

1.5Msps, Single-Supply, Low-Power,

True-Differential, 12-Bit ADCs

_______________________________________________________________________________________ 9

Detailed Description

The MAX1224/MAX1225 use an input T/H and succes-

sive-approximation register (SAR) circuitry to convert

an analog input signal to a digital 12-bit output. The

serial interface requires only three digital lines (SCLK,

CNVST, and DOUT) and provides easy interfacing to

microprocessors (µPs) and DSPs. Figure 3 shows the

simplified internal structure for the MAX1224/MAX1225.

True-Differential Analog Input T/H

The equivalent circuit of Figure 4 shows the input archi-

tecture of the MAX1224/MAX1225, which is composed

of a T/H, a comparator, and a switched-capacitor digi-

tal-to-analog converter (DAC). The T/H enters its track-

ing mode on the 14th SCLK rising edge of the previous

conversion. Upon power-up, the T/H enters its tracking

mode immediately. The positive input capacitor is con-

nected to AIN+. The negative input capacitor is con-

nected to AIN-. The T/H enters its hold mode on the

falling edge of CNVST and the difference between the

sampled positive and negative input voltages is con-

verted. The time required for the T/H to acquire an input

signal is determined by how quickly its input capaci-

tance is charged. If the input signal’s source imped-

ance is high, the acquisition time lengthens. The

acquisition time, tACQ, is the minimum time needed for

the signal to be acquired. It is calculated by the follow-

ing equation:

tACQ ≥9 x (RS + RIN) x 16pF

where RIN = 200Ω, and RS is the source impedance of

the input signal.

Note: tACQ is never less than 125ns, and any source

impedance below 12Ωdoes not significantly affect the

ADC’s AC performance.

Input Bandwidth

The ADC’s input-tracking circuitry has a 15MHz small-

signal bandwidth, making it possible to digitize high-

speed transient events and measure periodic

signals with bandwidths exceeding the ADC’s sam-

pling rate by using undersampling techniques. To

avoid high-frequency signals being aliased into the fre-

quency band of interest, anti-alias filtering is recom-

mended.

Analog Input Protection

Internal protection diodes that clamp the analog input

to VDD and GND allow the analog input pins to swing

from GND - 0.3V to VDD + 0.3V without damage. Both

inputs must not exceed VDD or be lower than GND for

accurate conversions.

RGND

AIN+

GND

DOUT

SCLK

CNVST

CONTROL

LOGIC AND

TIMING

AIN-

VDD

REF

12-BIT

SAR

ADC

MAX1224

MAX1225

T/H OUTPUT

BUFFER

Figure 3. Functional Diagram

CIN+ RIN+

RIN-

CIN-

VAZ

AIN+

AIN-

CONTROL

LOGIC

CAPACITIVE

DAC

COMP

ACQUISITION MODE

CIN+ RIN+

RIN-

CIN-

VAZ

AIN+

AIN-

CONTROL

LOGIC

CAPACITIVE

DAC

COMP

HOLD/CONVERSION MODE

Figure 4. Equivalent Input Circuit

MAX1224/MAX1225

Serial Interface

Initialization After Power-Up

and Starting a Conversion

Upon initial power-up, the MAX1224/MAX1225 require a

complete conversion cycle to initialize the internal cali-

bration. Following this initial conversion, the part is ready

for normal operation. This initialization is only required

after a hardware power-up sequence and is not required

after exiting partial or full power-down mode.

To start a conversion, pull CNVST low. At CNVST’s

falling edge, the T/H enters its hold mode and a conver-

sion is initiated. SCLK runs the conversion and the data

can then be shifted out serially on DOUT.

Timing and Control

Conversion-start and data-read operations are con-

trolled by the CNVST and SCLK digital inputs. Figures 1

and 5 show timing diagrams, which outline the serial-

interface operation.

A CNVST falling edge initiates a conversion sequence:

the T/H stage holds the input voltage, the ADC begins

to convert, and DOUT changes from high impedance to

logic low. SCLK is used to drive the conversion

process, and it shifts data out as each bit of the conver-

sion is determined.

SCLK begins shifting out the data after the 4th rising

edge of SCLK. DOUT transitions tDOUT after each

SCLK’s rising edge and remains valid 4ns (tDHOLD)

after the next rising edge. The 4th rising clock edge

produces the MSB of the conversion at DOUT, and the

MSB remains valid 4ns after the 5th rising edge. Since

there are 12 data bits and 3 leading zeros, at least 16

rising clock edges are needed to shift out these bits.

For continuous operation, pull CNVST high between the

14th and the 16th SCLK rising edges. If CNVST stays

low after the falling edge of the 16th SCLK cycle, the

DOUT line goes to a high-impedance state on either

CNVST’s rising edge or the next SCLK’s rising edge.

1.5Msps, Single-Supply, Low-Power,

True-Differential, 12-Bit ADCs

10 ______________________________________________________________________________________

DOUT

MODE

SCLK

CNVST

DOUT GOES HIGH IMPEDANCE ONCE CNVST GOES HIGH

CNVST MUST GO HIGH AFTER THE 3RD BUT BEFORE THE 14TH SCLK RISING EDGE

ONE 8-BIT TRANSFER

1ST SCLK RISING EDGE

PPD

0 0 0 D11 D10 D9 D8 D7

NORMAL

Figure 6. SPI Interface—Partial Power-Down Mode

Figure 5. Interface-Timing Sequence

tACQUIRE

CONTINUOUS-CONVERSION

SELECTION WINDOW

CNVST

tSETUP

DOUT

SCLK 41412 83 16

HIGH IMPEDANCE D1D4D6 D5D9 D8 D7D11 D10

POWER-MODE SELECTION WINDOW

D0D2D3

Partial Power-Down and

Full Power-Down Modes

Power consumption can be reduced significantly by plac-

ing the MAX1224/MAX1225 in either partial power-down

mode or full power-down mode. Partial power-down

mode is ideal for infrequent data sampling and fast wake-

up time applications. Pull CNVST high after the 3rd SCLK

rising edge and before the 14th SCLK rising edge to

enter and stay in partial power-down mode (see Figure

6). This reduces the supply current to 1mA. Drive CNVST

low and allow at least 14 SCLK cycles to elapse before

driving CNVST high to exit partial power-down mode.

Full power-down mode is ideal for infrequent data sam-

pling and very low supply-current applications. The

MAX1224/MAX1225 have to be in partial power-down

mode in order to enter full power-down mode. Perform

the SCLK/CNVST sequence described above to enter

partial power-down mode. Then repeat the same

sequence to enter full power-down mode (see Figure

7). Drive CNVST low, and allow at least 14 SCLK cycles

to elapse before driving CNVST high to exit full power-

down mode. In partial/full power-down mode, maintain

a logic low or a logic high on SCLK to minimize power

consumption.

Transfer Function

Figure 8 shows the unipolar transfer function for the

MAX1224. Figure 9 shows the bipolar transfer function for

the MAX1225. The MAX1224 output is straight binary,

while the MAX1225 output is two’s complement.

Applications Information

External Reference

An external reference is required for the MAX1224/

MAX1225. Use a 4.7µF and 0.01µF bypass capacitor on

the REF pin for best performance. The reference input

structure allows a voltage range of +1V to VDD.

How to Start a Conversion

An analog-to-digital conversion is initiated by CNVST and

clocked by SCLK, and the resulting data is clocked out

on DOUT by SCLK. With SCLK idling high or low, a falling

edge on CNVST begins a conversion. This causes the

analog input stage to transition from track to hold mode,

and for DOUT to transition from high impedance to being

actively driven low. A total of 16 SCLK cycles are required

to complete a normal conversion. If CNVST is low during

the 16th falling SCLK edge, DOUT returns to high imped-

ance on the next rising edge of CNVST or SCLK,

enabling the serial interface to be shared by multiple

devices. If CNVST returns high after the 14th, but before

the 16th SCLK rising edge, DOUT remains active so con-

tinuous conversions can be sustained. The highest

throughput is achieved when performing continuous con-

versions. Figure 10 illustrates a conversion using a typical

serial interface.

MAX1224/MAX1225

1.5Msps, Single-Supply, Low-Power,

True-Differential, 12-Bit ADCs

______________________________________________________________________________________ 11

Figure 7. SPI Interface—Full Power-Down Mode

1ST SCLK RISING EDGE 1ST SCLK RISING EDGE

0 0 0 D11 D10 D9 D8 D7

DOUT

MODE

SCLK

CNVST

0000000

FPDRECOVERYPPDNORMAL

DOUT ENTERS TRI-STATE ONCE CNVST GOES HIGH

EXECUTE PARTIAL POWER-DOWN TWICE

FIRST 8-BIT TRANSFER SECOND 8-BIT TRANSFER

MAX1224/MAX1225

Connection to

Standard Interfaces

The MAX1224/MAX1225 serial interface is fully compati-

ble with SPI/QSPI and MICROWIRE (see Figure 11). If a

serial interface is available, set the CPU’s serial interface

in master mode so the CPU generates the serial clock.

Choose a clock frequency up to 28.8MHz.

SPI and MICROWIRE

When using SPI or MICROWIRE, the MAX1224/MAX1225

are compatible with all four modes programmed with the

CPHA and CPOL bits in the SPI or MICROWIRE control

DOUT goes low, indicating a conversion is in progress.

Two consecutive 1-byte reads are required to get the full

12 bits from the ADC. DOUT transitions on SCLK rising

edges. DOUT is guaranteed to be valid tDOUT later and

remains valid until tDHOLD after the following SCLK rising

edge. When using CPOL = 0 and CPHA = 0, or CPOL =

1 and CPHA = 1, the data is clocked into the µP on the

following rising edge. When using CPOL = 0 and CPHA

= 1, or CPOL = 1 and CPHA = 0, the data is clocked

into the µP on the next falling edge. See Figure 11 for

connections and Figures 12 and 13 for timing. See the

Timing Characteristics

section to determine the best

mode to use.

QSPI

Unlike SPI, which requires two 1-byte reads to acquire

the 12 bits of data from the ADC, QSPI allows the mini-

mum number of clock cycles necessary to clock in the

data. The MAX1224/MAX1225 require 16 clock cycles

from the µP to clock out the 12 bits of data. Figure 14

shows a transfer using CPOL = 1 and CPHA = 1. The

conversion result contains three zeros, followed by the

12 data bits, and a trailing zero with the data in MSB-

first format.

DSP Interface to the TMS320C54_

The MAX1224/MAX1225 can be directly connected

to the TMS320C54_ family of DSPs from Texas

Instruments, Inc. Set the DSP to generate its own

clocks or use external clock signals. Use either the

standard or buffered serial port. Figure 15 shows the

simplest interface between the MAX1224/MAX1225 and

the TMS320C54_, where the transmit serial clock

(CLKX) drives the receive serial clock (CLKR) and

SCLK, and the transmit frame sync (FSX) drives the

receive frame sync (FSR) and CNVST.

For continuous conversion, set the serial port to trans-

mit a clock, and pulse the frame sync signal for a clock

period before data transmission. The serial-port config-

uration (SPC) register should be set up with internal

1.5Msps, Single-Supply, Low-Power,

True-Differential, 12-Bit ADCs

12 ______________________________________________________________________________________

OUTPUT CODE

FULL-SCALE

TRANSITION

111...111

12 3

0FS

FS - 3/2 LSB

FS = VREF

DIFFERENTIAL INPUT

VOLTAGE (LSB)

1 LSB = VREF

4096

111...110

111...101

000...011

000...010

000...001

000...000

ZS = 0

Figure 8. Unipolar Transfer Function (MAX1224 Only)

OUTPUT CODE

FULL-SCALE

TRANSITION

FS0-FS

FS - 3/2 LSB

DIFFERENTIAL INPUT

VOLTAGE (LSB)

011...111

011...110

000...010

000...001

000...000

111...111

111...110

111...101

100...001

100...000

1 LSB = VREF

4096

FS = VREF

- FS = -VREF

ZS = 0

Figure 9. Bipolar Transfer Function (MAX1225 Only)

MAX1224/MAX1225

1.5Msps, Single-Supply, Low-Power,

True-Differential, 12-Bit ADCs

______________________________________________________________________________________ 13

Figure 11. Common Serial-Interface Connections to the MAX1224/MAX1225

0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0

DOUT

SCLK

CNVST

11614

Figure 10. Continuous Conversion with Burst/Continuous Clock

MAX1224

MAX1225

+3V TO +5V

CNVST

SCLK

DOUT

I/O

SCK

MISO

A) SPI

MAX1224

MAX1225

+3V TO +5V

CNVST

SCLK

DOUT

SCK

MISO

B) QSPI

MAX1224

MAX1225

CNVST

SCLK

DOUT

I/O

C) MICROWIRE

frame sync (TXM = 1), CLKX driven by an on-chip clock

source (MCM = 1), burst mode (FSM = 1), and 16-bit

word length (FO = 0).

This setup allows continuous conversions provided that

the data-transmit register (DXR) and the data-receive

Alternatively, autobuffering can be enabled when using

the buffered serial port to execute conversions and

read the data without CPU intervention. Connect the VL

pin to the TMS320C54_ supply voltage when the

MAX1224/MAX1225 are operating with an analog sup-

ply voltage higher than the DSP supply voltage. The

word length can be set to 8 bits with FO = 1 to imple-

ment the power-down modes. The CNVST pin must idle

high to remain in either power-down state.

Another method of connecting the MAX1224/MAX1225

to the TMS320C54_ is to generate the clock signals

external to either device. This connection is shown in

Figure 16, where serial clock (CLOCK) drives the

CLKR, and SCLK and the convert signal (CONVERT)

drive the FSR and CNVST.

The serial port must be set up to accept an external

receive-clock and external receive-frame sync.

MAX1224/MAX1225

1.5Msps, Single-Supply, Low-Power,

True-Differential, 12-Bit ADCs

14 ______________________________________________________________________________________

SCLK

DOUT

916

D11 D10 D8 D7 D6 D5 D4 D3

HIGH-Z HIGH-Z

CNVST

D1 D0

Figure 13. SPI/MICROWIRE Serial-Interface Timing—Continuous Conversion (CPOL = CPHA = 0), (CPOL = CPHA = 1)

0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0

DOUT

SCLK

CNVST

14 16

Figure 12. SPI/MICROWIRE Serial-Interface Timing—Single Conversion (CPOL = CPHA = 0), (CPOL = CPHA = 1)

Figure 14. QSPI Serial-Interface Timing—Single Conversion (CPOL = 1, CPHA = 1)

SCLK

DOUT

CNVST

D11 D10 D6D7D8 D5 D4 D3 D2

HIGH-Z

MAX1224/MAX1225

1.5Msps, Single-Supply, Low-Power,

True-Differential, 12-Bit ADCs

______________________________________________________________________________________ 15

The SPC register should be written as follows:

TXM = 0, external frame sync

MCM = 0, CLKX is taken from the CLKX pin

FSM = 1, burst mode

FO = 0, data transmitted/received as 16-bit words

This setup allows continuous conversion, provided that

the DRR is serviced before the next conversion.

Alternatively, autobuffering can be enabled when using

the buffered serial port to read the data without CPU

intervention. Connect the VL pin to the TMS320C54_

supply voltage when the MAX1224/MAX1225 are oper-

ating with an analog supply voltage higher than the

DSP supply voltage.

The MAX1224/MAX1225 can also be connected to the

TMS320C54_ by using the data transmit (DX) pin to

drive CNVST and the CLKX generated internally to

drive SCLK. A pullup resistor is required on the CNVST

signal to keep it high when DX goes high impedance

and 0001hex should be written to the DXR continuously

for continuous conversions. The power-down modes

may be entered by writing 00FFhex to the DXR (see

Figures 17 and 18).

DSP Interface to the ADSP21_ _ _

The MAX1224/MAX1225 can be directly connected to

the ADSP21_ _ _ family of DSPs from Analog Devices,

Inc. Figure 19 shows the direct connection of the

MAX1224/MAX1225 to the ADSP21_ _ _. There are two

modes of operation that can be programmed to interface

with the MAX1224/MAX1225. For continuous conver-

sions, idle CNVST low and pulse it high for one clock

cycle during the LSB of the previous transmitted word.

The ADSP21_ _ _ STCTL and SRCTL registers should be

configured for early framing (LAFR = 0) and for an

active-high frame (LTFS = 0, LRFS = 0) signal. In this

mode, the data-independent frame-sync bit (DITFS = 1)

can be selected to eliminate the need for writing to the

transmit-data register more than once. For single conver-

sions, idle CNVST high and pulse it low for the entire

conversion. The ADSP21_ _ _ STCTL and SRCTL regis-

ters should be configured for late framing (LAFR = 1)

and for an active-low frame (LTFS = 1, LRFS = 1) signal.

This is also the best way to enter the power-down modes

by setting the word length to 8 bits (SLEN = 1001).

Connect the VL pin to the ADSP21_ _ _ supply voltage

when the MAX1224/MAX1225 are operating with a sup-

ply voltage higher than the DSP supply voltage (see

Figures 17 and 18).

Figure 15. Interfacing to the TMS320C54_ Internal Clocks

Figure 16. Interfacing to the TMS320C54_ External Clocks

MAX1224

MAX1225

TMS320C54_

SCLK

CNVST

DOUT

DVDD

CLKR

FSR

CLKX

FSX

MAX1224

MAX1225

TMS320C54_

VLDVDD

SCLK CLKR

CNVST FSR

DOUT DR

CLOCK

CONVERT

0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0

DOUT

SCLK

CNVST

00D0

1 1

Figure 17. DSP Interface—Continuous Conversion

MAX1224/MAX1225

Layout, Grounding, and Bypassing

For best performance, use PC boards. Wire-wrap

boards are not recommended. Board layout should

ensure that digital and analog signal lines are separat-

ed from each other. Do not run analog and digital

(especially clock) lines parallel to one another, or digital

lines underneath the ADC package.

Figure 20 shows the recommended system ground

connections. Establish a single-point analog ground

(star ground point) at GND, separate from the logic

ground. Connect all other analog grounds and DGND

to this star ground point for further noise reduction. The

ground return to the power supply for this ground

should be low impedance and as short as possible for

noise-free operation.

High-frequency noise in the VDD power supply can

affect the ADC’s high-speed comparator. Bypass this

supply to the single-point analog ground with 0.01µF

and 10µF bypass capacitors. Minimize capacitor lead

lengths for best supply-noise rejection.

Definitions

Integral Nonlinearity

Integral nonlinearity (INL) is the deviation of the values on

an actual transfer function from a straight line. This

straight line can be either a best-straight-line fit or a line

drawn between the end points of the transfer function,

once offset and gain errors have been nullified. The static

linearity parameters for the MAX1224/MAX1225 are mea-

sured using the end-points method.

Differential Nonlinearity

Differential nonlinearity (DNL) is the difference between

an actual step width and the ideal value of 1 LSB. A DNL

error specification of 1 LSB or less guarantees no missing

codes and a monotonic transfer function.

Aperture Jitter

Aperture jitter (tAJ) is the sample-to-sample variation in

the time between the samples.

Aperture Delay

Aperture delay (tAD) is the time defined between the

falling edge of CNVST and the instant when an actual

sample is taken.

1.5Msps, Single-Supply, Low-Power,

True-Differential, 12-Bit ADCs

16 ______________________________________________________________________________________

MAX1224

MAX1225 ADSP21_ _ _

SCLK

CNVST

DOUT

VDDINT

RCLK

RFS

TCLK

TFS

Figure 19. Interfacing to the ADSP21_ _ _

10μF

0.1μF

10μF

0.1μF

GND VL

SUPPLIES

DGND VL

DIGITAL

CIRCUITRY

VDD GND RGND VL

MAX1224

MAX1225

Figure 20. Power-Supply Grounding Condition

0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0

DOUT

SCLK

CNVST

0 0

Figure 18. DSP Interface—Single-Conversion, Continuous/Burst Clock

Signal-to-Noise Ratio

For a waveform perfectly reconstructed from digital sam-

ples, signal-to-noise ratio (SNR) is the ratio of the full-

scale analog input (RMS value) to the RMS quantization

error (residual error). The theoretical minimum analog-to-

digital noise is caused by quantization error, and results

directly from the ADC’s resolution (N bits):

SNR = (6.02 x N + 1.76)dB

In reality, there are other noise sources besides quantiza-

tion noise, including thermal noise, reference noise, clock

jitter, etc. Therefore, SNR is computed by taking the ratio

of the RMS signal to the RMS noise, which includes all

spectral components minus the fundamental, the first five

harmonics, and the DC offset.

Signal-to-Noise Plus Distortion

Signal-to-noise plus distortion (SINAD) is the ratio of the

fundamental input frequency’s RMS amplitude to the

RMS equivalent of all other ADC output signals:

SINAD(dB) = 20 x log (SignalRMS / NoiseRMS)

Effective Number of Bits

Effective number of bits (ENOB) indicates the global

accuracy of an ADC at a specific input frequency and

sampling rate. An ideal ADC’s error consists of quantiza-

tion noise only. With an input range equal to the full-scale

range of the ADC, calculate the ENOB as follows:

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the RMS

sum of the first five harmonics of the input signal to the

fundamental itself. This is expressed as:

where V1is the fundamental amplitude, and V2

through V5are the amplitudes of the 2nd- through 5th-

order harmonics.

Spurious-Free Dynamic Range

Spurious-free dynamic range (SFDR) is the ratio of the

RMS amplitude of the fundamental (maximum signal

component) to the RMS value of the next largest distor-

tion component.

Full-Power Bandwidth

Full-power bandwidth is the frequency at which the

input signal amplitude attenuates by 3dB for a full-scale

input.

Full-Linear Bandwidth

Full-linear bandwidth is the frequency at which the sig-

nal-to-noise plus distortion (SINAD) is equal to 68dB.

Intermodulation Distortion (IMD)

Any device with nonlinearities creates distortion prod-

ucts when two sine waves at two different frequencies

(f1and f2) are input into the device. Intermodulation

distortion (IMD) is the total power of the IM2 to IM5

intermodulation products to the Nyquist frequency rela-

tive to the total input power of the two input tones, f1

and f2. The individual input tone levels are at -7dBFS.

The intermodulation products are as follows:

• 2nd-order intermodulation products (IM2): f1+ f2,

f2- f1

• 3rd-order intermodulation products (IM3): 2f1- f2,

2f2- f1, 2f1+ f2, 2f2+ f1

• 4th-order intermodulation products (IM4): 3f1- f2,

3f2- f1, 3f1+ f2, 3f2+ f1

• 5th-order intermodulation products (IM5): 3f1- 2f2,

3f2- 2f1, 3f1+ 2f2, 3f2+ 2f1

THD x VVVV

log=+++

⎛

⎝

⎜

⎞

⎠

⎟

20 2

ENOB SINAD

( .)

=−176

602

MAX1224/MAX1225

1.5Msps, Single-Supply, Low-Power,

True-Differential, 12-Bit ADCs

______________________________________________________________________________________ 17

Chip Information

TRANSISTOR COUNT: 13,016

PROCESS: BiCMOS

Package Information

For the latest package outline information and land patterns, go

to www.maxim-ic.com/packages.

PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

12 TQFN T1244+3 21-0139

MAX1224/MAX1225

1.5Msps, Single-Supply, Low-Power,

True-Differential, 12-Bit ADCs

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

Revision History

REVISION

NUMBER

REVISION

DATE DESCRIPTION PAGES

CHANGED

0 5/04 Initial release —

1 4/09 Removed commercial temperature grade parts from data sheet 1–8