AD9631/AD9632
Ultralow Distortion, Wide Bandwidth
Voltage Feedback Op Amps
a
REV. C
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Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
FEATURES
Wide Bandwidth
AD9631, G = +1
AD9632, G = +2
Small Signal
320 MHz
250 MHz
Large Signal (4 V p-p)
175 MHz
180 MHz
Ultralow Distortion (SFDR), Low Noise
–113 dBc Typ @ 1 MHz
–95 dBc Typ @ 5 MHz
–72 dBc Typ @ 20 MHz
46 dBm Third Order Intercept @ 25 MHz
7.0 nV/
÷
Hz Spectral Noise Density
High Speed
Slew Rate 1300 V/s
Settling 16 ns to 0.01%, 2 V Step
3 V to 5 V Supply Operation
17 mA Supply Current
APPLICATIONS
ADC Input Driver
Differential Amplifiers
IF/RF Amplifiers
Pulse Amplifiers
Professional Video
DAC Current to Voltage
Baseband and Video Communications
Pin Diode Receivers
Active Filters/Integrators/Log Amps
PIN CONFIGURATION
8-Lead PDIP (N)
and SOIC (R) Packages
1
2
3
4
NC
–INPUT
+INPUT
–V
S
TOP VIEW
8
7
6
5
NC
+V
S
OUTPUT
NC
AD9631/
AD9632
NC = NO CONNECT
A proprietary design architecture has produced an amplifier
that combines many of the best characteristics of both current
feedback and voltage feedback amplifiers. The AD9631 and
AD9632 exhibit exceptionally fast and accurate pulse response
(16 ns to 0.01%) as well as extremely wide small signal and large
signal bandwidth and ultralow distortion. The AD9631 achieves
–72 dBc at 20 MHz, and 320 MHz small signal and 175 MHz
large signal bandwidths.
These characteristics position the AD9631/AD9632 ideally for
driving flash as well as high resolution ADCs. Additionally, the
balanced high impedance inputs of the voltage feedback archi-
tecture allow maximum flexibility when designing active filters.
The AD9631/AD9632 are offered in the industrial (–40C to
+85C) temperature range. They are available in PDIP and SOIC.
FREQUENCY – Hz
–30
10k
HARMONIC DISTORTION – dBc
100k 1M 10M 100M
–50
–70
–90
–110
–130
SECOND HARMONIC
THIRD HARMONIC
VS = 5V
RL = 500
VO = 2V p-p
Figure 1. AD9631 Harmonic Distortion vs.
Frequency, G = +1
GENERAL DESCRIPTION
The AD9631 and AD9632 are very high speed and wide band-
width amplifiers. They are an improved performance alternative
to the AD9621 and AD9622. The AD9631 is unity gain stable.
The AD9632 is stable at gains of 2 or greater. Using a voltage
feedback architecture, the AD9631/AD9632’s exceptional settling
time, bandwidth, and low distortion meet the requirements of
many applications that previously depended on current feedback
amplifiers. Its classical op amp structure works much more
predictably in many designs.
REV. C–2–
AD9631/AD9632–SPECIFICATIONS
AD9631A AD9632A
Parameter Conditions Min Typ Max Min Typ Max Unit
DYNAMIC PERFORMANCE
Bandwidth (–3 dB)
Small Signal V
OUT
ⱕ 0.4 V p-p 220 320 180 250 MHz
Large Signal
1
V
OUT
= 4 V p-p 150 175 155 180 MHz
Bandwidth for 0.1 dB Flatness V
OUT
= 300 mV p-p
AD9631, R
F
=140 W;130 130 MHz
AD9632, R
F
=425 W
Slew Rate, Average ±V
OUT
= 4 V Step 1000 1300 1200 1500 V/ms
Rise/Fall Time V
OUT
= 0.5 V Step 1.2 1.4 ns
V
OUT
= 4 V Step 2.5 2.1 ns
Settling Time
To 0.1% V
OUT
= 2 V Step 11 11 ns
To 0.01% V
OUT
= 2 V Step 16 16 ns
HARMONIC/NOISE PERFORMANCE
Second Harmonic Distortion 2 V p-p; 20 MHz, R
L
= 100 W–64 –57 –54 –47 dBc
R
L
= 500 W–72 –65 –72 –65 dBc
Third Harmonic Distortion 2 V p-p; 20 MHz, R
L
= 100 W–76 –69 –74 –67 dBc
R
L
= 500 W–81 –74 –81 –74 dBc
Third Order Intercept 25 MHz 46 41 dBm
Noise Figure R
S
= 50 W18 14 dB
Input Voltage Noise 1 MHz to 200 MHz 7.0 4.3 nV/÷Hz
Input Current Noise 1 MHz to 200 MHz 2.5 2.0 pA/÷Hz
Average Equivalent Integrated
Input Noise Voltage 0.1 MHz to 200 MHz 100 60 mV rms
Differential Gain Error (3.58 MHz) R
L
= 150 W0.03 0.06 0.02 0.04 %
Differential Phase Error (3.58 MHz) R
L
= 150 W0.02 0.04 0.02 0.04 Degree
Phase Nonlinearity DC to 100 MHz 1.1 1.1 Degree
DC PERFORMANCE
2,
R
L
= 150 W
Input Offset Voltage
3
310 25 mV
T
MIN
–T
MAX
13 8 mV
Offset Voltage Drift ±10 ±10 mV/ⴗC
Input Bias Current 2 7 2 7 mA
T
MIN
–T
MAX
10 10 mA
Input Offset Current 0.1 3 0.1 3 mA
T
MIN
–T
MAX
55mA
Common-Mode Rejection Ratio V
CM
= ±2.5 V 70 90 70 90 dB
Open-Loop Gain V
OUT
= ±2.5 V 46 52 46 52 dB
T
MIN
–T
MAX
40 40 dB
INPUT CHARACTERISTICS
Input Resistance 500 500 kW
Input Capacitance 1.2 1.2 pF
Input Common-Mode Voltage Range ±3.4 ±3.4 V
OUTPUT CHARACTERISTICS
Output Voltage Range, R
L
= 150 W±3.2 ±3.9 ±3.2 ±3.9 V
Output Current 70 70 mA
Output Resistance 0.3 0.3 W
Short Circuit Current 240 240 mA
POWER SUPPLY
Operating Range ±3.0 ±5.0 ±6.0 ±3.0 ±5.0 ±6.0 V
Quiescent Current 17 18 16 17 mA
T
MIN
–T
MAX
21 20 mA
Power Supply Rejection Ratio T
MIN
–T
MAX
50 60 56 66 dB
NOTES
1
See Absolute Maximum Ratings and Theory of Operation sections of this data sheet.
2
Measured at A
V
= 50.
3
Measured with respect to the inverting input.
Specifications subject to change without notice.
ELECTRICAL CHARACTERISTICS
(ⴞVS = ⴞ5 V; RLOAD = 100 ⍀; AV = 1 (AD9631); AV = 2 (AD9632), unless otherwise noted.)
REV. C
AD9631/AD9632
–3–
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage (+V
S
to –V
S
) . . . . . . . . . . . . . . . . . . . . . 12.6 V
Voltage Swing ¥ Bandwidth Product . . . . . . . . . . . 550 V-MHz
Internal Power Dissipation
2
Plastic Package (N) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 W
Small Outline Package (R) . . . . . . . . . . . . . . . . . . . . . . 0.9 W
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ±V
S
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ±1.2 V
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . . .Observe Power Derating Curves
Storage Temperature Range N, R . . . . . . . . . –65ⴗC to +125ⴗC
Operating Temperature Range (A Grade) . . . . –40ⴗC to +85ⴗC
Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300ⴗC
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Specification is for device in free air:
8-Lead PDIP Package: q
JA
= 90∞C/W
8-Lead SOIC Package: q
JA
= 140∞C/W
METALLIZATION PHOTO
Dimensions shown in inches and (millimeters)
Connect Substrate to –V
S
AD9631
AD9632
–IN
2
+VS
7
6
OUT
–IN
2
+VS
7
6
OUT
3
+IN
4
–VS
3
+IN
4
–VS
0.046
(1.17)
0.046
(1.17)
0.050 (1.27)
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by these
devices is limited by the associated rise in junction temperature.
The maximum safe junction temperature for plastic encapsulated
devices is determined by the glass transition temperature of the
plastic, approximately 150ⴗC. Exceeding this limit temporarily
may cause a shift in parametric performance due to a change in
the stresses exerted on the die by the package. Exceeding a junc-
tion temperature of 175ⴗC for an extended period can result in
device failure.
While the AD9631 and AD9632 are internally short circuit
protected, this may not be sufficient to guarantee that the maxi-
mum junction temperature (150ⴗC) is not exceeded under all
conditions. To ensure proper operation, it is necessary to observe
the maximum power derating curves.
AMBIENT TEMPERATURE – ⴗC
2.0
1.5
0
–50
MAXIMUM POWER DISSIPATION – W
1.0
0.5
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90
8-LEAD PDIP PACKAGE
8-LEAD SOIC PACKAGE
T
J
= +150 C
Figure 2. Maximum Power Dissipation
vs. Temperature
ORDERING GUIDE
Temperature Package Package
Model Range Description Option
AD9631AN –40∞C to +85∞CPDIP N-8
AD9631AR –40∞C to +85∞CSOIC R-8
AD9631AR-REEL –40∞C to +85∞CSOIC R-8
AD9631AR-REEL7 –40∞C to +85∞CSOIC R-8
AD9631CHIPS Die
AD9632AN –40∞C to +85∞CPDIP N-8
AD9632AR –40∞C to +85∞CSOIC R-8
AD9632AR-REEL –40∞C to +85∞CSOIC R-8
AD9632AR-REEL7 –40∞C to +85∞CSOIC R-8
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD9631/AD9632 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. C–4–
AD9631/AD9632–Typical Performance Characteristics
AD9631
0.1F
10F
+V
S
0.1F
10F
–V
S
R
F
130
V
IN
R
T
49.9
PULSE
GENERATOR
T
R
/T
F
= 350ps
R
L
= 100
V
OUT
TPC 1. AD9631 Noninverting Configuration, G = +1
1V
5ns
TPC 2. AD9631 Large Signal Transient Response;
V
O
= 4 V p-p, G = +1, R
F
= 250
W
100mV
5ns
TPC 3. AD9631 Small Signal Transient Response;
V
O
= 400 mV p-p, G = +1, R
F
= 140
W
AD9631
0.1F
10F
+V
S
0.1F
10F
–V
S
R
F
267
R
T
49.9
V
IN
PULSE
GENERATOR
T
R
/T
F
= 350ps
100
R
L
= 100
V
OUT
TPC 4. AD9631 Inverting Configuration, G = –1
1V 5ns
TPC 5. AD9631 Large Signal Transient Response;
V
O
= 4 V p-p, G = –1, R
F
= R
IN
= 267
W
100mV
5ns
TPC 6. AD9631 Small Signal Transient Response;
V
O
= 400 mV p-p, G = –1, R
F
= R
IN
= 267
W
REV. C
AD9631/AD9632
–5–
AD9632
0.1F
10F
+V
S
0.1F
10F
–V
S
R
F
130
V
IN
R
T
49.9
PULSE
GENERATOR
T
R
/T
F
= 350ps
R
L
= 100
V
OUT
R
IN
TPC 7. AD9632 Noninverting Configuration, G = +2
1V
5ns
TPC 8. AD9632 Large Signal Transient Response;
V
O
= 4 V p-p, G = +2, R
F
= R
IN
= 422
W
100mV
5ns
TPC 9. AD9632 Small Signal Transient Response;
V
O
= 400 mV p-p, G = +2, R
F
= R
IN
= 274
W
AD9632
0.1F
10F
+V
S
0.1F
10F
–V
S
R
F
R
T
49.9
V
IN
PULSE
GENERATOR
T
R
/T
F
= 350ps
100
R
L
= 100
V
OUT
R
IN
TPC 10. AD9632 Inverting Configuration, G = –1
1V
5ns
TPC 11. AD9632 Large Signal Transient Response;
V
O
= 4 V p-p, G = –1, R
F
=
R
IN
= 422
W
, R
T
= 56.2
W
100mV 5ns
TPC 12. AD9632 Small Signal Transient Response;
V
O
= 400 mV p-p, G = –1, R
F
= R
IN
= 267
W
, R
T
= 61.9
W
REV. C–6–
AD9631/AD9632
FREQUENCY – Hz
1
1M
GAIN – dB
10M 100M 1G
VS = 5V
RL = 100
VO = 300mV p-p
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
RF
50
RF
200
RF
100
RF
150
TPC 13. AD9631 Small Signal Frequency
Response, G = +1
FREQUENCY – Hz
0.1
1M
GAIN – dB
10M 100M
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
500M
RF
140
RF
100
RF
150
VS = 5V
RL = 100
G = +1
VO = 300mV p-p
RF
120
TPC 14. AD9631 0.1 dB Flatness, N Package
(for R Package Add 20
W
to R
F
)
90
GAIN – dB
80
70
60
50
40
30
20
10
0
–10
–20
FREQUENCY – Hz
10k 100k 1M 1G
10M 100M
100
20
0
–20
40
60
80
–80
–100
–60
–40
PHASE MARGIN – Degrees
–120
PHASE
GAIN
TPC 15. AD9631 Open-Loop Gain and
Phase Margin vs. Frequency, R
L
= 100
W
VALUE OF FEEDBACK RESISTOR ( RF
) –
20
–3dB BANDWIDTH – MHz
40 60 80
450
400
350
300
250
100 120 140 160 180 200 220 240
VS = 5V
RL = 100
GAIN = +1
N PACKAGE
R PACKAGE
AD9631
RL
130
RF
TPC 16. AD9631 Small Signal –3 dB Bandwidth vs. R
F
FREQUENCY – Hz
1
1M 10M 100M
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
500M
OUTPUT – dB
RF
250
RF = 50 TO 250
BY 50
VS = 5V
RL = 100
VO = 4V p-p
TPC 17. AD9631 Large Signal Frequency
Response, G = +1
FREQUENCY – Hz
1
1M
GAIN – dB
10M 100M 1G
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
V
S
= 5V
R
L
= 100
V
O
= 300mV p-p
R
F
267
TPC 18. AD9631 Small Signal Frequency
Response, G = –1
REV. C
AD9631/AD9632
–7–
FREQUENCY – Hz
–30
10k
HARMONIC DISTORTION – dBc
100k 1M 10M
–50
–70
–90
–110
–130
100M
VS = 5V
RL = 500
G = +1
VO = 2V p-p
THIRD
HARMONIC
SECOND
HARMONIC
TPC 19. AD9631 Harmonic Distortion vs.
Frequency, R
L
= 500
W
FREQUENCY – Hz
–30
10k
HARMONIC DISTORTION – dBc
100k 1M 10M
–50
–70
–90
–110
–130
100M
VS = 5V
RL = 100
G = +1
VO = 2V p-p
THIRD
HARMONIC
SECOND
HARMONIC
TPC 20. AD9631 Harmonic Distortion vs.
Frequency, R
L
= 100
W
FREQUENCY – MHz
60
10
INTERCEPT – dBm
20 30 40
55
50
45
35
30
10050 60 70 80 90
40
25
20
TPC 21. AD9631 Third Order Intercept vs. Frequency
0.10
1ST 11TH6TH
DIFF GAIN – %
0.05
0.00
–0.05
–0.10
2ND 7TH3RD 8TH4TH 9TH5TH 10TH
0.00
–0.05
–0.10
0.10
DIFF PHASE – Degrees
1ST 11TH6TH2ND 7TH3RD 8TH4TH 9TH5TH 10TH
0.05
TPC 22. AD9631 Differential Gain and Phase
Error, G = +2, R
L
= 150
W
SETTLING TIME – ns
0.3
0
ERROR – %
10 20 30
0.2
0.1
0.0
–0.2
–0.3
40 50 60 70 80
–0.1
TPC 23. AD9631 Short-Term Settling Time,
2 V Step, R
L
= 100
W
SETTLING TIME – s
0.3
0
ERROR – %
123
0.2
0.1
0.0
–0.2
45678
–0.1
910
TPC 24. AD9631 Long-Term Settling Time,
2 V Step, R
L
= 100
W
REV. C–8–
AD9631/AD9632
FREQUENCY – Hz
7
1M
GAIN – dB
10M 100M 1G
V
S
= 5V
R
L
= 100
V
O
= 300mV p-p
6
5
4
3
2
1
0
–1
–2
–3
R
F
225
R
F
125
R
F
425
R
F
325
TPC 25. AD9632 Small Signal Frequency
Response, G = +2
FREQUENCY – Hz
0.1
1M
OUTPUT – dB
10M 100M
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
V
S
= 5V
R
L
= 100
G = +2
V
O
= 300mV p-p
R
F
325
R
F
275
R
F
375
R
F
425
TPC 26. AD9632 0.1 dB Flatness, N Package
(for R Package Add 20
W
to R
F
)
65
A
OL
– dB
60
55
50
45
40
35
30
25
20
15
10
FREQUENCY – Hz
10k 100k 1M 1G
10M 100M
50
0
100
–150
–200
–100
–50
PHASE – Degrees
–250
5
0
–5
–10
–15
PHASE
GAIN
TPC 27. AD9632 Open-Loop Gain and Phase
Margin vs. Frequency, R
L
= 100
W
VAL UE OF RF, RIN –
100
–3dB BANDWIDTH – MHz
150 200 250
350
300
250
200
150
300 350 400 450 500 550
VS = 5V
RL = 100
GAIN = +2
AD9632
RL
100
49.9
RIN
RF
N PACKAGE
R PACKAGE
TPC 28. AD9632 Small Signal –3 dB Bandwidth
vs. R
F
, R
IN
FREQUENCY – Hz
7
1M 10M 100M
6
5
4
3
2
1
0
–1
–2
–3
500M
OUTPUT – dB
RF
525
RF = 125TO 525
BY 100
VS = 5V
RL = 100
VO = 4V p-p
TPC 29. AD9632 Large Signal Frequency
Response, G = +2
FREQUENCY – Hz
1
1M
GAIN – dB
10M 100M 1G
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
V
S
= 5V
R
L
= 100
V
O
= 300mV p-p
R
F
, R
IN
267
TPC 30. AD9632 Small Signal Frequency
Response, G = –1
REV. C
AD9631/AD9632
–9–
FREQUENCY – Hz
–30
10k
HARMONIC DISTORTION – dBc
100k 1M 10M
–50
–70
–90
–110
–130
100M
V
S
= 5V
R
L
= 500
G = +2
V
O
= 2V p-p
THIRD
HARMONIC
SECOND
HARMONIC
TPC 31. AD9632 Harmonic Distortion vs.
Frequency, R
L
= 500
W
FREQUENCY – Hz
–30
10k
HARMONIC DISTORTION – dBc
100k 1M 10M
–50
–70
–90
–110
–130
100M
V
S
= 5V
R
L
= 100
G = +2
V
O
= 2V p-p
THIRD
HARMONIC
SECOND
HARMONIC
TPC 32. AD9632 Harmonic Distortion vs.
Frequency, R
L
= 100
W
FREQUENCY – MHz
50
10
INTERCEPT – dBm
20 30 40
45
40
35
25
20
10050 60 70 80 90
30
15
10
TPC 33. AD9632 Third Order Intercept vs. Frequency
0.04
1ST 11TH6TH
DIFF GAIN – %
0.02
0.00
–0.02
–0.04
2ND 7TH3RD 8TH4TH 9TH5TH 10TH
0.00
–0.02
–0.04
0.04
DIFF PHASE – Degrees
1ST 11TH6TH2ND 7TH3RD 8TH4TH 9TH5TH 10TH
0.02
TPC 34. AD9632 Differential Gain and Phase
Error G = +2, R
L
= 150
W
SETTLING TIME – ns
0
ERROR – %
10 20 30
0.2
0.1
0.0
–0.2
–0.3
40 50 60 70 80
–0.1
TPC 35. AD9632 Short-Term Settling Time,
2 V Step, R
L
= 100
W
SETTLING TIME – s
0.3
0
ERROR – %
123
0.2
0.1
0.0
–0.2
45678
–0.1
910
TPC 36. AD9632 Long-Term Settling Time,
2 V Step, R
L
= 100
W
REV. C–10–
AD9631/AD9632
FREQUENCY – Hz
24
10
INPUT NOISE VOLTAGE – nV/ Hz
100 1k 10k
21
18
15
12
9
100k
6
3
V
S
= 5V
TPC 37. AD9631 Noise vs. Frequency
80
PSRR – dB
75
70
65
60
55
50
45
40
35
30
25
FREQUENCY – Hz
10k 100k 1M 1G
10M 100M
20
15
10
5
0
–PSRR
+PSRR
TPC 38. AD9631 PSRR vs. Frequency
FREQUENCY – Hz
100
100k
CMRR – dB
1M 10M 100M
90
80
70
60
50
1G
40
30
20
VS = 5V
VCM = 1V
RL = 100
TPC 39. AD9631 CMRR vs. Frequency
FREQUENCY – Hz
17
10
INPUT NOISE VOLTAGE – nV/ Hz
100 1k 10k
15
13
11
9
7
100k
5
3
V
S
= 5V
TPC 40. AD9632 Noise vs. Frequency
80
PSRR – dB
75
70
65
60
55
50
45
40
35
30
25
FREQUENCY – Hz
10k 100k 1M 1G
10M 100M
20
15
10
5
0
–PSRR
+PSRR
TPC 41. AD9632 PSRR vs. Frequency
FREQUENCY – Hz
100
100k
CMRR – dB
1M 10M 100M
90
80
70
60
50
1G
40
30
20
VS = 5V
VCM = 1V
RL = 100
TPC 42. AD9632 CMRR vs. Frequency
REV. C
AD9631/AD9632
–11–
FREQUENCY – Hz
1000
10k
R
OUT
–
100k 1M 10M
100
10
1
0.1
0.01
100M
V
S
= 5V
GAIN = +1
TPC 43. AD9631 Output Resistance vs. Frequency
FREQUENCY – Hz
1000
10k
R
OUT
–
100k 1M 10M
100
10
1
0.1
0.01
100M
V
S
= 5V
GAIN = +1
TPC 44. AD9632 Output Resistance vs. Frequency
JUNCTION TEMPERATURE – C
–60
OUTPUT SWING – V
–40 –20 0
4.1
4.0
3.9
3.7
3.6
20 40 60 80 100
3.8
3.5
3.4
3.3
120 140
VS = 5V
RL = 150
RL = 50
+VOUT
–VOUT
+VOUT
–VOUT
TPC 45. AD9631/AD9632 Output Swing vs. Temperature
JUNCTION TEMPERATURE – C
–60
OPEN-LOOP GAIN – V/V
–40 –20 0
1350
1250
1150
950
850
20 40 60 80 100
1050
750
650
550
120 140
450
350
AD9632
AD9631
+AOL
–AOL
+AOL
–AOL
TPC 46. Open-Loop Gain vs. Temperature
JUNCTION TEMPERATURE – C
–60
PSRR – dB
–40 –20 0
76
74
72
68
66
20 40 60 80 100
70
64
62
60
120 140
58
56
–PSRR
+PSRR
–PSRR
+PSRR
AD9632
AD9631
AD9632
AD9631
TPC 47. PSRR vs. Temperature
JUNCTION TEMPERATURE – C
–60
CMRR – dB
–40 –20 0
98
96
94
90
88
20 40 60 80 100
92
86
120 140
+CMRR
–CMRR
TPC 48. AD9631/AD9632 CMRR vs. Temperature
REV. C–12–
AD9631/AD9632
JUNCTION TEMPERATURE – C
–60
SUPPLY CURRENT – mA
–40 –20 0
21
20
19
17
16
20 40 60 80 100
18
15
120 140
14
AD9632
AD9631
6V
5V
6V
5V AD9632
AD9631
TPC 49. Supply Current vs. Temperature
JUNCTION TEMPERATURE – C
–60
INPUT OFFSET VOLTAGE – mV
–40 –20 0
–1.0
–1.5
–2.0
–3.0
–3.5
20 40 60 80 100
–2.5
–4.0
120 140
–4.5
AD9632
AD9631
–5.0
V
S
= 5V
V
S
= 6V
V
S
= 5V
V
S
= 6V
TPC 50. Input Offset Voltage vs. Temperature
INPUT OFFSET VOLTAGE – mV
–7
COUNT
–6 –5 –4
220
200
180
140
120
–3 –2 –1 0 1
160
100
23
80
60
4567
40
20
0
100
90
80
70
60
50
40
30
20
10
0
PERCENT
CUMULATIVE
FREQ. DIST
3 WAFER LOTS
COUNT = 1373
TPC 51. AD9631 Input Offset Voltage Distribution
JUNCTION TEMPERATURE – C
–60
SHORT CIRCUIT CURRENT – mA
–40 –20 0
250
240
230
210
200
20 40 60 80 100
220
190
120 140
180
AD9632
AD9631
SINK
SOURCE
SINK
SOURCE
TPC 52. Short Circuit Current vs. Temperature
JUNCTION TEMPERATURE – C
–60
INPUT BIAS CURRENT – A
–40 –20 0
2.0
1.5
1.0
0.0
–0.5
20 40 60 80 100
0.5
–1.0
120 140
–1.5
AD9632
AD9631
–2.0
–I
B
+I
B
–I
B
+I
B
TPC 53. Input Bias Current vs. Temperature
INPUT OFFSET VOLTAGE – mV
–7
COUNT
–6 –5 –4
180
140
120
–3 –2 –1 0 1
160
100
23
80
60
4567
40
20
0
100
90
80
70
60
50
40
30
20
10
0
PERCENT
3 WAFER LOTS
COUNT = 573
CUMULATIVE
FREQ. DIST
TPC 54. AD9632 Input Offset Voltage Distribution
REV. C
AD9631/AD9632
–13–
THEORY OF OPERATION
General
The AD9631 and AD9632 are wide bandwidth, voltage feedback
amplifiers. Since their open-loop frequency response follows the
conventional 6 dB/octave roll-off, their gain bandwidth product
is basically constant. Increasing their closed-loop gain results in
a corresponding decrease in small signal bandwidth. This can
be observed by noting the bandwidth specification between the
AD9631 (gain of +1) and AD9632 (gain of +2). The AD9631/
AD9632 typically maintain 65 degrees of phase margin. This
high margin minimizes the effects of signal and noise peaking.
Feedback Resistor Choice
The value of the feedback resistor is critical for optimum perfor-
mance on the AD9631 (gain of +1) and less critical as the gain
increases. Therefore, this section is specifically targeted at the
AD9631.
At minimum stable gain (+1), the AD9631 provides optimum
dynamic performance with R
F
= 140 W. This resistor acts as a
parasitic suppressor only against damped RF oscillations that
can occur due to lead (input, feedback) inductance and parasitic
capacitance. This value of R
F
provides the best combination of
wide bandwidth, low parasitic peaking, and fast settling time.
In fact, for the same reasons, a 100 W–130 W resistor should be
placed in series with the positive input for other AD9631 noninver-
ting and all AD9631 inverting configurations. The correct
connection is shown in Figures 3 and 4.
AD9631/
AD9632
+V
S
–V
S
100–130
R
TERM
R
IN
V
IN
R
G
0.1F
10F
0.1F
10F
R
F
V
OUT
G = 1 + R
F
R
G
Figure 3. Noninverting Operation
AD9631/
AD9632
+V
S
–V
S
100–130
R
TERM
R
IN
R
G
0.1F
10F
0.1F
10F
R
F
V
OUT
V
IN
G = – R
F
R
G
Figure 4. Inverting Operation
When the AD9631 is used in the transimpedance (I to V) mode,
such as in photodiode detection, the value of R
F
and diode capaci-
tance (C
I
) are usually known. Generally, the value of R
F
selected
will be in the kW range, and a shunt capacitor (C
F
) across R
F
will
be required to maintain good amplifier stability. The value of
C
F
required to maintain optimal flatness (<1 dB peaking) and
settling time can be estimated as
CCR R
FOIF OF
@
()
[]
21
22
1
2

–/
where
w
O
is equal to the unity gain bandwidth product of the
amplifier in rad/sec, and C
I
is the equivalent total input
capacitance at the inverting input. Typically
w
O
= 800 10
6
rad/sec (see TPC 15).
As an example, choosing R
F
= 10 kW and C
I
= 5 pF requires C
F
to be 1.1 pF (Note: C
I
includes both source and parasitic circuit
capacitance). The bandwidth of the amplifier can be estimated
using the C
F
calculated as
fRC
d
FF
3
16
2
@.
AD9631
R
F
VOUT
CI
II
CF
Figure 5. Transimpedance Configuration
For general voltage gain applications, the amplifier bandwidth
can be closely estimated as
f21R/R
3dB
FG
@+
()
O
This estimation loses accuracy for gains of +2/–1 or lower due
to the amplifier’s damping factor. For these “low gain” cases,
the bandwidth will actually extend beyond the calculated value
(see TPCs 13 and 25).
As a general rule, capacitor C
F
will not be required if
RR C NG
FG I
()
¥£
4
O
where NG is the noise gain (1 + R
F
/R
G
) of the circuit. For most
voltage gain applications, this should be the case.
REV. C–14–
AD9631/AD9632
Pulse Response
Unlike a traditional voltage feedback amplifier, where the slew
speed is dictated by its front end dc quiescent current and
gain bandwidth product, the AD9631 and AD9632 provide
“on-demand” current that increases proportionally to the input
“step” signal amplitude. This results in slew rates (1300 V/ms)
comparable to wideband current feedback designs. This, combined
with relatively low input noise current (2.0 pA/÷Hz), gives the
AD9631 and AD9632 the best attributes of both voltage and
current feedback amplifiers.
Large Signal Performance
The outstanding large signal operation of the AD9631 and AD9632
is due to a unique, proprietary design architecture. In order to
maintain this level of performance, the maximum 550 V-MHz
product must be observed (e.g., @ 100 MHz, V
O
£ 5.5 V p-p).
Power Supply Bypassing
Adequate power supply bypassing can be critical when optimizing
the performance of a high frequency circuit. Inductance in the
power supply leads can form resonant circuits that produce
peaking in the amplifier’s response. In addition, if large current
transients must be delivered to the load, then bypass capacitors
(typically greater than 1 mF) will be required to provide the best
settling time and lowest distortion. A parallel combination of at
least 4.7 mF, and between 0.1 mF and 0.01 mF, is recommended.
Some brands of electrolytic capacitors will require a small series
damping resistor ª4.7 W for optimum results.
Driving Capacitive Loads
The AD9631 and AD9632 were designed primarily to drive
nonreactive loads. If driving loads with a capacitive component is
desired, the best frequency response is obtained by the addition of
a small series resistance as shown in Figure 6. The accompany-
ing graph shows the optimum value for R
SERIES
versus capacitive
load. It is worth noting that the frequency response of the circuit
when driving large capacitive loads will be dominated by the
passive roll-off of R
SERIES
and C
L
.
AD9631/
AD9632
R
F
C
L
R
IN
R
IN
R
L
1k
R
SERIES
Figure 6. Driving Capacitive Loads
C
L
– pF
0
R
SERIES
–
51015
40
30
20
20 25
10
Figure 7. Recommended R
SERIES
vs. Capacitive Load
APPLICATIONS
The AD9631 and AD9632 are voltage feedback amplifiers well
suited for applications such as photodetectors, active filters, and
log amplifiers. The devices’ wide bandwidth (320 MHz), phase
margin (65), low current noise (2.0 pA/÷Hz), and slew rate
(1300 V/ms) give higher performance capabilities to these appli-
cations over previous voltage feedback designs.
With a settling time of 16 ns to 0.01% and 11 ns to 0.1%, the
devices are an excellent choice for DAC I/V conversion. The same
characteristics along with low harmonic distortion make them
agood choice for ADC buffering/amplification. With superb
linearity at relatively high signal frequencies, the AD9631 and
AD9632 are ideal drivers for ADCs up to 12 bits.
Operation as a Video Line Driver
The AD9631 and AD9632 have been designed to offer outstand-
ing performance as video line drivers. The important specifications
of differential gain (0.02%) and differential phase (0.02) meet
the most exacting HDTV demands for driving video loads.
75
0.1F
AD9631/
AD9632
+VS
–VS
274
10F
VOUT
0.1F
10F
274
VIN
75
CABLE
75
CABLE
75
75
Figure 8. Video Line Driver
REV. C
AD9631/AD9632
–15–
Active Filters
The wide bandwidth and low distortion of the AD9631 and
AD9632 are ideal for the realization of higher bandwidth active
filters. These characteristics, while being more common in
many current feedback op amps, are offered in the AD9631 and
AD9632 in a voltage feedback configuration. Many active filter
configurations are not realizable with current feedback amplifiers.
A multiple feedback active filter requires a voltage feedback
amplifier and is more demanding of op amp performance than
other active filter configurations, such as the Sallen-Key. In
general, the amplifier should have a bandwidth that is at least
10 times the bandwidth of the filter if problems due to phase shift
of the amplifier are to be avoided.
Figure 9 is an example of a 20 MHz low-pass multiple feedback
active filter using an AD9632.
–5V
10F
0.1F
0.1F
+5V 10F
AD9632
100
C1
50pF
R3
78.7
R4
154
C2
100pF
R1
154
V
IN
V
OUT
Figure 9. Active Filter Circuit
Choose
F
O
= Cutoff Frequency = 20 MHz
a
= Damping Ratio = 1/Q = 2
H = Absolute Value of Circuit Gain =
–R4
R1
= 1
Then
kFC
CCH
RHK
RKH
RHR
O
=
=+
=
=+
=
21
241 1
12
321
41
()
()
()
2
A/D Converter Driver
As A/D converters move toward higher speeds with higher resolu-
tions, there becomes a need for high performance drivers that
will not degrade the analog signal to the converter. It is desirable
from a system’s standpoint that the A/D be the element in the
signal chain that ultimately limits overall distortion. This places
new demands on the amplifiers that are used to drive fast, high
resolution A/Ds.
With high bandwidth, low distortion, and fast settling time, the
AD9631 and AD9632 make high performance A/D drivers for
advanced converters. Figure 10 is an example of an AD9631 used
as an input driver for an AD872, a 12-bit, 10 MSPS A/D converter.
–5V ANALOG
10F
0.1F
0.1F
+5V ANALOG
10F
AD9631
140
130
AV
DD
AGND
0.1F
4
5
+5V ANALOG
V
INA
1
2
27
28
V
INB
REF GND
0.1F
REF IN
26 REF OUT
1F
AV
SS
AV
SS
DV
DD
DGND
10
0.1F
7
6
+5V DIGITAL
CLK
MSB
BIT2
BIT3
BIT4
BIT5
BIT6
BIT7
BIT8
BIT9
BIT10
BIT11
BIT12
AGND
DV
DD
DGND
0.1F
22
23
+5V DIGITAL
21
20
OTR
19
18
17
16
15
14
13
12
11
10
9
8
49.9
DIGITAL OUTPUT
0.1F 0.1F
–5V ANALOG
325
AD872
CLOCK INPUT
ANALOG
IN
Figure 10. AD9631 Used as Driver for an AD872, a 12-Bit, 10 MSPS A/D Converter
REV. C–16–
AD9631/AD9632
Layout Considerations
The specified high speed performance of the AD9631 and AD9632
requires careful attention to board layout and component
selection. Proper RF design techniques and low-pass parasitic
component selection are mandatory.
The PCB should have a ground plane covering all unused portions
of the component side of the board to provide a low impedance
path. The ground plane should be removed from the area near
the input pins to reduce stray capacitance.
Chip capacitors should be used for supply bypassing (see
Figure 10). One end should be connected to the ground plane,
and the other within 1/8 inch of each power pin. An additional
large (0.47 mF–10 mF) tantalum electrolytic capacitor should be
connected in parallel, though not necessarily so close, to supply
current for fast, large signal changes at the output.
The feedback resistor should be located close to the inverting input
pin in order to keep the stray capacitance at this node to a mini-
mum. Capacitance variations of less than 1 pF at the inverting
input will significantly affect high speed performance.
Stripline design techniques should be used for long signal traces
(greater than about 1 inch). These should be designed with a
characteristic impedance of 50 W or 75 W and be properly termi-
nated at each end.
REV. C
AD9631/AD9632
–17–
OUTLINE DIMENSIONS
8-Lead Plastic Dual In-Line Package [PDIP]
(N-8)
Dimensions shown in inches and (millimeters)
SEATING
PLANE
0.180
(4.57)
MAX
0.150 (3.81)
0.130 (3.30)
0.110 (2.79) 0.060 (1.52)
0.050 (1.27)
0.045 (1.14)
8
14
5
0.295 (7.49)
0.285 (7.24)
0.275 (6.98)
0.100 (2.54)
BSC
0.375 (9.53)
0.365 (9.27)
0.355 (9.02)
0.150 (3.81)
0.135 (3.43)
0.120 (3.05)
0.015 (0.38)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MO-095AA
0.015
(0.38)
MIN
8-Lead Standard Small Outline Package [SOIC]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45
8
0
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
85
41
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2440)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-012AA
REV. C–18–
AD9631/AD9632
Revision History
Location Page
7/03—Data Sheet changed from REV. B to REV. C.
Deleted Evaluation Boards information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Deleted military CERDIP version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Change to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Change to TPC 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Change to TPC 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Change to Figure 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1/03—Data Sheet changed from REV. A to REV. B.
Deleted DIP (N) Inverter, SOIC (R) Inverter, and DIP (N) Noninverter Evaluation Boards in Figures 12–14 . . . . . . . . . . . . . . . 17
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
–19–
C00601–0–7/03(C)
–20–