Copyright Cirrus Logic, Inc. 2012
(All Rights Reserved)
Preliminary Product Information This document contains information for a product under development.
Cirrus Logic reserves the right to modify this product without notice.
http://www.cirrus.com
103-dB, 192-kHz, Stereo Audio ADC with 6:1 Input Mux
ADC Features
Multi-bit Delta–Sigma Modulator
103 dB Dynamic Range
-95 dB THD+N
Stereo 6:1 Input Multiplexer
Programmable Gain Amplifier (PGA)
– ± 12 dB Gain, 0.5-dB Step Size
– Zero-crossing, Click-free Transitions
Stereo Microphone Inputs
– +32 dB Gain Stage
– Low-noise Bias Supply
Up to 192 kHz Sampling Rates
Selectable 24-bit, Left-justified or I²S Serial
Audio Interface Formats
System Features
Power-down Mode
+5 V Analog Power Supply, Nominal
+3.3 V Digital Power Supply, Nominal
Direct Interface with 3.3 V to 5 V Logic Levels
Pin Compatible with CS5345 (*See Section 2
for details.)
General Description
The CS5346 integrates an analog multiplexer, program-
mable gain amplifier, and stereo audio analog-to-digital
converter. The CS5346 performs stereo analog-to-digi-
tal (A/D) conve rsion of 24-bit serial values at sa mple
rates up to 192 kHz.
A 6:1 stereo input multiplexer is included for selecting
between line-level and microphone-level inputs. The
microphone input path includes a +32 dB gain stage
and a low-noise bias voltage supply. The PGA is avail-
able for line or microphone inputs and provides
gain/attenuation of ±12 dB in 0.5 dB steps.
The output of the PGA is followed by an advanced 5th-
order, multi-bit delta-sigma modulator and digital filter-
ing/decimation. Sampled data is transmitted by the
serial audio interface at rates from 8 kHz to 192 kHz in
either Slave or Master Mode.
Integrated level translators allow easy interfacing be-
tween the CS5346 and other devices operating over a
wide range of logic levels.
The CS5346 is available in a 48-pin LQFP package in
Commercial (-40° to +85° C) grade. The CDB5346 Cus-
tomer Demonstration board is also available for device
evaluation and implementation suggestions. Please re-
fer to “Ordering Information” on page 38 for complete
details.
3.3 V to 5 V
Low-Latency
Anti-Alias Filter
Internal Voltage
Reference
Multibit
Oversampling
ADC
Multibit
Oversampling
ADC
Low-Latency
Anti-Alias Filter
High Pass
Filter
High Pass
Filter
Stereo Input 1
Serial
Audio
Output
3.3 V 5 V
MUX
PCM Serial Interface
Register Configuration
Level
Translator
Stereo Input 2
Stereo Input 3
Stereo Input 4 /
Mic Input 1 & 2
Stereo Input 5
Stereo Input 6
PGA
+32 dB
+32 dB
Level Translator
Reset
I²C/SPI
Control Data
Interrupt
Overflow
Left PGA Output
Right PGA Output
PGAA
AUG ‘12
DS861PP3
CS5346
2DS861PP3
CS5346
TABLE OF CONTENTS
1. PIN DESCRIPTIONS - CS5346 ............................................................................................................. 5
2. PIN COMPATIBILITY - CS5345/CS5346 DIFFERENCES ..................................................................... 7
3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 8
RECOMMENDED OPERATING CONDITIONS ................................................................................... 8
ABSOLUTE MAXIMUM RATINGS .......................................................................................................8
ANALOG CHARACTERISTICS ............................................................................................................ 9
ANALOG CHARACTERISTICS CONT. .............................................................................................. 10
DIGITAL FILTER CHARACTERISTICS .............................................................................................. 11
DC ELECTRICAL CHARACTERISTICS ............................................................................................. 12
DIGITAL INTERFACE CHARACTERISTICS ...................................................................................... 13
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT ............................................................. 14
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT ............................................ 16
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT ........................................... 17
4. TYPICAL CONNECTION DIAGRAM ................................................................................................... 18
5. APPLICATIONS ................................................................................................................................... 19
5.1 Recommended Power-Up Sequence ............................................................................................. 19
5.2 System Clocking ............................................................................................................................. 19
5.2.1 Master Clock ......................................................................................................................... 19
5.2.2 Master Mode ......................................................................................................................... 20
5.2.3 Slave Mode ........................................................................................................................... 20
5.3 High-Pass Filter and DC Offset Calibration .................................................................................... 20
5.4 Analog Input Multiplexer, PGA, and Mic Gain ................................................................................21
5.5 Input Connections ........................................................................................................................... 21
5.5.1 Analog Input Configuration for 1 VRMS Input Levels ............................................................ 21
5.5.2 Analog Input Configuration for 2 VRMS Input Levels ............................................................ 22
5.6 PGA Auxiliary Analog Output ......................................................................................................... 23
5.7 Control Port Description and Timing ............................................................................................... 23
5.7.1 SPI Mode ............................................................................................................................... 23
5.7.2 I²C Mode ................................................................................................................................ 24
5.8 Interrupts and Overflow .................................................................................................................. 25
5.9 Reset .............................................................................................................................................. 26
5.10 Synchronization of Multiple Devices ............................................................................................. 26
5.11 Grounding and Power Supply Decoupling .................................................................................... 26
6. REGISTER QUICK REFERENCE ........................................................................................................ 27
7. REGISTER DESCRIPTION .................................................................................................................. 28
7.1 Chip ID - Register 01h .................................................................................................................... 28
7.2 Power Control - Address 02h ......................................................................................................... 28
7.2.1 Freeze (Bit 7) ......................................................................................................................... 28
7.2.2 Power-Down MIC (Bit 3) ........................................................................................................ 28
7.2.3 Power-Down ADC (Bit 2) ....................................................................................................... 28
7.2.4 Power-Down Device (Bit 0) ................................................................................................... 28
7.3 ADC Control - Address 04h ............................................................................................................ 29
7.3.1 Functional Mode (Bits 7:6) .................................................................................................... 29
7.3.2 Digital Interface Format (Bit 4) .............................................................................................. 29
7.3.3 Mute (Bit 2) ............................................................................................................................ 29
7.3.4 High-Pass Filter Freeze (Bit 1) .............................................................................................. 29
7.3.5 Master / Slave Mode (Bit 0) ................................................................................................... 29
7.4 MCLK Frequency - Address 05h .................................................................................................... 30
7.4.1 Master Clock Dividers (Bits 6:4) ............................................................................................ 30
7.5 PGAOut Control - Address 06h ...................................................................................................... 30
7.5.1 PGAOut Source Select (Bit 6) ............................................................................................... 30
7.6 Channel B PGA Control - Address 07h .......................................................................................... 30
DS861PP3 3
CS5346
7.6.1 Channel B PGA Gain (Bits 5:0) ............................................................................................. 30
7.7 Channel A PGA Control - Address 08h .......................................................................................... 31
7.7.1 Channel A PGA Gain (Bits 5:0) ............................................................................................. 31
7.8 ADC Input Control - Address 09h ................................................................................................... 31
7.8.1 PGA Soft Ramp or Zero Cross Enable (Bits 4:3) .................................................................. 31
7.8.2 Analog Input Selection (Bits 2:0) ........................................................................................... 32
7.9 Active Level Control - Address 0Ch ................................................................................................ 32
7.9.1 Active High/ Low (Bit 0) ......................................................................................................... 32
7.10 Status - Address 0Dh ................................................................................................................... 32
7.10.1 Clock Error (Bit 3) ................................................................................................................ 33
7.10.2 Overflow (Bit 1) .................................................................................................................... 33
7.10.3 Underflow (Bit 0) .................................................................................................................. 33
7.11 Status Mask - Address 0Eh .......................................................................................................... 33
7.12 Status Mode MSB - Address 0Fh ................................................................................................. 33
7.13 Status Mode LSB - Address 10h .................................................................................................. 33
8. PARAMETER DEFINITIONS ................................................................................................................ 34
9. FILTER PLOTS .................................................................................................................................. 35
10. PACKAGE DIMENSIONS .................................................................................................................. 37
11. THERMAL CHARACTERISTICS AND SPECIFICATIONS .............................................................. 37
12. ORDERING INFORMATION ......................................................................................................... 38
13. REVISION HISTORY .......................................................................................................................... 38
LIST OF FIGURES
Figure 1.Master Mode Serial Audio Port Timing ....................................................................................... 15
Figure 2.Slave Mode Serial Audio Port Timing ......................................................................................... 15
Figure 3.Format 0, 24-Bit Data Left-Justified ............................................................................................ 15
Figure 4.Format 1, 24-Bit Data I²S ............................................................................................................ 15
Figure 5.Control Port Timing - I²C Format ................................................................................................. 16
Figure 6.Control Port Timing - SPI Format ................................................................................................ 17
Figure 7.Typical Connection Diagram ....................................................................................................... 18
Figure 8.Master Mode Clocking ................................................................................................................ 20
Figure 9.Analog Input Architecture ............................................................................................................ 21
Figure 10.CS5346 PGA ............................................................................................................................ 22
Figure 11.1 VRMS Input Circuit .................................................................................................................. 22
Figure 12.1 VRMS Input Circuit with RF Filtering ....................................................................................... 22
Figure 13.2 VRMS Input Circuit .................................................................................................................. 22
Figure 14.Control Port Timing in SPI Mode .............................................................................................. 24
Figure 15.Control Port Timing, I²C Write ................................................................................................... 24
Figure 16.Control Port Timing, I²C Read ................................................................................................... 25
Figure 17.Single-Speed Stopband Rejection ............................................................................................ 35
Figure 18.Single-Speed Stopband Rejection ............................................................................................ 35
Figure 19.Single-Speed Transition Band (Detail) ...................................................................................... 35
Figure 20.Single-Speed Passband Ripple ................................................................................................ 35
Figure 21.Double-Speed Stopband Rejection ........................................................................................... 35
Figure 22.Double-Speed Stopband Rejection ........................................................................................... 35
Figure 23.Double-Speed Transition Band (Detail) .................................................................................... 36
Figure 24.Double-Speed Passband Ripple ............................................................................................... 36
Figure 25.Quad-Speed Stopband Rejection ............................................................................................. 36
Figure 26.Quad-Speed Stopband Rejection ............................................................................................. 36
Figure 27.Quad-Speed Transition Band (Detail) ....................................................................................... 36
Figure 28.Quad-Speed Passband Ripple ................................................................................................. 36
4DS861PP3
CS5346
LIST OF TABLES
Table 1. Speed Modes .............................................................................................................................. 19
Table 2. Common Clock Frequencies ....................................................................................................... 19
Table 3. Slave Mode Serial Bit Clock Ratios ............................................................................................. 20
Table 4. Device Revision .......................................................................................................................... 28
Table 5. Freeze-able Bits .......................................................................................................................... 28
Table 6. Functional Mode Selection .......................................................................................................... 29
Table 7. Digital Interface Formats ............................................................................................................. 29
Table 8. MCLK Frequency ........................................................................................................................ 30
Table 9. PGAOut Source Selection ........................................................................................................... 30
Table 10. Example Gain and Attenuation Settings ................................................................................... 31
Table 11. PGA Soft Cross or Zero Cross Mode Selection ........................................................................ 32
Table 12. Analog Input Multiplexer Selection ............................................................................................ 32
DS861PP3 5
CS5346
1. PIN DESCRIPTIONS - CS5346
Pin Name # Pin Description
SDA/CDOUT 1 Serial Control Data (Input/Output) - SDA is a data I/O in I²C® Mode. CDOUT is the output data line for
the control port interface in SPITM Mode.
SCL/CCLK 2 Serial Control Port Clock (Input) - Serial clock for the serial control port.
AD0/CS 3Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C Mode;
CS is the chip-select signal for SPI format.
AD1/CDIN 4 Address Bit 1 (I²C) / Serial Control Data Input (SPI) (Input) - AD1 is a chip address pin in I²C Mode;
CDIN is the input data line for the control port interface in SPI Mode.
VLC 5 Control Port Power (Input) - Determines the required signal level for the control port interface. Refer
to the Recommended Operating Conditions for appropriate voltages.
RST 6Reset (Input) - The device enters a low-power mode when this pin is driven low.
AIN3A
AIN3B
7
8
Stereo Analog Input 3 (Input) - The full-scale level is specified in the Analog Characteristics specifica-
tion table.
AIN2A
AIN2B
9
10
Stereo Analog Input 2 (Input) - The full-scale level is specified in the Analog Characteristics specifica-
tion table.
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
32
31
30
29
28
27
26
25
VLSSDA/CDOUT
AGND OVFL
SCL/CCLK
AD0/CS
AD1/CDIN
VLC
RST
AIN3A
AIN3B
AIN2A
AIN2B
AIN1A
AIN1B
VA
AFILTB
VQ
VQ
FILT+
NC
AIN4A/MICIN1
AIN4B/MICIN2
AIN5A
AIN5B
AFILTA
NC
NC
NC
AGND
NC
NC
PGAOUTB
PGAOUTA
AIN6B
AIN6A
MICBIAS
INT
VD
DGND
MCLK
LRCK
SCLK
SDOUT
NC
NC
NC
NC
CS5346
6DS861PP3
CS5346
AIN1A
AIN1B
11
12
Stereo Analog Input 1 (Input) - The full-scale level is specified in the Analog Characteristics specifica-
tion table.
AGND 13 Analog Ground (Input) - Ground reference for the internal analog section.
VA 14 Analog Power (Input) - Positive power for the internal analog section.
AFILTA 15 Anti-alias Filter Connection (Output) - Antialias filter connection for the channel A ADC input.
AFILTB 16 Anti-alias Filter Connection (Output) - Antialias filter connection for the channel B ADC input.
VQ 17
18 Quiescent Voltage (Output) - Filter connection for the internal quiescent reference voltage.
FILT+ 19 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
NC 20 No Connect - This pin is not connected internally and should be tied to ground to minimize any poten-
tial coupling effects.
AIN4A/MICIN1
AIN4B/MICIN2
21
22
Stereo Analog Input 4 / Microphone Input 1 & 2 (Input) - The full-scale level is specified in the Ana-
log Characteristics specification table.
AIN5A
AIN5B
23
24
Stereo Analog Input 5 (Input) - The full-scale level is specified in the Analog Characteristics specifica-
tion table.
MICBIAS 25 Microphone Bias Supply (Output) - Low-noise bias supply for external microphone. Electrical charac-
teristics are specified in the DC Electrical Characteristics specification table.
AIN6A
AIN6B
26
27
Stereo Analog Input 6 (Input) - The full-scale level is specified in the Analog Characteristics specifica-
tion table.
PGAOUTA
PGAOUTB
28
29
PGA Analog Audio Output (Output) - Either an analog output from the PGA block or high impedance.
See “PGAOut Source Select (Bit 6)” on page 30.
NC 30
31
No Connect - These pins are not connected internally and should be tied to ground to minimize any
potential coupling effects.
AGND 32 Analog Ground (Input) - Ground reference for the internal analog section.
NC
33
34
35
No Connect - These pins are not connected internally and should be tied to ground to minimize any
potential coupling effects.
VLS 36 Serial Audio Interface Power (Input) - Determines the required signal level for the serial audio inter-
face. Refer to the Recommended Operating Conditions for appropriate voltages.
NC
37
38
39
40
No Connect - These pins are not connected internally and should be tied to ground to minimize any
potential coupling effects.
SDOUT 41 Serial Audio Data Output (Output) - Output for two’s complement serial audio data.
SCLK 42 Serial Clock (Input/Output) - Serial clock for the serial audio interface.
LRCK 43 Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the
serial audio data line.
MCLK 44 Master Clock (Input) - Clock source for the ADC’s delta-sigma modulators.
DGND 45 Digital Ground (Input) - Ground reference for the internal digital section.
VD 46 Digital Power (Input) - Positive power for the internal digital section.
INT 47 Interrupt (Output) - Indicates an interrupt condition has occurred.
OVFL 48 Overflow (Output) - Indicates an ADC overflow condition is present.
DS861PP3 7
CS5346
2. PIN COMPATIBILITY - CS5345/CS5346 DIFFERENCES
The CS5346 is p in compatible with the CS5345 and is a drop in replacement for CS5345 applications where
VA = 5 V, VD = 3.3 V, VLS 3.3 V, and VLC 3.3 V. The pinout diagram and table below show the requirements
for the remaining pins when replacing the CS5345 in these designs with a CS5346.
#
CS5345
Pin Name
CS5346
Pin Name
CS5346
Connection for Compatibility
5VLC VLCControl Port Power (Input) -Limited to nominal 5 or 3.3 V.
14 VA VA Analog Power (Input) - Limited to nominal 5 V.
18 TSTO VQ This pin must be left unconnected.
20 TSTI NC This pin should be tied to ground.
30 VA NC This pin may be connected to the analog supply voltage. The decoupling capacitor for the
CS5345 is not required.
31 AGND NC This pin should be connected to ground.
35 TSTO NC This pin may be left unconnected.
36 VLS VLS Serial Audio Interface Power (Input) - Limited to nominal 5 or 3.3 V.
37 TSTI NC This pin should be tied to ground.
46 VD VD Digital Power (Input) - Limited to nominal 3.3 V
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
32
31
30
29
28
27
26
25
VLSSDA/CDOUT
AGND OVFL
SCL/CCLK
AD0/CS
AD1/CDIN
VLC
RST
AIN3A
AIN3B
AIN2A
AIN2B
AIN1A
AIN1B
VA
AFILTB
VQ
TSTO
FILT+
TSTI
AIN4A/MICIN1
AIN4B/MICIN2
AIN5A
AIN5B
AFILTA
TSTO
NC
NC
AGND
AGND
VA
PGAOUTB
PGAOUTA
AIN6B
AIN6A
MICBIAS
INT
VD
DGND
MCLK
LRCK
SCLK
SDOUT
NC
NC
NC
TSTI
CS5345
Compatibility
8DS861PP3
CS5346
3. CHARACTERISTICS AND SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
AGND = DGND = 0 V; All voltages with respect to ground.
ABSOLUTE MAXIMUM RATINGS
AGND = DGND = 0 V All voltages with respect to ground. (Note 1)
Notes: 1. Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
2. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause
SCR latch-up.
Parameters Symbol Min Nom Max Units
DC Power Supplies: Analog
Digital
Logic - Serial Port
Logic - Control Port
VA
VD
VLS
VLC
4.75
3.13
3.13
3.13
5.0
3.3
3.3
3.3
5.25
3.47
5.25
5.25
V
V
V
V
Ambient Operating Temperature (Power Applied) Commercial TA-40 - +85 C
Parameter Symbol Min Max Units
DC Power Supplies: Analog
Digital
Logic - Serial Port
Logic - Control Port
VA
VD
VLS
VLC
-0.3
-0.3
-0.3
-0.3
+6.0
+3.63
+6.0
+6.0
V
V
V
V
Input Current (Note 2) Iin -10 mA
Analog Input Voltage VINA AGND-0.3 VA+0.3 V
Digital Input Voltage Logic - Serial Port
Logic - Control Port
VIND-S
VIND-C
-0.3
-0.3
VLS+0.3
VLC+0.3
V
V
Ambient Operating Temperature (Power Applied) TA-50 +125 C
Storage Temperature Tstg -65 +150 C
DS861PP3 9
CS5346
ANALOG CHARACTERISTICS
Test conditions (unless otherwise specified): VA = 5 V; VD = VLS = VLC = 3.3 V; AGND = DGND = 0 V;
TA= +25° C; Input test signal: 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Fs = 48/96/192 kHz;
PGA gain = 0 dB; All connections as shown in Figure 7 on page 18.
3. Valid for Double- and Quad-Speed Modes only.
4. Referred to the typical A/D full-scale input voltage
5. Valid when the microphone-level inputs are selected.
Parameter Symbol Min Typ Max Unit
Analog-to-Digital Converter Characteristics
Dynamic Range (Line Level Inputs)
A-weighted
unweighted
(Note 3) 40 kHz bandwidth unweighted
97
94
-
103
100
98
-
-
-
dB
dB
dB
Total Harmonic Distortion + Noise (Line Level Inputs) (Note 4)
-1 dB
-20 dB
-60 dB
(Note 3) 40 kHz bandwidth -1 dB
THD+N
-
-
-
-
-95
-80
-40
-92
-89
-
-
-
dB
dB
dB
dB
Dynamic Range (Mic Level Inputs)
A-weighted
(Note 3) unweighted
77
74
83
80
-
-
dB
dB
Total Harmonic Distortion + Noise (Mic Level Inputs) (Note 4)
-1 dB
-20 dB
(Note 3) -60 dB
THD+N -
-
-
-80
-60
-20
-74
-
-
dB
dB
dB
Interchannel Isolation (Line Level Inputs)
(Mic Level Inputs)
-
-
90
80
-
-
dB
dB
A/D Full-scale Input Voltage 0.51*VA 0.57*VA 0.63*VA Vpp
Gain Error --10 %
Interchannel Gain Mismatch - 0.1 - dB
Microphone - Level Input Characteristics
Preamplifier Gain 31
35.5
32
40
33
44.7
dB
V/V
Interchannel Gain Mismatch - 0.1 - dB
Input Impedance (Note 5) -60-k
10 DS861PP3
CS5346
ANALOG CHARACTERISTICS CONT.
6. Referred to the typical A/D Full-Scale Input Voltage.
Parameter Symbol Min Typ Max Unit
Line-Level Input and Programmable Gain Amplifier
Gain Range - 12
-4
-
-
+ 12
+4
dB
V/V
Gain Step Size -0.5-dB
Absolute Gain Step Error - - 0.4 dB
Maximum Input Level - - 0.85*VA Vpp
Input Impedance
Selected inputs
Un-selected inputs
28.8
-
36
-
43.2
38
k
k
Selected Interchannel Input Impedance Mismatch - 5 - %
Analog Outputs
Dynamic Range (Line Level Inputs)
A-weighted
unweighted
98
95
104
101
-
-
dB
dB
Total Harmonic Distortion + Noise (Line Level Inputs) (Note 6)
-1 dB
-20 dB
-60 dB
THD+N -
-
-
-80
-81
-41
-74
-
-
dB
dB
dB
Dynamic Range (Mic Level Inputs)
A-weighted
unweighted
77
74
83
80
-
-
dB
dB
Total Harmonic Distortion + Noise (Mic Level Inputs) (Note 6)
-1 dB
-20 dB
-60 dB
THD+N -
-
-
-74
-60
-20
-68
-
-
dB
dB
dB
Frequency Response 10 Hz to 20 kHz -0.1dB - +0.1dB dB
Analog In to Analog Out Phase Shift - 180 - deg
DC Current draw from a PGAOUT pin IOUT --1A
AC-Load Resistance RL100 - - k
Load Capacitance CL--20pF
DS861PP3 11
CS5346
DIGITAL FILTER CHARACTERISTICS
7. Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 17 to 28) are
normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
8. Response shown is for Fs = 48 kHz.
Parameter (Note 7) Symbol Min Typ Max Unit
Single-Speed Mode
Passband (-0.1 dB) 0 - 0.4896 Fs
Passband Ripple - - 0.035 dB
Stopband 0.5688 - - Fs
Stopband Attenuation 70 - - dB
Total Group Delay (Fs = Output Sample Rate) tgd -12/Fs - s
Double-Speed Mode
Passband (-0.1 dB) 0 - 0.4896 Fs
Passband Ripple - - 0.025 dB
Stopband 0.5604 - - Fs
Stopband Attenuation 69 - - dB
Total Group Delay (Fs = Output Sample Rate) tgd -9/Fs - s
Quad-Speed Mode
Passband (-0.1 dB) 0 - 0.2604 Fs
Passband Ripple - - 0.025 dB
Stopband 0.5000 - - Fs
Stopband Attenuation 60 - - dB
Total Group Delay (Fs = Output Sample Rate) tgd -5/Fs - s
High-Pass Filter Characteristics
Frequency Response -3.0 dB
-0.13 dB (Note 8)
-1
20
-
-
Hz
Hz
Phase Deviation @ 20 Hz (Note 8) -10 -Deg
Passband Ripple -- 0dB
Filter Settling Time 105/Fs s
12 DS861PP3
CS5346
DC ELECTRICAL CHARACTERISTICS
AGND = DGND = 0 V, all voltages with respect to ground. MCLK=12.288 MHz; Fs=48 kHz; Master Mode.
9. Power-Down Mode is defines as RST = Low with all clock and data lines held static and no analog input.
10. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection
Diagram.
Parameter Symbol Min Typ Max Unit
Power Supply Current VA = 5 V
(Normal Operation) VD, VLS, VLC = 3.3 V
IA
ID
-
-
41
23
50
28
mA
mA
Power Supply Current VA = 5 V
(Power-Down Mode) (Note 9) VLS, VLC, VD = 3.3 V
IA
ID
-
-
0.50
0.54
-
-
mA
mA
Power Consumption
(Normal Operation) VA = 5 V
VD, VLS, VLC = 3.3 V
(Power-Down Mode) VA = 5V; VD, VLS, VLC = 3.3 V
-
-
-
-
-
-
205
76
4.2
250
93
-
mW
mW
mW
Power Supply Rejection Ratio (1 kHz) (Note 10) PSRR - 55 - dB
VQ Characteristics
Quiescent Voltage VQ - 0.5 x VA - VDC
Maximum DC Current from VQ IQ-1 -A
VQ Output Impedance ZQ-23 -k
FILT+ Nominal Voltage FILT+ - VA - VDC
Microphone Bias Voltage MICBIAS - 0.8 x VA - VDC
Current from MICBIAS IMB -- 2mA
DS861PP3 13
CS5346
DIGITAL INTERFACE CHARACTERISTICS
Test conditions (unless otherwise specified): AGND = DGND = 0 V; VLS = VLC = 3.3 V.
11. Serial Port signals include: MCLK, SCLK, LRCK, SDOUT.
Control Port signals include: SCL/CCLK, SDA/CDOUT, AD0/CS, AD1/CDIN, RST, INT, OVFL.
Parameters (Note 11) Symbol Min Typ Max Units
High-Level Input Voltage
Serial Port
Control Port
VIH
VIH
0.7xVLS
0.7xVLC
-
-
-
-
V
V
Low-Level Input Voltage Serial Port
Control Port
VIL
VIL
-
-
-
-
0.3xVLS
0.3xVLC
V
V
High-Level Output Voltage at Io= 2 mA Serial Port
Control Port
VOH
VOH
VLS-1.0
VLC-1.0
-
-
-
-
V
V
Low-Level Output Voltage at Io= 2 mA Serial Port
Control Port
VOL
VOL
-
-
-
-
0.4
0.4
V
V
Input Leakage Current Iin --±10A
Input Capacitance - 1 - pF
Minimum OVFL Active Time - - s
106
LRCK
-----------------
14 DS861PP3
CS5346
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT
Logic ‘0’ = DGND = AGND = 0 V; Logic ‘1’ = VLS, CL = 20 pF. (Note 12)
12. See Figure 1 and Figure 2 on page 15.
Parameter Symbol Min Typ Max Unit
Sample Rate Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
Fs
Fs
Fs
8
50
100
-
-
-
50
100
200
kHz
kHz
kHz
MCLK Specifications
MCLK Frequency fmclk 2.048 - 51.200 MHz
MCLK Input Pulse Width High/Low tclkhl 8--ns
Master Mode
LRCK Duty Cycle - 50 - %
SCLK Duty Cycle - 50 - %
SCLK falling to LRCK edge tslr -10 - 10 ns
SCLK falling to SDOUT valid tsdo 0-36ns
Slave Mode
LRCK Duty Cycle 40 50 60 %
SCLK Period
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
tsclkw
tsclkw
tsclkw
-
-
-
-
-
-
ns
ns
ns
SCLK Pulse Width High tsclkh 30 - - ns
SCLK Pulse Width Low tsclkl 48 - - ns
SCLK falling to LRCK edge tslr -10 - 10 ns
SCLK falling to SDOUT valid tsdo 0-36ns
109
128Fs
---------------------
109
64Fs
------------------
109
64Fs
------------------
DS861PP3 15
CS5346
slr
t
SDOUT
SCLK
Output
LRCK
Output
sdo
t
slr
t
SDOUT
SCLK
Input
LRCK
Input
sdo
t
sclkh
tsclkl
t
sclkw
t
Figure 1. Master Mode Serial Audio Port Timing
Figure 2. Slave Mode Serial Audio Port Timing
Figure 3. Format 0, 24-Bit Data Left-Justified
LRCK
SCLK
SDATA +3 +2 +1+5 +4
-1 -2 -3 -4 -5 +3 +2 +1+5 +4
MSB -1 -2 -3 -4
Channel A - Left Channel B - Right
LSBLSBMSB
Figure 4. Format 1, 24-Bit Data I²S
16 DS861PP3
CS5346
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT
Inputs: Logic 0 = DGND = AGND = 0 V, Logic 1 = VLC, CL=30pF.
13. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
Parameter Symbol Min Max Unit
SCL Clock Frequency fscl - 100 kHz
RST Rising Edge to Start tirs 500 - ns
Bus Free Time Between Transmissions tbuf 4.7 - µs
Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - µs
Clock Low time tlow 4.7 - µs
Clock High Time thigh 4.0 - µs
Setup Time for Repeated Start Condition tsust 4.7 - µs
SDA Hold Time from SCL Falling (Note 13) thdd 0-µs
SDA Setup time to SCL Rising tsud 250 - ns
Rise Time of SCL and SDA trc, trd -1µs
Fall Time SCL and SDA tfc, tfd - 300 ns
Setup Time for Stop Condition tsusp 4.7 - µs
Acknowledge Delay from SCL Falling tack 300 1000 ns
tbuf thdst
tlow thdd
thigh
tsud
Stop Start
SDA
SCL
tirs
RST
thdst
trc
tfc
tsust
tsusp
Start Stop
Repeated
trd tfd
tack
Figure 5. Control Port Timing - I²C Format
DS861PP3 17
CS5346
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT
Inputs: Logic 0 = DGND = AGND = 0 V, Logic 1 = VLC, CL=30pF.
14. Data must be held for sufficient time to bridge the transition time of CCLK.
15. For fsck <1 MHz.
Parameter Symbol Min Max Units
CCLK Clock Frequency fsck -6.0MHz
RST Rising Edge to CS Falling tsrs 500 - ns
CS High Time Between Transmissions tcsh 1.0 - s
CS Falling to CCLK Edge tcss 20 - ns
CCLK Low Time tscl 66 - ns
CCLK High Time tsch 66 - ns
CDIN to CCLK Rising Setup Time tdsu 40 - ns
CCLK Rising to DATA Hold Time (Note 14) tdh 15 - ns
CCLK Falling to CDOUT Stable tpd -50ns
Rise Time of CDOUT tr1 -25ns
Fall Time of CDOUT tf1 -25ns
Rise Time of CCLK and CDIN (Note 15) tr2 - 100 ns
Fall Time of CCLK and CDIN (Note 15) tf2 - 100 ns
tr2 tf2
tdsu tdh
tsch
tscl
CS
CCLK
CDIN
tcss
tpd
CDOUT
tcsh
RST tsrs
Figure 6. Control Port Timing - SPI Format
18 DS861PP3
CS5346
4. TYPICAL CONNECTION DIAGRAM
VLS
0.1 µF
+3.3V
to +5V
DGND
VLC
0.1 µF
+3.3V
to +5V
SCL/CCLK
SDA/CDOUT
AD1/CDIN
RST
2 k
See Note 1
AD0/CS
Notes:
1. Resistors are required for I²C control port
operation.
2. The value of RL is dictated by the microphone
cartridge.
3. See Section 5.5.1.
Micro-
Controller
Digital Audio
Capture LRCK
SDOUT
MCLK
SCLK
PGAOUTA
PGAOUTB
2.2nF
AFILTA
AFILTB
OVFL
2.2nF
3.3 µF
3.3 µF
47 µF
0.1 µF
VQ
FILT+
10 µF
AGND
2 k
INT
47 µF
AIN1A Left Analog Input 1
AIN1B Right Analog Input 1
AIN2A Left Analog Input 2
AIN2B Right Analog Input 2
AIN3A Left Analog Input 3
AIN3B Right Analog Input 3
AIN4A/MICIN1 Left Analog Input 4
AIN4B/MICIN2 Right Analog Input 4
AIN5A Left Analog Input 5
AIN5B Right Analog Input 5
AIN6A Left Analog Input 6
AIN6B Right Analog Input 6
MICBIAS
AGND
0.1 µF
NC
NC
NC
NC
NC
NC
NC
NC
NC
10 µF
+3.3V
0.1 µF
10 µF 0.1 µF
VAVD
+5V
RLSee Note 2
CS5346 Analog Input 3
Analog Input 3
Analog Input 3
Analog Input 3
Analog Input 3
Analog Input 3
Analog Input 3
Analog Input 3
Analog Input 3
Analog Input 3
Analog Input 3
Analog Input 3
VQ
AFILTA and AFILTB
capacitors must be C0G or
equivalent
Figure 7. Typical Connection Diagram
Section 5.5.1.
DS861PP3 19
CS5346
5. APPLICATIONS
5.1 Recommended Power-Up Sequence
1. Hold RST low until the power supply, MCLK, and LRCK are stable. In this state, the Control Port is reset
to its default settings.
2. Bring RST high. The device will remain in a low power state with the PDN bit set by default. The control
port will be accessible.
3. The desired register settings can be loaded while the PDN bit remains set.
4. Clear the PDN bit to initiate the power-up sequence.
5.2 System Clocking
The CS5346 will operate at sa mpling frequencies from 8 kHz to 200 kHz. This range is div ided into three
speed modes as shown in Table 1.
5.2.1 Master Clock
MCLK/LRCK must maintain an integer ratio as shown in Table 2. The LRCK frequency is equal to Fs, the
frequency at which audio samples for each channel are clocked out of the device. The FM bits (See “Func-
tional Mode (Bits 7:6)” on page 29.) and the MCLK Freq bits (See “MCLK Frequency - Address 05h” on
page 30.) configure the device to generate the proper clocks in Master Mode and receive the proper
clocks in Slave Mode. Table 2 illustrates several standard audio sample rates and the required MCLK and
LRCK frequencies.
Mode Sampling Frequency
Single-Speed 8-50 kHz
Double-Speed 50-100 kHz
Quad-Speed 100-200 kHz
Table 1. Speed Modes
LRCK
(kHz)
MCLK (MHz)
* 64x * 96x 128x 192x 256x 384x 512x 768x 1024x
32 ----8.1920 12.2880 16.3840 24.5760 32.7680
44.1 ----11.2896 16.9344 22.5792 33.8680 45.1584
48 ----12.2880 18.4320 24.5760 36.8640 49.1520
64 -- 8.1920 12.2880 16.3840 24.5760 32.7680 - -
88.2 -- 11.2896 16.9344 22.5792 33.8680 45.1584 - -
96 -- 12.2880 18.4320 24.5760 36.8640 49.1520 - -
128 8.1920 12.2880 16.3840 24.5760 32.7680 - - - -
176.4 11.2896 16.9344 22.5792 33.8680 45.1584 - - - -
192 12.2880 18.4320 24.5760 36.8640 49.1520 - - - -
Mode QSM DSM SSM
* Only available in master mode.
Table 2. Common Clock Frequencies
20 DS861PP3
CS5346
5.2.2 Master Mode
As a clock master, LRCK and SCLK will operate as outputs. LRCK and SCLK are internally derived from
MCLK with LRCK equal to Fs and SCLK equal to 64 x Fs as shown in Figure 8.
5.2.3 Slave Mode
In Slave Mode, SCLK and LRCK operate as inputs. The Left/Right clock signal must be equal to the sam-
ple rate, Fs, and must be synchronously derived from the supplied master clock, MCLK.
The serial bit clock, SCLK, must be synchronously derived from the master clock, MCLK, and be equal to
128x, 64x or 48x Fs, depending on the desired speed mode. Refer to Table 3 for required clock ratios.
5.3 High-Pass Filter and DC Offset Calibration
When using operational amplifiers in the input circuitry driving the CS5346, a small DC offset may be driven
into the A/D converter. The CS5346 includes a high-pass filter after the decimator to remove any DC offset
which could result in recording a DC level, possibly yielding clicks when switching between devices in a mul-
tichannel system.
The high-pass filter continuously subtracts a measure of the DC offset fro m the output of the decimation
filter. If the HPFFreeze bit (See “High-Pass Filter Freeze (Bit 1)” on page 29.) is set during normal operation,
the current value of the DC offset for the each channel is frozen and this DC offset will continue to be sub-
tracted from the conversion result. This feature makes it possible to perform a system DC offset calibration
by:
1. Running the CS5346 with the high-pass filter enabled until the filter settles. See the Digital Filter Char-
acteristics section for filter settling time.
2. Disabling the high-pass filter and freezing the stored DC offset.
A system calibration performed in this way will eliminate offsets anywhere in the signal path between the
calibration point and the CS5346.
Single-Speed Double-Speed Quad-Speed
SCLK/LRCK Ratio 48x, 64x, 128x 48x, 64x 48x, 64x
Table 3. Slave Mode Serial Bit Clock Ratios
÷256
÷128
÷64
÷4
÷2
÷1
00
01
10
00
01
10
LRCK
SCLK
000
001
010
÷1
÷1.5
÷2
011
100
÷3
÷4
MCLK FM Bits
MCLK Freq Bits
Figure 8. Master Mode Clocking
DS861PP3 21
CS5346
5.4 Analog Input Multiplexer, PGA, and Mic Gain
The CS5346 contains a stereo 6-to-1 analog input multiplexer followed by a programmable gain amplifier
(PGA). The input multiplexer can select one of six possible stereo analog input sources and route it to the
PGA. Analog inputs 4A and 4B are able to insert a +32 dB (+40x) gain stage before the input multiplexer,
allowing them to be used for microphone-level signals without the need for any external gain. The PGA
stage provides 12 dB (4x) adjustment in 0.5 dB steps. Figure 9 shows the architecture of the input multi-
plexer, PGA, and microphone gain stages.
The ““Analog Input Selection (Bits 2:0)” on page 32” outlines the bit settings necessary to control the input
multiplexer and mic gain. “Channel B PGA Control - Address 07h” on page 30 and “Channel A PGA Control
- Address 08h” on page 31 outline the register settings necessary to control the PGA. By default, line-
level input 1 is selected, and the PGA is set to 0 dB.
5.5 Input Connections
The analog modulator samples the input at 6.144 MHz (MCLK=12.288 MHz). The digital filter will reject sig-
nals within the stopband of the filter. However, there is no rejection for input signals which are
(n 6.144 MHz) the digital passband frequency, where n=0,1,2,... Refer to the Typical Connection Diagram
for the recommended analog input circuit that will attenuate noise energy at 6.144 MHz. The use of capac-
itors which have a lar ge voltage coefficient (such as ge neral-purpose ceramics) must be avoided since
these can degrade signal linearity. Any unused analog input pairs should be left unconnected.
5.5.1 Analog Input Configuration for 1 VRMS Input Levels
The CS5346 PGA, excluding the input multiplexer, is shown in Figure 10 with nominal component values.
Interfacing to this circuit is a relatively simple matter and several options are available. The simplest option
is shown in Figure 11. However, it may be advantageous in some applications to provide a low-pass filter
prior to the PGA to prevent radio frequency interference within the amplifier. The circuit shown in Figure 12
MUX
+32 dB
AIN1A
AIN2A
AIN3A
AIN4A/MICIN1
AIN5A
AIN6A
PGA
MUX
+32 dB
AIN1B
AIN2B
AIN3B
AIN4B/MICIN2
AIN5B
AIN6B
Analog Input
Selection Bits
Channel A
PGA Gain Bits
Channel B
PGA Gain Bits
Out to ADC
Channel A
Out to ADC
Channel B
PGA
Figure 9. Analog Input Architecture
22 DS861PP3
CS5346
demonstrates a simple solution. The 1800 pF capacitors in the low-pass filter should be C0G or equivalent
to avoid distortion issues
.
5.5.2 Analog Input Configuration for 2 VRMS Input Levels
The CS5346 can also be easily configured to support an external 2 VRMS input signal, as shown in
Figure 13. In this configuration, the 2 VRMS input signal is attenuated to 1.5 VRMS at the analog input with
the external 12 k resistor and the input impedance to the network is increased to 48 k. The PGA gain
must also be configured to attenuate the 1.5 VRMS at the input pin to the 1.0 VRMS maximum A/D input level
to prevent clipping in the ADC.
36 k
VCM
9 k to 144 k
A/ D Input
-
+
Analog Input
CS5346
Figure 10. CS5346 PGA
36 k
VCM
9 k to 144 k
A/ D Input
-
+
2. 2 µF
100 k
Analog Input
CS5346
Figure 11. 1 VRMS Input Circuit
36 k
V
CM
9 k to 144 k
A/D Input
2.2 µF
1800 pF
100 k
100
-
+
Analog Input
Figure 12. 1 VRMS Input Circuit with RF Filtering
36 k
VCM
9 k to 144 k
A/ D Input
-
+
2. 2 µF
18 pF
100 k
12 k
Analog Input
CS5346
Figure 13. 2 VRMS Input Circuit
DS861PP3 23
CS5346
5.6 PGA Auxiliary Analog Output
The CS5346 includes an auxiliary analog output through the PGAOUT pins. These pins can be configured
to output the analog input to the ADC as selected by the input MUX and gained or attenuated with the PGA,
or alternatively, they may be set to high impedance. See the “PGAOut Source Select (Bit 6)” on page 30 for
information on configuring the PGA auxiliary analog output.
The PGA auxiliary analog output can source very little current. As current from the PGAOUT pins increases,
distortion will increase. For this reason, a high-input impedance buffer must be used on the PGAOUT pins
to achieve full performance. An example buffer for PGAOUT is provided on the CDB5346 for reference. Re-
fer to the table in “DC Electrical Characteristics” on page 12 for acceptable loading conditions.
5.7 Control Port Description and Timing
The control port is used to access the registers, allowing the CS5346 to be configured for the desired oper-
ational modes and formats. The operation of the control port may be completely asynchronous with respect
to the audio sample rates. However, to avoid potential interference problems, the control port pins should
remain static if no operation is required.
The control port has two modes: SPI and I²C, with the CS5346 acting as a slave device. SPI Mode is se-
lected if there is a high-to-low transition on the AD0/CS pin, after the RST pin has been brought high. I²C
Mode is selected by connecting the AD0/CS pin through a resistor to VLC or DGND, thereby permanently
selecting the desired AD0 bit address state.
5.7.1 SPI Mode
In SPI Mode, CS is the chip-select signal; CCLK is the control port bit clock (input into the CS5346 from
the microcontroller); CDIN is the input data line from the microcontroller; CDOUT is the output data line
to the microcontroller. Data is clocked in on the rising edge of CCLK and out on the falling edge.
Figure 14 shows the operation of the control port in SPI Mode. To write to a register, bring CS low. The
first seven bits on CDIN form the chip address and must be 1001111. The eighth bit is a read/write indi-
cator (R/W), which should be low to write. The next eight bits form the Memory Address Pointer (MAP),
which is set to the address of the register that is to be updated. The next eight bits are the data that will
be placed into the register designated by the MAP. During writes, the CDOUT output stays in the Hi-Z
state. It may be externally pulled high or low with a 47 k resistor, if desired.
To read a register, the MAP has to be set to the correct address by executing a partial write cycle which
finishes (CS high) immediately after the MAP byte. To begin a read, bring CS low, send out the chip ad-
24 DS861PP3
CS5346
dress and set the read/write bit (R/W) high. The next falling edge of CCLK will clock out the MSB of the
addressed register (CDOUT will leave the high-impedance state).
For both read and write cycles, the memory address pointer will automatically increment following each
data byte in order to facilitate block reads and writes of successive registers.
5.7.2 I²C Mode
In I²C Mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL.
There is no CS pin. Pins AD0 and AD1 form the two least-significant bits of the chip address and should
be connected through a resistor to VLC or DGND as desired. The state of the pins is sensed while the
CS5346 is being reset.
The signal timings for a read and write cycle are shown in Figure 15 and Figure 16. A Start condition is
defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while
the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS5346
after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low for a write).
The upper 5 bits of the 7-bit address field are fixed at 10011. To communicate with a CS5346, the chip
address field, which is the first byte sent to the CS5346, should match 10011 followed by the settings of
the AD1 and AD0. The 8th bit of the address is the R/W bit. If the operation is a write, the next byte is the
Memory Address Pointer (MAP) which selects the register to be read or written. If the operation is a read,
the contents of the register pointed to by the MAP will be output. Following each data byte, the memory
address pointer will automatically increment to facilitate block reads and writes of successive registers.
Each byte is separated by an acknowledge bit. The ACK bit is output from the CS5346 after each input
byte is read, and is input to the CS5346 from the microcontroller after each transmitted byte.
MAP
MSB LSB
DATA
byte 1 byte n
R/W R/W
ADDRESS
CHIP
ADDRESS
CHIP
CDIN
CCLK
CS
CDOUT MSB LSB MSB LSB
1001111
1001111
MAP = Memory Address Pointer, 8 bits, MSB first
High Impedance
Figure 14. Control Port Timing in SPI Mode
4 5 6 7 24 25
SCL
CHIP ADDRESS (WRITE) MAP BYTE DATA DATA +1
START
ACK
STOP
ACKACKACK
1 0 0 1 1 AD1 AD0 0
SDA 6 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 1 0
0 1 2 3 8 9 12 16 17 18 19 10 11 13 14 15 27 28
26
DATA +n
Figure 15. Control Port Timing, I²C Write
DS861PP3 25
CS5346
Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown
in Figure 16, the write operation is aborted after the acknowledge for the MAP byte by sending a stop con-
dition. The following pseudocode illustrates an aborted write operation followed by a read operation.
• Send start condition.
• Send 10011xx0 (chip address & write operation).
• Receive acknowledge bit.
• Send MAP byte.
• Receive acknowledge bit.
• Send stop condition, aborting write.
• Send start condition.
• Send 10011xx1(chip address & read operation).
• Receive acknowledge bit.
• Receive byte, contents of selected register.
• Send acknowledge bit.
• Send stop condition.
5.8 Interrupts and Overflow
The CS5346 has a comprehensive interrupt capability. The INT output pin is intended to drive the interrupt
input pin on the host microcontroller. The INT pin may function as either an active high CMOS driver or
an active-low, open-drain driver (see “Active High/Low (Bit 0)” on page 35). When configured as active
low open-drain, the INT pin has no active pull-up transistor, allowing it to be used for wired-OR hook-ups
with multiple peripherals connected to the microcontroller interrupt input pin. In this configuration, an ex-
ternal pull-up resistor must be placed on the INT pin for proper operation.
Many conditions can cause an interrupt, as listed in the interrupt status register descriptions (see “Inter-
rupt Status - Address 0Dh” on page 35). Each source may be masked off through mask register bits. In
addition, Each source may be set to rising edge, falling edge, or level-sensitive. Combined with the option
of level-sensitive or edge-sensitive modes within the microcontroller, many different configurations are
possible, depending on the needs of the equipment designer.
The CS5346 also has a dedicated overflow output. The OVFL pin functions as active low open drain and
has no active pull-up transistor, thereby requiring an external pull-up resistor. The OVFL pin outputs an
OR of the ADCOverflow and ADCUnderflow conditions available in the Interrupt Status register; however,
these conditions do not need to be unmasked for proper operation of the OVFL pin.
SCL
CHIP ADDRESS (WRITE) MAP BYTE DATA DATA +1
START
ACK
STOP
ACK
ACK
ACK
1 0 0 1 1 AD1 AD0 0
SDA 1 0 0 1 1 AD1 AD0 1
CHIP ADDRESS (READ)
START
7 6 5 4 3 2 1 0 7 0 7 0 7 0
NO
16 8 9 12 13 14 15 4 5 6 7 0 1 20 21 22 23 24 26 27 28
2 3 10 11 17 18 19 25
ACK
DATA + n
STOP
Figure 16. Control Port Timing, I²C Read
26 DS861PP3
CS5346
5.9 Reset
When RST is low, the CS5346 enters a low-power mode and all internal states are reset, including the con-
trol port and registers, the outputs are muted. When RST is high, the control port becomes operational, and
the desired settings should be loaded into the control registers. Writing a 0 to the PDN bit in the Power Con-
trol register will then cause the part to leave the low-power state and begin operation.
The delta-sigma modulators settle in a matter of microseconds after the analog section is powered, either
through the application of power or by setting the RST pin high. However, the voltage reference will take
much longer to reach a final value due to the presence of external capacitance on the FILT+ pin. During this
voltage reference ramp delay, SDOUT will be automatically muted.
It is recommended that RST be activated if the analog or digital supplies drop below the recommended op-
erating condition to prevent power-glitch-related issues.
5.10 Synchronization of Multiple Devices
In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To
ensure synchronous sampling, the mast er clocks and left/ right clocks must be the same f or all of the
CS5346s in the system. If only one master clock source is needed, one solution is to place one CS5346 in
Master Mode, and slave all of the other CS5346s to the one master. If multiple master clock sources are
needed, a possible solution would be to supply all cl ocks from the same external source and time the
CS5346 reset with the inactive edge of master clock. This will ensure that all converters begin sampling on
the same clock edge.
5.11 Grounding and Power Supply Decoupling
As with any high-resolution converter, the CS5346 requires careful attention to power supply and grounding
arrangements if its potential performance is to be realized. Figure 7 shows the recommended power ar-
rangements, with VA connected to a clean supply. VD, which powers the digital filter, may be run from the
system logic supplies (VLS or VLC). Power supply decoupling capacitors should be as near to the CS5346
as possible, with the low value ceramic capacitor being the nearest. All signals, especially clocks, should be
kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+
and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the electrical path
from FILT+ and AGND. The CS5346 evaluation board demonstrates the optimum layout and power supply
arrangements. To minimize digital noise, connect the CS5346 digital outputs only to CMOS inputs.
DS861PP3 27
CS5346
6. REGISTER QUICK REFERENCE
This table shows the register names and their associated default values.
Addr Function 7 6 5 4 3 2 1 0
01h Chip ID PART3 PART2 PART1 PART0 REV3 REV2 REV1 REV0
pg. 28 1100 x x x x
02h Power Control Freeze Reserved Reserved Reserved PDN_MIC PDN_ADC Reserved PDN
pg. 28 0000 0 0 0 1
03h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
0000 1 0 0 0
04h ADC Control FM1 FM0 Reserved DIF Reserved Mute HPFFreeze M/S
pg. 29 0000 0 0 0 0
05h MCLK
Frequency
Reserved MCLK
Freq2
MCLK
Freq1
MCLK
Freq0
Reserved Reserved Reserved Reserved
pg. 30 0000 0 0 0 0
06h PGAOut
Control
Reserved PGAOut Reserved Reserved Reserved Reserved Reserved Reserved
pg. 30 0100 0 0 0 0
07h PGA Ch B
Gain Control
Reserved Reserved Gain5 Gain4 Gain3 Gain2 Gain1 Gain0
pg. 30 0000 0 0 0 0
08h PGA Ch A
Gain Control
Reserved Reserved Gain5 Gain4 Gain3 Gain2 Gain1 Gain0
pg. 31 0000 0 0 0 0
09h Analog Input
Control
Reserved Reserved Reserved PGASoft PGAZero Sel2 Sel1 Sel0
pg. 31 0001 1 0 0 1
0Ah -
0Bh
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
0000 0 0 0 0
0Ch Active Level
Control
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Active_H/L
pg. 32 1100 0 0 0 0
0Dh Interrupt Status Reserved Reserved Reserved Reserved ClkErr Reserved Ovfl Undrfl
pg. 32 0000 0 0 0 0
0Eh Interrupt Mask Reserved Reserved Reserved Reserved ClkErrM Reserved OvflM UndrflM
pg. 33 0000 0 0 0 0
0Fh Interrupt Mode
MSB
Reserved Reserved Reserved Reserved ClkErr1 Reserved Ovfl1 Undrfl1
pg. 33 0000 0 0 0 0
10h Interrupt Mode
LSB
Reserved Reserved Reserved Reserved ClkErr0 Reserved Ovfl0 Undrfl0
pg. 33 0000 0 0 0 0
28 DS861PP3
CS5346
7. REGISTER DESCRIPTION
7.1 Chip ID - Register 01h
Function:
This register is Read-Only. Bits 7 through 4 are the part number ID, which is 1100b, and the remaining bits
(3 through 0) indicate the device revision as shown in Table 4 below.
7.2 Power Control - Address 02h
7.2.1 Freeze (Bit 7)
Function:
This function allows modifications to be made to certain control port bits without the changes taking effect
until the Freeze bit is disabled. To make multiple changes to these bits take effect simultaneously, set the
Freeze bit, make all changes, then clear the Freeze bit. The bits affected by the Freeze function are listed
in Table 5.
7.2.2 Power-Down MIC (Bit 3)
Function:
The microphone preamplifier block will enter a low-power state whenever this bit is set.
7.2.3 Power-Down ADC (Bit 2)
Function:
The ADC pair will remain in a reset state whenever this bit is set.
7.2.4 Power-Down Device (Bit 0)
Function:
The device will enter a low-power state whenever this bit is set. The power-down bit is set by default and
must be cleared before normal operation can occur. The contents of the control registers are retained
when the device is in power-down.
76543210
PART3 PART2 PART1 PART0 REV3 REV2 REV1 REV0
REV[3:0] Revision
0000 A1
Table 4. Device Revision
76543210
Freeze Reserved Reserved Reserved PDN_MIC PDN_ADC Reserved PDN
Name Register Bit(s)
Mute 04h 2
Gain[5:0] 07h 5:0
Gain[5:0] 08h 5:0
Table 5. Freeze-able Bits
DS861PP3 29
CS5346
7.3 ADC Control - Address 04h
7.3.1 Functional Mode (Bits 7:6)
Function:
Selects the required range of sample rates.
7.3.2 Digital Interface Format (Bit 4)
Function:
The required relationship between LRCK, SCLK and SDOUT is defined by the Digital Interface Format
bit. The options are detailed in Table 7 and may be seen in Figure 3 and Figure 4.
7.3.3 Mute (Bit 2)
Function:
When this bit is set, the serial audio output of the both channels is muted.
7.3.4 High-Pass Filter Freeze (Bit 1)
Function:
When this bit is set, the internal high-pass filter is disabled. The current DC offset value will be frozen and
continue to be subtracted from the conversion result. See “High-Pass Filter and DC Offset Calibration” on
page 20.
7.3.5 Master / Slave Mode (Bit 0)
Function:
This bit selects either master or slave operation for the serial audio port. Setting this bit selects Master
Mode, while clearing this bit selects Slave Mode.
76543210
FM1 FM0 Reserved DIF Reserved Mute HPFFreeze M/S
FM1 FM0 Mode
0 0 Single-Speed Mode: 8 to 50 kHz sample rates
0 1 Double-Speed Mode: 50 to 100 kHz sample rates
1 0 Quad-Speed Mode: 100 to 200 kHz sample rates
11Reserved
Table 6. Functional Mode Selection
DIF Description Format Figure
0 Left-Justified (default) 0 3
1I²S 14
Table 7. Digital Interface Formats
30 DS861PP3
CS5346
7.4 MCLK Frequency - Address 05h
7.4.1 Master Clock Dividers (Bits 6:4)
Function:
Sets the frequency of the supplied MCLK signal. See Table 8 for the appropriate settings.
7.5 PGAOut Control - Address 06h
7.5.1 PGAOut Source Select (Bit 6)
Function:
This bit is used to configure the PGAOut pins to be either high impedance or PGA outputs. Refer to
Table 9.
7.6 Channel B PGA Control - Address 07h
7.6.1 Channel B PGA Gain (Bits 5:0)
Function:
See “Channel A PGA Gain (Bits 5:0)” on page 31.
76543210
Reserved MCLK
Freq2
MCLK
Freq1
MCLK
Freq0 Reserved Reserved Reserved Reserved
MCLK Divider MCLK Freq2 MCLK Freq1 MCLK Freq0
÷1 000
÷1.5 001
÷2 010
÷3 011
÷4 100
Reserved 101
Reserved 11x
Table 8. MCLK Frequency
76543210
Reserved PGAOut Reserved Reserved Reserved Reserved Reserved Reserved
PGAOut PGAOutA & PGAOutB
0 High Impedance
1 PGA Output
Table 9. PGAOut Source Selection
76543210
Reserved Reserved Gain5 Gain4 Gain3 Gain2 Gain1 Gain0
DS861PP3 31
CS5346
7.7 Channel A PGA Control - Address 08h
7.7.1 Channel A PGA Gain (Bits 5:0)
Function:
Sets the gain or attenuation for the ADC input PGA stage. The gain may be adjusted from -12 dB to
+12 dB in 0.5 dB steps. The gain bits are in two’s complement with the Gain0 bit set for a 0.5 dB step.
Register settings outside of the ±12 dB range are reserved and must not be used. See Table 10 for ex-
ample settings.
7.8 ADC Input Control - Address 09h
7.8.1 PGA Soft Ramp or Zero Cross Enable (Bits 4:3)
Function:
Soft Ramp Enable
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramp-
ing, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.
See Table 11.
Zero Cross Enable
Zero Cross Enable dictates that signal-level changes, either by attenuation changes or muting, will occur
on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a time-
out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal
does not encounter a zero crossing. The zero cross function is independently monitored and implemented
for each channel. See Table 11.
Soft Ramp and Zero Cross Enable
Soft Ramp and Zero Cross Enable dictate that signal-level changes, either by attenuation changes or mut-
ing, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will
occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sam-
ple rate) if the signal does not encounter a zero crossing. The zero cross function is independently mon-
itored and implemented for each channel. See Table 11.
76543210
Reserved Reserved Gain5 Gain4 Gain3 Gain2 Gain1 Gain0
Gain[5:0] Setting
101000 -12 dB
000000 0 dB
011000 +12 dB
Table 10. Example Gain and Attenuation Settings
76543210
Reserved Reserved Reserved PGASoft PGAZero Sel2 Sel1 Sel0
32 DS861PP3
CS5346
7.8.2 Analog Input Selection (Bits 2:0)
Function:
These bits are used to select the input source for the PGA and ADC. Please see Table 12.
7.9 Active Level Control - Address 0Ch
7.9.1 Active High/ Low (Bit 0)
Function:
When this bit is set, the INT pin functions as an active high CMOS driver.
When this bit is cleared, the INT pin functions as an active low open drain driver and will require an exter-
nal pull-up resistor for proper operation.
7.10 Status - Address 0Dh
For all bits in this register, a ‘1’ means the associated condition has occurred at least once since the register
was last read. A ‘0’ means the associated condition has NOT occurred since the last reading of the register.
Status bits that are masked off in the associated mask register will always be ‘0’ in this register. This register
defaults to 00h.
PGASoft PGAZeroCross Mode
0 0 Changes to affect immediately
0 1 Zero Cross enabled
1 0 Soft Ramp enabled
1 1 Soft Ramp and Zero Cross enabled (default)
Table 11. PGA Soft Cross or Zero Cross Mode Selection
Sel2 Sel1 Sel0 PGA/ADC Input
0 0 0 Microphone-Level Inputs (+32 dB Gain Enabled)
0 0 1 Line-Level Input Pair 1
0 1 0 Line-Level Input Pair 2
0 1 1 Line-Level Input Pair 3
1 0 0 Line-Level Input Pair 4
1 0 1 Line-Level Input Pair 5
1 1 0 Line-Level Input Pair 6
1 1 1 Reserved
Table 12. Analog Input Multiplexer Selection
76543210
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Active_H/L
76543210
Reserved Reserved Reserved Reserved ClkErr Reserved Ovfl Undrfl
DS861PP3 33
CS5346
7.10.1 Clock Error (Bit 3)
Function:
Indicates the occurrence of a clock error condition.
7.10.2 Overflow (Bit 1)
Function:
Indicates the occurrence of an ADC overflow condition.
7.10.3 Underflow (Bit 0)
Function:
Indicates the occurrence of an ADC underflow condition.
7.11 Status Mask - Address 0Eh
Function:
The bits of this register serve as a mask for the Status sources found in the register “Status - Address 0Dh”
on page 32. If a mask bit is set to 1, the error is unmasked, meaning that its occurrence will affect the status
register. If a mask bit is set to 0, the error is masked, meaning that its occurrence will not affect the status
register. The bit positions align with the corresponding bits in the Status register.
7.12 Status Mode MSB - Address 0Fh
7.13 Status Mode LSB - Address 10h
Function:
The two Status Mode registers form a 2-bit code for each Status register function. There are three ways to
update the Status register in accordance with the status condition. In the Rising-Edge Active Mode, the sta-
tus bit becomes active on the arrival of the condition. In the Falling-Edge Active Mode, the status bit be-
comes active on the removal of th e condition. In L evel-Active Mode, the status bit is active during the
condition.
00 - Rising edge active
01 - Falling edge active
10 - Level active
11 - Reserved
76543210
Reserved Reserved Reserved Reserved ClkErrM Reserved OvflM UndrflM
76543210
Reserved Reserved Reserved Reserved ClkErr1 Reserved Ovfl1 Undrfl1
Reserved Reserved Reserved Reserved ClkErr0 Reserved Ovfl0 Undrfl0
34 DS861PP3
CS5346
8. PARAMETER DEFINITIONS
Dynamic Range
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with
a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full scale. This
technique ensures that the distortion components are below the noise level and do not affect the measure-
ment. This measurement technique has been accepted by the Au dio Engineering Society, AES17-1991,
and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels.
Total Harmonic Distortion + Noise
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured
at -1 and -20 dBFS as suggested in AES17-1991 Annex A.
Frequency Response
A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at
1 kHz. Units in decibels.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with no signal to the input under test and a full-scale signal applied to the other channel. Units in deci-
bels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
DS861PP3 35
CS5346
9. FILTER PLOTS
Figure 17. Single-Speed Stopband Rejection Figure 18. Single-Speed Stopband Rejection
Figure 19. Single-Speed Transition Band (Detail) Figure 20. Single-Speed Passband Ripple
Figure 21. Double-Speed Stopband Rejection Figure 22. Double-Speed Stopband Rejection
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.0 0.1 0.2 0 .3 0 .4 0 .5 0 .6 0.7 0 .8 0.9 1.0
Frequency (normalized to Fs)
Amplitude (dB)
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60
Frequency (normalized to Fs)
Amplitude (dB)
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55
Frequency (normalized to Fs)
Amplitude (dB)
-0.10
-0.08
-0.06
-0.04
-0.02
0.00
0.02
0.04
0.06
0.08
0.10
0 0 .05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0 .45 0.5
Frequency (normalized to Fs)
Amplitude (dB)
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.0 0.1 0.2 0 .3 0 .4 0 .5 0 .6 0.7 0.8 0.9 1.0
Frequency (normalized to Fs)
Amplitude (dB)
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60
Frequency (normalized to Fs)
Amplitude (dB)
36 DS861PP3
CS5346
Figure 23. Double-Speed Transition Band (Detail) Figure 24. Double-Speed Passband Ripple
Figure 25. Quad-Speed Stopband Rejection Figure 26. Quad-Speed Stopband Rejection
Figure 27. Quad-Speed Transition Band (Detail) Figure 28. Quad-Speed Passband Ripple
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
0.46 0.47 0.48 0.49 0.50 0.51 0.52
Frequency (normalized to Fs)
Amplitude (dB)
-0.10
-0.08
-0.06
-0.04
-0.02
0.00
0.02
0.04
0.06
0.08
0.10
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Frequency (normalized to Fs)
Amplitude (dB)
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.0 0.1 0.2 0 .3 0 .4 0 .5 0 .6 0.7 0.8 0.9 1.0
Frequency (normalized to Fs)
Amplitude (dB)
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85
Frequency (normalized to Fs)
Amplitude (dB)
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Frequency (normalized to Fs)
Amplitude (dB)
-0.10
-0.08
-0.06
-0.04
-0.02
0.00
0.02
0.04
0.06
0.08
0.10
0.00 0.03 0.05 0.08 0.10 0.13 0.15 0.18 0.20 0.23 0.25 0.28
Frequency (normalized to Fs)
Amplitude (dB)
DS861PP3 37
CS5346
10.PACKAGE DIMENSIONS
11.THERMAL CHARACTERISTICS AND SPECIFICATIONS
1. JA is specified according to JEDEC specifications for multi-layer PCBs.
INCHES MILLIMETERS
DIM MIN NOM MAX MIN NOM MAX
A --- 0.055 0.063 --- 1.40 1.60
A1 0.002 0.004 0.006 0.05 0.10 0.15
B 0.007 0.009 0.011 0.17 0.22 0.27
D 0.343 0.354 0.366 8.70 9.0 BSC 9.30
D1 0.272 0.28 0.280 6.90 7.0 BSC 7.10
E 0.343 0.354 0.366 8.70 9.0 BSC 9.30
E1 0.272 0.28 0.280 6.90 7.0 BSC 7.10
e* 0.016 0.020 0.024 0.40 0.50 BSC 0.60
L 0.018 0.24 0.030 0.45 0.60 0.75
0.000° 4° 7.000° 0.00° 4° 7.00°
* Nominal pin pitch is 0.50 mm *Controlling dimension is mm. *JEDEC Designation: MS022
Parameters Symbol Min Typ Max Units
Package Thermal Resistance (Note 1) 48-LQFP JA
JC
-
-
48
15
-
-
°C/Watt
°C/Watt
Allowable Junction Temperature --125
C
48L LQFP PACKAGE DRAWING
E1
E
D1
D
1
e
L
B
A1
A
38 DS861PP3
CS5346
12.ORDERING INFORMATION
13.REVISION HISTORY
Product Description Package Pb-Free Grade Temp Range Container Order #
CS5346 24-bit, 192 kHz
Stereo Audio ADC 48-LQFP Yes Commercial -40° to +85° C Tray CS5346-CQZ
Tape & Reel CS5346-CQZR
CDB5346 CS5346 Evaluation Board No - - - CDB5346
Release Changes
PP1
-Updated Title
-Added text to Section 2. on page 7
-Added V/V representations for PGA and MIC gain specifications
-Updated Automotive THD+N and DNR limits
-Added reference to CDB5346 in Section 5.6 on page 23
PP2 -Added note 3 and note for AFILTA/AFILTB capacitors in Figure 7.
PP3 -Removed references to automotive grade parts.
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find the one nearest you, go to www.cirrus.com
IMPORTANT NOTICE
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is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before
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