Freescale Semiconductor, Inc. MOTOROLA Order number: MC100ES7011H Rev 0, 05/2004 SEMICONDUCTOR TECHNICAL DATA DATA SHEET Product Preview MC100ES7011H MC100ES7011H Low Voltage 1:2 Differential HSTL/LVDS to LVDS Clock Low Voltage 1:2 Differential HSTL/ Fanout Buffer LVDS to LVDS Clock Fanout Buffer Freescale Semiconductor, Inc... The MC100ES7011H is a low voltage 1:2 Differential HSTL/LVDS to LVDS clock fanout buffer. Designed for the most demanding clock distribution systems, the MC100ES7011H supports various applications that require the distribution of precisely aligned differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target applications for this clock driver are in high performance clock distribution in computing, networking and telecommunication systems. 1:2 DIFFERENTIAL HSTL/LVDS TO LVDS CLOCK FANOUT DRIVER Features * * * * * * * * * 1:2 differential clock fanout buffer 50 ps maximum device skew SiGe Technology Supports DC to 1000 MHz operation LVDS compatible differential clock outputs HSTL/LVDS compatible differential clock inputs 3.3V power supply Supports industrial temperature range Standard 8 lead SOIC package D SUFFIX 8 LEAD SOIC PACKAGE CASE 751 ORDERING INFORMATION Device 1 VCC 8 Package MC100ES7011HD SO-8 MC100ES7011HDR2 SO-8 Q0 PIN DESCRIPTION 2 D D VEE 3 4 7 6 5 Q0 Q1 Pin Function D, D HSTL/LVDS Data Inputs Qn, Qn LVDS Data Outputs VCC Positive Supply VEE Negative Supply Q1 Figure 1. 8-Lead Pinout (Top View) and Logic Diagram This document contains certain information on a new product. Specifications and information herein are subject to change without notice. (c) Motorola, Inc. 2004 IDTTM Low Voltage 1:2 Differential HSTL/LVDS to LVDS Clock Fanout Buffer For More Information On This Product, Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Go to: www.freescale.com 1 MC100ES7011H MC100ES7011H Low Voltage 1:2 Differential HSTL/LVDS to LVDS Clock Fanout Buffer Freescale Semiconductor, Inc. NETCOM MC100ES7011H Table 1. General Specifications Characteristics Value Internal Input Pulldown Resistor TBD Internal Input Pullup Resistor TBD ESD Protection Human Body Model Machine Model TBD JA Thermal Resistance (Junction to Ambient) 0 LFPM, 8 SOIC 500 LFPM, 8 SOIC TBD Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Table 2. Absolute Maximum Ratings1 Freescale Semiconductor, Inc... Symbol Parameter Conditions Rating Unit 3.9 V VCC + 0.3 VEE - 0.3 V V 50 100 mA mA VSUPPLY Power Supply Voltage Difference between VCC & VEE VIN Input Voltage VCC - VEE 3.6V IOUT Output Current Continuous Surge TA Operating Temperature Range -40 to +85 C TSTG Storage Temperature Range -65 to +150 C 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 3. DC Characteristics (VCC = 3.3V5%; TJ = 0C to 110C)1 Symbol Characteristic Min Typ Max Unit Condition HSTL/LVDS differential input signals (D, D) VDIF Differential input voltage2 0.2 VX, IN Differential cross point voltage3 0.25 VIH Input high voltage VIL Input low voltage IIN Input current V 0.68 - 0.9 VCC - 1.3 VX + 0.1 V V VX - 0.1 V 150 mA VIN = VX 0.1V mV LVDS 1275 mV LVDS TBD mA VCC pin (core) LVDS clock outputs (Q[0:4], Q[0:4]) VPP Output differential voltage (peak-to-peak) 250 VOS Output offset voltage 1125 Supply Current ICC Maximum Quiescent Supply Current without output termination current TBD 1. DC characteristics are design targets and pending characterization. 2. VDIF (DC) is the minimum differential HSTL/LVDS input voltage swing required for device functionality. 3. VX (DC) is the crosspoint of the differential HSTL/LVDS input signal. Functional operation is obtained when the crosspoint is within the VX (DC) range and the input swing lies within the VPP (DC) specification. MOTOROLA 2 IDTTM Low Voltage 1:2 Differential HSTL/LVDS to LVDS Clock Fanout Buffer Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 2 For More Information On This Product, TIMING SOLUTIONS MC100ES7011H MC100ES7011H Low Voltage 1:2 Differential HSTL/LVDS to LVDS Clock Fanout Buffer Freescale Semiconductor, Inc. NETCOM MC100ES7011H Table 4. AC Characteristics (VCC = 3.3V5%; TJ = 0C to 110C)1 2 Symbol Characteristic Min Typ Max Unit Condition HSTL/LVDS differential input signals (D, D) VDIF Differential input voltage (peak-to-peak)3 0.4 VX, IN Differential cross point voltage4 0.68 fCLK Input Frequency tPD Propagation Delay D to Q[0:1} V 1000 1.275 V TBD MHz Differential TBD ps Differential 50 ps Differential ps Differential TBD % DCfref = 50% TBD ns 20% to 80% Freescale Semiconductor, Inc... LVDS clock outputs (Q[0:1], Q[0:1]) tSK(O) Output-to-output skew tSK(PP) Output-to-output skew (part-to-part) TBD tJIT(CC) Output cycle-to-cycle jitter TBD DCO Output duty cycle TBD tr / tf Output Rise/Fall Times 0.05 50 1. AC characteristics are design targets and pending characterization. 2. AC characteristics apply for parallel output termination of 50 to VTT. 3. VDIF (AC) is the minimum differential HSTL/LVDS input voltage swing required to maintain AC characteristics including tpd and device-to-device skew. 4. VX (AC) is the crosspoint of the differential HSTL/LVDS input signal. Functional operation is obtained when the crosspoint is within the VX (AC) range and the input swing lies within the VDIF (AC) specification. Violation of VX (AC) or VDIF (AC) impacts the device propagation delay, device and part-to-part skew. TIMING SOLUTIONS 3 IDTTM Low Voltage 1:2 Differential HSTL/LVDS to LVDS Clock Fanout Buffer Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 3 For More Information On This Product, MOTOROLA MC100ES7011H MC100ES7011H Low Voltage 1:2 Differential HSTL/LVDS to LVDS Clock Fanout Buffer Freescale Semiconductor, Inc. NETCOM MC100ES7011H Differential Pulse Generator Z = 50 ZO = 50 RT = 50 ZO = 50 DUT MC100ES7011H RT = 50 VTT=GND VTT=GND Figure 2. MC100ES7011H AC Test Reference Freescale Semiconductor, Inc... D VDIF=0.6V VX=0.75V D Q[0-1] Q[0-1] tPD (D to Q[0-1]) Figure 3. MC100ES7011H AC Reference Measurement Waveform (HSTL Input) D VDIF=0.6V VX=1.2V D Q[0-1] Q[0-1] tPD (D to Q[0-1]) Figure 4. MC100ES7011H AC Reference Measurement Waveform (LVDS Input) MOTOROLA 4 IDTTM Low Voltage 1:2 Differential HSTL/LVDS to LVDS Clock Fanout Buffer Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 4 For More Information On This Product, TIMING SOLUTIONS MC100ES7011H MC100ES7011H Low Voltage 1:2 Differential HSTL/LVDS to LVDS Clock Fanout Buffer Freescale Semiconductor, Inc. NETCOM MC100ES7011H PACKAGE DIMENSIONS D SUFFIX 8 LEAD SOIC PACKAGE CASE 751 D A 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS ARE IN MILLIMETER. 3. DIMENSION D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. C 5 0.25 H E M B M 1 4 h Freescale Semiconductor, Inc... B X 45 e A C SEATING PLANE L 0.10 A1 B 0.25 M C B S A S DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.35 0.49 0.19 0.25 4.80 5.00 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0 7 STYLE 1: PIN 1. 2. 3. 4. 5. 6. 7. 8. EMITTER COLLECTOR COLLECTOR EMITTER EMITTER BASE BASE EMITTER STYLE 2: PIN 1. 2. 3. 4. 5. 6. 7. 8. COLLECTOR, DIE, #1 COLLECTOR, #1 COLLECTOR, #2 COLLECTOR, #2 BASE, #2 EMITTER, #2 BASE, #1 EMITTER, #1 STYLE 3: PIN 1. 2. 3. 4. 5. 6. 7. 8. DRAIN, DIE #1 DRAIN, #1 DRAIN, #2 DRAIN, #2 GATE, #2 SOURCE, #2 GATE, #1 SOURCE, #1 STYLE 4: PIN 1. 2. 3. 4. 5. 6. 7. 8. ANODE ANODE ANODE ANODE ANODE ANODE ANODE COMMON CATHODE STYLE 5: PIN 1. 2. 3. 4. 5. 6. 7. 8. DRAIN DRAIN DRAIN DRAIN GATE GATE SOURCE SOURCE STYLE 6: PIN 1. 2. 3. 4. 5. 6. 7. 8. SOURCE DRAIN DRAIN SOURCE SOURCE GATE GATE SOURCE STYLE 7: PIN 1. 2. 3. 4. 5. 6. 7. 8. INPUT EXTERNAL BYPASS THIRD STAGE SOURCE GROUND DRAIN GATE 3 SECOND STAGE Vd FIRST STAGE Vd STYLE 8: PIN 1. 2. 3. 4. 5. 6. 7. 8. COLLECTOR, DIE #1 BASE, #1 BASE, #2 COLLECTOR, #2 COLLECTOR, #2 EMITTER, #2 EMITTER, #1 COLLECTOR, #1 STYLE 9: PIN 1. 2. 3. 4. 5. 6. 7. 8. EMITTER, COMMON COLLECTOR, DIE #1 COLLECTOR, DIE #2 EMITTER, COMMON EMITTER, COMMON BASE, DIE #2 BASE, DIE #1 EMITTER, COMMON STYLE 10: PIN 1. 2. 3. 4. 5. 6. 7. 8. GROUND BIAS 1 OUTPUT GROUND GROUND BIAS 2 INPUT GROUND STYLE 11: PIN 1. 2. 3. 4. 5. 6. 7. 8. SOURCE 1 GATE 1 SOURCE 2 GATE 2 DRAIN 2 DRAIN 2 DRAIN 1 DRAIN 1 STYLE 12: PIN 1. 2. 3. 4. 5. 6. 7. 8. SOURCE SOURCE SOURCE GATE DRAIN DRAIN DRAIN DRAIN STYLE 13: PIN 1. 2. 3. 4. 5. 6. 7. 8. N.C. SOURCE SOURCE GATE DRAIN DRAIN DRAIN DRAIN STYLE 14: PIN 1. 2. 3. 4. 5. 6. 7. 8. N-SOURCE N-GATE P-SOURCE P-GATE P-DRAIN P-DRAIN N-DRAIN N-DRAIN STYLE 15: PIN 1. 2. 3. 4. 5. 6. 7. 8. ANODE 1 ANODE 1 ANODE 1 ANODE 1 CATHODE, COMMON CATHODE, COMMON CATHODE, COMMON CATHODE, COMMON STYLE 16: PIN 1. 2. 3. 4. 5. 6. 7. 8. EMITTER, DIE #1 BASE, DIE #1 EMITTER, DIE #2 BASE, DIE #2 COLLECTOR, DIE #2 COLLECTOR, DIE #2 COLLECTOR, DIE #1 COLLECTOR, DIE #1 STYLE 17: PIN 1. 2. 3. 4. 5. 6. 7. 8. VCC V2OUT V1OUT TXE RXE VEE GND ACC STYLE 18: PIN 1. 2. 3. 4. 5. 6. 7. 8. ANODE ANODE SOURCE GATE DRAIN DRAIN CATHODE CATHODE TIMING SOLUTIONS 5 IDTTM Low Voltage 1:2 Differential HSTL/LVDS to LVDS Clock Fanout Buffer Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 5 For More Information On This Product, MOTOROLA MC100ES7011H MC100ES7011H MPC92459 PART NUMBERS 900 Low MHz Voltage Low1:2 Voltage Differential LVDS Clock HSTL/LVDS Synthesizer to LVDS INSERT PRODUCT NAME AND DOCUMENT TITLEClock Fanout Buffer NETCOM NETCOM Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 netcom@idt.com 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE +44 1372 363 339 (c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. 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