MC100ES7011HDR2 - Integrated Device Technology

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

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Order number: MC100ES7011H

Rev 0, 05/2004

This document contains certain information on a new product.

Specifications and information herein are subject to change without notice.

Low Voltage 1:2 Differential HSTL/

LVDS to LVDS Clock Fanout Buffer

The MC100ES7011H is a low voltage 1:2 Differential HSTL/LVDS to LVDS

clock fanout buffer. Designed for the most demanding clock distribution

systems, the MC100ES7011H supports various applications that require the

distribution of precisely aligned differential clock signals. Using SiGe

technology and a fully differential architecture, the device offers very low skew

outputs and superior digital signal characteristics. Target applications for this

clock driver are in high performance clock distribution in computing,

networking and telecommunication systems.

Features

• 1:2 differential clock fanout buffer

• 50 ps maximum device skew

• SiGe Technology

• Supports DC to 1000 MHz operation

• LVDS compatible differential clock outputs

• HSTL/LVDS compatible differential clock inputs

• 3.3V power supply

• Supports industrial temperature range

• Standard 8 lead SOIC package

Figure 1. 8-Lead Pinout (Top View) and Logic Diagram

8

7

6

5

1

2

3

4

VCC

D

VEE

Q0

Q1

MC100ES7011H

D SUFFIX

8 LEAD SOIC PACKAGE

CASE 751

1:2 DIFFERENTIAL HSTL/LVDS TO LVDS

CLOCK FANOUT DRIVER

ORDERING INFORMATION

Device Package

MC100ES7011HD SO-8

MC100ES7011HDR2 SO-8

PIN DESCRIPTION

Pin Function

D, D HSTL/LVDS Data Inputs

Qn, Qn LVDS Data Outputs

VCC Positive Supply

VEE Negative Supply

Freescale Semiconductor, I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

nc...

DATA SHEET

MC100ES7011H

IDT™ Low Voltage 1:2 Differential HSTL/LVDS to LVDS Clock Fanout Buffer

Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc

MC100ES7011H

1

Low Voltage 1:2 Differential HSTL/LVDS to LVDS Clock

Fanout Buffer

MC100ES7011H

MOTOROLA 2 TIMING SOLUTIONS

Table 1. General Specifications

Characteristics Value

Internal Input Pulldown Resistor TBD

Internal Input Pullup Resistor TBD

ESD Protection Human Body Model

Machine Model

TBD

θJA Thermal Resistance (Junction to Ambient) 0 LFPM, 8 SOIC

500 LFPM, 8 SOIC

TBD

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

Table 2. Absolute Maximum Ratings1

1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions

or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not

implied.

Symbol Parameter Conditions Rating Unit

VSUPPLY Power Supply Voltage Difference between VCC & VEE 3.9 V

VIN Input Voltage VCC – VEE ≤ 3.6V VCC + 0.3

VEE – 0.3

V

IOUT Output Current Continuous

Surge

50

100

mA

TAOperating Temperature Range –40 to +85 °C

TSTG Storage Temperature Range –65 to +150 °C

Table 3. DC Characteristics (VCC = 3.3V±5%; TJ = 0°C to 110°C)1

1. DC characteristics are design targets and pending characterization.

Symbol Characteristic Min Typ Max Unit Condition

HSTL/LVDS differential input signals (D, D)

VDIF Differential input voltage2

2. VDIF (DC) is the minimum differential HSTL/LVDS input voltage swing required for device functionality.

0.2 V

VX, IN Differential cross point voltage3

3. VX (DC) is the crosspoint of the differential HSTL/LVDS input signal. Functional operation is obtained when the crosspoint is within the VX (DC)

range and the input swing lies within the VPP (DC) specification.

0.25 0.68 – 0.9 VCC – 1.3 V

VIH Input high voltage VX + 0.1 V

VIL Input low voltage VX – 0.1 V

IIN Input current ±150 mA VIN = VX ± 0.1V

LVDS clock outputs (Q[0:4], Q[0:4])

VPP Output differential voltage (peak-to-peak) 250 mV LVDS

VOS Output offset voltage 1125 1275 mV LVDS

Supply Current

ICC Maximum Quiescent Supply Current without

output termination current

TBD TBD mA VCC pin (core)

Freescale Semiconductor, I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

nc...

MC100ES7011H

Low Voltage 1:2 Differential HSTL/LVDS to LVDS Clock Fanout Buffer NETCOM

IDT™ Low Voltage 1:2 Differential HSTL/LVDS to LVDS Clock Fanout Buffer

Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc

MC100ES7011H

2

MC100ES7011H

TIMING SOLUTIONS 3 MOTOROLA

Table 4. AC Characteristics (VCC = 3.3V±5%; TJ = 0°C to 110°C)1 2

1. AC characteristics are design targets and pending characterization.

2. AC characteristics apply for parallel output termination of 50Ω to VTT.

Symbol Characteristic Min Typ Max Unit Condition

HSTL/LVDS differential input signals (D, D)

VDIF Differential input voltage (peak-to-peak)3

3. VDIF (AC) is the minimum differential HSTL/LVDS input voltage swing required to maintain AC characteristics including tpd and device-to-device

skew.

0.4 V

VX, IN Differential cross point voltage4

4. VX (AC) is the crosspoint of the differential HSTL/LVDS input signal. Functional operation is obtained when the crosspoint is within the VX (AC)

range and the input swing lies within the VDIF (AC) specification. Violation of VX (AC) or VDIF (AC) impacts the device propagation delay, device

and part-to-part skew.

0.68 1.275 V

fCLK Input Frequency 1000 TBD MHz Differential

tPD Propagation Delay D to Q[0:1} TBD ps Differential

LVDS clock outputs (Q[0:1], Q[0:1])

tSK(O) Output-to-output skew 50 ps Differential

tSK(PP) Output-to-output skew (part-to-part) TBD ps Differential

tJIT(CC) Output cycle-to-cycle jitter TBD

DCOOutput duty cycle TBD 50 TBD % DCfref = 50%

tr / tfOutput Rise/Fall Times 0.05 TBD ns 20% to 80%

Freescale Semiconductor, I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

nc...

MC100ES7011H

Low Voltage 1:2 Differential HSTL/LVDS to LVDS Clock Fanout Buffer NETCOM

IDT™ Low Voltage 1:2 Differential HSTL/LVDS to LVDS Clock Fanout Buffer

Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc

MC100ES7011H

3

MC100ES7011H

MOTOROLA 4 TIMING SOLUTIONS

Figure 2. MC100ES7011H AC Test Reference

Differential Pulse

Generator

Z = 50Ω

RT = 50Ω

ZO = 50Ω

DUT

MC100ES7011H

VTT=GND

RT = 50Ω

ZO = 50Ω

VTT=GND

Figure 3. MC100ES7011H AC Reference

Measurement Waveform (HSTL Input)

D

tPD (D to Q[0–1])

VX=0.75V

VDIF=0.6V

D

Q[0–1]

Figure 4. MC100ES7011H AC Reference

Measurement Waveform (LVDS Input)

D

tPD (D to Q[0–1])

VX=1.2V

VDIF=0.6V

D

Q[0–1]

Freescale Semiconductor, I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

nc...

MC100ES7011H

Low Voltage 1:2 Differential HSTL/LVDS to LVDS Clock Fanout Buffer NETCOM

IDT™ Low Voltage 1:2 Differential HSTL/LVDS to LVDS Clock Fanout Buffer

Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc

MC100ES7011H

4

MC100ES7011H

TIMING SOLUTIONS 5 MOTOROLA

PACKAGE DIMENSIONS

D SUFFIX

8 LEAD SOIC PACKAGE

CASE 751

STYLE 4:

PIN 1. ANODE

2. ANODE

3. ANODE

4. ANODE

5. ANODE

6. ANODE

7. ANODE

8. COMMON CATHODE

STYLE 1:

PIN 1. EMITTER

2. COLLECTOR

3. COLLECTOR

4. EMITTER

5. EMITTER

6. BASE

7. BASE

8. EMITTER

STYLE 2:

PIN 1. COLLECTOR, DIE, #1

2. COLLECTOR, #1

3. COLLECTOR, #2

4. COLLECTOR, #2

5. BASE, #2

6. EMITTER, #2

7. BASE, #1

8. EMITTER, #1

STYLE 3:

PIN 1. DRAIN, DIE #1

2. DRAIN, #1

3. DRAIN, #2

4. DRAIN, #2

5. GATE, #2

6. SOURCE, #2

7. GATE, #1

8. SOURCE, #1

STYLE 6:

PIN 1. SOURCE

2. DRAIN

3. DRAIN

4. SOURCE

5. SOURCE

6. GATE

7. GATE

8. SOURCE

STYLE 5:

PIN 1. DRAIN

2. DRAIN

3. DRAIN

4. DRAIN

5. GATE

6. GATE

7. SOURCE

8. SOURCE

STYLE 7:

PIN 1. INPUT

2. EXTERNAL BYPASS

3. THIRD STAGE SOURCE

4. GROUND

5. DRAIN

6. GATE 3

7. SECOND STAGE Vd

8. FIRST STAGE Vd

STYLE 8:

PIN 1. COLLECTOR, DIE #1

2. BASE, #1

3. BASE, #2

4. COLLECTOR, #2

5. COLLECTOR, #2

6. EMITTER, #2

7. EMITTER, #1

8. COLLECTOR, #1

STYLE 9:

PIN 1. EMITTER, COMMON

2. COLLECTOR, DIE #1

3. COLLECTOR, DIE #2

4. EMITTER, COMMON

5. EMITTER, COMMON

6. BASE, DIE #2

7. BASE, DIE #1

8. EMITTER, COMMON

STYLE 10:

PIN 1. GROUND

2. BIAS 1

3. OUTPUT

4. GROUND

5. GROUND

6. BIAS 2

7. INPUT

8. GROUND

STYLE 11:

PIN 1. SOURCE 1

2. GATE 1

3. SOURCE 2

4. GATE 2

5. DRAIN 2

6. DRAIN 2

7. DRAIN 1

8. DRAIN 1

STYLE 12:

PIN 1. SOURCE

2. SOURCE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 14:

PIN 1. N-SOURCE

2. N-GATE

3. P-SOURCE

4. P-GATE

5. P-DRAIN

6. P-DRAIN

7. N-DRAIN

8. N-DRAIN

STYLE 13:

PIN 1. N.C.

2. SOURCE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

STYLE 15:

PIN 1. ANODE 1

2. ANODE 1

3. ANODE 1

4. ANODE 1

5. CATHODE, COMMON

6. CATHODE, COMMON

7. CATHODE, COMMON

8. CATHODE, COMMON

STYLE 16:

PIN 1. EMITTER, DIE #1

2. BASE, DIE #1

3. EMITTER, DIE #2

4. BASE, DIE #2

5. COLLECTOR, DIE #2

6. COLLECTOR, DIE #2

7. COLLECTOR, DIE #1

8. COLLECTOR, DIE #1

STYLE 17:

PIN 1. VCC

2. V2OUT

3. V1OUT

4. TXE

5. RXE

6. VEE

7. GND

8. ACC

STYLE 18:

PIN 1. ANODE

2. ANODE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. CATHODE

8. CATHODE

L

h

X 45˚

θ

C

SEATING

PLANE

S

B

M

0.25 A

S

C

B

A1

CA

0.10

1

4

58

M

B

M

0.25

D

EH

A

Be

DIM MIN MAX

MILLIMETERS

A1.35 1.75

A1 0.10 0.25

B0.35 0.49

C0.19 0.25

D4.80 5.00

E

1.27 BSCe

3.80 4.00

H5.80 6.20

h

0˚ 7˚

L0.40 1.25

q

0.25 0.50

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

2. DIMENSIONS ARE IN MILLIMETER.

3. DIMENSION D AND E DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS

OF THE B DIMENSION AT MAXIMUM MATERIAL

CONDITION.

Freescale Semiconductor, I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

nc...

MC100ES7011H

Low Voltage 1:2 Differential HSTL/LVDS to LVDS Clock Fanout Buffer NETCOM

IDT™ Low Voltage 1:2 Differential HSTL/LVDS to LVDS Clock Fanout Buffer

Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc

MC100ES7011H

5

Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered

trademarks used to identify products or services of their respective owners.

Printed in USA

XX-XXXX-XXXXX

Corporate Headquarters

Integrated Device Technology, Inc.

6024 Silver Creek Valley Road

San Jose, CA 95138

United States

800 345 7015

+408 284 8200 (outside U.S.)

Asia Pacific and Japan

Integrated Device Technology

Singapore (1997) Pte. Ltd.

Reg. No. 199707558G

435 Orchard Road

#20-03 Wisma Atria

Singapore 238877

+65 6 887 5505

Europe

IDT Europe, Limited

Prime House

Barnett Wood Lane

Leatherhead, Surrey

United Kingdom KT22 7DE

+44 1372 363 339

For Sales

800-345-7015

408-284-8200

Fax: 408-284-2775

For Tech Support

netcom@idt.com

480-763-2056

Innovate with IDT and accelerate your future networks. Contact:

www.IDT.com

PART NUMBERS

INSERT PRODUCT NAME AND DOCUMENT TITLE NETCOM

MPC92459

900 MHz Low Voltage LVDS Clock Synthesizer NETCOM

MC100ES7011H

Low Voltage 1:2 Differential HSTL/LVDS to LVDS Clock Fanout Buffer NETCOM