DATA SH EET
Product specification
Supersedes data of December 1990
File under Integrated Circuits, IC06
1997 Nov 25
INTEGRATED CIRCUITS
74HC/HCT109
Dual JK flip-flop with set and reset;
positive-edge trigger
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
1997 Nov 25 2
Philips Semiconductors Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger 74HC/HCT109
FEATURES
•J, K inputs for easy D-type flip-flop
•Toggle flip-flop or “do nothing” mode
•Output capability: standard
•ICC category: flip-flops
GENERAL DESCRIPTION
The 74HC/HCT109 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT109 are dual positive-edge triggered, JK
flip-flops with individual J, K inputs, clock (CP) inputs, set
(SD) and reset (RD) inputs; also complementary Q and Q
outputs.
The set and reset are asynchronous active LOW inputs
and operate independently of the clock input.
The J and K inputs control the state changes of the
flip-flops as described in the mode select function table.
The J and K inputs must be stable one set-up time prior to
the LOW-to-HIGH clock transition for predictable
operation.
The JK design allows operation as a D-type flip-flop by
tying the J and K inputs together.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr= tf= 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PDin µW):
PD= CPD ×VCC2×fi+∑(CL×VCC2×fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑(CL×VCC2×fo) = sum of outputs
CL= output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI= GND to VCC
For HCT the condition is VI= GND to VCC −1.5 V.
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
HC HCT
tPHL/ tPLH propagation delay
CL= 15 pF;
VCC = 5 V
nCP to nQ, nQ1517ns
n
S
D
to nQ, nQ1214ns
n
R
D
to nQ, nQ1215ns
f
max maximum clock frequency 75 61 MHz
CIinput capacitance 3.5 3.5 pF
CPD power dissipation
capacitance per flip-flop notes 1 and 2 20 22 pF
1997 Nov 25 3
Philips Semiconductors Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger 74HC/HCT109
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1, 15 1RD, 2RDasynchronous reset-direct input (active LOW)
2, 14, 3, 13 1J, 2J, 1K, 2K synchronous inputs; flip-flops 1 and 2
4, 12 1CP, 2CP clock input (LOW-to-HIGH, edge-triggered)
5, 11 1SD, 2SDasynchronous set-direct input (active LOW)
6, 10 1Q, 2Q true flip-flop outputs
7, 9 1Q, 2Q complement flip-flop outputs
8 GND ground (0 V)
16 VCC positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
1997 Nov 25 4
Philips Semiconductors Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger 74HC/HCT109
Fig.4 Functional diagram.
FUNCTION TABLE
Notes
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
q = lower case letters indicate the state of the referenced output one set-up time
prior to the LOW-to-HIGH CP transition
X = don’t care
↑= LOW-to-HIGH CP transition
OPERATING
MODE INPUTS OUTPUTS
SDRDCP J KQQ
asynchronous set L H X X X H L
asynchronous reset H L X X X L H
undetermined L L X X X H H
toggle H H ↑hl qq
load “0” (reset) H H ↑llLH
load “1” (set) H H ↑hh H L
hold “no change” H H ↑lhq q
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
Fig.5 Logic diagram (one flip-flop).
handbook, full pagewidth
MBK217
C
C
C
C
C
K
J
CP
S
R
C
C
C
C
C
Q
Q
1997 Nov 25 5
Philips Semiconductors Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger 74HC/HCT109
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: flip-flops
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr= tf= 6 ns; CL= 50 pF
SYMBOL PARAMETER
Tamb (°C) TEST CONDITIONS
74HC UNIT VCC
(V) WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
nCP to nQ, nQ
50
18
14
175
35
30
220
44
37
265
53
45 ns 2.0
4.5
6.0 Fig.6
tPLH propagation delay
nSDto nQ
30
11
9
120
24
20
150
30
26
180
36
31 ns 2.0
4.5
6.0 Fig.7
tPHL propagation delay
nSDto nQ
41
15
12
155
31
26
195
39
33
235
47
40 ns 2.0
4.5
6.0 Fig.7
tPHL propagation delay
nRDto nQ
41
15
12
185
37
31
230
46
39
280
56
48 ns 2.0
4.5
6.0 Fig.7
tPLH propagation delay
nRDto nQ
39
14
11
170
34
29
215
43
37
255
51
43 ns 2.0
4.5
6.0 Fig.7
tTHL/ tTLH output transition
time
19
7
6
75
15
13
95
19
16
110
22
19 ns 2.0
4.5
6.0 Fig.6
tWclock pulse width
HIGH or LOW
80
16
14
19
7
6
100
20
17
120
24
20 ns 2.0
4.5
6.0 Fig.6
tWset or reset pulse
width HIGH or LOW
80
16
14
14
5
4
100
20
17
120
24
20 ns 2.0
4.5
6.0 Fig.7
trem removal time
nSD,nR
Dto nCP
70
14
12
19
7
6
90
18
15
105
21
18 ns 2.0
4.5
6.0 Fig.7
tsu set-up time
nJ, nK to nCP
70
14
12
17
6
5
90
18
15
105
21
18 ns 2.0
4.5
6.0 Fig.6
thhold time
nJ, nK to nCP
5
5
5
0
0
0
5
5
5
5
5
5ns 2.0
4.5
6.0 Fig.6
fmax maximum clock
pulse frequency
6.0
30
35
22
68
81
5.0
24
28
4.0
20
24 MHz 2.0
4.5
6.0 Fig.6
1997 Nov 25 6
Philips Semiconductors Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger 74HC/HCT109
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: flip-flops
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr= tf= 6 ns; CL= 50 pF
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCT VCC
(V) WAVEFORMS+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
nCP to nQ, nQ 20 35 44 53 ns 4.5 Fig.6
tPLH propagation delay
nSDto nQ 13 26 33 39 ns 4.5 Fig.7
tPHL propagation delay
nSDto nQ 19 35 44 53 ns 4.5 Fig.7
tPHL propagation delay
nRDto nQ 19 35 44 53 ns 4.5 Fig.7
tPLH propagation delay
nRDto nQ 16 32 40 48 ns 4.5 Fig.7
tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Fig.6
tWclock pulse width
HIGH or LOW 18 9 23 27 ns 4.5 Fig.6
tWset or reset pulse width
HIGH or LOW 16 8 20 24 ns 4.5 Fig.7
trem removal time
nSD, nRDto nCP 16 8 20 24 ns 4.5 Fig.7
tsu set-up time
nJ, nK to nCP 18 8 23 27 ns 4.5 Fig.6
thhold time
nJ, nK to nCP 3−3 3 3 ns 4.5 Fig.6
fmax maximum clock
pulse frequency 27 55 22 18 MHz 4.5 Fig.6
1997 Nov 25 7
Philips Semiconductors Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger 74HC/HCT109
AC WAVEFORMS
Fig.6 Waveforms showing the clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nJ,
nK to nCP set-up, the nCP to nJ, nK hold times, the output transition times and the maximum clock pulse
frequency.
The shaded areas indicate when the
input is permitted to change for
predictable output performance.
handbook, full pagewidth
MBK216
VM(1)
nCP INPUT
nSD INPUT
nRD INPUT
nQ OUTPUT
nQ OUTPUT
VM(1)
VM(1)
VM(1)
VM(1)
tW
trem
trem
tW
tPHL
tPLH
tPLH
tPHL
Fig.7 Waveforms showing the set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set
and reset pulse widths and the nRD, nSDto nCP removal time.
(1) HC: VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
1997 Nov 25 8
Philips Semiconductors Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger 74HC/HCT109
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our
“IC Package Databook”
(order code 9398 652 90011).
DIP
SOLDERING BY DIPPING OR BY WAVE
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
REPAIRING SOLDERED JOINTS
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
SO, SSOP and TSSOP
REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO, SSOP
and TSSOP packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method.
Typical reflow temperatures range from 215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
WAVE SOLDERING
Wave soldering can be used for all SO packages. Wave
soldering is not recommended for SSOP and TSSOP
packages, because of the likelihood of solder bridging due
to closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
If wave soldering is used - and cannot be avoided for
SSOP and TSSOP packages - the following conditions
must be observed:
•A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
•The longitudinal axis of the package footprint must be
parallel to the solder flow and must incorporate solder
thieves at the downstream end.
Even with these conditions:
•Only consider wave soldering SSOP packages that
have a body width of 4.4 mm, that is
SSOP16 (SOT369-1) or SSOP20 (SOT266-1).
•Do not consider wave soldering TSSOP packages
with 48 leads or more, that is TSSOP48 (SOT362-1)
and TSSOP56 (SOT364-1).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
REPAIRING SOLDERED JOINTS
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
1997 Nov 25 9
Philips Semiconductors Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger 74HC/HCT109
DEFINITIONS
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Semiconductors - PIP - 74HC/HCT109; Dual JK flip-flop with set and reset; positive-edge trigger
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Product Information
74HC/HCT109; Dual
JK flip-flop with set
and reset; positive-
edge trigger
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General description
The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP) inputs, set
(SD ) and reset (RD ) inputs; also complementary Q and Q outputs.
The set and reset are asynchronous active LOW inputs and operate independently of the clock input.
The J and K inputs control the state changes of the flip-flops as described in the mode select function table.
The J and K inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable
operation.
The JK design allows operation as a D-type flip-flop by tying the J and K inputs together.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
top
Features
● J, K inputs for easy D-type flip-flop
● Toggle flip-flop or "do nothing" mode
● Output capability: standard
● ICC category: flip-flops
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Philips Semiconductors - PIP - 74HC/HCT109; Dual JK flip-flop with set and reset; positive-edge trigger
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Datasheet
Type number Title Publication release
date Datasheet status Page
count File
size
(kB)
Datasheet
74HC/HCT109 Dual JK flip-
flop with set
and reset;
positive-edge
trigger
11/25/1997 Product specification 9 59
Download
PDF
File
Download
Additional datasheet info
To complete the device datasheet with package and family information, also download the following PDF files. The
"Logic Package Information" document is required to determine in which package(s) this device is available.
Document Description
1
Download
PDF
File
HCT_FAMILY_SPECIFICATIONS HC/T Family Specifications, The IC06 74HC/HCT/HCMOS Logic
Family Specifications
2
Download
PDF
File
HCT_PACKAGE_INFO HC/T Package Info, The IC06 74HC/HCT/HCMOS Logic Package
Information
3
Download
PDF
File
HCT_PACKAGE_OUTLINES HC/T Package Outlines, The IC06 74HC/HCT/HCMOS Logic
Package Outlines
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Blockdiagram(s)
Block diagram of
74HC109N
top
Parametrics
Type number Package Description Propagation
Delay(ns) Voltage No.
of
Pins
Power
Dissipation
Considerations
Logic
Switching
Levels
Output
Drive
Capability
74HC109D SOT109
(SO16)
Dual J-/K
Flip-Flop
with Set and
Reset;
Positive-
Edge
Trigger
15 5 Volts
+16 Low Power or
Battery
Applications CMOS Low
74HC109DB SOT338-1
(SSOP16)
Dual J-/K
Flip-Flop
with Set and
Reset;
Positive-
Edge
Trigger
15 5 Volts
+16 Low Power or
Battery
Applications CMOS Low
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Philips Semiconductors - PIP - 74HC/HCT109; Dual JK flip-flop with set and reset; positive-edge trigger
74HC109N SOT38-1
(DIP16)
Dual J-/K
Flip-Flop
with Set and
Reset;
Positive-
Edge
Trigger
15 5 Volts
+16 Low Power or
Battery
Applications CMOS Low
74HCT109D SOT109
(SO16)
Dual J-/K
Flip-Flop
with Set and
Reset;
Positive-
Edge
Trigger;
TTL
Enabled
15 5 Volts
+16 Low Power or
Battery
Applications TTL Low
74HCT109DB SOT338-1
(SSOP16)
Dual J-/K
Flip-Flop
with Set and
Reset;
Positive-
Edge
Trigger;
TTL
Enabled
15 5 Volts
+16 Low Power or
Battery
Applications TTL Low
74HCT109N SOT38-1
(DIP16)
Dual J-/K
Flip-Flop
with Set and
Reset;
Positive-
Edge
Trigger;
TTL
Enabled
15 5 Volts
+16 Low Power or
Battery
Applications TTL Low
74HCT109PW SOT403-1
(TSSOP16)
Dual J-/K
Flip-Flop
with Set and
Reset;
Positive-
Edge
Trigger;
TTL
Enabled
15 5 Volts
+16 Low Power or
Battery
Applications TTL Low
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Products, packages, availability and ordering
Type number North
American type
number
Ordering code
(12NC) Marking/Packing
Download
PDF
File
Discretes
packing info
Package Device status Buy online
74HC109D 74HC109D 9337 144 80652 Standard Marking
* Bulk Pack,
CECC
SOT109
(SO16) Full production
order this
product
online
-
74HC109D-T 9337 144 80653 Standard Marking
* Reel Pack,
SMD, 13", CECC
SOT109
(SO16) Full production
order this
product
-
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Philips Semiconductors - PIP - 74HC/HCT109; Dual JK flip-flop with set and reset; positive-edge trigger
online
74HC109DB 74HC109DB 9351 863 40112 Standard Marking
* Bulk Pack SOT338-1
(SSOP16) Full production
order this
product
online
-
74HC109DB-
T 9351 863 40118 Standard Marking
* Reel Pack,
SMD, 13"
SOT338-1
(SSOP16) Full production
order this
product
online
-
74HC109N 74HC109N 9336 692 60652 Standard Marking
* Bulk Pack,
CECC
SOT38-1
(DIP16) Full production
order this
product
online
-
74HCT109D 74HCT109D 9337 149 60652 Standard Marking
* Bulk Pack,
CECC
SOT109
(SO16) Full production
order this
product
online
-
74HCT109D-
T 9337 149 60653 Standard Marking
* Reel Pack,
SMD, 13", CECC
SOT109
(SO16) Full production
order this
product
online
-
74HCT109DB 74HCT109DB 9351 863 20112 Standard Marking
* Bulk Pack SOT338-1
(SSOP16) Full production
order this
product
online
-
74HCT109DB-
T 9351 863 20118 Standard Marking
* Reel Pack,
SMD, 13"
SOT338-1
(SSOP16) Full production
order this
product
online
-
74HCT109N 74HCT109N 9336 698 90652 Standard Marking
* Bulk Pack,
CECC
SOT38-1
(DIP16) Full production
order this
product
online
-
74HCT109PW 74HCT109PW 9351 863 30112 Standard Marking
* Bulk Pack
SOT403-1
(TSSOP16)
Full production
order this
product
online
-
74HCT109PW-
T 9351 863 30118 Standard Marking
* Reel Pack,
SMD, 13"
SOT403-1
(TSSOP16)
Full production
order this
product
online
-
Products in the above table are all in production. Some variants are discontinued; click here for information on these
variants.
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Products
similar
to
74HC/HCT109
74HC/HCT109 links to the similar products page containing an overview of products that are similar in
function or related to the type number(s) as listed on this page. The similar products page includes products from the
same catalog tree(s), relevant selection guides and products from the same functional category.
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Support & tools
Download
PDF
File
HC/T Family Specifications, The IC06 74HC/HCT/HCMOS Logic Family Specifications(date 01-Mar-98)
Download
PDF
File
HC/T User Guide(date 01-Nov-97)
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