ASAHI KASEI [AK4527B] AK4527B High Performance Multi-channel Audio CODEC GENERAL DESCRIPTION The AK4527B is a single chip CODEC that includes two channels of ADC and six channels of DAC. The ADC outputs 24bit data and the DAC accepts up to 24bit input data. The ADC has the Enhanced Dual Bit architecture with wide dynamic range. The DAC introduces the new developed Advanced Multi-Bit architecture, and achieves wider dynamic range and lower outband noise. An auxiliary digital audio input interface maybe used instead of the ADC for passing audio data to the primary audio output port. Control may be set directly by pins or programmed through a separate serial interface. The AK4527B has a dynamic range of 102dB for ADC, 106dB for DAC and is well suited for digital surround for home theater and car audio. An AC-3 system can be built with a IEC60958(SPDIF) receiver such as the AK4112A. The AK4527B is available in a small 44pin LQFP package which will reduce system space. *AC-3 is a trademark of Dolby Laboratories. FEATURES o 2ch 24bit ADC - 64x Oversampling - Sampling Rate up to 96kHz - Linear Phase Digital Anti-Alias Filter - Differential Inputs with single-ended use capability - S/(N+D): 92dB - Dynamic Range, S/N: 102dB - Digital HPF for offset cancellation - I/F format: MSB justified or I2S - Overflow flag o 6ch 24bit DAC - 128x Oversampling - Sampling Rate up to 96kHz - 24bit 8 times Digital Filter - Single-Ended Outputs - On-chip Switched-Capacitor Filter - S/(N+D): 90dB - Dynamic Range, S/N: 106dB - I/F format: MSB justified, LSB justified(20bit,24bit) or I2S - Individual channel digital volume with 256 levels and 0.5dB step - Soft mute - De-emphasis for 32kHz, 44.1kHz and 48kHz - Zero Detect Function o High Jitter Tolerance o TTL Level Digital I/F o 3-wire Serial and I2C Bus P I/F for mode setting o Master clock:256fs, 384fs or 512fs for fs=32kHz to 48kHz 128fs, 192fs or 256fs for fs=64kHz to 96kHz o Power Supply: 4.5 to 5.5V o Power Supply for output buffer: 2.7 to 5.5V o Small 44pin LQFP MS0056-E-00 2000/10 -1- ASAHI KASEI [AK4527B] n Block Diagram LIN+ LIN- ADC HPF RIN+ RIN- ADC HPF Audio I/F RX1 RX2 RX3 RX4 XTI LOUT1 ROUT1 LPF LPF DAC DAC DATT DATT MCLK LRCK BICK MCLK XTO MCKO DIR LRCK BICK LRCK AK4112A DAUX LOUT2 LPF DAC BICK SDTO DATT Format Converter ROUT2 LPF DAC DATT SDOUT LOUT3 LPF DAC SDOS DATT SDTO ROUT3 LPF DAC AK4527B DATT SDTI1 SDTI2 SDTI3 SDIN1 SDIN2 SDIN3 LRCK BICK AC3 SDIN SDOUT1 SDOUT2 SDOUT3 Block Diagram (DIR and AC-3 DSP are external parts) MS0056-E-00 2000/10 -2- ASAHI KASEI [AK4527B] n Ordering Guide -40 +85C 44pin LQFP(0.8mm pitch) Evaluation Board for AK4527B AK4527BVQ AKD4527B SDOS VCOM VREFH 36 34 AVDD 37 35 DZF1 AVSS 38 P/S MCLK 39 DIF0/CSN 40 DIF1/SCL/CCLK 41 LOOP0/SDA/CDTI 42 43 44 LOOP1 n Pin Layout 1 33 DZF2/OVF I2C 2 32 RIN+ SMUTE 3 31 RIN- 30 LIN+ 29 LIN- 28 ROUT1 27 LOUT1 26 ROUT2 BICK 4 LRCK 5 SDTI1 6 SDTI2 7 SDTI3 8 AK4527BVQ Top View 16 17 18 19 20 21 22 DVSS PDN TST NC ADIF CAD1 CAD0 LOUT3 15 23 DVDD 11 TVDD DFS 14 ROUT3 13 LOUT2 24 DZFE 25 10 12 9 DAUX NC SDTO MS0056-E-00 2000/10 -3- ASAHI KASEI [AK4527B] n Compatibility with AK4527 1. Functions Functions Overflow flag Clock mode Sampling speed mode auto setting Serial mode only Pin/Register Not available Hi-Z AK4527B Available Auto setting Available (MCLK is fixed at auto setting mode; Normal: 512fs, Double: 256fs) Parallel/Serial mode Register only Available VCOM voltage 2. Pin Configuration Pin# 12 13 18 19 20 33 AK4527 DEM1 DEM0 ICKS2 ICKS1 ICKS0 DZF2 AK4527B NC DZFE TST NC ADIF DZF2/OVF 3. Register Addr 00H 01H 08H 09H 0AH Changed items DIF1-0 default values are changed from mode 0 to mode 2. ACKS (Clock auto setting mode) is added. DEMA1-C0 default values are changed from "44.1kHz" to "OFF". ICKS2-0 are removed. OVFE (Overflow detection enable) is added. Zero detection De-emphasis setting I2C bus mode Analog output at power down mode AK4527 Not available Setting by pin/bit Not available MS0056-E-00 2000/10 -4- ASAHI KASEI [AK4527B] PIN/FUNCTION No. 1 Pin Name SDOS I/O I 2 I2C I 3 SMUTE I 4 5 6 7 8 9 10 11 BICK LRCK SDTI1 SDTI2 SDTI3 SDTO DAUX DFS I I I I I O I I 12 NC - 13 DZFE I 14 15 16 17 TVDD DVDD DVSS PDN I 18 TST I 19 NC - 20 ADIF I 21 22 CAD1 CAD0 I I Function SDTO Source Select Pin (Note 1) "L": Internal ADC output, "H": DAUX input Control Mode Select Pin "L": 3-wire Serial, "H": I2C Bus Soft Mute Pin (Note 1) When this pin goes to "H", soft mute cycle is initialized. When returning to "L", the output mute releases. Audio Serial Data Clock Pin Input Channel Clock Pin DAC1 Audio Serial Data Input Pin DAC2 Audio Serial Data Input Pin DAC3 Audio Serial Data Input Pin Audio Serial Data Output Pin AUX Audio Serial Data Input Pin Double Speed Sampling Mode Pin (Note 1) "L": Normal Speed, "H": Double Speed No Connect No internal bonding. Zero Input Detect Enable Pin "L": mode 7 (disable) at parallel mode, zero detect mode is selectable by DZFM2-0 bits at serial mode "H": mode 0 (DZF1 is AND of all six channels) Output Buffer Power Supply Pin, 2.7V5.5V Digital Power Supply Pin, 4.5V5.5V Digital Ground Pin, 0V Power-Down & Reset Pin When "L", the AK4527B is powered-down and the control registers are reset to default state. If the state of P/S or CAD0-1 changes, then the AK4527B must be reset by PDN. Test Pin This pin should be connected to DVSS. No Connect No internal bonding. Analog Input Format Select Pin "H": Full-differential input, "L": Single-ended input Chip Address 1 Pin Chip Address 0 Pin MS0056-E-00 2000/10 -5- ASAHI KASEI No. 23 24 25 26 27 28 29 30 31 32 33 Pin Name LOUT3 ROUT3 LOUT2 ROUT2 LOUT1 ROUT1 LINLIN+ RINRIN+ DZF2 [AK4527B] I/O O O O O O O I I I I O OVF O 34 VCOM O 35 36 37 38 VREFH AVDD AVSS DZF1 I O 39 40 MCLK P/S I I 41 DIF0 CSN I I 42 DIF1 SCL/CCLK I I 43 LOOP0 I SDA/CDTI 44 LOOP1 I/O I Function DAC3 Lch Analog Output Pin DAC3 Rch Analog Output Pin DAC2 Lch Analog Output Pin DAC2 Rch Analog Output Pin DAC1 Lch Analog Output Pin DAC1 Rch Analog Output Pin Lch Analog Negative Input Pin Lch Analog Positive Input Pin Rch Analog Negative Input Pin Rch Analog Positive Input Pin Zero Input Detect 2 Pin (Note 2) When the input data of the group 1 follow total 8192 LRCK cycles with "0" input data, this pin goes to "H". Analog Input Overflow Detect Pin (Note 3) This pin goes to "H" if the analog input of Lch or Rch is overflows. Common Voltage Output Pin, AVDD/2 Large external capacitor around 2.2F is used to reduce power-supply noise. Positive Voltage Reference Input Pin, AVDD Analog Power Supply Pin, 4.5V5.5V Analog Ground Pin, 0V Zero Input Detect 1 Pin (Note 2) When the input data of the group 1 follow total 8192 LRCK cycles with "0" input data, this pin goes to "H". Master Clock Input Pin Parallel/Serial Select Pin "L": Serial control mode, "H": Parallel control mode Audio Data Interface Format 0 Pin in parallel control mode Chip Select Pin in 3-wire serial control mode This pin should be connected to DVDD at I2C bus control mode Audio Data Interface Format 1 Pin in parallel control mode Control Data Clock Pin in serial control mode I2C = "L": CCLK (3-wire Serial), I2C = "H": SCL (I2C Bus) Loopback Mode 0 Pin in parallel control mode Enables digital loop-back from ADC to 3 DACs. Control Data Input Pin in serial control mode I2C = "L": CDTI (3-wire Serial), I2C = "H": SDA (I2C Bus) Loopback Mode 1 Pin (Note 1) Enables all 3 DAC channels to be input from SDTI1. Notes: 1. SDOS, SMUTE, DFS, and LOOP1 pins are ORed with register data if P/S = "L". 2. The group 1 and 2 can be selected by DZFM2-0 bits if P/S = "L" and DZFE = "L". 3. This pin becomes OVF pin if OVFE bit is set to "1" at serial control mode. 4. All input pins should not be left floating. MS0056-E-00 2000/10 -6- ASAHI KASEI [AK4527B] ABSOLUTE MAXIMUM RATINGS (AVSS, DVSS=0V; Note 5) Parameter Symbol min Power Supplies Analog AVDD -0.3 Digital DVDD -0.3 Output buffer TVDD -0.3 |AVSS-DVSS| (Note 6) GND Input Current (any pins except for supplies) IIN Analog Input Voltage VINA -0.3 Digital Input Voltage VIND -0.3 Ambient Temperature (power applied) Ta -40 Storage Temperature Tstg -65 max 6.0 6.0 6.0 0.3 10 AVDD+0.3 DVDD+0.3 85 150 Units V V V V mA V V C C Notes: 5. All voltages with respect to ground. 6. AVSS and DVSS must be connected to the same analog ground plane. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AVSS, DVSS=0V; Note 5) Parameter Symbol min typ Power Supplies Analog AVDD 4.5 5.0 (Note 7) Digital DVDD 4.5 5.0 Output buffer TVDD 2.7 5.0 max 5.5 5.5 5.5 Units V V V Notes: 5. All voltages with respect to ground. 7. The power up sequence between AVDD, DVDD and TVDD is not critical. WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet. MS0056-E-00 2000/10 -7- ASAHI KASEI [AK4527B] ANALOG CHARACTERISTICS (Ta=25C; AVDD, DVDD, TVDD=5V; AVSS, DVSS=0V; VREFH=AVDD; fs=44.1kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement Frequency=20Hz20kHz at fs=44.1kHz, 20Hz~40kHz at fs=96kHz; unless otherwise specified) Parameter min typ max Units ADC Analog Input Characteristics: Differential Inputs; Analog Source Impedance=470 Resolution 24 Bits S/(N+D) (-0.5dBFS) fs=44.1kHz 84 92 dB (Note 8) fs=96kHz 83 dB DR (-60dBFS) fs=44.1kHz, A-weighted 94 102 dB fs=96kHz 88 96 dB fs=96kHz, A-weighted 93 102 dB S/N (Note 9) fs=44.1kHz, A-weighted 94 102 dB fs=96kHz 88 96 dB fs=96kHz, A-weighted 93 102 dB Interchannel Isolation 90 110 dB DC Accuracy Interchannel Gain Mismatch 0.2 0.3 dB Gain Drift 20 ppm/C Input Voltage AIN=0.6xVREFH (Note 10) 2.85 3.0 3.15 Vpp Input Resistance (Note 11) 18 28 k Power Supply Rejection (Note 12) 50 dB DAC Analog Output Characteristics: Resolution 24 Bits S/(N+D) fs=44.1kHz 80 90 dB fs=96kHz 78 88 dB DR (-60dBFS) fs=44.1kHz, A-weighted 95 106 dB fs=96kHz 88 100 dB fs=96kHz, A-weighted 94 106 dB S/N (Note 13) fs=44.1kHz, A-weighted 95 106 dB fs=96kHz 88 100 dB fs=96kHz, A-weighted 94 106 dB Interchannel Isolation 90 110 dB DC Accuracy Interchannel Gain Mismatch 0.2 0.5 dB Gain Drift 20 ppm/C Output Voltage AOUT=0.6xVREFH 2.75 3.0 3.25 Vpp Load Resistance 5 k Power Supply Rejection (Note 12) 50 dB Power Supplies Power Supply Current Normal Operation (PDN = "H") AVDD 35 56 mA DVDD+TVDD fs=44.1kHz (Note 14) 25 40 mA fs=96kHz 35 56 mA Power-down mode (PDN = "L") (Note 15) 80 200 A Notes: 8. In case of single ended input, S/(N+D)=80dB(typ, @AVDD=5V, fs=44.1kHz). 9. S/N measured by CCIR-ARM is 98dB(@fs=44.1kHz). 10. Full scale input for each AIN+/- pin is 1.5Vpp in differential mode. 11. Input resistance is 14k typically at fs=96kHz. 12. PSR is applied to AVDD, DVDD and TVDD with 1kHz, 50mVpp. VREFH pin is held a constant voltage. 13. S/N measured by CCIR-ARM is 102dB(@fs=44.1kHz). 14. DVDD=TBDmA, TVDD=TBDmA(typ). 15. In the power-down mode. All digital input pins including clock pins (MCLK, BICK, LRCK) are held DVSS. MS0056-E-00 2000/10 -8- ASAHI KASEI [AK4527B] FILTER CHARACTERISTICS (Ta=25C; AVDD, DVDD=4.55.5V; TVDD=2.75.5V; fs=44.1kHz; DEM=OFF) Parameter Symbol min ADC Digital Filter (Decimation LPF): Passband (Note 16) -0.005dB PB 0 -0.02dB -0.06dB -6.0dB Stopband SB 24.34 Passband Ripple PR Stopband Attenuation SA 80 Group Delay (Note 17) GD Group Delay Distortion GD ADC Digital Filter (HPF): Frequency Response (Note 16) -3dB FR -0.5dB -0.1dB DAC Digital Filter: Passband (Note 16) -0.1dB PB 0 -6.0dB Stopband SB 24.2 Passband Ripple PR Stopband Attenuation SA 56 Group Delay (Note 17) GD DAC Digital Filter + Analog Filter: FR Frequency Response: 0 20.0kHz FR 40.0kHz (Note 18) typ max Units 20.02 20.20 22.05 19.76 - 27.6 0 kHz kHz kHz kHz kHz dB dB 1/fs s 0.9 2.7 6.0 Hz Hz Hz 0.005 21.9 kHz kHz kHz dB dB 1/fs 0.2 0.3 dB dB 22.05 20.0 0.02 Notes: 16. The passband and stopband frequencies scale with fs. For example, 20.02kHz at -0.02dB is 0.454 x fs. The reference frequency of these responses is 1kHz. 17. The calculating delay time which occurred by digital filtering. This time is from setting the input of analog signal to setting the 24bit data of both channels to the output register for ADC. For DAC, this time is from setting the 20/24bit data of both channels on input register to the output of analog signal. 18. fs=96kHz. MS0056-E-00 2000/10 -9- ASAHI KASEI [AK4527B] DC CHARACTERISTICS (Ta=25C; AVDD, DVDD=4.55.5V; TVDD=2.75.5V) Parameter Symbol min High-Level Input Voltage VIH 2.2 Low-Level Input Voltage VIL High-Level Output Voltage (SDTO pin: Iout=-100A) VOH TVDD-0.5 (DZF1, DZF2/OZF pins: Iout=-100A) VOH AVDD-0.5 Low-Level Output Voltage (SDTO, DZF1, DZF2/OZF pins: Iout= 100A) VOL (SDA pin: Iout= 3mA) VOL Input Leakage Current Iin - SWITCHING CHARACTERISTICS (Ta=25C; AVDD, DVDD=4.55.5V; TVDD=2.75.5V; CL=20pF) Parameter Symbol min Master Clock Input 256fsn, 128fsd: fCLK 8.192 Pulse Width Low tCLKL 27 Pulse Width High tCLKH 27 384fsn, 192fsd: fCLK 12.288 Pulse Width Low tCLKL 20 Pulse Width High tCLKH 20 512fsn, 256fsd: fCLK 16.384 Pulse Width Low tCLKL 15 Pulse Width High tCLKH 15 LRCK frequency Normal Speed Mode fsn 32 Double Speed Mode fsd 64 Duty Cycle Duty 45 Audio Interface Timing BICK Period tBCK 160 BICK Pulse Width Low tBCKL 65 Pulse Width High tBCKH 65 LRCK Edge to BICK "" (Note 19) tLRB 45 BICK "" to LRCK Edge (Note 19) tBLR 45 LRCK to SDTO(MSB) tLRS BICK "" to SDTO tBSD SDTI1-3, DAUX Hold Time tSDH 40 SDTI1-3, DAUX Setup Time tSDS 25 typ - max 0.8 Units V V - - V V - 0.5 0.4 10 V V A typ max Units 12.288 MHz ns ns MHz ns ns MHz ns ns 18.432 24.576 48 96 55 40 40 kHz kHz % ns ns ns ns ns ns ns ns ns Notes: 19. BICK rising edge must not occur at the same time as LRCK edge. MS0056-E-00 2000/10 - 10 - ASAHI KASEI [AK4527B] Parameter Control Interface Timing (3-wire Serial mode): CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN "H" Time CSN "" to CCLK "" CCLK "" to CSN "" Rise Time of CSN Fall Time of CSN Rise Time of CCLK Fall Time of CCLK Control Interface Timing (I2C Bus mode): SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling (Note 20) SDA Setup Time from SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition Pulse Width of Spike Noise Suppressed by Input Filter Power-down & Reset Timing PDN Pulse Width (Note 21) PDN "" to SDTO valid (Note 22) Symbol tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH tR1 tF1 tR2 tF2 min typ max Units 20 20 20 20 ns ns ns ns ns ns ns ns ns ns ns ns 100 1.0 0.3 50 kHz s s s s s s s s s s ns 200 80 80 40 40 0.025*1/fs 50 50 fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tSP 4.7 4.0 4.7 4.0 4.7 0 0.25 4.0 0 tPD tPDV 150 522 ns 1/fs Notes: 20. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. 21. The AK4527B can be reset by bringing PDN "L" to "H" upon power-up. 22. These cycles are the number of LRCK rising from PDN rising. 23. I2C is a registered trademark of Philips Semiconductors. Purchase of Asahi Kasei Microsystems Co., Ltd I2C components conveys a license under the Philips I2C patent to use the components in the I2C system, provided the system conform to the I2C specifications defined by Philips. MS0056-E-00 2000/10 - 11 - ASAHI KASEI [AK4527B] n Timing Diagram 1/fCLK VIH MCLK VIL tCLKH tCLKL 1/fs VIH LRCK VIL tBCK VIH BICK VIL tBCKH tBCKL Clock Timing VIH LRCK VIL tBLR tLRB VIH BICK VIL tLRS tBSD SDTO 50%TVDD tSDS tSDH VIH SDTI VIL Audio Interface Timing MS0056-E-00 2000/10 - 12 - ASAHI KASEI [AK4527B] VIH CSN VIL tCSS tCCKL tCCKH VIH CCLK VIL tCDS CDTI C1 tCDH C0 R/W VIH A4 VIL WRITE Command Input Timing (3-wire Serial mode) tCSW VIH CSN VIL tCSH VIH CCLK VIL CDTI D3 D2 D1 VIH D0 VIL WRITE Data Input Timing (3-wire Serial mode) VIH SDA VIL tLOW tBUF tR tHIGH tF tSP VIH SCL VIL tHD:STA Stop tHD:DAT tSU:DAT tSU:STA tSU:STO Start Stop Start I2C Bus mode Timing tPD VIH PDN VIL tPDV SDTO 50%TVDD Power-down & Reset Timing MS0056-E-00 2000/10 - 13 - ASAHI KASEI [AK4527B] OPERATION OVERVIEW n System Clock The external clocks, which are required to operate the AK4527B, are MCLK, LRCK and BICK. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS = "0": Default), the sampling speed is set by DFS (Table 1). The frequency of MCLK at each sampling speed is set automatically. (Table 2, 3). In Auto Setting Mode (ACKS = "1"), as MCLK frequency is detected automatically (Table 4), and the internal master clock becomes the appropriate frequency (Table 5), it is not necessary to set DFS. MCLK should be synchronized with LRCK but the phase is not critical. External clocks (MCLK, BICK) should always be present whenever the AK4527B is in normal operation mode (PDN = "H"). If these clocks are not provided, the AK4527B may draw excess current because the device utilizes dynamic refreshed logic internally. If the external clocks are not present, the AK4527B should be in the power-down mode (PDN = "L") or in the reset mode (RSTN = "0"). After exiting reset at power-up etc., the AK4527B is in the power-down mode until MCLK and LRCK are input. DFS 0 1 Sampling Speed (fs) Normal Speed Mode 32kHz~48kHz Double Speed Mode 64kHz~96kHz Default Table 1. Sampling Speed (Manual Setting Mode) LRCK fs 32.0kHz 44.1kHz 48.0kHz 256fs 8.1920 11.2896 12.2880 MCLK (MHz) 384fs 12.2880 16.9344 18.4320 512fs 16.3840 22.5792 24.5760 BICK (MHz) 64fs 2.0480 2.8224 3.0720 Table 2. System Clock Example (Normal Speed Mode @Manual Setting Mode) LRCK fs 88.2kHz 96.0kHz 128fs 11.2896 12.2880 MCLK (MHz) 192fs 16.9344 18.4320 256fs 22.5792 24.5760 BICK (MHz) 64fs 5.6448 6.1440 Table 3. System Clock Example (Double Speed Mode @Manual Setting Mode) (Note: At double speed mode(DFS = "1"), 128fs and 192fs are not available for ADC.) MCLK 512fs 256fs Sampling Speed Normal Double Table 4. Sampling Speed (Auto Setting Mode) MS0056-E-00 2000/10 - 14 - ASAHI KASEI [AK4527B] LRCK fs 32.0kHz 44.1kHz 48.0kHz 88.2kHz 96.0kHz MCLK (MHz) 256fs 512fs 16.3840 22.5792 24.5760 22.5792 24.5760 - Sampling Speed Normal Double Table 5. System Clock Example (Auto Setting Mode) n De-emphasis Filter The AK4527B includes the digital de-emphasis filter (tc=50/15s) by IIR filter. This filter corresponds to three sampling frequencies (32kHz, 44.1kHz, 48kHz). De-emphasis of each DAC can be set individually by register data of DEMA1-C0 (DAC1: DEMA1-0, DAC2: DEMB1-0, DAC3: DEMC1-0, see "Register Definitions"). Mode 0 1 2 3 4 5 6 7 Sampling Speed Normal Speed Normal Speed Normal Speed Normal Speed Double Speed Double Speed Double Speed Double Speed DEM1 0 0 1 1 0 0 1 1 DEM0 0 1 0 1 0 1 0 1 DEM 44.1kHz OFF 48kHz 32kHz OFF OFF OFF OFF Default Table 6. De-emphasis control n Digital High Pass Filter The ADC has a digital high pass filter for DC offset cancel. The cut-off frequency of the HPF is 0.9Hz at fs=44.1kHz and also scales with sampling rate (fs). n Audio Serial Interface Format Four serial data modes can be selected by the DIF0 and DIF1 pins (P/S = "H") or bits (P/S = "L") as shown in Table 7. In all modes the serial data is MSB-first, 2's compliment format. The SDTO is clocked out on the falling edge of BICK and the SDTI/DAUX are latched on the rising edge of BICK. Figures 14 shows the timing at SDOS = "L". In this case, the SDTO outputs the ADC output data. When SDOS = "H", the data input to DAUX is converted to SDTO's format and output from SDTO. Mode 2 and mode 3 in SDTI/DAUX input formats can be used for 16-20bit data by zeroing the unused LSBs. Mode 0 1 2 3 DIF1 0 0 1 1 DIF0 0 1 0 1 SDTO 24bit, MSB justified 24bit, MSB justified 24bit, MSB justified 24bit, IIS (I2S) SDTI1-3, DAUX 20bit, LSB justified 24bit, LSB justified 24bit, MSB justified 24bit, IIS (I2S) LRCK H/L H/L H/L L/H Default Table 7. Audio data formats MS0056-E-00 2000/10 - 15 - ASAHI KASEI [AK4527B] LRCK 0 1 2 12 13 14 24 25 31 0 1 2 12 13 14 24 25 31 0 1 BICK(64fs) SDTO(o) 23 22 SDTI(i) 12 11 10 Don't Care 0 19 18 23 22 8 7 1 12 11 10 Don't Care 0 0 19 18 SDTO-23:MSB, 0:LSB; SDTI-19:MSB, 0:LSB Lch Data 23 8 7 1 0 Rch Data Figure 1. Mode 0 Timing LRCK 0 1 2 8 9 10 24 25 31 0 1 2 8 9 10 24 25 31 0 1 BICK(64fs) SDTO(o) 23 22 SDTI(i) 16 15 14 0 23 22 8 Don't Care 23 22 7 1 16 15 14 Don't Care 0 0 23 22 8 23 7 1 0 23:MSB, 0:LSB Lch Data Rch Data Figure 2. Mode 1 Timing LRCK 0 1 2 18 19 20 21 28 29 30 31 0 1 2 19 20 21 28 29 30 31 0 1 BICK(64fs) SDTO(o) 23 22 2 1 0 SDTI(i) 23 22 2 1 0 Don't Care 23 22 2 1 0 23 22 2 1 0 23 Don't Care 23 23:MSB, 0:LSB Lch Data Rch Data Figure 3. Mode 2 Timing LRCK 0 1 2 3 23 24 25 26 29 30 31 0 1 2 3 23 24 25 26 29 30 31 0 1 BICK(64fs) SDTO(o) 23 22 2 1 0 SDTI(i) 23 22 2 1 0 23:MSB, 0:LSB Don't Care 23 22 2 1 0 23 22 2 1 0 Lch Data Don't Care Rch Data Figure 4. Mode 3 Timing MS0056-E-00 2000/10 - 16 - ASAHI KASEI [AK4527B] n Overflow Detection The AK4527B has overflow detect function for analog input. Overflow detection is enabled when OVFE bit is set to "1" at serial control mode. OVF pin goes to "H" if analog input of Lch or Rch overflows. OVF output for overflowed analog input has the same group delay as ADC (GD=27.6/fs=626s@fs=44.1kHz). OVF is "L" for 522/fs(=11.8ms@fs=44.1kHz) after PDN = "", and then overflow detection is enabled. n Zero detection The AK4527B has two pins for zero detect flag outputs. Channel grouping can be selected by DZFM2-0 bits if P/S = "L" and DZFE = "L" (table 8). DZF1 pin corresponds to the group 1 channels and DZF2 pin corresponds to the group 2 channels. However DZF2 pin becomes OVF pin if OVFE bit is set to "1". Zero detection mode is set to mode 0 if DZFE= "H" regardless of P/S pin. DZF1 is AND of all six channels and DZF2 is disabled ("L") at mode 0. Table 9 shows the relation of P/S, DZFE, OVFE and DZF. When the input data of all channels in the group 1(group 2) are continuously zeros for 8192 LRCK cycles, DZF1(DZF2) pin goes to "H". DZF1(DZF2) pin immediately goes to "L" if input data of any channels in the group 1(group 2) is not zero after going DZF1(DZF2) "H". Mode 0 1 2 3 4 5 6 7 2 0 0 0 0 1 1 1 1 DZFM 1 0 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 L1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF2 AOUT R1 L2 R2 L3 DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF2 DZF1 DZF1 DZF2 DZF2 DZF1 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 disable (DZF1=DZF2 = "L") R3 DZF1 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 Default Table 8. Zero detect control P/S pin "H" (parallel mode) "L" (serial mode) DZFE pin "L" "H" "L" "H" OVFE bit disable disable "0" "1" "0" "1" DZF mode Mode 7 Mode 0 Selectable Selectable Mode 0 Mode 0 DZF1 pin "L" AND of 6ch Selectable Selectable AND of 6ch AND of 6ch DZF2/OVF pin "L" "L" Selectable OVF output "L" OVF output Table 9. DZF1-2 pins outputs MS0056-E-00 2000/10 - 17 - ASAHI KASEI [AK4527B] n Digital Attenuator AK4527B has channel-independent digital attenuator (256 levels, 0.5dB step). Attenuation level of each channel can be set by each ATT7-0 bits (table 10). ATT7-0 00H 01H 02H : FDH FEH FFH Attenuation Level 0dB -0.5dB -1.0dB : -126.5dB -127.0dB MUTE (-) Default Table 10. Attenuation level of digital attenuator The transition between set values is soft transition of 7425 levels. It takes 7424/fs (168ms@fs=44.1kHz) from 00H(0dB) to FFH(MUTE). If PDN pin goes to "L", the ATTs are initialized to 00H. The ATTs are 00H when RSTN = "0". When RSTN return to "1", the ATTs fade to their current value. Digital attenuator is independent of soft mute function. MS0056-E-00 2000/10 - 18 - ASAHI KASEI [AK4527B] n Soft mute operation Soft mute operation is performed at digital domain. When the SMUTE pin goes to "H", the output signal is attenuated by - during 1024 LRCK cycles. When the SMUTE pin is returned to "L", the mute is cancelled and the output attenuation gradually changes to 0dB during 1024 LRCK cycles. If the soft mute is cancelled within 1024 LRCK cycles after starting the operation, the attenuation is discontinued and returned to 0dB. The soft mute is effective for changing the signal source without stopping the signal transmission. SMUTE 1024/fs 0dB 1024/fs (1) (3) Attenuation - GD (2) GD AOUT DZF1,2 (4) 8192/fs Notes: (1) The output signal is attenuated by - during 1024 LRCK cycles (1024/fs). (2) Analog output corresponding to digital input have the group delay (GD). (3) If the soft mute is cancelled within 1024 LRCK cycles, the attenuation is discontinued and returned to 0dB. (4) When the input data of all channels in the group are continuously zeros for 8192 LRCK cycles, DZF pin corresponding to the group goes to "H". DZF pin immediately goes to "L" if input data of any channel in the group is not zero after going DZF "H". Figure 5. Soft mute and zero detection n System Reset The AK4527B should be reset once by bringing PDN = "L" upon power-up. The AK4527B is powered up and the internal timing starts clocking by LRCK "" after exiting reset and power down state by MCLK. The AK4527B is in the power-down mode until MCLK and LRCK are input. MS0056-E-00 2000/10 - 19 - ASAHI KASEI [AK4527B] n Power-Down The ADC and DACs of AK4527B are placed in the power-down mode by bringing PDN "L" and both digital filters are reset at the same time. PDN "L" also reset the control registers to their default values. In the power-down mode, the analog outputs go to VCOM voltage and DZF1-2 pins go to "L". This reset should always be done after power-up. In case of the ADC, an analog initialization cycle starts after exiting the power-down mode. Therefore, the output data, SDTO becomes available after 522 cycles of LRCK clock. In case of the DAC, an analog initialization cycle starts after exiting the power-down mode. The analog outputs are VCOM voltage during the initialization. Figure 6 shows the power-up sequence. The ADC and DACs can be powered-down individually by PWADN and PWDAN bits. In this case, the internal register values are not initialized. When PWADN = "0", SDTO goes to "L". When PWDAN = "0", the analog outputs go to VCOM voltage and DZF1-2 pins go to "H". Because some click noise occurs, the analog output should muted externally if the click noise influences system application. PDN 522/fs ADC Internal State Normal Operation Power-down (1) Init Cycle Normal Operation 516/fs (2) DAC Internal State Normal Operation Power-down Init Cycle Normal Operation GD (3) GD ADC In (Analog) (4) ADC Out (Digital) "0"data DAC In (Digital) "0"data GD (5) (3) GD (6) DAC Out (Analog) (6) (7) Clock In Don't care MCLK,LRCK,SCLK 1011/fs (10) (8) DZF1/DZF2 External Mute (9) Mute ON Notes: (1) The analog part of ADC is initialized after exiting the power-down state. (2) The analog part of DAC is initialized after exiting the power-down state. (3) Digital output corresponding to analog input and analog output corresponding to digital input have the group delay (GD). (4) ADC output is "0" data at the power-down state. (5) Click noise occurs at the end of initialization of the analog part. Please mute the digital output externally if the click noise influences system application. Required muting time depends on the configuration of the input buffer circuits. Figure 12,13: 1s Figure 14,15: 200ms (6) Click noise occurs at the falling edge of PDN and at 512/fs after the rising edge of PDN. (7) When the external clocks (MCLK, BICK and LRCK) are stopped, the AK4527B should be in the power-down mode. (8) DZF pins are "L" in the power-down mode (PDN = "L"). (9) Please mute the analog output externally if the click noise (6) influences system application. (10) DZF= "L" for 1011/fs after PDN= "". Figure 6. Power-down/up sequence example MS0056-E-00 2000/10 - 20 - ASAHI KASEI [AK4527B] n Reset Function When RSTN = "0", ADC and DACs are powered-down but the internal register are not initialized. The analog outputs go to VCOM voltage, DZF1-2 pins go to "H" and SDTO pin goes to "L". Because some click noise occurs, the analog output should muted externally if the click noise influences system application. Figure 7 shows the power-up sequence. RSTN bit 4~5/fs (9) 1~2/fs (9) Internal RSTN bit 516/fs (1) ADC Internal State Normal Operation Digital Block Power-down DAC Internal State Normal Operation Digital Block Power-down Normal Operation Init Cycle Normal Operation GD (2) GD ADC In (Analog) (3) ADC Out (Digital) (4) "0"data DAC In (Digital) "0"data (2) GD DAC Out (Analog) GD (6) (6) (5) (7) Clock In MCLK,LRCK,SCLK Don't care 45/fs (8) DZF1/DZF2 Notes: (1) The analog part of ADC is initialized after exiting the reset state. (2) Digital output corresponding to analog input and analog output corresponding to digital input have the group delay (GD). (3) ADC output is "0" data at the power-down state. (4) Click noise occurs when the internal RSTN bit becomes "1". Please mute the digital output externally if the click noise influences system application. Required muting time depends on the configuration of the input buffer circuits. Figure 12,13: 1s Figure 14,15: 200ms (5) The analog outputs go to VCOM voltage. (6) Click noise occurs at 45/fs after RSTN bit becomes "0", and occurs at 12/fs after RSTN bit becomes "1". This noise is output even if "0" data is input. (7) The external clocks (MCLK, BICK and LRCK) can be stopped in the reset mode. When exiting the reset mode, "1" should be written to RSTN bit after the external clocks (MCLK, BICK and LRCK) are fed. (8) DZF pins go to "H" when the RSTN bit becomes "0", and go to "L" at 6~7/fs after RSTN bit becomes "1". (9) There is a delay, 4~5/fs from RSTN bit "0" to the internal RSTN bit "0". Figure 7. Reset sequence example MS0056-E-00 2000/10 - 21 - ASAHI KASEI [AK4527B] n Serial Control Interface The AK4527B can control its functions via registers. Internal registers may be written by 2 types of control mode. The chip address is determined by the state of the CAD0 and CAD1 inputs. PDN = "L" initializes the registers to their default values. Writing "0" to the RSTN bit can initialize the internal timing circuit. But in this case, the register data is not be initialized. When the state of P/S pin is changed, the AK4527B should be reset by PDN pin. * Writing to control register is invalid when PDN = "L" or the MCLK is not fed. * AK4527B does not support the read command. (1) 3-wire Serial Control Mode (I2C = "L") Internal registers may be written to the 3 wire P interface pins (CSN,CCLK and CDTI). The data on this interface consists of Chip address (2bits, CAD0/1), Read/Write (1bit, Fixed to "1"; Write only), Register address (MSB first, 5bits) and Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of CCLK and data is clocked out on the falling edge. For write operations, data is latched after a low-to-high transition of CSN. The clock speed of CCLK is 5MHz(max). The CSN pins should be held to "H" except for access. CSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CCLK CDTI C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 C1-C0: Chip Address (C1=CAD1, C0=CAD0) R/W: Read/Write (Fixed to "1" : Write only) A4-A0: Register Address D7-D0: Control Data Figure 8. 3-wire Serial Control I/F Timing (2) I2C Bus Control Mode (I2C = "H") Internal registers may be written to I2C Bus interface pins: SCL & SDA. The data on this interface consists of Chip address (2bits, CAD0/1), Read/Write (1bit, Fixed to "0"; Write only), Register address (MSB first, 5bits) and Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of SCL and data is clocked out on the falling edge. Data can be written after a high-to-low transition of SDA when SCL is "H"(start condition), and is latched after a low-to-high transition of SDA when SCL is "H"(stop condition). The clock speed of SCL is 100kHz(max). The CSN pin should be connected to DVDD at I2C Bus control mode. The AK4527B does not have a register address auto increment capability. R/W ACK SDA 0 0 1 0 0 C1 C0 ACK 0 0 0 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 SCL Stop Start C1-C0: Chip Address (C1=CAD1, C0=CAD0) R/W: Read/Write (Fixed to "0" : Write only) A4-A0: Register Address D7-D0: Control Data ACK: Acknowledge Figure 9. I2C-bus Control I/F Timing MS0056-E-00 2000/10 - 22 - ASAHI KASEI [AK4527B] n Mapping of Program Registers Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH Register Name Control 1 Control 2 LOUT1 Volume Control ROUT1 Volume Control LOUT2 Volume Control ROUT2 Volume Control LOUT3 Volume Control ROUT3 Volume Control De-emphasis Reset Zero detect D7 0 0 ATT7 ATT7 ATT7 ATT7 ATT7 ATT7 D6 0 0 ATT6 ATT6 ATT6 ATT6 ATT6 ATT6 D5 0 LOOP1 ATT5 ATT5 ATT5 ATT5 ATT5 ATT5 D4 0 LOOP0 ATT4 ATT4 ATT4 ATT4 ATT4 ATT4 D3 DIF1 SDOS ATT3 ATT3 ATT3 ATT3 ATT3 ATT3 D2 DIF0 DFS ATT2 ATT2 ATT2 ATT2 ATT2 ATT2 D1 0 ACKS ATT1 ATT1 ATT1 ATT1 ATT1 ATT1 D0 SMUTE 0 ATT0 ATT0 ATT0 ATT0 ATT0 ATT0 0 0 DEMA1 DEMA0 DEMB1 DEMB0 DEMC1 0 0 0 0 0 0 0 DEMC0 RSTN OVFE 0 DZFM2 DZFM1 DZFM0 PWVRN PWADN PWDAN Note: For addresses from 0BH to 1FH, data is not written. When PDN goes to "L", the registers are initialized to their default values. When RSTN bit goes to "0", the internal timing is reset and DZF1-2 pins go to "H", but registers are not initialized to their default values. SMUTE, DFS, SDOS and LOOP1 are ORed with pins. MS0056-E-00 2000/10 - 23 - ASAHI KASEI [AK4527B] n Register Definitions Addr 00H Register Name Control 1 default D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 DIF1 1 D2 DIF0 0 D1 0 0 SMUTE D0 D2 DFS 0 D1 ACKS 0 D0 0 0 0 SMUTE: Soft Mute Enable 0: Normal operation 1: All DAC outputs soft-muted Register bit of SMUTE is ORed with the SMUTE pin if P/S = "L". DIF1-0: Audio Data Interface Modes (see table 7.) Initial: "10", mode 2 Addr 01H Register Name Control 2 default D7 0 0 D6 0 0 D5 LOOP1 0 D4 LOOP0 0 D3 SDOS 0 ACKS: Master Clock Frequency Auto Setting Mode Enable 0: Disable, Manual Setting Mode 1: Enable, Auto Setting Mode Master clock frequency is detected automatically at ACKS bit "1". In this case, the setting of DFS are ignored. When this bit is "0", DFS sets the sampling speed mode. DFS: Sampling speed mode (see table 1.) 0: Normal speed 1: Double speed Register bit of DFS is ORed with DFS pin if P/S = "L". The setting of DFS are ignored at ACKS bit "1". SDOS: SDTO source select 0: ADC 1: DAUX Register bit of SDOS is ORed with SDOS pin if P/S = "L". LOOP1-0: Loopback mode enable 00: Normal (No loop back) 01: LIN LOUT1, LOUT2, LOUT3 RIN ROUT1, ROUT2, ROUT3 The digital ADC output (DAUX input if SDOS = "1") is connected to the digital DAC input. In this mode, the input DAC data to SDTI1-3 is ignored. The audio format of SDTO at loopback mode becomes mode 2 at mode 0, and mode 3 at mode 1, respectively. 10: SDTI1(L) SDTI2(L), SDTI3(L) SDTI1(R) SDTI2(R), SDTI3(R) In this mode the input DAC data to SDTI2-3 is ignored. 11: N/A Register bit of LOOP1 is ORed with LOOP1 pin if P/S = "L". MS0056-E-00 2000/10 - 24 - ASAHI KASEI Addr 02H 03H 04H 05H 06H 07H Register Name LOUT1 Volume Control ROUT1 Volume Control LOUT2 Volume Control ROUT2 Volume Control LOUT3 Volume Control ROUT3 Volume Control Default [AK4527B] D7 ATT7 ATT7 ATT7 ATT7 ATT7 ATT7 0 D6 ATT6 ATT6 ATT6 ATT6 ATT6 ATT6 0 D5 ATT5 ATT5 ATT5 ATT5 ATT5 ATT5 0 D4 ATT4 ATT4 ATT4 ATT4 ATT4 ATT4 0 D3 ATT3 ATT3 ATT3 ATT3 ATT3 ATT3 0 D2 ATT2 ATT2 ATT2 ATT2 ATT2 ATT2 0 D1 ATT1 ATT1 ATT1 ATT1 ATT1 ATT1 0 D0 ATT0 ATT0 ATT0 ATT0 ATT0 ATT0 0 ATT7-0: Attenuation Level (see table 9.) Addr 08H Register Name De-emphasis Default D7 D6 D5 D4 D3 D2 D1 D0 0 0 DEMA1 DEMA0 DEMB1 DEMB0 DEMC1 DEMC0 0 0 0 1 0 1 0 1 DEMA1-0: De-emphasis response control for DAC1 data on SDTI1 (see table 6.) Initial: "01", OFF DEMB1-0: De-emphasis response control for DAC2 data on SDTI2 (see table 6.) Initial: "01", OFF DEMC1-0: De-emphasis response control for DAC3 data on SDTI3 (see table 6.) Initial: "01", OFF MS0056-E-00 2000/10 - 25 - ASAHI KASEI Addr 09H [AK4527B] Register Name Clock mode Default D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 0 0 D1 0 0 D0 RSTN 1 RSTN: Internal timing reset 0: Reset. DZF1-2 pins go to "H", but registers are not initialized. 1: Normal operation Addr 0AH Register Name Zero detect Default D7 D6 D5 D4 D3 D2 D1 D0 OVFE 0 DZFM2 DZFM1 DZFM0 PWVRN PWADN PWDAN 0 0 1 1 1 1 1 1 PWDAN: Power-down control of DAC1-3 0: Power-down 1: Normal operation PWADN: Power-down control of ADC 0: Power-down 1: Normal operation PWVRN: Power-down control of reference voltage 0: Power-down 1: Normal operation DZFM2-0: Zero detect mode select (see table 8.) Initial: "111", disable OVFE: Overflow detection enable 0: Disable, pin#33 becomes DZF2 pin. 1: Enable, pin#33 becomes OVF pin. MS0056-E-00 2000/10 - 26 - ASAHI KASEI [AK4527B] SYSTEM DESIGN Figure 10 shows the system connection diagram. An evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. Condition: TVDD=5V, 3-wire serial control mode, CAD1-0 = "00", Full-differential input Analog 5V + uP 10u + 2.2u 0.1u 1 SDOS VCOM 34 AVDD 36 AVSS 37 DZF1 38 P/S 40 MCLK 39 CSN 41 VREFH 35 (DIR) CCLK 42 Digital Audio Source CDTI 43 LOOP1 44 0.1u DZF2 33 470 RIN+ 32 2 I2C 1n 3 SMUTE RIN- 31 4 BICK LIN+ 30 470 470 ROUT1 28 MUTE 7 SDTI2 LOUT1 27 MUTE 8 SDTI3 ROUT2 26 MUTE + 22 CAD0 21 CAD1 20 ADIF 19 NC MUTE 18 TST LOUT3 23 17 PDN MUTE 11 DFS 16 DVSS MUTE ROUT3 24 15 DVDD LOUT2 25 14 TVDD 9 SDTO 10 DAUX 12 NC (MPEG/ AC3) 470 LIN- 29 6 SDTI1 13 DZFE Audio DSP 1n AK4527B 5 LRCK 0.1u 10u 5 Power-down control Digital Ground Analog Ground Figure 10. Typical Connection Diagram MS0056-E-00 2000/10 - 27 - ASAHI KASEI [AK4527B] 3 SMUTE 4 BICK 5 LRCK AK4527B RIN+ 32 RIN- 31 LIN+ 30 LIN- 29 21 CAD1 20 ADIF LOUT3 23 19 NC ROUT3 24 11 DFS 18 TST LOUT2 25 10 DAUX 17 PDN ROUT2 26 9 SDTO 15 DVDD LOUT1 27 8 SDTI3 14 TVDD 7 SDTI2 13 DZFE ROUT1 28 12 NC 6 SDTI1 16 DVSS Controller VCOM 34 AVDD 36 VREFH 35 DZF1 38 AVSS 37 P/S 40 MCLK 39 DZF2/OVF 33 22 CAD0 System DIF0/CSN 41 1 SDOS 2 I2C DIF1/SCL/CCLK 42 LOOP1 44 Analog Ground LOOP0/SDA/CDTI 43 Digital Ground Figure 11. Ground Layout Note: AVSS and DVSS must be connected to the same analog ground plane. 1. Grounding and Power Supply Decoupling The AK4527B requires careful attention to power supply and grounding arrangements. AVDD and DVDD are usually supplied from analog supply in system. Alternatively if AVDD and DVDD are supplied separately, the power up sequence is not critical. AVSS and DVSS of the AK4527B must be connected to analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4527B as possible, with the small value ceramic capacitor being the nearest. 2. Voltage Reference Inputs The voltage of VREFH sets the analog input/output range. VREFH pin is normally connected to AVDD with a 0.1F ceramic capacitor. VCOM is a signal ground of this chip. An electrolytic capacitor 2.2F parallel with a 0.1F ceramic capacitor attached to VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from VCOM pin. All signals, especially clocks, should be kept away from the VREFH and VCOM pins in order to avoid unwanted coupling into the AK4527B. 3. Analog Inputs The ADC inputs are differential. Figures 12 and 13 are circuit examples which analog signal is input by single end (ADIF= "L"). The signal can be input from either positive or negative input and the input signal range scales with the supply voltage and nominally 0.6 x VREFH Vpp. In case of single ended input, the distortion around full scale degrades compared with differential input (ADIF= "H"). Figures 14 and 15 are circuit examples which analog signal is input to both positive and negative input and the input signal range scales with the supply voltage and nominally 0.3 x VREFH Vpp. The AK4527B can accept input voltages from AVSS to AVDD. The ADC output data format is 2's complement. The output code is 7FFFFFH(@24bit) for input above a positive full scale and 800000H(@24bit) for input below a negative fill scale. The ideal code is 000000H(@24bit) with no input signal. The DC offset is removed by the internal HPF. The AK4527B samples the analog inputs at 64fs. The digital filter rejects noise above the stop band except for multiples of 64fs. A simple RC filter (fc=150kHz) may be used to attenuate any noise around 64fs and most audio signals do not have significant energy at 64fs. MS0056-E-00 2000/10 - 28 - ASAHI KASEI [AK4527B] AK4527B 2.2nF 22 470 RIN+ 32 3.0Vpp Signal AVDD 470 RIN- 31 4.7k 0.1 LIN+ 30 BIAS + 4.7k LIN- 29 10 Same circuit Figure 12. Single End Input Example (ADIF= "L"; Not using op-amp) 4.7k NJM2100 Vop=AVDD=5V AK4527B 2.2nF Vop RIN+ 32 22 10k + 470 Signal AVDD 470 6.4Vpp RIN- 31 4.7k 3.0Vpp 0.1 LIN+ 30 4.7k LIN- 29 BIAS + 10 Same circuit Figure 13. Single End Input Example (ADIF= "L"; Using op-amp) 4.7k 10k 1.5Vpp AK4527B 1nF 470 RIN+ 32 470 Vop 10k + NJM2100 22 10k + Signal AVDD 3.2Vpp RIN- 31 4.7k 1.5Vpp Vop=AVDD=5V LIN+ 30 0.1 BIAS + 4.7k LIN- 29 10 Same circuit Figure 14. Differential Input Buffer Example (ADIF= "H"; Using op-amp with single power supply) 1.5Vpp AVDD 4.7k 10k AK4527B 1nF 470 RIN+ 32 470 +Vop 10k + NJM5532 10k + 22 Signal AVDD 3.2Vpp -Vop RIN- 31 4.7k Vop=12V LIN+ 30 0.1 BIAS 1.5Vpp LIN- 29 4.7k + 10 Same circuit Figure 15. Differential Input Buffer Example (ADIF= "H"; Using op-amp with dual power supply) MS0056-E-00 2000/10 - 29 - ASAHI KASEI [AK4527B] 4. Analog Outputs The analog outputs are also single-ended and centered around the VCOM voltage. The input signal range scales with the supply voltage and nominally 0.6 x VREFH Vpp. The DAC input data format is 2's complement. The output voltage is a positive full scale for 7FFFFFH(@24bit) and a negative full scale for 800000H(@24bit). The ideal output is VCOM voltage for 000000H(@24bit). The internal analog filters remove most of the noise generated by the delta-sigma modulator of DAC beyond the audio passband. DC offsets on analog outputs are eliminated by AC coupling since DAC outputs have DC offsets of a few mV. n Peripheral I/F Example The AK4527B can accept the signal of device with a nominal 3.3V supply because of TTL input. The power supply for output buffer (TVDD) of the AK4527B should be 3.3V when the peripheral devices operate at a nominal 3.3V supply. Figure 16 shows an example with the mixed system of 3.3V and 5V. 3.3V Analog 5V for input 3.3V Digital Audio signal PLL I/F DSP AK4112A 5V Analog 3.3V for output 5V Digital uP & Others Analog Digital Control signal AK4527B Figure 16. Power supply connection example MS0056-E-00 2000/10 - 30 - ASAHI KASEI [AK4527B] n Applications 1) Zoran AC3 decoder, ZR38650 Analog Input AK4527B Analog Output DFS SDTO SDA SDTI1 SDB SDTI2 SDC SDTI3 SDD LRCK BICK WSB MCLK SCKB ZR38650 WSA SCKA SCKIN GPIO2 SPFRX Digital Input Figure 17. Application circuit example (ZR38650) 2) Yamaha AC3 decoder, YSS912 Analog Input Analog Output SDTO SDTI1 AK4527B SDTI2 SDTI3 LRCK BICK MCLK 256fs 256fs Digital Input SDIA1 SDOB0 SDOB1 SDOB2 SDWCK0 SDBCK0 YSS912 MCKO1 LRCK YM3436 or AK4112A BICK SDTO RX SDIA0 Figure 18. Application circuit example (YSS912) 3) Motorola AC3 decoder, DSP56362 Analog Input Analog Output SDTO SDTI1 AK4527B SDTI2 SDTI3 LRCK BICK MCLK 256fs MCKO1 256fs AK4112A Digital Input LRCK BICK SDTO SDI1 SDO0 SDO1 SDO2 FSR SCKR FST SCKT DSP56362 SDI0 RX Figure 19. Application circuit example (DSP56362) MS0056-E-00 2000/10 - 31 - ASAHI KASEI [AK4527B] PACKAGE 44pin LQFP (Unit: mm) 1.70max 12.800.30 00.2 10.00 23 33 0.80 12.800.30 22 10.00 34 12 44 1 11 0.370.10 0.170.05 010 0.600.20 0.15 n Package & Lead frame material Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder plate MS0056-E-00 2000/10 - 32 - ASAHI KASEI [AK4527B] MARKING AKM AK4527BVQ XXXXXXX JAPAN 1 1) Pin #1 indication 2) Date Code: XXXXXXX(7 digits) 3) Marking Code: AK4527BVQ 4) Country of Origin 5) Asahi Kasei Logo IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0056-E-00 2000/10 - 33 -