ZERO DELAY, LOW SKEW BUFFER AND
MDS 671-01 C 4Revision 111502
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 295-9800 l www.icst.com
ICS671-01
AC Electrical Characteristics
VDD = 3.3V ±10%, Ambient Temperature 0to +70°C, CLOAD at CLK = 15 pF, unless stated otherwise
Note 1: With CLKIN = 20 MHz, FBIN to CLK8, all outputs at 40 MHz
Note 2:With CLKIN = 80 MHz, FBIN to CLK8, all outputs at 160 MHz
Note 3: These specs do not apply to mode 01
Input Low Current IIL VIN = 0V 50 µA
Input High Current IIH VIN = VDD 100 µA
Output High Voltage VOH IOH = -25 mA 2.4 V
Ouput Low Voltage VOL IOL = 25mA 0.4 V
Output High Voltage,
CMOS level VOH IOH = -8 mA VDD-0.4 V
Operating Supply Current IDD No Load, S1 = 1, S0 = 0,
Note 1 25 mA
No Load, S1 = 1, S0 =0
Note 2
Power Down Supply
Current IDDPD CLKIN = 0, S0 = 0, S1 = 0 500 µA
Short Circuit Current IOS Each output ±50 mA
Input Capacitance CIN S0, S1, FBIN 7 pF
Parameter Symbol Conditions Min. Typ. Max. Units
Parameter Symbol Conditions Min. Typ. Max. Units
Input Clock Frequency fIN See table on page 2 5 80 MHz
Output Clock Frequency See table on page 2 5 160 MHz
Output Rise Time tOR 0.8 to 2.0V, CL=30pF 1.5 ns
Output Fall Time tOF 2.0 to 0.8V, CL=30pF 1.5 ns
Output Clock Duty Cycle tDC measured at VDD/2 40 50 60 %
Device to Device Skew rising edges at VDD/2, Note 3 700 ps
Output to Output Skew rising edges at VDD/2, Note 3 250 ps
Input to Output Skew rising edges at VDD/2, FBIN to
CLK8 ±350 ps
Maximum Absolute JItter 15pF 300 ps
Cycle to Cycle Jitter 30pF loads 500 ps
PL L Lock Time Note 3 1.0 ms