APL5605 600mA Linear Regulator for DC Fan Speed Control Features General Description * Low Dropout Voltage: 220mV (typical) @ 600mA * Low Quiescent Current: 140A * Enable/Shutdown function * Output Voltage / VSET Voltage: 1.6 times * Stable with Low ESR Ceramic Capacitors * Over-Temperature Protection * Current Limit Protection with Foldback Current * Internal Soft-start * SOP-8 Package * Lead Free Available (RoHS Compliant) The APL5605 is a low quiescent current and low dropout linear regulator which is designed to power a DC fan and delivers up to 600mA output current. The output voltage follows the 1.6 times of VSET voltage and typical dropout voltage is only 220mV (typical) at 600mA output current. The APL5605 with low 140A quiescent current is ideal for battery-powered system appliances and stable with a 2.2F ceramic output capacitor. The features of current limit (with foldback current) and overtemperature protection protect the device against current over-loads and over temperature. The APL5605 is available in a SOP-8 package. Simplified Application Circuit Applications * Notebook Fan Driver * Motherboards * PC Peripherals * Battery-Powered System VOUT VIN VOUT VIN C2 C1 2.2F APL5605 1F ON EN VSET GND VSET OFF Ordering and Marking Information APL5605 Package Code K : SOP-8 Operating Ambient Temperature Range I : -40 to 85 C Handling Code TR : Tape & Reel Lead Free Code L : Lead Free Device Lead Free Code Handling Code Temperature Range Package Code APL5605 APL5605 K : XXXXX - Date Code XXXXX Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldering operations. ANPEC lead-free products meet or exceed the leadfree requirements of IPC/JEDEC J STD-020C for MSL classification at lead-free peak reflow temperature. ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.1 - Jan., 2008 1 www.anpec.com.tw APL5605 Pin Configuration SOP-8 Top View EN 1 8 GND VIN 2 7 GND VOUT 3 6 GND VSET 4 5 GND APL5605 Absolute Maximum Ratings Symbol (Note 1) Rating Unit VIN VIN to GND Parameter -0.3 ~ 6.5 V VEN EN to GND -0.3 ~ VIN+0.3 V VOUT VOUT to GND -0.3 ~ VIN+0.3 TJ Maximum Junction Temperature PD Power Dissipation 150 V o C Internally Limited TSTG Storage Temperature Range TSDR Maximum Lead Temperature (Soldering, 10 sec) -65 ~ 150 o 260 o C C Note 1: Stresses beyond the absolute maximum rating may damage the device and exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol JA Parameter Junction to Ambient Thermal Resistance SOP-8 Rating Unit 80 C/W Note 2: JA is measured with the component mounted on a high effective thermal conductivity test board in free air. Recommended Operating Conditions Symbol Parameter Range Unit VIN VIN to GND 4.5 ~ 6 V VEN EN to GND 0 ~ VIN V VOUT VOUT to GND 0 ~ VIN-VDROP V VSET VSET to GND 0 ~ 3.3 V IOUT Output Current 0 ~ 0.6 A CIN Input Capacitor 0.82 ~ 470 COUT Output Capacitor 1 ~ 330 F TJ Junction Temperature -40 ~ 125 C TA Ambient Temperature -40 ~ 85 C Copyright ANPEC Electronics Corp. Rev. A.1 - Jan., 2008 2 www.anpec.com.tw APL5605 Electrical Characteristics Refer to the typical application circuit. VIN = 5V, VEN = VIN, IOUT = 1mA~600mA, TJ = -40 to 125 C, TA = -40 to 85C, unless otherwise specified. Typical values are at TA = 25 C. Parameter Symbol Test Conditions Min Typ Max Unit VEN = 0V - - 1 A VEN = 5V, IOUT = 0A - 140 200 A 2.1 2.5 2.9 V - 0.15 - V SUPPLY CURRENT IQ Quiescent Current UNDER-VOLTAGE-LOCKOUT (UVLO) VIN UVLO Threshold VIN rising VIN UVLO Hysteresis OUTPUT VOLTAGE VDROP VOUT Voltage / VSET Voltage TJ = 25C, VIN=5.5V, IOUT=1mA, VSET=3.3V 1.552 1.6 1.648 V/V VOUT Voltage / VSET Voltage TJ = 40 ~ 125C, VIN=5.5V, IOUT=1mA, VSET=1 ~ 3.3V 1.504 1.6 1.696 V/V VSET pin Current VSET=5V - 0.05 1 A Load Regulation IOUT = 1mA to 600mA - 60 100 mV IOUT=600mA, VOUT=2.5V - 250 400 mV IOUT=600mA, VOUT=3.3V - 220 350 mV IOUT=600mA, VOUT=5V - 200 320 mV Dropout Voltage PROTECTION AND SOFT-START Output Current Limit 700 - - mA Thermal Shutdown Temperature - 150 - C Thermal Shutdown Hysteresis - 40 - C - 250 - mA - 130 300 s - 60 - EN Logic Input-High Level 1.6 - - V EN Logic Input-Low Level - - 0.4 V - 2 - M Foldback Current Limit TSS VOUT < 0.6V Soft-Start Time VOUT Pull Low Resistance VEN=0V, VOUT=0.5V LOGIC INPUT EN Pull-Low Resistance Copyright ANPEC Electronics Corp. Rev. A.1 - Jan., 2008 VEN<3V 3 www.anpec.com.tw APL5605 Typical Operating Characteristics VIN=5V, VSET=2V, VOUT=3.2V, CIN=1F, COUT=2.2F, unless otherwise specified. EN Voltage threshold vs. Input Voltage Quiescent Current vs. VSET Voltage 180 160 1.5 Quiescent Current, IQ (A) EN Voltage Threshold (V) 1.6 1.4 1.3 1.2 1.1 1 0.9 IOUT=0mA 140 120 100 80 60 40 20 0 0.8 3 3.5 4 4.5 5 5.5 6 0 6.5 0.5 1 Input Voltage (V) 1.5 2 2.5 3 VSET Voltage (V) Dropout vs. Junction Temperature VSET Voltage vs. Output Voltage 6 300 VOUT=5V IOUT=10mA 250 Dropout Voltage (mV) Output Voltage (V) 5 4 3 2 1 IOUT=600mA 200 IOUT=400mA 150 IOUT=200mA 100 50 0 0 0.5 1 1.5 2 2.5 3 0 -50 3.5 0 0 VOUT=3.3V -5 150 VIN=5, CIN=1F, COUT=2.2F, VSET=2V, VOUT=3.2V -10 IOUT=600mA 250 -15 PSRR (dB) Dropout Voltage (mV) 300 100 Power Supply Rejection Ratio (PSRR) Dropout vs. Junction Temperature 350 50 Junction Temperature, TJ ( C) VSET Voltage (V) 200 IOUT=400mA 150 IOUT=200mA 100 -20 IOUT=500mA -25 -30 IOUT=400mA -35 -40 50 -45 0 -50 0 50 100 -50 1000 150 Junction Temperature, TJ ( C) Copyright ANPEC Electronics Corp. Rev. A.1 - Jan., 2008 10000 100000 1000000 Frequency (Hz) 4 www.anpec.com.tw APL5605 Typical Operating Characteristics (Cont.) VIN=5V, VSET=2V, VOUT=3.2V, CIN=1F, COUT=2.2F, unless otherwise specified. Quiescent Current vs. Input Voltage Quiescent Current (A) 200 IOUT=0mA 160 120 80 40 0 0 1 2 3 4 5 6 Input Voltage, VIN (V) Operating Waveforms VIN=5V, VSET=2V, VOUT=3.2V, CIN=1F, COUT=2.2F, unless otherwise specified. Power On Power Off V SET V IN V IN 1 1 V SET 2 2 I OUT V OUT I OUT I OUT 4 CH1 : VIN , 2V/div CH2 : VSET , 1V/div CH3 : VOUT , 1V/div CH4 : IOUT , 500mA/div Time : 200ms/div CH1 : VIN , 2V/div CH2 : VSET , 1V/div CH3 : VOUT , 1V/div CH4 : IOUT , 500mA/div Time : 1ms/div Copyright ANPEC Electronics Corp. Rev. A.1 - Jan., 2008 V OUT 3 3 4 V OUT 5 www.anpec.com.tw APL5605 Operating Waveforms (Cont.) VIN=5V, VSET=2V, VOUT=3.2V, CIN=1F, COUT=2.2F, unless otherwise specified. Line transient Load transient VIN=5V, VSET=2V , VOUT=3.2V CIN=1F, COUT=2.2F VIN=5V, VSET=2V , VOUT=3.2V CIN=1F, COUT=2.2F 1 VIN V OUT VOUT I OUT 2 1 2 CH1 : VIN , 1V/div CH2 : VOUT , 100mV/div Time : 1ms/div CH1 : VOUT , 100mV/div CH2 : IOUT , 200mV/div Time : 200s/div Shutdown Enable VSET VSET VEN VEN 1 1 2 2 VOUT VOUT 3 3 IOUT IOUT 4 4 CH1 : VEN , 2V/div CH2 : VSET , 1V/div CH3 : VOUT , 1V/div CH4 : IOUT , 500mA/div Time : 10s/div CH1 : VEN , 2V/div CH2 : VSET , 1V/div CH3 : VOUT , 1V/div CH4 : IOUT , 500mA/div Time : 200s/div Copyright ANPEC Electronics Corp. Rev. A.1 - Jan., 2008 6 www.anpec.com.tw APL5605 Operating Waveforms (Cont.) VIN=5V, VSET=2V, VOUT=3.2V, CIN=1F, COUT=2.2F, unless otherwise specified. Current Limit and Foldback Current Limit Thermal Shutdown VIN 1 VIN VOUT 1 VOUT 2 2 IOUT IOUT 3 3 CH1 : VIN , 5V/div CH2 : VOUT , 2V/div CH3 : IOUT , 1A/div Time : 2ms/div CH1 : VIN , 5V/div CH2 : VOUT , 2V/div CH3 : IOUT , 500mA/div Time : 500ms/div Pin Descriptions Pin Function Descriptions No. Name 1 EN 2 VIN 3 VOUT 4 VSET Output Voltage-Set Input. The output voltage follows the 1.6 times of the VSET voltage. 5,6,7,8 GND Ground. These pins are internally connected with the internal leadframe. Connect these pins to a wide ground plane for good heat dissipation. Enable Control Input. Driving the EN high turns on the regulator. Pulling the EN low turns the regulator into shutdown mode. The EN is pulled low by an internal resistor. Supply Voltage Input Pin. Supply voltage can range from 4.5V to 6V. Bypass with a 1F (typical) capacitor to GND Regulator Output. Sources up to 600mA. A small capacitor is needed from this pin to ground to assure stability. Copyright ANPEC Electronics Corp. Rev. A.1 - Jan., 2008 7 www.anpec.com.tw APL5605 Block Diagram VIN VOUT = VSET x 1.6 Current Limit and Foldback UVLO and Soft-Start EN VSET VOUT Thermal Shutdown 0.6R R GND Typical Application Circuit APL5605 VIN CIN 1F VIN VSET EN VOUT VOUT GND ON VSET COUT 2.2F VEN OFF Copyright ANPEC Electronics Corp. Rev. A.1 - Jan., 2008 VOUT = 1.6 VSET 8 www.anpec.com.tw APL5605 Function Descriptions Under-Voltage Lock-Out (UVLO) Thermal Shutdown The APL5605 has a built-in under-voltage lock-out circuit to keep the output off until the internal circuitry is operat- A thermal shutdown circuit limits the junction temperature of APL5605. When the junction temperature exceeds ing properly. The UVLO function initiates a soft start process after input voltage exceeds its rising UVLO thresh- +150 C, the thermal shutdown circuitry disables the output, allowing the device to cool down. The output old during power on. Typical UVLO threshold is 2.5V with 0.15V hysteresis. circuitry is enabled again after the junction temperature cools down by 40 C, resulting in a pulsed output during continuous thermal overload conditions. Soft-Start The APL5605 provides an internal soft-start circuitry to control rise rate of the output voltage and limit the current surge during start-up. Approximate 20s delay time after the VIN is over the UVLO threshold, the IC starts a soft-start. The typical soft-start interval is about 130s. Enable/Shutdown Driving the EN high turns on the regulator, driving the EN low puts the regulator into shutdown mode. A logic low also causes the output voltage to discharge to GND. The EN is pulled low by an internal resistor. Current Limit The APL5605 provides a current limit circuitry, which monitors the output current and controls P-MOS's gate voltage to limit the output current at 700mA. Foldback Current Limit When the output voltage drops below 0.6V (typical),which is caused by over load or short circuit, the foldback current limit circuitry limits the output current to 250mA. The foldback current limit is used to ruduce the power dissipation during short circuit condition. The foldback current limits is disabled for 0.8ms(typical) after UVLO threshold is reached, so that the IC has normal 700mA (typical) current limit level during start-up. Copyright ANPEC Electronics Corp. Rev. A.1 - Jan., 2008 9 www.anpec.com.tw APL5605 Application Information Input Capacitor PCB Layout Considerations The APL5605 requires proper input capacitors to supply surge current during stepping load transients to prevent Figure 1 illustrates the layout. Below is a checklist for your layout: the input rail from dropping. Because the parasitic inductor from the voltage sources or other bulk capacitors to 1. Please place the input capacitors close to the VIN 2. Ceramic capacitors for load must be placed near the the VIN limits the slew rate of the surge current, place the Input capacitors near VIN as close as possible. Input load as close as possible 3. To place APL5605 and output capacitors near the load capacitors should be larger than 0.82F. is good for performance. 4. Large current paths, the bold lines in figure 1, must Output Capacitor have wide tracks. The APL5605 needs a proper output capacitor to maintain circuit stability and to improve transient response APL5605 VIN over temperature and current. In order to insure the circuit stability, the proper output capacitor value should be VIN VSET VSET EN VOUT VOUT CIN larger than 1F. With X5R and X7R dielectrics, 2.2F is sufficient at all operating temperatures. Maximum output VEN GND COUT capacitor should be less than 330F to insure the system can be powered on effectively. Figure 1 Operation Region and Power Dissipation The APL5605 maximum power dissipation depends on Optimum performance can only be achieved when the device is mounted on a PC board according to the SOP-8 the thermal resistance and temperature difference between the die junction and ambient air. The power dissi- Board Layout diagram. For dissipating heat pation PD across the device is: PD = GND ( TJ - TA ) JA COUT SOP-8 where (TJ-TA) is the temperature difference between the junction and ambient air. JA is the thermal resistance between Junction and ambient air. Assuming the TA=25C and maximum TJ=150 C (typical thermal limit threshold), VIN VOUT CIN GND the maximum power dissipation is calculated as: Figure 2 PD(max)=(150-25)/80 = 1.56(W) Recommanded Minimum Footprint For normal operation, do not exceed the maximum junc8 7 6 5 1 2 3 4 0.072 0.024 tion temperature rating of TJ = 125 C. The calculated power dissipation should less than: 0.212 PD =(125-25)/80 = 1.25(W) The GND provides an electrical connection to ground and channels heat away. Connect the GND to ground by using a large pad or ground plane. 0.050 Copyright ANPEC Electronics Corp. Rev. A.1 - Jan., 2008 10 Unit : Inch www.anpec.com.tw APL5605 Package Information SOP-8 D E E1 SEE VIEW A h X 45 c A 0.25 b GAUGE PLANE SEATING PLANE A1 A2 e L VIEW A S Y M B O L SOP-8 INCHES MILLIMETERS MIN. MAX. A MIN. MAX. 1.75 0.069 0.004 0.25 0.010 A1 0.10 A2 1.25 b 0.31 0.51 0.012 0.020 c 0.17 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 E 5.80 6.20 0.228 0.244 E1 3.80 4.00 0.150 0.157 e 0.049 1.27 BSC 0.050 BSC h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 0 0 8 0 8 Note: 1. Follow JEDEC MS-012 AA. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. Dimension "E" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.1 - Jan., 2008 11 www.anpec.com.tw APL5605 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 OD1 B A B T SECTION A-A SECTION B-B H A d T1 Application SOP-8 A H T1 C d D W E1 F 12.4+2.00 13.0+0.50 330.02.00 50 MIN. 1.5 MIN. 20.2 MIN. 12.00.30 1.750.10 5.50.05 -0.00 -0.20 P0 P1 P2 D0 D1 T A0 B0 K0 1.5+0.10 0.6+0.00 4.00.10 8.00.10 2.00.05 6.400.20 5.200.20 2.100.20 1.5 MIN. -0.00 -0.40 (mm) Devices Per Unit Package Type Unit Quantity SOP-8 Tape & Reel 2500 Copyright ANPEC Electronics Corp. Rev. A.1 - Jan., 2008 12 www.anpec.com.tw APL5605 Reflow Condition (IR/Convection or VPR Reflow) tp TP Critical Zone TL to TP Ramp-up Temperature TL tL Tsmax Tsmin Ramp-down ts Preheat 25 t 25C to Peak Time Reliability Test Program Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B, A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245C, 5 sec 1000 Hrs Bias @125C 168 Hrs, 100%RH, 121C -65C~150C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1tr > 100mA Classification Reflow Profiles Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classification Temperature (Tp) Time within 5C of actual Peak Temperature (tp) Ramp-down Rate Time 25C to Peak Temperature Sn-Pb Eutectic Assembly Pb-Free Assembly 3C/second max. 3C/second max. 100C 150C 60-120 seconds 150C 200C 60-180 seconds 183C 60-150 seconds 217C 60-150 seconds See table 1 See table 2 10-30 seconds 20-40 seconds 6C/second max. 6C/second max. 6 minutes max. 8 minutes max. Note: All temperatures refer to topside of the package. Measured on the body surface. Copyright ANPEC Electronics Corp. Rev. A.1 - Jan., 2008 13 www.anpec.com.tw APL5605 Classification Reflow Profiles (Cont.) Table 1. SnPb Eutectic Process - Package Peak Reflow Temperatures 3 3 Package Thickness <2.5 mm 2.5 mm Volume mm 350 225 +0/-5C 225 +0/-5C Volume mm <350 240 +0/-5C 225 +0/-5C Table 2. Pb-free Process - Package Classification Reflow Temperatures 3 3 3 Volume mm Volume mm Volume mm <350 350-2000 >2000 <1.6 mm 260 +0C* 260 +0C* 260 +0C* 1.6 mm - 2.5 mm 260 +0C* 250 +0C* 245 +0C* 2.5 mm 250 +0C* 245 +0C* 245 +0C* * Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0C. For example 260C+0C) at the rated MSL level. Package Thickness Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.1 - Jan., 2008 14 www.anpec.com.tw