APL5605KI-TRL - Anpec Electronics Corp.

Rev. A.1 - Jan., 2008

APL5605

www.anpec.com.tw1

ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and

advise customers to obtain the latest version of relevant information to verify before placing orders.

600mA Linear Regulator for DC Fan Speed Control

The APL5605 is a low quiescent current and low dropout

linear regulator which is designed to power a DC fan

and delivers up to 600mA output current. The output

voltage follows the 1.6 times of VSET voltage and typi-

cal dropout voltage is only 220mV (typical) at 600mA

output current. The APL5605 with low 140µA quiescent

current is ideal for battery-powered system appliances

and stable with a 2.2µF ceramic output capacitor. The

features of current limit (with foldback current) and over-

temperature protection protect the device against cur-

rent over-loads and over temperature. The APL5605 is

available in a SOP-8 package.

FeaturesGeneral Description

ApplicationsSimplified Application Circuit

Ordering and Marking Information

Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully

compliant with RoHS and compatible with both SnPb and lead-free soldering operations. ANPEC lead-free products meet or exceed the lead-

free requirements of IPC/JEDEC J STD-020C for MSL classification at lead-free peak reflow temperature.

•Low Dropout Voltage: 220mV (typical) @ 600mA

•Low Quiescent Current: 140µA

•Enable/Shutdown function

• Output Voltage / VSET Voltage: 1.6 times

•Stable with Low ESR Ceramic Capacitors

•Over-Temperature Protection

•Current Limit Protection with Foldback Current

•Internal Soft-start

•SOP-8 Package

•Lead Free Available (RoHS Compliant)

•Notebook Fan Driver

•Motherboards

•PC Peripherals

•Battery-Powered System

VIN VOUT

C1 C2

1µF2.2µF

VIN VOUT

GND

APL5605

OFF

EN VSET

VSET

Package Code

K : SOP-8

Operating Ambient Temperature Range

I : -40 to 85 C

Handling Code

TR : Tape & Reel

Lead Free Code

L : Lead Free Device

APL5605

Handling Code

Temperature Range

Package Code

Lead Free Code

APL5605 K : XXXXX - Date Code

APL5605

XXXXX

Rev. A.1 - Jan., 2008 www.anpec.com.tw2

APL5605

Pin Configuration

Absolute Maximum Ratings (Note 1)

Symbol Parameter Rating Unit

VIN VIN to GND -0.3 ~ 6.5 V

VEN EN to GND -0.3 ~ VIN+0.3 V

VOUT VOUT to GND -0.3 ~ VIN+0.3 V

TJ Maximum Junction Temperature 150 oC

PD Power Dissipation Internally Limited

TSTG Storage Temperature Range -65 ~ 150 oC

TSDR Maximum Lead Temperature (Soldering, 10 sec) 260 oC

Note 1: Stresses beyond the absolute maximum rating may damage the device and exposure to absolute maximum rating conditions for extended

periods may affect device reliability.

Symbol Parameter Rating Unit

θJA Junction to Ambient Thermal Resistance

SOP-8 80 °C/W

Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.

Thermal Characteristics

Recommended Operating Conditions

Symbol Parameter Range Unit

VIN VIN to GND 4.5 ~ 6 V

VEN EN to GND 0 ~ VIN V

VOUT VOUT to GND 0 ~ VIN-VDROP V

VSET VSET to GND 0 ~ 3.3 V

IOUT Output Current 0 ~ 0.6 A

CIN Input Capacitor 0.82 ~ 470

COUT Output Capacitor 1 ~ 330 µF

TJ Junction Temperature -40 ~ 125 °C

TA Ambient Temperature -40 ~ 85 °C

7 GND

VOUT 3

VIN 2

VSET 4 6 GND

5 GND

8 GND

EN 1

SOP-8 Top View

APL5605

Rev. A.1 - Jan., 2008 www.anpec.com.tw3

APL5605

Electrical Characteristics

Symbol

Parameter Test Conditions Min Typ Max Unit

SUPPLY CURRENT

VEN = 0V - - 1 µA

IQ Quiescent Current VEN = 5V, IOUT = 0A - 140 200 µA

UNDER-VOLTAGE-LOCKOUT (UVLO)

VIN UVLO Threshold VIN rising 2.1 2.5 2.9 V

VIN UVLO Hysteresis - 0.15 - V

OUTPUT VOLTAGE

VOUT Voltage / VSET Voltage TJ = 25°C, VIN=5.5V, IOUT=1mA,

VSET=3.3V 1.552 1.6 1.648 V/V

VOUT Voltage / VSET Voltage TJ = 40 ~ 125°C, VIN=5.5V, IOUT=1mA,

VSET=1 ~ 3.3V 1.504 1.6 1.696 V/V

VSET pin Current VSET=5V - 0.05 1 µA

Load Regulation IOUT = 1mA to 600mA - 60 100 mV

IOUT=600mA, VOUT=2.5V - 250 400 mV

IOUT=600mA, VOUT=3.3V - 220 350 mV

VDROP

Dropout Voltage

IOUT=600mA, VOUT=5V - 200 320 mV

PROTECTION AND SOFT -START

Output Current Limit 700 - - mA

Thermal Shutdown Temperature

- 150 - °C

Thermal Shutdown Hysteresis - 40 - °C

Foldback Current Limit VOUT < 0.6V - 250 - mA

TSS Soft-Start Time - 130 300 µs

VOUT Pull Low Resistance VEN=0V, VOUT=0.5V - 60 - Ω

LOGIC INPUT

EN Logic Input-High Level 1.6 - - V

EN Logic Input-Low Level - - 0.4 V

EN Pull-Low Resistance VEN<3V - 2 - MΩ

Refer to the typical application circuit. VIN = 5V, VEN = VIN, IOUT = 1mA~600mA, TJ = -40 to 125 °C, TA = -40 to 85°C,

unless otherwise specified. Typical values are at TA = 25 °C.

Rev. A.1 - Jan., 2008 www.anpec.com.tw4

APL5605

EN Voltage threshold vs.

Input VoltageQuiescent Current vs. VSET Voltage

VSET Voltage vs. Output VoltageDropout vs. Junction Temperature

Dropout vs. Junction TemperaturePower Supply Rejection Ratio

(PSRR)

Typical Operating Characteristics

VIN=5V, VSET=2V, VOUT=3.2V, CIN=1µF, COUT=2.2µF, unless otherwise specified.

Input Voltage (V)

EN Voltage Threshold (V)

0.8

0.9

1.1

1.2

1.3

1.4

1.5

1.6

33.5 44.5 55.5 66.5

00.5 11.5 22.5 33.5

VSET Voltage (V)

Output Voltage (V)

IOUT=10mA

Quiescent Current, IQ (μA)

VSET Voltage (V)

100

120

140

160

180

00.5 11.5 22.5 3

IOUT=0mA

100

150

200

250

300

350

-50 050 100 150

IOUT=200mA

IOUT=600mA

IOUT=400mA

VOUT=3.3V

Junction Temperature, TJ (°C)

Dropout Voltage (mV)

Junction Temperature, TJ (°C)

Dropout Voltage (mV)

100

150

200

250

300

-50 0 50 100 150

IOUT=200mA

IOUT=600mA

IOUT=400mA

VOUT=5V

-50

-45

-40

-35

-30

-25

-20

-15

-10

-5

1000 10000 100000 1000000

Frequency (Hz)

PSRR (dB)

VIN=5, CIN=1µF, COUT=2.2µF,

VSET=2V, VOUT=3.2V

IOUT=500mA

IOUT=400mA

Rev. A.1 - Jan., 2008 www.anpec.com.tw5

APL5605

Quiescent Current vs. Input Voltage

Typical Operating Characteristics (Cont.)

Operating Waveforms

120

160

200

0 1 2 3 4 5 6

IOUT=0mA

Input Voltage, VIN (V)

Quiescent Current (µA)

VIN=5V, VSET=2V, VOUT=3.2V, CIN=1µF, COUT=2.2µF, unless otherwise specified.

Power On

CH1 : VIN , 2V/div

CH2 : VSET , 1V/div

Time : 1ms/div

CH3 : VOUT , 1V/div

CH4 : IOUT , 500mA/div

V IN

V SET

V OUT

I OUT

Power Off

CH1 : VIN , 2V/div

CH2 : VSET , 1V/div

Time : 200ms/div

CH3 : VOUT , 1V/div

CH4 : IOUT , 500mA/div

V IN

V SET

V OUT

I OUT

V OUT

I OUT

Rev. A.1 - Jan., 2008 www.anpec.com.tw6

APL5605

Operating Waveforms (Cont.)

VIN=5V, VSET=2V, VOUT=3.2V, CIN=1µF, COUT=2.2µF, unless otherwise specified.

Line transient

CH2 : VOUT , 100mV/div

Time : 1ms/div

VIN

VOUT

VIN=5V, VSET=2V , VOUT=3.2V

CIN=1µF, COUT=2.2µF

CH1 : VIN , 1V/div

Load transient

CH1 : VOUT , 100mV/div

CH2 : IOUT , 200mV/div

Time : 200µs/div

V OUT

I OUT

VIN=5V, VSET=2V , VOUT=3.2V

CIN=1µF, COUT=2.2µF

Enable

CH1 : VEN , 2V/div

CH2 : VSET , 1V/div

Time : 200µs/div

VSET

VOUT

VEN

IOUT

CH3 : VOUT , 1V/div

CH4 : IOUT , 500mA/div

Shutdown

CH1 : VEN , 2V/div

CH2 : VSET , 1V/div

Time : 10µs/div

VSET

VOUT

VEN

IOUT

CH3 : VOUT , 1V/div

CH4 : IOUT , 500mA/div

Rev. A.1 - Jan., 2008 www.anpec.com.tw7

APL5605

Operating Waveforms (Cont.)

VIN=5V, VSET=2V, VOUT=3.2V, CIN=1µF, COUT=2.2µF, unless otherwise specified.

Thermal Shutdown

CH1 :VIN ,5V/div

Time :500ms/div

CH2 :VOUT ,2V/div

CH3 : IOUT ,500mA/div

VIN

VOUT

IOUT

No. Name Function Descriptions

1 EN Enable Control Input. Driving the EN high turns on the regulator. Pulling the EN low turns the

regulator into shutdown mode. The EN is pulled low by an internal resistor.

2 VIN Supply Voltage Input Pin. Supply voltage can range from 4.5V to 6V. Bypass with a 1µF (typical)

capacitor to GND

3 VOUT Regulator Output. Sources up to 600mA. A small capacitor is needed from this pin to ground to

assure stability.

4 VSET Output Voltage-Set Input. The output voltage follows the 1.6 times of the VSET voltage.

5,6,7,8 GND Ground. These pins are internally connected with the internal leadframe. Connect these pins to a

wide ground plane for good heat dissipation.

Pin Descriptions

Current Limit and Foldback

Current Limit

VIN

VOUT

IOUT

CH1 :VIN ,5V/div

Time :2ms/div

CH2 :VOUT ,2V/div

CH3 : IOUT ,1A/div

Rev. A.1 - Jan., 2008 www.anpec.com.tw8

APL5605

Block Diagram

VOUT = VSET x 1.6

UVLO and

Soft-Start

Thermal

Shutdown

VIN

GND

Current Limit

and Foldback

VOUT

VSET

0.6R

Typical Application Circuit

SETOUT V1.6 V⋅=

VIN

GND VOUT

APL5605

COUT

2.2µF

CIN

1µF

VIN

VOUT

VEN

VSET VSET

OFF

Rev. A.1 - Jan., 2008 www.anpec.com.tw9

APL5605

Function Descriptions

Under-Voltage Lock-Out (UVLO)

The APL5605 has a built-in under-voltage lock-out circuit

to keep the output off until the internal circuitry is operat-

ing properly. The UVLO function initiates a soft start pro-

cess after input voltage exceeds its rising UVLO thresh-

old during power on. Typical UVLO threshold is 2.5V

with 0.15V hysteresis.

Soft-Start

The APL5605 provides an internal soft-start circuitry to

control rise rate of the output voltage and limit the cur-

rent surge during start-up. Approximate 20µs delay time

after the VIN is over the UVLO threshold, the IC starts a

soft-start. The typical soft-start interval is about 130µs.

Enable/Shutdown

Driving the EN high turns on the regulator, driving the EN

low puts the regulator into shutdown mode. A logic low

also causes the output voltage to discharge to GND. The

EN is pulled low by an internal resistor.

Current Limit

The APL5605 provides a current limit circuitry, which

monitors the output current and controls P-MOS’s gate

voltage to limit the output current at 700mA.

Thermal Shutdown

A thermal shutdown circuit limits the junction temperature

of APL5605. When the junction temperature exceeds

+150οC, the thermal shutdown circuitry disables the

output, allowing the device to cool down. The output

circuitry is enabled again after the junction tempera-

ture cools down by 40οC, resulting in a pulsed output

during continuous thermal overload conditions.

When the output voltage drops below 0.6V (typical),which

is caused by over load or short circuit, the foldback cur-

rent limit circuitry limits the output current to 250mA. The

foldback current limit is used to ruduce the power dissi-

pation during short circuit condition. The foldback current

limits is disabled for 0.8ms(typical) after UVLO threshold

is reached, so that the IC has normal 700mA (typical)

current limit level during start-up.

Foldback Current Limit

Rev. A.1 - Jan., 2008 www.anpec.com.tw10

APL5605

Application Information

Input Capacitor

The APL5605 requires proper input capacitors to supply

surge current during stepping load transients to prevent

the input rail from dropping. Because the parasitic induc-

tor from the voltage sources or other bulk capacitors to

the VIN limits the slew rate of the surge current, place the

Input capacitors near VIN as close as possible. Input

capacitors should be larger than 0.82µF.

Output Capacitor

The APL5605 needs a proper output capacitor to main-

tain circuit stability and to improve transient response

over temperature and current. In order to insure the cir-

cuit stability, the proper output capacitor value should be

larger than 1µF. With X5R and X7R dielectrics, 2.2 µF is

sufficient at all operating temperatures. Maximum output

capacitor should be less than 330µF to insure the sys-

tem can be powered on effectively.

Operation Region and Power Dissipation

The APL5605 maximum power dissipation depends on

the thermal resistance and temperature difference be-

tween the die junction and ambient air. The power dissi-

pation PD across the device is:

D)TT(

Pθ−

where (TJ-TA) is the temperature difference between the

junction and ambient air. θJA is the thermal resistance

between Junction and ambient air. Assuming the TA=25οC

and maximum TJ=150οC (typical thermal limit threshold),

the maximum power dissipation is calculated as:

PD(max)=(150-25)/80

= 1.56(W)

For normal operation, do not exceed the maximum junc-

tion temperature rating of TJ = 125οC. The calculated

power dissipation should less than:

PD =(125-25)/80

= 1.25(W)

PCB Layout Considerations

Figure 1 illustrates the layout. Below is a checklist for

your layout:

1. Please place the input capacitors close to the VIN

2. Ceramic capacitors for load must be placed near the

load as close as possible

3. To place APL5605 and output capacitors near the load

is good for performance.

4. Large current paths, the bold lines in figure 1, must

have wide tracks.

Figure 1

Figure 2

Optimum performance can only be achieved when the

device is mounted on a PC board according to the SOP-8

Board Layout diagram.

The GND provides an electrical connection to ground and

channels heat away. Connect the GND to ground by us-

ing a large pad or ground plane.

VIN

VOUT

GND

APL5605

CIN

COUT

VIN

VOUT

VEN

VSET VSET

Recommanded Minimum Footprint

0.212

0.072

0.050

0.024

1 2 3 4

8 7 6 5

Unit : Inch

SOP-8

GND

VOUT

VIN

GND

CIN

COUT

For dissipating heat

Rev. A.1 - Jan., 2008 www.anpec.com.tw11

APL5605

Package Information

SOP-8

LMIN. MAX.

1.75

0.10

0.17 0.25

0.25

MILLIMETERS

b0.31 0.51

SOP-8

0.25 0.50

0.40 1.27

MIN. MAX.

INCHES

0.069

0.004

0.012 0.020

0.007 0.010

0.010 0.020

0.016 0.050

0.010

1.27 BSC 0.050 BSC

A2 1.25 0.049

SEE VIEW A

h X 45

A1A2

VIEW A

0.25

SEATING PLANE

GAUGE PLANE

Note: 1. Follow JEDEC MS-012 AA.

2. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion or gate burrs shall not exceed 6 mil per side.

3. Dimension “E” does not include inter-lead flash or protrusions.

Inter-lead flash and protrusions shall not exceed 10 mil per side.

3.80

5.80

4.80

4.00

6.20

5.00 0.189 0.197

0.228 0.244

0.150 0.157

Rev. A.1 - Jan., 2008 www.anpec.com.tw12

APL5605

Application

A H T1 C d D W E1 F

330.0±2.00

50 MIN.

12.4+2.00

-0.00

13.0+0.50

-0.20

1.5 MIN.

20.2 MIN.

12.0±0.30

1.75±0.10

5.5±0.05

P0 P1 P2 D0 D1 T A0 B0 K0

SOP-8

4.0±0.10

8.0±0.10

2.0±0.05

1.5+0.10

-0.00

1.5 MIN.

0.6+0.00

-0.40

6.40±0.20

5.20±0.20

2.10±0.20

(mm)

Carrier Tape & Reel Dimensions

OD0

BA0

SECTION B-B

SECTION A-A

OD1

Devices Per Unit

Package Type Unit Quantity

SOP-8 Tape & Reel 2500

Rev. A.1 - Jan., 2008 www.anpec.com.tw13

APL5605

Test item Method Description

SOLDERABILITY MIL-STD-883D-2003 245°C, 5 sec

HOLT MIL-STD-883D-1005.7 1000 Hrs Bias @125°C

PCT JESD-22-B, A102 168 Hrs, 100%RH, 121°C

TST MIL-STD-883D-1011.9 -65°C~150°C, 200 Cycles

ESD MIL-STD-883D-3015.7 VHBM > 2KV, VMM > 200V

Latch-Up JESD 78 10ms, 1tr > 100mA

Reflow Condition (IR/Convection or VPR Reflow)

Classification Reflow Profiles

Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly

Average ramp-up rate

(TL to TP) 3°C/second max. 3°C/second max.

Preheat

- Temperature Min (Tsmin)

- Temperature Max (Tsmax)

- Time (min to max) (ts)

100°C

150°C

60-120 seconds

150°C

200°C

60-180 seconds

Time maintained above:

- Temperature (TL)

- Time (tL) 183°C

60-150 seconds 217°C

60-150 seconds

Peak/Classification Temperature (Tp) See table 1 See table 2

Time within 5°C of actual

Peak Temperature (tp) 10-30 seconds 20-40 seconds

Ramp-down Rate 6°C/second max. 6°C/second max.

Time 25°C to Peak Temperature 6 minutes max. 8 minutes max.

Note: All temperatures refer to topside of the package. Measured on the body surface.

t 25 C to Peak

Ramp-up

Ramp-down

Preheat

Tsmax

Tsmin

Temperature

Time

Critical Zone

TL to TP

Reliability Test Program

Rev. A.1 - Jan., 2008 www.anpec.com.tw14

APL5605

Table 2. Pb-free Process – Package Classification Reflow Temperatures

Package Thickness Volume mm3

<350 Volume mm3

350-2000 Volume mm3

>2000

<1.6 mm 260 +0°C* 260 +0°C* 260 +0°C*

1.6 mm – 2.5 mm 260 +0°C* 250 +0°C* 245 +0°C*

≥2.5 mm 250 +0°C* 245 +0°C* 245 +0°C*

* Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated

classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C) at the rated MSL

level.

Customer Service

Table 1. SnPb Eutectic Process – Package Peak Reflow Temperatures

Package Thickness Volume mm3

<350 Volume mm3

≥350

<2.5 mm 240 +0/-5°C 225 +0/-5°C

≥2.5 mm 225 +0/-5°C 225 +0/-5°C

Classification Reflow Profiles (Cont.)

Anpec Electronics Corp.

Head Office :

No.6, Dusing 1st Road, SBIP,

Hsin-Chu, Taiwan, R.O.C.

Tel : 886-3-5642000

Fax : 886-3-5642050

Taipei Branch :

2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,

Sindian City, Taipei County 23146, Taiwan

Tel : 886-2-2910-3838

Fax : 886-2-2917-3838