NT1GD72S4NB0FU 1GB : 128M x 72 Low Profile Registered DDR SDRAM DIMM 184pin Low Profile Registered DDR SDRAM MODULE Based on 64Mx4 DDR SDRAM Features * 128Mx72 Low Profile Registered DDR DIMM based on 64Mx4 * Data is read or written on both clock edges DDR SDRAM * Bi-directional data strobe with one clock cycle preamble and * JEDEC Standard 184-pin Dual In-Line Memory Module one-half clock post-amble * Error Check Correction (ECC) Support * Address and control signals are fully synchronous to positive * Phase-lock loop (PLL) clock driver to reduce loading clock edge * Registered inputs with one-clock delay * Programmable Operation: - Device CAS Latency: 2, 2.5 * Performance: - Burst Type: Sequential or Interleave PC2100 Speed Sort -75B * DIMM CAS Latency 3.5 f CK Clock Frequency 133 - Burst Length: 2, 4, 8 Unit - Operation: Burst Read and Write * Auto Refresh (CBR) and Self Refresh Modes MHz t CK Clock Cycle 7.5 ns f DQ DQ Burst Frequency 266 MHz * Automatic and controlled precharge commands * 13/11/2 Addressing (row/column/bank) * Intended for 133 MHz applications * 7.8 s Max. Average Periodic Refresh Interval * Inputs and outputs are SSTL-2 compatible * Serial Presence Detect * VDD = 2.5Volt 0.2, VDDQ = 2.5Volt 0.2 * Gold contacts * SDRAMs have 4 internal banks for concurrent operation * SDRAMs in 60-ball FBGA Package * Differential clock inputs * One clock cycle added for registered DIMMs to account for input register. Description NT1GD72S4NB0FU is a Low Profile Registered 184-Pin 1U Double Data Rate (DDR) Synchronous DRAM Dual In-Line Memory Module (DIMM), organized as a dual-bank 128Mx72 high-speed memory array. The module uses 36 64Mx4 DDR SDRAMs in BGA packages. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between suppliers. All NANYA DDR SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25" long space-saving footprint. The DIMM is intended for use in applications operating up to 133 MHz clock speeds and achieves high-speed data transfer rates of up to 266 MHz. Prior to any access operation, the device CAS latency and burst type/ length/operation type must be programmed into the DIMM by address inputs A0-A12 and I/O inputs BA0 and BA1 using the mode register set cycle. The DIMM uses serial presence-detect implemented via a serial 2,048-bit EEPROM using a standard IIC protocol. The first 128 bytes of serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer. Ordering Information Part Number Speed Organization Leads Power 128Mx72 Gold 2.5V 133MHz (7.5ns @ CL= 2.5) NT1GD72S4NB0FU-75B DDR266B PC2100 100MHz (10ns @ CL = 2) REV 0.2 (Preliminary) 05/2003 1 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GD72S4NB0FU 1GB : 128M x 72 Low Profile Registered DDR SDRAM DIMM Pin Description CK0, CK0 CKE0, CKE1 Differential Clock Inputs DQ0-DQ63 Clock Enable CB0-CB7 Data input/output Check Bit Data Input/Output RAS Row Address Strobe CAS Column Address Strobe VDD Power (2.5V) WE Write Enable VDDQ Supply voltage for DQs (2.5V) S0, S1 Chip Selects VSS Ground Address Inputs NC No Connect Address Input/Autoprecharge SCL Serial Presence Detect Clock Input A0-A9, A11, A12 A10/AP BA0, BA1 RESET DQS0-DQS17 SDRAM Bank Address Inputs SDA Reset pin VREF Ref. Voltage for SSTL_2 inputs VDDID VDD Identification flag. Bidirectional data strobes Serial Presence Detect Data input/output SA0-2 Serial Presence Detect Address Inputs VDDSPD Serial EEPROM positive power supply (2.5V) Pinout Pin Front Pin Front Pin Front 1 VREF 2 DQ0 3 VSS Pin Back Pin Back 32 A5 62 VDDQ 33 DQ24 63 WE 34 VSS 64 DQ41 95 Pin Back 93 VSS 124 VSS 154 RAS 94 DQ4 125 A6 155 DQ45 DQ5 126 DQ28 156 VDDQ 4 DQ1 35 DQ25 65 CAS 96 VDDQ 127 DQ29 157 S0 5 DQS0 36 DQS3 66 VSS 97 DQS9 128 VDDQ 158 S1 6 DQ2 37 A4 67 DQS5 98 DQ6 129 DQS12 159 DQS14 7 VDD 38 VDD 68 DQ42 99 DQ7 130 A3 160 VSS 8 DQ3 39 DQ26 69 DQ43 100 VSS 131 DQ30 161 DQ46 9 NC 40 DQ27 70 VDD 101 NC 132 VSS 162 DQ47 10 RESET 41 A2 71 NC 102 NC 133 DQ31 163 NC 11 VSS 42 VSS 72 DQ48 103 NC 134 CB4 164 VDDQ 12 DQ8 43 A1 73 DQ49 104 VDDQ 135 CB5 165 DQ52 13 DQ9 44 CB0 74 VSS 105 DQ12 136 VDDQ 166 DQ53 14 DQS1 45 CB1 75 NC 106 DQ13 137 CK0 167 NC 15 VDDQ 46 VDD 76 NC 107 DQS10 138 CK0 168 VDD 16 NC 47 DQS8 77 VDDQ 108 VDD 139 VSS 169 DQS15 17 NC 48 A0 78 DQS6 109 DQ14 140 DQS17 170 DQ54 18 VSS 49 CB2 79 DQ50 110 DQ15 141 A10 171 DQ55 19 DQ10 50 VSS 80 DQ51 111 CKE1 142 CB6 172 VDDQ 20 DQ11 51 CB3 81 VSS 112 VDDQ 143 VDDQ 173 NC 21 CKE0 52 BA1 82 VDDID 113 NC 144 CB7 174 DQ60 22 VDDQ 83 DQ56 114 DQ20 175 DQ61 KEY KEY 23 DQ16 53 DQ32 84 DQ57 115 A12 145 VSS 176 VSS 24 DQ17 54 VDDQ 85 VDD 116 VSS 146 DQ36 177 DQS16 25 DQS2 55 DQ33 86 DQS7 117 DQ21 147 DQ37 178 DQ62 26 VSS 56 DQS4 87 DQ58 118 A11 148 VDD 179 DQ63 27 A9 57 DQ34 88 DQ59 119 DQS11 149 DQS13 180 VDDQ 28 DQ18 58 VSS 89 VSS 120 VDD 150 DQ38 181 SA0 29 A7 59 BA0 90 NC 121 DQ22 151 DQ39 182 SA1 30 VDDQ 60 DQ35 91 SDA 122 A8 152 VSS 183 SA2 31 DQ19 61 DQ40 92 SCL 123 DQ23 153 DQ44 184 VDDSPD REV 0.2 (Preliminary) 05/2003 2 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GD72S4NB0FU 1GB : 128M x 72 Low Profile Registered DDR SDRAM DIMM Input/Output Functional Description Symbol Type Polarity Function CK0 (SSTL) The positive line of the differential pair of system clock inputs which drives the input to Positive the on-DIMM PLL. All the DDR SDRAM address and control inputs are sampled on the Edge rising edge of their associated clocks. CK0 (SSTL) Negative The negative line of the differential pair of system clock inputs which drives the input to Edge the on-DIMM PLL. CKE0, CKE1 (SSTL) Active High Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode. S0, S1 (SSTL) Active Low Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS, CAS, WE (SSTL) Active Low When sampled at the positive rising edge of the clock, RAS, CAS, WE define the operation to be executed by the SDRAM. VREF Supply Reference voltage for SSTL-2 inputs VDDQ Supply Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity BA0, BA1 (SSTL) - Selects which SDRAM bank is to be active. A0 - A9 A10/AP A11, A12 (SSTL) - During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9, A11 defines the column address (CA0-CA10) when sampled at the rising clock edge. In addition to the column address, AP is used to invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high, autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge. DQ0 - DQ63 (SSTL) - Data and Check Bit input/output pins operate in the same manner as on conventional DRAMs. DQ0 - DQ63 CB0 - CB7 (SSTL) Active High VDD, VSS Supply DQS0 - DQS17 (SSTL) RESET (LVC-MOS) Data and Check Bit Input/Output pins. Check bits are only applicable on the x72 DIMM configurations. Power and ground for the DDR SDRAM input buffers and core logic Negative and Data strobe for input and output data Positive Edge Active Low SA0 - SA2 - Address inputs. Connected to either VDD or VSS on the system board to configure the Serial Presence Detect EEPROM address. SDA - This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to V DD to act as a pullup. SCL - This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to V DD to act as a pullup. V DDSPD Supply REV 0.2 (Preliminary) 05/2003 Serial EEPROM positive power supply. 3 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GD72S4NB0FU 1GB : 128M x 72 Low Profile Registered DDR SDRAM DIMM Functional Block Diagram (2 Bank, 64Mx4 DDR SDRAMs) REV 0.2 (Preliminary) 05/2003 4 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GD72S4NB0FU 1GB : 128M x 72 Low Profile Registered DDR SDRAM DIMM Serial Presence Detect -- Part 1 of 2 128Mx72 2 BANK REGISTERED DDR SDRAM DIMM based on 64Mx4, 4Banks, 8K Refresh, 2.5V DDR SDRAMs with SPD Byte SPD Entry Value Serial PD Data Entry (Hexadecimal) DDR266 -75B DDR266 -75B 80 Description 0 Number of Serial PD Bytes Written during Production 128 1 Total Number of Bytes in Serial PD device 256 08 2 Fundamental Memory Type SDRAM DDR 07 3 Number of Row Addresses on Assembly 13 0D 4 Number of Column Addresses on Assembly 11 0B 5 Number of DIMM Bank 2 02 6 Data Width of Assembly X72 48 X72 00 7 Data Width of Assembly (cont') 8 Voltage Interface Level of this Assembly 9 SSTL 2.5V 04 DDR SDRAM Device Cycle Time at CL=2.5 7.5ns 75 10 DDR SDRAM Device Access Time from Clock at CL=2.5 0.75ns 75 11 DIMM Configuration Type ECC 02 12 Refresh Rate/Type SR/1x(7.8us) 82 13 Primary DDR SDRAM Width X4 04 14 Error Checking DDR SDRAM Device Width X4 04 15 DDR SDRAM Device Attr: Min CLK Delay, Random Col Access 1 Clock 01 16 DDR SDRAM Device Attributes: Burst Length Supported 2,4,8 0E 17 DDR SDRAM Device Attributes: Number of Device Banks 4 04 18 DDR SDRAM Device Attributes: CAS Latencies Supported 2/2.5 0C 19 DDR SDRAM Device Attributes: CS Latency 0 01 20 DDR SDRAM Device Attributes: WE Latency 1 02 21 DDR SDRAM Device Attributes: Differential Clock, PLL, REGISTER 26 22 DDR SDRAM Device Attributes: General 23 Minimum Clock Cycle at CL=2 24 Maximum Data Access Time from Clock at CL=2 +/-0.2V Voltage Tolerance 00 10ns A0 0.75ns 75 25 Minimum Clock Cycle Time at CL=1 N/A 00 26 Maximum Data Access Time from Clock at CL=1 N/A 00 27 Minimum Row Precharge Time (tRP) 20ns 50 28 Minimum Row Active to Row Active delay (tRRD) 15ns 3C 29 Minimum RAS to CAS delay (tRCD) 20ns 50 30 Minimum RAS Pulse Width (tRAS) 45ns 2D 31 Module Bank Density 512MB 80 32 Address and Command Setup Time Before Clock 0.9ns 90 33 Address and Command Hold Time After Clock 0.9ns 90 34 Data Input Setup Time Before Clock 0.5ns 50 35 Data Input Hold Time After Clock 0.5ns 50 36-61 Reserved 62 SPD Revision 63 Checksum Data REV 0.2 (Preliminary) 05/2003 Undefined 00 Initial 00 Note 11 5 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GD72S4NB0FU 1GB : 128M x 72 Low Profile Registered DDR SDRAM DIMM Serial Presence Detect -- Part 2 of 2 128Mx72 2 BANK REGISTERED DDR SDRAM DIMM based on 64Mx4, 4Banks, 8K Refresh, 2.5V DDR SDRAMs with SPD Byte Serial PD Data Entry (Hexadecimal) DDR266 -75B DDR266 -75B NANYA 7F7F7F0B00000000 N/A 00 N/A 00 Description 64-71 Manufacturer's JEDEC ID Code 72 SPD Entry Value Module Manufacturing Location 73-90 Module Part number 91-92 Module Revision Code 93-94 Module Manufacturing Data 95-98 Module Serial Number 99-255 Reserved N/A 00 Year/Week Code yy/ww Serial Number 00 Undefined 00 Note 1, 2 yy= Binary coded decimal year code, 0-99(Decimal), 00-63(Hex) ww= Binary coded decimal year code, 01-52(Decimal), 01-34(Hex) REV 0.2 (Preliminary) 05/2003 6 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GD72S4NB0FU 1GB : 128M x 72 Low Profile Registered DDR SDRAM DIMM Absolute Maximum Ratings Symbol VIN, VOUT Parameter Voltage on I/O pins relative to Vss Rating Units -0.5 to VDDQ+0.5 V VIN Voltage on Input relative to Vss -0.5 to +2.7 V VDD Voltage on VDD supply relative to Vss -0.5 to +2.7 V Voltage on VDDQ supply relative to Vss -0.5 to +2.7 V 0 to +70 C -55 to +150 C Power Dissipation 36 W Short Circuit Output Current 50 mA VDDQ TA TSTG PD IOUT Operating Temperature (Ambient) Storage Temperature (Plastic) Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Capacitance Parameter Symbol Max. Units Notes Input Capacitance: CK0, CK0 CI1 TBD pF 1 Input Capacitance: A0-A12, BA0, BA1, WE, RAS, CAS, CKE0, S0 CI2 TBD pF 1 Input Capacitance: RESET CI3 TBD pF 1 Input Capacitance: SA0-SA2, SCL CI4 TBD pF 1 Input/Output Capacitance DQ0-63; DQS0-17, CB0-7 CIO1 TBD pF 1, 2 Input/Output Capacitance: SDA CIO3 TBD pF 1. 2. VDDQ = VDD = 2.5V 0.2V, f = 100 MHz, TA = 25 C, VOUT (DC) = VDDQ/2, VOUT (Peak to Peak) = 0.2V. DM inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching at the board level. REV 0.2 (Preliminary) 05/2003 7 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GD72S4NB0FU 1GB : 128M x 72 Low Profile Registered DDR SDRAM DIMM DC Electrical Characteristics and Operating Conditions (TA = 0 C ~ 70 C; VDDQ = 2.5V 0.2V; VDD = 2.5V 0.2V, See AC Characteristics) Symbol VDD VDDQ VSS, VSSQ Units Notes 2.7 V 1 I/O Supply Voltage 2.3 2.7 V 1 0 0 V Supply Voltage, I/O Supply Voltage 0.49 x VDDQ 0.51 x VDDQ V 1, 2 VREF - 0.04 VREF + 0.04 V 1, 3 VIH (DC) Input High (Logic1) Voltage VREF + 0.15 VDDQ + 0.3 V 1 VIL (DC) Input Low (Logic0) Voltage -0.3 VREF - 0.15 V 1 VIN (DC) Input Voltage Level, CK and CK Inputs -0.3 VDDQ + 0.3 V 1 Input Differential Voltage, CK and CK Inputs VID (DC) 0.30 V DDQ + 0.6 V 1, 4 Input Leakage Current Any input 0V VIN VDD; (All other pins not under test = 0V) -5 5 uA 1 IOZ Output Leakage Current (DQs are disabled; 0V Vout VDDQ -5 5 uA 1 IOH Output High Current (VOUT = VDDQ -0.373V, min VREF, min VTT) -16.8 - mA 1 IOL Output Low Current (VOUT = 0.373, max VREF, max VTT) 16.8 - mA 1 II 4. Max 2.3 I/O Reference Voltage VTT 3. Parameter I/O Termination Voltage (System) VREF 1. 2. Min Supply Voltage Inputs are not recognized as valid until VREF stabilizes. VREF is expected to be equal to 0.5 V DDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 2% of the DC value. VTT is not applied directly to the DIMM. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. VID is the magnitude of the difference between the input level on CK and the input level on CK. REV 0.2 (Preliminary) 05/2003 8 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GD72S4NB0FU 1GB : 128M x 72 Low Profile Registered DDR SDRAM DIMM AC Characteristics (Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, Operating, Standby, and Refresh Currents, and Electrical Characteristics and AC Timing.) 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below. 4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between VIL (AC) and VIH (AC) unless otherwise specified. 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input LOW (HIGH) level. AC Output Load Circuits VTT 50 ohms Output Timing Reference Point VOUT 30 pF AC Operating Conditions (TA = 0 C ~ 70 C; VDDQ = 2.5V 0.2V; VDD = 2.5V 0.2V, See AC Characteristics) Symbol Parameter/Condition Min Max Unit Notes VIH (AC) Input High (Logic 1) Voltage V REF + 0.31 - V 1, 2 VIL (AC) Input Low (Logic 0) Voltage - V REF - 0.31 V 1, 2 0.7 V DDQ + 0.6 V 1, 2, 3 0.5 x VDDQ - 0.2 0.5 x VDDQ + 0.2 V 1, 2, 4 VID (AC) Input Differential Voltage, CK and CK Inputs VIX (AC) Input Differential Pair Cross Point Voltage, CK and CK Inputs 1. 2. 3. 4. Input slew rate = 1V/ ns. Inputs are not recognized as valid until VREF stabilizes. VID is the magnitude of the difference between the input level on CK and the input level on CK. The value of VIX is expected to equal 0.5 x VDDQ of the transmitting device and must track variations in the DC level of the same. REV 0.2 (Preliminary) 05/2003 9 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GD72S4NB0FU 1GB : 128M x 72 Low Profile Registered DDR SDRAM DIMM Operating, Standby, and Refresh Currents (TA = 0 C ~ 70 C; VDDQ = 2.5V 0.2V; VDD = 2.5V 0.2V, See AC Characteristics) Symbol Parameter/Condition PC2100 (-75B) Unit Notes I DD0 Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle TBD mA 1, 2 I DD1 Operating Current: one bank; active/read/precharge; Burst = 2; tRC = tRC (MIN); CL=2.5; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle TBD mA 1, 2 I DD2P Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) TBD mA 1, 2 I DD2N Idle Standby Current: CS VIH (MIN); all banks idle; CKE VIH (MIN); tCK = tCK (MIN); address and control inputs changing once per clock cycle TBD mA 1, 2 I DD3P Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) TBD mA 1, 2 I DD3N Active Standby Current: one bank; active/precharge; CS VIH (MIN); CKE VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle TBD mA 1, 2 I DD4R Operating Current: one bank; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA TBD mA 1, 2 I DD4W Operating Current: one bank; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL=2.5; tCK = tCK (MIN) TBD mA 1, 2 I DD5 Auto-Refresh Current: tRC = tRFC (MIN) TBD mA 1, 2, 4 I DD6 Self-Refresh Current: CKE 0.2V TBD mA 1, 2 I DD7 Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. TBD mA 1, 2 1. 2. 3. 4. I DD specifications are tested after the device is properly initialized. Input slew rate = 1V/ ns. Enables on-chip refresh and address counters. Current at 7.8 s is time-averaged value of IDD5 at tRFC (MIN) and IDD2P over 7.8 s. REV 0.2 (Preliminary) 05/2003 10 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GD72S4NB0FU 1GB : 128M x 72 Low Profile Registered DDR SDRAM DIMM AC Timing Specifications for DDR SDRAM Devices Used on Module (TA = 0 C ~ 70 C; VDDQ = 2.5V 0.2V; VDD = 2.5V 0.2V, See AC Characteristics) (Part 1 of 2) Symbol tAC tDQSCK -75B Parameter Unit Notes +0.75 ns 1-4 +0.75 ns 1-4 Min. Max. DQ output access time from CK/CK -0.75 DQS output access time from CK/CK -0.75 tCH CK high-level width 0.45 0.55 tCK 1-4 tCL CK low-level width 0.45 0.55 tCK 1-4 tCK Clock cycle time tCK CL=2.5 7.5 12 ns 1-4 CL=2 10 12 ns 1-4 tDH DQ and DM input hold time 0.5 ns 1-4, 15, 16 tDS DQ and DM input setup time 0.5 ns 1-4, 15, 16 tDIPW DQ and DM input pulse width (each input) 1.75 ns 1-4 tHZ Data-out high-impedance time from CK/CK -0.75 +0.75 ns 1-4, 5 tLZ Data-out low-impedance time from CK/CK -0.75 +0.75 ns 1-4, 5 0.5 ns 1-4 tDQSQ DQS-DQ skew (DQS & associated DQ signals) tHP Minimum half clk period for any given cycle; defined by clk high (tCH) or clk low (tCL) time tCH or tCL tCK 1-4 tQH Data output hold time from DQS tHP tQHS tCK 1-4 0.75ns tCK 1-4 1.25 tCK 1-4 tQHS Data hold Skew Factor tDQSS Write command to 1st DQS latching transition 0.75 DQS input low (high) pulse width (write cycle) 0.35 tCK 1-4 tDSS DQS falling edge to CK setup time (write cycle) 0.2 tCK 1-4 tDSH DQS falling edge hold time from CK (write cycle) 0.2 tCK 1-4 tMRD Mode register set command cycle time 2 tCK 1-4 Write preamble setup time 0 ns 1-4, 7 tCK 1-4, 6 tDQSL,H tWPRES tWPST Write postamble 0.40 tWPRE Write preamble 0.25 tCK 1-4 tIH Address and control input hold time (fast slew rate) 0.9 ns 2-4, 9, 11, 12 tIS Address and control input setup time (fast slew rate) 0.9 ns 2-4, 9, 11, 12 tIH Address and control input hold time (slow slew rate) 1.0 ns 2-4, 10, 11, 12, 14 REV 0.2 (Preliminary) 05/2003 0.60 11 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GD72S4NB0FU 1GB : 128M x 72 Low Profile Registered DDR SDRAM DIMM AC Timing Specifications for DDR SDRAM Devices Used on Module (TA = 0 C ~ 70 C; VDDQ = 2.5V 0.2V; VDD = 2.5V 0.2V, See AC Characteristics) (Part 2 of 2) Symbol -75B Parameter Min. tIS tIPW Address and control input setup time (slow slewrate) 1.0 Input pulse width 2.2 Read preamble 0.9 tRPST Read postamble tRAS Active to Precharge command tRC Active to Active/Auto-refresh command period tRFC Unit Notes ns 2-4, 10-12, 14 Max. ns 2-4, 12 1.1 tCK 1-4 0.40 0.60 tCK 1-4 45 120,000 ns 1-4 65 ns 1-4 Auto-refresh to Active/Auto-refresh command period 75 ns 1-4 tRCD Active to Read or Write delay 20 ns 1-4 tRAP Active to Read Command with Autoprecharge 20 ns 1-4 tRP Precharge command period 20 ns 1-4 tRRD Active bank A to Active bank B command 15 ns 1-4 tWR Write recovery time 15 ns 1-4 tDAL Auto precharge write recovery + precharge time (tWR/tCK ) + (tRP/tCK ) tCK 1-4, 13 tWTR Internal write to read command delay 1 tCK 1-4 tRPRE tPDEX Power down exit time 7.5 ns 1-4 tXSNR Exit self-refresh to non-read command 75 ns 1-4 tXSRD Exit self-refresh to read command 200 tREFI Average Periodic Refresh Interval REV 0.2 (Preliminary) 05/2003 7.8 tCK 1-4 s 1-4, 8 12 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GD72S4NB0FU 1GB : 128M x 72 Low Profile Registered DDR SDRAM DIMM AC Timing Specification Notes 1. Input slew rate = 1V/ns. 2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK is VREF. 3. Inputs are not recognized as valid until VREF stabilizes. 4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT. 5. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from high to low at this time, depending on tDQSS. 8. A maximum of eight Auto refresh commands can be posted to any given DDR SDRAM device. 9. For command/address input slew rate >= 1.0 V/ns. Slew rate is measured between VOH (AC) and VOL (AC). 10. For command/address input slew rate >= 0.5 V/ns and < 1.0 V/ns. Slew rate is measured between VOH (AC) and VOL (AC). 11. CK/CK slew rates are >= 1.0 V/ns. 12. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by design or tester characterization. 13. For each of the terms in parentheses, if not already an integer, round to the next highest integer. t CK is equal to the actual system clock cycle time. For example, for PC2100 at CL= 2.5, t DAL = (15ns/7.5ns) +(20ns/7.0ns) = 2 + 3 = 5. 14. An input setup and hold time derating table is used to increase t IS and t IH in the case where the input slew rate is below 0.5 V/ns. Input Slew Rate 1. 2. Delta (tIH) Delta (tIS) Unit Note 0.5 V/ns 0 0 ps 1, 2 0.4 V/ns +50 0 ps 1, 2 0.3 V/ns +100 0 ps 1, 2 Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC), similarly for rising transitions. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device. 15. An input setup and hold time derating table is used to increase t DS and t DH in the case where the I/O slew rate is below 0.5 V/ns. 1. 2. Input Slew Rate Delta (tDS) Delta (tDH) Unit 0.5 V/ns 0 0 ps 1, 2 0.4 V/ns +75 +75 ps 1, 2 0.3 V/ns +150 +150 ps 1, 2 Note I/O slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC), similarly for rising transitions. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device. 16. An I/O Delta Rise, Fall Derating table is used to increase t DS and t DH in the case where DQ, DM, and DQS slew rates differ. 1. 2. 3. 4. Delta Rise and Fall Rate Delta (tDS) Delta (tDH) Unit Note 0.0 ns/V 0 0 ps 1-4 0.25 ns/V +50 +50 ps 1-4 0.5 ns/V +100 +100 ps 1-4 Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC), similarly for rising transitions. Input slew rate is based on the larger of AC to AC delta rise, fall rate and DC to DC delta rise, fall rate. The delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)] For example: slew rate 1 = 0.5 V/ns; slew rate 2 = 0.4 V/ns. Delta rise, fall = (1/0.5) - (1/0.4) [ns/V] = -0.5 ns/V Using the table above, this would result in an increase in t DS and t DH of 100 ps. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device. REV 0.2 (Preliminary) 05/2003 13 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GD72S4NB0FU 1GB : 128M x 72 Low Profile Registered DDR SDRAM DIMM Package Dimensions FRONT 133.35 5.250 131.35 5.171 30.48 1.200 10.0 0.394 (2X) 4.00 0.157 128.95 5.077 Detail B 17.80 0.700 Detail A 2.5 0.098 2.3 0.091 Register BACK SIDE 3.99 0.157 max. (Front) 4.50 0.177 Register PLL 3.80 0.15 1.27 0.050 Detail B 4.00 0.157 Detail A 1.80 0.071 1.00 Width 0.039 1.27 Pitch 0.050 Note: All dimensions are typical with tolerances of +/- 0.15 (0.006) unless otherwise stated. Units: Millimeters (Inches) REV 0.2 (Preliminary) 05/2003 14 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT1GD72S4NB0FU 1GB : 128M x 72 Low Profile Registered DDR SDRAM DIMM Revision Log Rev Date 0.1 04/2003 Preliminary Release Modification 0.2 05/2003 Updated Functional Block Diagram REV 0.2 (Preliminary) 05/2003 15 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.