PIC18F97J60 Family Data Sheet 64/80/100-Pin, High-Performance, 1-Mbit Flash Microcontrollers with Ethernet 2011 Microchip Technology Inc. DS39762F Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-61341-069-1 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS39762F-page 2 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 64/80/100-Pin High-Performance, 1-Mbit Flash Microcontrollers with Ethernet Ethernet Features: Peripheral Highlights: * * * * * * * * * High-Current Sink/Source: 25 mA/25 mA on PORTB and PORTC * Five Timer modules (Timer0 to Timer4) * Four External Interrupt pins * Two Capture/Compare/PWM (CCP) modules * Three Enhanced Capture/Compare/PWM (ECCP) modules: - One, two or four PWM outputs - Selectable polarity - Programmable dead time - Auto-shutdown and auto-restart * Up to Two Master Synchronous Serial Port (MSSP) modules supporting SPI (all 4 modes) and I2CTM Master and Slave modes * Up to Two Enhanced USART modules: - Supports RS-485, RS-232 and LIN/J2602 - Auto-wake-up on Start bit - Auto-Baud Detect (ABD) * 10-Bit, Up to 16-Channel Analog-to-Digital Converter module (A/D): - Auto-acquisition capability - Conversion available during Sleep * Dual Analog Comparators with Input Multiplexing * Parallel Slave Port (PSP) module (100-pin devices only) * * * * IEEE 802.3TM Compatible Ethernet Controller Fully Compatible with 10/100/1000Base-T Networks Integrated MAC and 10Base-T PHY 8-Kbyte Transmit/Receive Packet Buffer SRAM Supports One 10Base-T Port Programmable Automatic Retransmit on Collision Programmable Padding and CRC Generation Programmable Automatic Rejection of Erroneous Packets Activity Outputs for 2 LED Indicators Buffer: - Configurable transmit/receive buffer size - Hardware-managed circular receive FIFO - Byte-wide random and sequential access - Internal DMA for fast memory copying - Hardware assisted checksum calculation for various protocols MAC: - Support for Unicast, Multicast and Broadcast packets - Programmable Pattern Match of up to 64 bytes within packet at user-defined offset - Programmable wake-up on multiple packet formats PHY: - Wave shaping output filter Special Microcontroller Features: Flexible Oscillator Structure: * Selectable System Clock derived from Single 25 MHz External Source: - 2.778 to 41.667 MHz * Internal 31 kHz Oscillator * Secondary Oscillator using Timer1 @ 32 kHz * Fail-Safe Clock Monitor: - Allows for safe shutdown if oscillator stops * Two-Speed Oscillator Start-up External Memory Bus (100-pin devices only): * Address Capability of up to 2 Mbytes * 8-Bit or 16-Bit Interface * 12-Bit, 16-Bit and 20-Bit Addressing modes 2011 Microchip Technology Inc. * 5.5V Tolerant Inputs (digital-only pins) * Low-Power, High-Speed CMOS Flash Technology: - Self-reprogrammable under software control * C compiler Optimized Architecture for Reentrant Code * Power Management Features: - Run: CPU on, peripherals on - Idle: CPU off, peripherals on - Sleep: CPU off, peripherals off * Priority Levels for Interrupts * 8 x 8 Single-Cycle Hardware Multiplier * Extended Watchdog Timer (WDT): - Programmable period from 4 ms to 134s * Single-Supply 3.3V In-Circuit Serial ProgrammingTM (ICSPTM) via Two Pins * In-Circuit Debug (ICD) with 3 Breakpoints via Two Pins * Operating Voltage Range of 2.35V to 3.6V (3.1V to 3.6V using Ethernet module) * On-Chip 2.5V Regulator DS39762F-page 3 Comparators PIC18F66J60 64K 3808 8192 39 11 2/3 1 Y Y 1 2 2/3 N N PIC18F66J65 96K 3808 8192 39 11 2/3 1 Y Y 1 2 2/3 N N PIC18F67J60 128K 3808 8192 39 11 2/3 1 Y Y 1 2 2/3 N N PIC18F86J60 64K 3808 8192 55 15 2/3 1 Y Y 2 2 2/3 N N PIC18F86J65 96K 3808 8192 55 15 2/3 1 Y Y 2 2 2/3 N N PIC18F87J60 128K 3808 8192 55 15 2/3 1 Y Y 2 2 2/3 N N PIC18F96J60 64K 3808 8192 70 16 2/3 2 Y Y 2 2 2/3 Y Y PIC18F96J65 96K 3808 8192 70 16 2/3 2 Y Y 2 2 2/3 Y Y PIC18F97J60 128K 3808 8192 70 16 2/3 2 Y Y 2 2 2/3 Y Y Device SRAM Flash Data Program Memory Memory (bytes) (bytes) DS39762F-page 4 MSSP Ethernet TX/RX Buffer (bytes) I/O 10-Bit A/D (ch) CCP/ ECCP SPI Master I2CTM Timers PSP 8/16-Bit External Memory Bus EUSART PIC18F97J60 FAMILY 2011 Microchip Technology Inc. PIC18F97J60 FAMILY VDDTX TPOUT- TPOUT+ VSSTX RBIAS VDDPLL VSSPLL VSS VDD RD2/CCP4/P3D RD0/P1B RE5/P1C RE4/P3B RE3/P3C RE2/P2B 64-Pin TQFP RD1/ECCP3/P3A Pin Diagrams 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RE1/P2C 1 48 RE0/P2D 2 RB0/INT0/FLT0 RB1/INT1 RB2/INT2 3 4 5 47 46 45 RB3/INT3 MCLR RG4/CCP5/P1D 6 VSS VDDCORE/VCAP RF7/SS1 7 8 9 RF4/AN9 10 11 12 13 14 RF3/AN8 RF2/AN7/C1OUT 15 16 RF6/AN11 RF5/AN10/CVREF 44 43 42 41 40 PIC18F66J60 PIC18F66J65 PIC18F67J60 39 38 37 36 35 34 33 VDDRX TPIN+ TPINVSSRX RB4/KBI0 RB5/KBI1 RB6/KBI2/PGC VSS OSC2/CLKO OSC1/CLKI VDD RB7/KBI3/PGD RC5/SDO1 RC4/SDI1/SDA1 RC3/SCK1/SCL1 RC2/ECCP1/P1A 2011 Microchip Technology Inc. RC7/RX1/DT1 RC6/TX1/CK1 RC0/T1OSO/T13CKI RA4/T0CKI RC1/T1OSI/ECCP2/P2A RA5/AN4 VDD VSS RA0/LEDA/AN0 RA1/LEDB/AN1 RA2/AN2/VREF- RA3/AN3/VREF+ AVSS AVDD ENVREG RF1/AN6/C2OUT 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DS39762F-page 5 PIC18F97J60 FAMILY Pin Diagrams (Continued) VDDTX TPOUT+ TPOUT- VSSTX RBIAS VDDPLL VSSPLL RD2 RD1 VSS VDD RE7/ECCP2(1)/P2A(1) RD0 RE6/P1B(2) RE5/P1C(2) RE4/P3B(2) RE3/P3C(2) RE2/P2B RH0 RH1 80-Pin TQFP 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 RH2 1 60 VDDRX RH3 2 RE1/P2C RE0/P2D 3 4 5 6 7 59 58 57 56 55 TPIN+ TPINVSSRX RG0/ECCP3/P3A RG1/TX2/CK2 RB4/KBI0 RB5/KBI1 RB6/KBI2/PGC VSS OSC2/CLKO OSC1/CLKI VDD RB7/KBI3/PGD RC5/SDO1 RB0/INT0/FLT0 RB1/INT1 RB2/INT2 RB3/INT3 MCLR RG4/CCP5/P1D VSS VDDCORE/VCAP RF7/SS1 RF6/AN11 RF5/AN10/CVREF RF4/AN9 RF3/AN8 RF2/AN7/C1OUT 8 9 10 11 12 13 14 15 16 RH7/AN15/P1B(2) 17 18 19 RH6/AN14/P1C(2) 20 54 53 52 51 50 PIC18F86J60 PIC18F86J65 PIC18F87J60 49 48 47 46 45 44 43 42 41 RC4/SDI1/SDA1 RC3/SCK1/SCL1 RC2/ECCP1/P1A RG2/RX2/DT2 RG3/CCP4/P3D DS39762F-page 6 RJ5 RJ4 RC7/RX1/DT1 RC6/TX1/CK1 RC1/T1OSI/ECCP2(1)/P2A(1) RC0/T1OSO/T13CKI RA4/T0CKI RA5/AN4 VDD VSS RA0/LEDA/AN0 RA1/LEDB/AN1 RA2/AN2/VREF- RA3/AN3/VREF+ AVSS AVDD ENVREG RF1/AN6/C2OUT RH5/AN13/P3B(2) Note 1: 2: RH4/AN12/P3C(2) 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 The ECCP2/P2A pin placement depends on the CCP2MX Configuration bit setting. P1B, P1C, P3B and P3C pin placement depends on the ECCPMX Configuration bit setting. 2011 Microchip Technology Inc. PIC18F97J60 FAMILY Pin Diagrams (Continued) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 RH1/A17 RH0/A16 RE2/AD10/CS/P2B RE3/AD11/P3C(2) RE4/AD12/P3B(2) RE5/AD13/P1C(2) RE6/AD14/P1B(2) RE7/AD15/ECCP2(1)/P2A(1) RD0/AD0/PSP0 RD1/AD1/PSP1 RD2/AD2/PSP2 RD3/AD3/PSP3 RD4/AD4/PSP4/SDO2 RD5/AD5/PSP5/SDI2/SDA2 VDD VSS RD6/AD6/PSP6/SCK2/SCL2 RD7/AD7/PSP7/SS2 VSSPLL VDDPLL RBIAS VSSTX TPOUT+ TPOUTVDDTX 100-Pin TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PIC18F96J60 PIC18F96J65 PIC18F97J60 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VDDRX TPIN+ TPINVSSRX RG0/ECCP3/P3A RG1/TX2/CK2 RB4/KBI0 RB5/KBI1 RB6/KBI2/PGC RJ2/WRL VSS OSC2/CLKO OSC1/CLKI VDD RJ3/WRH VSS VDD RJ6/LB RB7/KBI3/PGD RC5/SDO1 RC4/SDI1/SDA1 RC3/SCK1/SCL1 RC2/ECCP1/P1A RG2/RX2/DT2 RG3/CCP4/P3D Note 1: 2: RC1/T1OSI/ECCP2(1)/P2A(1) RC0/T1OSO/T13CKI RC6/TX1/CK1 RC7/RX1/DT1 RJ4/BA0 RJ5/CE RJ0/ALE RJ1/OE RH5/AN13/P3B(2) RH4/AN12/P3C(2) RF1/AN6/C2OUT ENVREG AVDD AVSS RA3/AN3/VREF+ RA2/AN2/VREFRA1/LEDB/AN1 RA0/LEDA/AN0 VSS VDD RG7 RJ7/UB VSS RA5/AN4 RA4/T0CKI 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 RH2/A18 RH3/A19 RE1/AD9/WR/P2C RE0/AD8/RD/P2D RB0/INT0/FLT0 RB1/INT1 RB2/INT2 RB3/INT3/ECCP2(1)/P2A(1) NC RG6 RG5 RF0/AN5 MCLR RG4/CCP5/P1D VSS VDDCORE/VCAP VDD RF7/SS1 RF6/AN11 RF5/AN10/CVREF RF4/AN9 RF3/AN8 RF2/AN7/C1OUT RH7/AN15/P1B(2) RH6/AN14/P1C(2) The ECCP2/P2A pin placement depends on the CCP2MX Configuration bit and Processor mode settings. P1B, P1C, P3B and P3C pin placement depends on the ECCPMX Configuration bit setting. 2011 Microchip Technology Inc. DS39762F-page 7 PIC18F97J60 FAMILY Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 11 2.0 Guidelines for Getting Started with PIC18FJ Microcontrollers ................................................................................................... 43 3.0 Oscillator Configurations ............................................................................................................................................................ 49 4.0 Power-Managed Modes ............................................................................................................................................................. 55 5.0 Reset .......................................................................................................................................................................................... 63 6.0 Memory Organization ................................................................................................................................................................. 77 7.0 Flash Program Memory ............................................................................................................................................................ 105 8.0 External Memory Bus ............................................................................................................................................................... 115 9.0 8 x 8 Hardware Multiplier.......................................................................................................................................................... 127 10.0 Interrupts .................................................................................................................................................................................. 129 11.0 I/O Ports ................................................................................................................................................................................... 145 12.0 Timer0 Module ......................................................................................................................................................................... 171 13.0 Timer1 Module ......................................................................................................................................................................... 175 14.0 Timer2 Module ......................................................................................................................................................................... 180 15.0 Timer3 Module ......................................................................................................................................................................... 183 16.0 Timer4 Module ......................................................................................................................................................................... 187 17.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 189 18.0 Enhanced Capture/Compare/PWM (ECCP) Modules .............................................................................................................. 197 19.0 Ethernet Module ....................................................................................................................................................................... 217 20.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 269 21.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 315 22.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 339 23.0 Comparator Module.................................................................................................................................................................. 349 24.0 Comparator Voltage Reference Module ................................................................................................................................... 355 25.0 Special Features of the CPU .................................................................................................................................................... 359 26.0 Instruction Set Summary .......................................................................................................................................................... 375 27.0 Development Support............................................................................................................................................................... 425 28.0 Electrical Characteristics .......................................................................................................................................................... 429 29.0 Packaging Information.............................................................................................................................................................. 465 Appendix A: Revision History............................................................................................................................................................. 475 Appendix B: Device Differences......................................................................................................................................................... 476 Index .................................................................................................................................................................................................. 477 The Microchip Web Site ..................................................................................................................................................................... 489 Customer Change Notification Service .............................................................................................................................................. 489 Customer Support .............................................................................................................................................................................. 489 Reader Response .............................................................................................................................................................................. 490 Product Identification System............................................................................................................................................................. 491 DS39762F-page 8 2011 Microchip Technology Inc. PIC18F97J60 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. 2011 Microchip Technology Inc. DS39762F-page 9 PIC18F97J60 FAMILY NOTES: DS39762F-page 10 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 1.0 DEVICE OVERVIEW This document contains device-specific information for the following devices: * PIC18F66J60 * PIC18F87J60 * PIC18F66J65 * PIC18F96J60 * PIC18F67J60 * PIC18F96J65 * PIC18F86J60 * PIC18F97J60 * PIC18F86J65 This family introduces a new line of low-voltage devices with the foremost traditional advantage of all PIC18 microcontrollers - namely, high computational performance and a rich feature set at an extremely competitive price point. These features make the PIC18F97J60 family a logical choice for many high-performance applications where cost is a primary consideration. 1.1 1.1.1 Core Features OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18F97J60 family offer five different oscillator options, allowing users a range of choices in developing application hardware. These options include: * Two Crystal modes, using crystals or ceramic resonators. * Two External Clock modes, offering the option of a divide-by-4 clock output. * A Phase Lock Loop (PLL) frequency multiplier, available to the external oscillator modes, which allows clock speeds of up to 41.667 MHz. * An internal RC oscillator with a fixed 31 kHz output which provides an extremely low-power option for timing-insensitive applications. The internal oscillator block provides a stable reference source that gives the family additional features for robust operation: 1.1.2 EXPANDED MEMORY The PIC18F97J60 family provides ample room for application code, from 64 Kbytes to 128 Kbytes of code space. The Flash cells for program memory are rated to last 100 erase/write cycles. Data retention without refresh is conservatively estimated to be greater than 20 years. The PIC18F97J60 family also provides plenty of room for dynamic application data with 3808 bytes of data RAM. 1.1.3 EXTERNAL MEMORY BUS In the unlikely event that 128 Kbytes of memory are inadequate for an application, the 100-pin members of the PIC18F97J60 family also implement an External Memory Bus (EMB). This allows the controller's internal program counter to address a memory space of up to 2 Mbytes, permitting a level of data access that few 8-bit devices can claim. This allows additional memory options, including: * Using combinations of on-chip and external memory up to the 2-Mbyte limit * Using external Flash memory for reprogrammable application code or large data tables * Using external RAM devices for storing large amounts of variable data 1.1.4 EXTENDED INSTRUCTION SET The PIC18F97J60 family implements the optional extension to the PIC18 instruction set, adding eight new instructions and an Indexed Addressing mode. Enabled as a device configuration option, the extension has been specifically designed to optimize reentrant application code originally developed in high-level languages, such as C. 1.1.5 EASY MIGRATION Regardless of the memory size, all devices share the same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve. * Fail-Safe Clock Monitor: This option constantly monitors the main clock source against a reference signal provided by the internal oscillator. If a clock failure occurs, the controller is switched to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown. * Two-Speed Start-up: This option allows the internal oscillator to serve as the clock source from Power-on Reset, or wake-up from Sleep mode, until the primary clock source is available. 2011 Microchip Technology Inc. DS39762F-page 11 PIC18F97J60 FAMILY 1.2 Other Special Features * Communications: The PIC18F97J60 family incorporates a range of serial communication peripherals, including up to two independent Enhanced USARTs and up to two Master SSP modules, capable of both SPI and I2CTM (Master and Slave) modes of operation. In addition, one of the general purpose I/O ports can be reconfigured as an 8-bit Parallel Slave Port for direct processor-to-processor communications. * CCP Modules: All devices in the family incorporate two Capture/Compare/PWM (CCP) modules and three Enhanced CCP (ECCP) modules to maximize flexibility in control applications. Up to four different time bases may be used to perform several different operations at once. Each of the three ECCP modules offers up to four PWM outputs, allowing for a total of twelve PWMs. The ECCP modules also offer many beneficial features, including polarity selection, programmable dead time, auto-shutdown and restart and Half-Bridge and Full-Bridge Output modes. * 10-Bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period and thus, reducing code overhead. * Extended Watchdog Timer (WDT): This enhanced version incorporates a 16-bit prescaler, allowing an extended time-out range. See Section 28.0 "Electrical Characteristics" for time-out periods. DS39762F-page 12 1.3 Details on Individual Family Members Devices in the PIC18F97J60 family are available in 64-pin, 80-pin and 100-pin packages. Block diagrams for the three groups are shown in Figure 1-1, Figure 1-2 and Figure 1-3. The devices are differentiated from each other in four ways: 1. 2. 3. 4. Flash program memory (three sizes, ranging from 64 Kbytes for PIC18FX6J60 devices to 128 Kbytes for PIC18FX7J60 devices). A/D channels (eleven for 64-pin devices, fifteen for 80-pin pin devices and sixteen for 100-pin devices). Serial communication modules (one EUSART module and one MSSP module on 64-pin devices, two EUSART modules and one MSSP module on 80-pin devices and two EUSART modules and two MSSP modules on 100-pin devices). I/O pins (39 on 64-pin devices, 55 on 80-pin devices and 70 on 100-pin devices). All other features for devices in this family are identical. These are summarized in Table 1-1, Table 1-2 and Table 1-3. The pinouts for all devices are listed in Table 1-4, Table 1-5 and Table 1-6. 2011 Microchip Technology Inc. PIC18F97J60 FAMILY TABLE 1-1: DEVICE FEATURES FOR THE PIC18F97J60 FAMILY (64-PIN DEVICES) Features Operating Frequency Program Memory (Bytes) Program Memory (Instructions) PIC18F66J60 PIC18F66J65 PIC18F67J60 DC - 41.667 MHz DC - 41.667 MHz DC - 41.667 MHz 64K 96K 128K 32764 49148 65532 Data Memory (Bytes) 3808 Interrupt Sources 26 I/O Ports Ports A, B, C, D, E, F, G I/O Pins 39 Timers 5 Capture/Compare/PWM Modules 2 Enhanced Capture/Compare/PWM Modules 3 Serial Communications MSSP (1), Enhanced USART (1) Ethernet Communications (10Base-T) Yes Parallel Slave Port Communications (PSP) No External Memory Bus No 10-Bit Analog-to-Digital Module Resets (and Delays) Instruction Set 11 Input Channels POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR , WDT (PWRT, OST) 75 Instructions, 83 with Extended Instruction Set Enabled Packages TABLE 1-2: 64-Pin TQFP DEVICE FEATURES FOR THE PIC18F97J60 FAMILY (80-PIN DEVICES) Features Operating Frequency Program Memory (Bytes) Program Memory (Instructions) Data Memory (Bytes) Interrupt Sources PIC18F86J60 PIC18F86J65 PIC18F87J60 DC - 41.667 MHz DC - 41.667 MHz DC - 41.667 MHz 64K 96K 128K 32764 49148 65532 3808 27 I/O Ports Ports A, B, C, D, E, F, G, H, J I/O Pins 55 Timers 5 Capture/Compare/PWM Modules 2 Enhanced Capture/Compare/PWM Modules 3 Serial Communications MSSP (1), Enhanced USART (2) Ethernet Communications (10Base-T) Yes Parallel Slave Port Communications (PSP) No External Memory Bus No 10-Bit Analog-to-Digital Module Resets (and Delays) Instruction Set Packages 2011 Microchip Technology Inc. 15 Input Channels POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR , WDT (PWRT, OST) 75 Instructions, 83 with Extended Instruction Set Enabled 80-Pin TQFP DS39762F-page 13 PIC18F97J60 FAMILY TABLE 1-3: DEVICE FEATURES FOR THE PIC18F97J60 FAMILY (100-PIN DEVICES) Features Operating Frequency Program Memory (Bytes) Program Memory (Instructions) Data Memory (Bytes) Interrupt Sources PIC18F96J60 PIC18F96J65 PIC18F97J60 DC - 41.667 MHz DC - 41.667 MHz DC - 41.667 MHz 64K 96K 128K 32764 49148 65532 3808 29 I/O Ports Ports A, B, C, D, E, F, G, H, J I/O Pins 70 Timers 5 Capture/Compare/PWM Modules 2 Enhanced Capture/Compare/PWM Modules 3 Serial Communications Ethernet Communications (10Base-T) MSSP (2), Enhanced USART (2) Yes Parallel Slave Port Communications (PSP) Yes External Memory Bus Yes 10-Bit Analog-to-Digital Module Resets (and Delays) Instruction Set Packages DS39762F-page 14 16 Input Channels POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR , WDT (PWRT, OST) 75 Instructions, 83 with Extended Instruction Set Enabled 100-Pin TQFP 2011 Microchip Technology Inc. PIC18F97J60 FAMILY FIGURE 1-1: PIC18F66J60/66J65/67J60 (64-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> 20 Address Latch PCU PCH PCL Program Counter 12 Data Address<12> 31 Level Stack 4 BSR Address Latch STKPTR Program Memory (64, 96, 128 Kbytes) PORTB RB0:RB7(1) 4 Access Bank 12 FSR0 FSR1 FSR2 12 Data Latch 8 RA0:RA5(1) Data Memory (3808 Bytes) PCLATU PCLATH 21 PORTA Data Latch 8 8 inc/dec logic PORTC RC0:RC7(1) inc/dec logic Table Latch Address Decode ROM Latch Instruction Bus <16> PORTD IR RD0:RD2(1) Instruction Decode and Control OSC2/CLKO OSC1/CLKI INTRC Oscillator ENVREG PRODH PRODL 3 Power-up Timer Timing Generation 8 State Machine Control Signals Precision Band Gap Reference Watchdog Timer Voltage Regulator Brown-out Reset(2) 8 W 8 8 8 8 Power-on Reset RE0:RE5(1) 8 x 8 Multiply BITOP Oscillator Start-up Timer PORTE 8 PORTF RF1:RF7(1) ALU<8> 8 PORTG RG4(1) VDDCORE/VCAP Note VDD, VSS MCLR ADC 10-Bit Timer0 Timer1 Timer2 Timer3 Timer4 Comparators ECCP1 ECCP2 ECCP3 CCP4 CCP5 MSSP1 EUSART1 1: See Table 1-4 for I/O port pin descriptions. 2: BOR functionality is provided when the on-board voltage regulator is enabled. 2011 Microchip Technology Inc. Ethernet DS39762F-page 15 PIC18F97J60 FAMILY FIGURE 1-2: PIC18F86J60/86J65/87J60 (80-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> 20 Address Latch PCU PCH PCL Program Counter 31 Level Stack 4 BSR STKPTR 12 FSR0 FSR1 FSR2 RB0:RB7(1) 4 Access Bank PORTC RC0:RC7(1) 12 Data Latch 8 PORTB 12 Data Address<12> Address Latch Program Memory (64, 96, 128 Kbytes) RA0:RA5(1) Data Memory (3808 Bytes) PCLATU PCLATH 21 PORTA Data Latch 8 8 inc/dec logic inc/dec logic Table Latch PORTD RD0:RD2(1) Address Decode ROM Latch Instruction Bus <16> PORTE IR RE0:RE7(1) 8 Instruction Decode & Control OSC2/CLKO OSC1/CLKI ENVREG 3 Power-on Reset 8 W 8 PORTG 8 RG0:RG4(1) 8 8 ALU<8> Watchdog Timer PORTH 8 Brown-out Reset(2) Voltage Regulator RF1:RF7(1) 8 x 8 Multiply BITOP 8 Oscillator Start-up Timer Precision Band Gap Reference PORTF PRODH PRODL Power-up Timer Timing Generation INTRC Oscillator State Machine Control Signals RH0:RH7(1) PORTJ VDDCORE/VCAP ECCP1 Note VDD, VSS RJ4:RJ5(1) MCLR ADC 10-Bit Timer0 Timer1 Timer2 Timer3 Timer4 Comparators ECCP2 ECCP3 CCP4 CCP5 EUSART1 EUSART2 MSSP1 1: See Table 1-5 for I/O port pin descriptions. 2: BOR functionality is provided when the on-board voltage regulator is enabled. DS39762F-page 16 Ethernet 2011 Microchip Technology Inc. PIC18F97J60 FAMILY FIGURE 1-3: PIC18F96J60/96J65/97J60 (100-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> inc/dec logic 21 Address Latch PCU PCH PCL Program Counter System Bus Interface 31 Level Stack STKPTR PORTB 12 Data Address<12> 4 Address Latch Program Memory (64, 96, 128 Kbytes) RA0:RA5(1) Data Memory (3808 Bytes) PCLATU PCLATH 20 PORTA Data Latch 8 8 4 12 BSR RB0:RB7(1) PORTC Access Bank FSR0 FSR1 FSR2 RC0:RC7(1) 12 Data Latch inc/dec logic 8 Table Latch PORTD RD0:RD7(1) Address Decode ROM Latch Instruction Bus <16> PORTE IR RE0:RE7(1) AD15:AD0, A19:A16 (Multiplexed with PORTD, PORTE and PORTH) State Machine Control Signals OSC2/CLKO OSC1/CLKI Timing Generation INTRC Oscillator ENVREG 8 Power-up Timer 3 Voltage Regulator Brown-out Reset(2) 8 W PORTG 8 8 RG0:RG7(1) 8 8 ALU<8> Power-on Reset Watchdog Timer RF0:RF7(1) 8 x 8 Multiply BITOP 8 Oscillator Start-up Timer Precision Band Gap Reference PORTF PRODH PRODL Instruction Decode & Control PORTH 8 RH0:RH7(1) PORTJ RJ0:RJ7(1) VDDCORE/VCAP VDD, VSS MCLR ADC 10-Bit Timer0 Timer1 Timer2 Timer3 Timer4 ECCP1 ECCP2 ECCP3 CCP4 CCP5 EUSART1 Note Comparators EUSART2 1: See Table 1-6 for I/O port pin descriptions. 2: BOR functionality is provided when the on-board voltage regulator is enabled. 2011 Microchip Technology Inc. MSSP1 MSSP2 Ethernet DS39762F-page 17 PIC18F97J60 FAMILY TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS Pin Number TQFP Pin Type Buffer Type MCLR 7 I ST OSC1/CLKI OSC1 39 Pin Name I CLKI I OSC2/CLKO OSC2 Master Clear (Reset) input. This pin is an active-low Reset to the device. Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in internal RC mode; CMOS otherwise. CMOS External clock source input. Always associated with pin function, OSC1. (See related OSC2/CLKO pin.) ST 40 CLKO Description O -- O -- Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In Internal RC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. PORTA is a bidirectional I/O port. RA0/LEDA/AN0 RA0 LEDA AN0 24 RA1/LEDB/AN1 RA1 LEDB AN1 23 RA2/AN2/VREFRA2 AN2 VREF- 22 RA3/AN3/VREF+ RA3 AN3 VREF+ 21 RA4/T0CKI RA4 T0CKI 28 RA5/AN4 RA5 AN4 27 Legend: TTL ST I P = = = = DS39762F-page 18 I/O O I TTL -- Analog Digital I/O. Ethernet LEDA indicator output. Analog Input 0. I/O O I TTL -- Analog Digital I/O. Ethernet LEDB indicator output. Analog Input 1. I/O I I TTL Analog Analog Digital I/O. Analog Input 2. A/D reference voltage (low) input. I/O I I TTL Analog Analog Digital I/O. Analog Input 3. A/D reference voltage (high) input. I/O I ST ST I/O I TTL Analog TTL compatible input Schmitt Trigger input with CMOS levels Input Power Digital I/O. Timer0 external clock input. Digital I/O. Analog Input 4. CMOS Analog O OD = = = = CMOS compatible input or output Analog input Output Open-Drain (no P diode to VDD) 2011 Microchip Technology Inc. PIC18F97J60 FAMILY TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0/FLT0 RB0 INT0 FLT0 3 RB1/INT1 RB1 INT1 4 RB2/INT2 RB2 INT2 5 RB3/INT3 RB3 INT3 6 RB4/KBI0 RB4 KBI0 44 RB5/KBI1 RB5 KBI1 43 RB6/KBI2/PGC RB6 KBI2 PGC 42 RB7/KBI3/PGD RB7 KBI3 PGD 37 Legend: TTL ST I P = = = = I/O I I TTL ST ST Digital I/O. External Interrupt 0. Enhanced PWM Fault input (ECCP modules); enabled in software. I/O I TTL ST Digital I/O. External Interrupt 1. I/O I TTL ST Digital I/O. External Interrupt 2. I/O I TTL ST Digital I/O. External Interrupt 3. I/O I TTL TTL Digital I/O. Interrupt-on-change pin. I/O I TTL TTL Digital I/O. Interrupt-on-change pin. I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSPTM programming clock pin. I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin. TTL compatible input Schmitt Trigger input with CMOS levels Input Power 2011 Microchip Technology Inc. CMOS Analog O OD = = = = CMOS compatible input or output Analog input Output Open-Drain (no P diode to VDD) DS39762F-page 19 PIC18F97J60 FAMILY TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI RC0 T1OSO T13CKI 30 RC1/T1OSI/ECCP2/P2A RC1 T1OSI ECCP2 P2A 29 RC2/ECCP1/P1A RC2 ECCP1 P1A 33 RC3/SCK1/SCL1 RC3 SCK1 SCL1 34 RC4/SDI1/SDA1 RC4 SDI1 SDA1 35 RC5/SDO1 RC5 SDO1 36 RC6/TX1/CK1 RC6 TX1 CK1 31 RC7/RX1/DT1 RC7 RX1 DT1 32 Legend: TTL ST I P = = = = DS39762F-page 20 I/O O I ST -- ST I/O I I/O O ST CMOS ST -- Digital I/O. Timer1 oscillator input. Capture 2 input/Compare 2 output/PWM2 output. ECCP2 PWM Output A. I/O I/O O ST ST -- Digital I/O. Capture 1 input/Compare 1 output/PWM1 output. ECCP1 PWM Output A. I/O I/O I/O ST ST ST Digital I/O. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2CTM mode. I/O I I/O ST ST ST Digital I/O. SPI data in. I2C data I/O. I/O O ST -- Digital I/O. SPI data out. I/O O I/O ST -- ST Digital I/O. EUSART1 asynchronous transmit. EUSART1 synchronous clock (see related RX1/DT1 pin). I/O I I/O ST ST ST Digital I/O. EUSART1 asynchronous receive. EUSART1 synchronous data (see related TX1/CK1 pin). TTL compatible input Schmitt Trigger input with CMOS levels Input Power Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input. CMOS Analog O OD = = = = CMOS compatible input or output Analog input Output Open-Drain (no P diode to VDD) 2011 Microchip Technology Inc. PIC18F97J60 FAMILY TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTD is a bidirectional I/O port. RD0/P1B RD0 P1B 60 RD1/ECCP3/P3A RD1 ECCP3 P3A 59 RD2/CCP4/P3D RD2 CCP4 P3D 58 Legend: TTL ST I P = = = = I/O O ST -- Digital I/O. ECCP1 PWM Output B. I/O I/O O ST ST -- Digital I/O. Capture 3 input/Compare 3 output/PWM3 output. ECCP3 PWM Output A. I/O I/O O ST ST -- Digital I/O. Capture 4 input/Compare 4 output/PWM4 output. CCP4 PWM Output D. TTL compatible input Schmitt Trigger input with CMOS levels Input Power 2011 Microchip Technology Inc. CMOS Analog O OD = = = = CMOS compatible input or output Analog input Output Open-Drain (no P diode to VDD) DS39762F-page 21 PIC18F97J60 FAMILY TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTE is a bidirectional I/O port. RE0/P2D RE0 P2D 2 RE1/P2C RE1 P2C 1 RE2/P2B RE2 P2B 64 RE3/P3C RE3 P3C 63 RE4/P3B RE4 P3B 62 RE5/P1C RE5 P1C 61 Legend: TTL ST I P = = = = DS39762F-page 22 I/O O ST -- Digital I/O. ECCP2 PWM Output D. I/O O ST -- Digital I/O. ECCP2 PWM Output C. I/O O ST -- Digital I/O. ECCP2 PWM Output B. I/O O ST -- Digital I/O. ECCP3 PWM Output C. I/O O ST -- Digital I/O. ECCP3 PWM Output B. I/O O ST -- Digital I/O. ECCP1 PWM Output C. TTL compatible input Schmitt Trigger input with CMOS levels Input Power CMOS Analog O OD = = = = CMOS compatible input or output Analog input Output Open-Drain (no P diode to VDD) 2011 Microchip Technology Inc. PIC18F97J60 FAMILY TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTF is a bidirectional I/O port. RF1/AN6/C2OUT RF1 AN6 C2OUT 17 RF2/AN7/C1OUT RF2 AN7 C1OUT 16 RF3/AN8 RF3 AN8 15 RF4/AN9 RF4 AN9 14 RF5/AN10/CVREF RF5 AN10 CVREF 13 RF6/AN11 RF6 AN11 12 RF7/SS1 RF7 SS1 11 Legend: TTL ST I P = = = = I/O I O ST Analog -- Digital I/O. Analog Input 6. Comparator 2 output. I/O I O ST Analog -- Digital I/O. Analog Input 7. Comparator 1 output. I/O I ST Analog Digital I/O. Analog Input 8. I/O I ST Analog Digital I/O. Analog Input 9. I/O I O ST Analog -- Digital I/O. Analog Input 10. Comparator reference voltage output. I/O I ST Analog Digital I/O. Analog Input 11. I/O I ST TTL TTL compatible input Schmitt Trigger input with CMOS levels Input Power 2011 Microchip Technology Inc. Digital I/O. SPI slave select input. CMOS Analog O OD = = = = CMOS compatible input or output Analog input Output Open-Drain (no P diode to VDD) DS39762F-page 23 PIC18F97J60 FAMILY TABLE 1-4: PIC18F66J60/66J65/67J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTG is a bidirectional I/O port. 8 RG4/CCP5/P1D RG4 CCP5 P1D I/O I/O O ST ST -- Digital I/O. Capture 5 input/Compare 5 output/PWM5 output. ECCP1 PWM Output D. VSS 9, 25, 41, 56 P -- Ground reference for logic and I/O pins. VDD 26, 38, 57 P -- Positive supply for peripheral digital logic and I/O pins. AVSS 20 P -- Ground reference for analog modules. AVDD 19 P -- Positive supply for analog modules. ENVREG 18 I ST Enable for on-chip voltage regulator. VDDCORE/VCAP VDDCORE 10 P -- VCAP P -- Core logic power or external filter capacitor connection. Positive supply for microcontroller core logic (regulator disabled). External filter capacitor connection (regulator enabled). P -- Ground reference for Ethernet PHY PLL. VSSPLL 55 VDDPLL 54 P -- Positive 3.3V supply for Ethernet PHY PLL. VSSTX 52 P -- Ground reference for Ethernet PHY transmit subsystem. VDDTX 49 P -- Positive 3.3V supply for Ethernet PHY transmit subsystem. VSSRX 45 P -- Ground reference for Ethernet PHY receive subsystem. VDDRX 48 P -- Positive 3.3V supply for Ethernet PHY receive subsystem. RBIAS 53 I TPOUT+ 51 O TPOUT- 50 O TPIN+ 47 I Analog Ethernet differential signal input. 46 I Analog Ethernet differential signal input. TPINLegend: TTL ST I P = = = = DS39762F-page 24 Analog Bias current for Ethernet PHY. Must be tied to VSS via a resistor; see Section 19.0 "Ethernet Module" for specification. -- Ethernet differential signal output. -- Ethernet differential signal output. TTL compatible input Schmitt Trigger input with CMOS levels Input Power CMOS Analog O OD = = = = CMOS compatible input or output Analog input Output Open-Drain (no P diode to VDD) 2011 Microchip Technology Inc. PIC18F97J60 FAMILY TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS Pin Number TQFP Pin Type Buffer Type MCLR 9 I ST OSC1/CLKI OSC1 49 Pin Name I CLKI I OSC2/CLKO OSC2 Master Clear (Reset) input. This pin is an active-low Reset to the device. Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in internal RC mode; CMOS otherwise. CMOS External clock source input. Always associated with pin function, OSC1. (See related OSC2/CLKO pin.) ST 50 CLKO Description O -- O -- Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In Internal RC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. PORTA is a bidirectional I/O port. RA0/LEDA/AN0 RA0 LEDA AN0 30 RA1/LEDB/AN1 RA1 LEDB AN1 29 RA2/AN2/VREFRA2 AN2 VREF- 28 RA3/AN3/VREF+ RA3 AN3 VREF+ 27 RA4/T0CKI RA4 T0CKI 34 RA5/AN4 RA5 AN4 33 Legend: Note 1: 2: 3: 4: I/O O I TTL -- Analog Digital I/O. Ethernet LEDA indicator output. Analog Input 0. I/O O I TTL -- Analog Digital I/O. Ethernet LEDB indicator output. Analog Input 1. I/O I I TTL Analog Analog Digital I/O. Analog Input 2. A/D reference voltage (low) input. I/O I I TTL Analog Analog Digital I/O. Analog Input 3. A/D reference voltage (high) input. I/O I ST ST I/O I TTL Analog Digital I/O. Timer0 external clock input. Digital I/O. Analog Input 4. TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set. Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared. Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). 2011 Microchip Technology Inc. DS39762F-page 25 PIC18F97J60 FAMILY TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0/FLT0 RB0 INT0 FLT0 5 RB1/INT1 RB1 INT1 6 RB2/INT2 RB2 INT2 7 RB3/INT3 RB3 INT3 8 RB4/KBI0 RB4 KBI0 54 RB5/KBI1 RB5 KBI1 53 RB6/KBI2/PGC RB6 KBI2 PGC 52 RB7/KBI3/PGD RB7 KBI3 PGD 47 Legend: Note 1: 2: 3: 4: I/O I I TTL ST ST Digital I/O. External Interrupt 0. Enhanced PWM Fault input (ECCP modules); enabled in software. I/O I TTL ST Digital I/O. External Interrupt 1. I/O I TTL ST Digital I/O. External Interrupt 2. I/O I TTL ST Digital I/O. External Interrupt 3. I/O I TTL TTL Digital I/O. Interrupt-on-change pin. I/O I TTL TTL Digital I/O. Interrupt-on-change pin. I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSPTM programming clock pin. I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin. TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set. Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared. Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). DS39762F-page 26 2011 Microchip Technology Inc. PIC18F97J60 FAMILY TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI RC0 T1OSO T13CKI 36 RC1/T1OSI/ECCP2/P2A RC1 T1OSI ECCP2(1) P2A(1) 35 RC2/ECCP1/P1A RC2 ECCP1 P1A 43 RC3/SCK1/SCL1 RC3 SCK1 SCL1 44 RC4/SDI1/SDA1 RC4 SDI1 SDA1 45 RC5/SDO1 RC5 SDO1 46 RC6/TX1/CK1 RC6 TX1 CK1 37 RC7/RX1/DT1 RC7 RX1 DT1 38 Legend: Note 1: 2: 3: 4: I/O O I ST -- ST Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input. I/O I I/O O ST CMOS ST -- Digital I/O. Timer1 oscillator input. Capture 2 input/Compare 2 output/PWM2 output. ECCP2 PWM Output A. I/O I/O O ST ST -- Digital I/O. Capture 1 input/Compare 1 output/PWM1 output. ECCP1 PWM Output A. I/O I/O I/O ST ST ST Digital I/O. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2CTM mode. I/O I I/O ST ST ST Digital I/O. SPI data in. I2C data I/O. I/O O ST -- Digital I/O. SPI data out. I/O O I/O ST -- ST Digital I/O. EUSART1 asynchronous transmit. EUSART1 synchronous clock (see related RX1/DT1 pin). I/O I I/O ST ST ST Digital I/O. EUSART1 asynchronous receive. EUSART1 synchronous data (see related TX1/CK1 pin). TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set. Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared. Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). 2011 Microchip Technology Inc. DS39762F-page 27 PIC18F97J60 FAMILY TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTD is a bidirectional I/O port. RD0 72 I/O ST Digital I/O. RD1 69 I/O ST Digital I/O. RD2 68 I/O ST Digital I/O. PORTE is a bidirectional I/O port. RE0/P2D RE0 P2D 4 RE1/P2C RE1 P2C 3 RE2/P2B RE2 P2B 78 RE3/P3C RE3 P3C(2) 77 RE4/P3B RE4 P3B(2) 76 RE5/P1C RE5 P1C(2) 75 RE6/P1B RE6 P1B(2) 74 RE7/ECCP2/P2A RE7 ECCP2(3) P2A(3) 73 Legend: Note 1: 2: 3: 4: I/O O ST -- Digital I/O. ECCP2 PWM Output D. I/O O ST -- Digital I/O. ECCP2 PWM Output C. I/O O ST -- Digital I/O. ECCP2 PWM Output B. I/O O ST -- Digital I/O. ECCP3 PWM Output C. I/O O ST -- Digital I/O. ECCP3 PWM Output B. I/O O ST -- Digital I/O. ECCP1 PWM Output C. I/O O ST -- Digital I/O. ECCP1 PWM Output B. I/O I/O O ST ST -- Digital I/O. Capture 2 input/Compare 2 output/PWM2 output. ECCP2 PWM Output A. TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set. Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared. Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). DS39762F-page 28 2011 Microchip Technology Inc. PIC18F97J60 FAMILY TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTF is a bidirectional I/O port. RF1/AN6/C2OUT RF1 AN6 C2OUT 23 RF2/AN7/C1OUT RF2 AN7 C1OUT 18 RF3/AN8 RF3 AN8 17 RF4/AN9 RF4 AN9 16 RF5/AN10/CVREF RF5 AN10 CVREF 15 RF6/AN11 RF6 AN11 14 RF7/SS1 RF7 SS1 13 Legend: Note 1: 2: 3: 4: I/O I O ST Analog -- Digital I/O. Analog Input 6. Comparator 2 output. I/O I O ST Analog -- Digital I/O. Analog Input 7. Comparator 1 output. I/O I ST Analog Digital I/O. Analog Input 8. I/O I ST Analog Digital I/O. Analog Input 9. I/O I O ST Analog -- Digital I/O. Analog Input 10. Comparator reference voltage output. I/O I ST Analog Digital I/O. Analog Input 11. I/O I ST TTL Digital I/O. SPI slave select input. TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set. Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared. Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). 2011 Microchip Technology Inc. DS39762F-page 29 PIC18F97J60 FAMILY TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTG is a bidirectional I/O port. RG0/ECCP3/P3A RG0 ECCP3 P3A 56 RG1/TX2/CK2 RG1 TX2 CK2 55 RG2/RX2/DT2 RG2 RX2 DT2 42 RG3/CCP4/P3D RG3 CCP4 P3D 41 RG4/CCP5/P1D RG4 CCP5 P1D 10 Legend: Note 1: 2: 3: 4: I/O I/O O ST ST -- Digital I/O. Capture 3 input/Compare 3 output/PWM3 output. ECCP3 PWM Output A. I/O O I/O ST -- ST Digital I/O. EUSART2 asynchronous transmit. EUSART2 synchronous clock (see related RX2/DT2 pin). I/O I I/O ST ST ST Digital I/O. EUSART2 asynchronous receive. EUSART2 synchronous data (see related TX2/CK2 pin). I/O I/O O ST ST -- Digital I/O. Capture 4 input/Compare 4 output/PWM4 output. ECCP3 PWM Output D. I/O I/O O ST ST -- Digital I/O. Capture 5 input/Compare 5 output/PWM5 output. ECCP1 PWM Output D. TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set. Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared. Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). DS39762F-page 30 2011 Microchip Technology Inc. PIC18F97J60 FAMILY TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTH is a bidirectional I/O port. RH0 79 I/O ST Digital I/O. RH1 80 I/O ST Digital I/O. RH2 1 I/O ST Digital I/O. RH3 2 I/O ST Digital I/O. RH4/AN12/P3C RH4 AN12 P3C(4) 22 I/O I O ST Analog -- Digital I/O. Analog Input 12. ECCP3 PWM Output C. RH5/AN13/P3B RH5 AN13 P3B(4) 21 I/O I O ST Analog -- Digital I/O. Analog Input 13. ECCP3 PWM Output B. RH6/AN14/P1C RH6 AN14 P1C(4) 20 I/O I O ST Analog -- Digital I/O. Analog Input 14. ECCP1 PWM Output C. RH7/AN15/P1B RH7 AN15 P1B(4) 19 I/O I O ST Analog -- Digital I/O. Analog Input 15. ECCP1 PWM Output B. Legend: Note 1: 2: 3: 4: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set. Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared. Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). 2011 Microchip Technology Inc. DS39762F-page 31 PIC18F97J60 FAMILY TABLE 1-5: PIC18F86J60/86J65/87J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTJ is a bidirectional I/O port. RJ4 39 I/O ST RJ5 40 I/O ST VSS 11, 31, 51, 70 P -- Ground reference for logic and I/O pins. VDD 32, 48, 71 P -- Positive supply for peripheral digital logic and I/O pins. AVSS 26 P -- Ground reference for analog modules. AVDD 25 P -- Positive supply for analog modules. ENVREG 24 I ST Enable for on-chip voltage regulator. VDDCORE/VCAP VDDCORE 12 P -- P -- Core logic power or external filter capacitor connection. Positive supply for microcontroller core logic (regulator disabled). External filter capacitor connection (regulator enabled). P -- Ground reference for Ethernet PHY PLL. VCAP Digital I/O. Digital I/O VSSPLL 67 VDDPLL 66 P -- Positive 3.3V supply for Ethernet PHY PLL. VSSTX 64 P -- Ground reference for Ethernet PHY transmit subsystem. VDDTX 61 P -- Positive 3.3V supply for Ethernet PHY transmit subsystem. VSSRX 57 P -- Ground reference for Ethernet PHY receive subsystem. VDDRX 60 P -- Positive 3.3V supply for Ethernet PHY receive subsystem. RBIAS 65 I TPOUT+ 63 O TPOUT- 62 O TPIN+ 59 I Analog Ethernet differential signal input. 58 I Analog Ethernet differential signal input. TPINLegend: Note 1: 2: 3: 4: Analog Bias current for Ethernet PHY. Must be tied to VSS via a resistor; see Section 19.0 "Ethernet Module" for specification. -- Ethernet differential signal output. -- Ethernet differential signal output. TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set. Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared. Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). DS39762F-page 32 2011 Microchip Technology Inc. PIC18F97J60 FAMILY TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS Pin Number TQFP Pin Type Buffer Type MCLR 13 I ST OSC1/CLKI OSC1 63 Pin Name I CLKI I OSC2/CLKO OSC2 Master Clear (Reset) input. This pin is an active-low Reset to the device. Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in internal RC mode; CMOS otherwise. CMOS External clock source input. Always associated with pin function, OSC1. (See related OSC2/CLKO pin.) ST 64 CLKO Description O -- O -- Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In Internal RC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. PORTA is a bidirectional I/O port. RA0/LEDA/AN0 RA0 LEDA AN0 35 RA1/LEDB/AN1 RA1 LEDB AN1 34 RA2/AN2/VREFRA2 AN2 VREF- 33 RA3/AN3/VREF+ RA3 AN3 VREF+ 32 RA4/T0CKI RA4 T0CKI 42 RA5/AN4 RA5 AN4 41 Legend: Note 1: 2: 3: 4: 5: I/O O I TTL -- Analog Digital I/O. Ethernet LEDA indicator output. Analog Input 0. I/O O I TTL -- Analog Digital I/O. Ethernet LEDB indicator output. Analog Input 1. I/O I I TTL Analog Analog Digital I/O. Analog Input 2. A/D reference voltage (low) input. I/O I I TTL Analog Analog Digital I/O. Analog Input 3. A/D reference voltage (high) input. I/O I ST ST I/O I TTL Analog Digital I/O. Timer0 external clock input. Digital I/O. Analog Input 4. TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode). Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX Configuration bit is set). Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode). Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). 2011 Microchip Technology Inc. DS39762F-page 33 PIC18F97J60 FAMILY TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0/FLT0 RB0 INT0 FLT0 5 RB1/INT1 RB1 INT1 6 RB2/INT2 RB2 INT2 7 RB3/INT3/ECCP2/P2A RB3 INT3 ECCP2(1) P2A(1) 8 RB4/KBI0 RB4 KBI0 69 RB5/KBI1 RB5 KBI1 68 RB6/KBI2/PGC RB6 KBI2 PGC 67 RB7/KBI3/PGD RB7 KBI3 PGD 57 Legend: Note 1: 2: 3: 4: 5: I/O I I TTL ST ST Digital I/O. External Interrupt 0. Enhanced PWM Fault input (ECCP modules); enabled in software. I/O I TTL ST Digital I/O. External Interrupt 1. I/O I TTL ST Digital I/O. External Interrupt 2. I/O I I/O O TTL ST ST -- Digital I/O. External Interrupt 3. Capture 2 input/Compare 2 output/PWM2 output. ECCP2 PWM Output A. I/O I TTL TTL Digital I/O. Interrupt-on-change pin. I/O I TTL TTL Digital I/O. Interrupt-on-change pin. I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSPTM programming clock pin. I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin. TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode). Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX Configuration bit is set). Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode). Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). DS39762F-page 34 2011 Microchip Technology Inc. PIC18F97J60 FAMILY TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI RC0 T1OSO T13CKI 44 RC1/T1OSI/ECCP2/P2A RC1 T1OSI ECCP2(2) P2A(2) 43 RC2/ECCP1/P1A RC2 ECCP1 P1A 53 RC3/SCK1/SCL1 RC3 SCK1 SCL1 54 RC4/SDI1/SDA1 RC4 SDI1 SDA1 55 RC5/SDO1 RC5 SDO1 56 RC6/TX1/CK1 RC6 TX1 CK1 45 RC7/RX1/DT1 RC7 RX1 DT1 46 Legend: Note 1: 2: 3: 4: 5: I/O O I ST -- ST Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input. I/O I I/O O ST CMOS ST -- Digital I/O. Timer1 oscillator input. Capture 2 input/Compare 2 output/PWM2 output. ECCP2 PWM Output A. I/O I/O O ST ST -- Digital I/O. Capture 1 input/Compare 1 output/PWM1 output. ECCP1 PWM Output A. I/O I/O I/O ST ST ST Digital I/O. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2CTM mode. I/O I I/O ST ST ST Digital I/O. SPI data in. I2C data I/O. I/O O ST -- Digital I/O. SPI data out. I/O O I/O ST -- ST Digital I/O. EUSART1 asynchronous transmit. EUSART1 synchronous clock (see related RX1/DT1 pin). I/O I I/O ST ST ST Digital I/O. EUSART1 asynchronous receive. EUSART1 synchronous data (see related TX1/CK1 pin). TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode). Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX Configuration bit is set). Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode). Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). 2011 Microchip Technology Inc. DS39762F-page 35 PIC18F97J60 FAMILY TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTD is a bidirectional I/O port. RD0/AD0/PSP0 RD0 AD0 PSP0 92 RD1/AD1/PSP1 RD1 AD1 PSP1 91 RD2/AD2/PSP2 RD2 AD2 PSP2 90 RD3/AD3/PSP3 RD3 AD3 PSP3 89 RD4/AD4/PSP4/SDO2 RD4 AD4 PSP4 SDO2 88 RD5/AD5/PSP5/ SDI2/SDA2 RD5 AD5 PSP5 SDI2 SDA2 87 RD6/AD6/PSP6/ SCK2/SCL2 RD6 AD6 PSP6 SCK2 SCL2 84 RD7/AD7/PSP7/SS2 RD7 AD7 PSP7 SS2 83 Legend: Note 1: 2: 3: 4: 5: I/O I/O I/O ST TTL TTL Digital I/O. External Memory Address/Data 0. Parallel Slave Port data. I/O I/O I/O ST TTL TTL Digital I/O. External Memory Address/Data 1. Parallel Slave Port data. I/O I/O I/O ST TTL TTL Digital I/O. External Memory Address/Data 2. Parallel Slave Port data. I/O I/O I/O ST TTL TTL Digital I/O. External Memory Address/Data 3. Parallel Slave Port data. I/O I/O I/O O ST TTL TTL -- Digital I/O. External Memory Address/Data 4. Parallel Slave Port data. SPI data out. I/O I/O I/O I I/O ST TTL TTL ST ST Digital I/O. External Memory Address/Data 5. Parallel Slave Port data. SPI data in. I2CTM data I/O. I/O I/O I/O I/O I/O ST TTL TTL ST ST Digital I/O. External Memory Address/Data 6. Parallel Slave Port data. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2CTM mode. I/O I/O I/O I ST TTL TTL TTL Digital I/O. External Memory Address/Data 7. Parallel Slave Port data. SPI slave select input. TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode). Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX Configuration bit is set). Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode). Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). DS39762F-page 36 2011 Microchip Technology Inc. PIC18F97J60 FAMILY TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTE is a bidirectional I/O port. RE0/AD8/RD/P2D RE0 AD8 RD P2D 4 RE1/AD9/WR/P2C RE1 AD9 WR P2C 3 RE2/AD10/CS/P2B RE2 AD10 CS P2B 98 RE3/AD11/P3C RE3 AD11 P3C(3) 97 RE4/AD12/P3B RE4 AD12 P3B(3) 96 RE5/AD13/P1C RE5 AD13 P1C(3) 95 RE6/AD14/P1B RE6 AD14 P1B(3) 94 RE7/AD15/ECCP2/P2A RE7 AD15 ECCP2(4) P2A(4) 93 Legend: Note 1: 2: 3: 4: 5: I/O I/O I O ST TTL TTL -- Digital I/O. External Memory Address/Data 8. Read control for Parallel Slave Port. ECCP2 PWM Output D. I/O I/O I O ST TTL TTL -- Digital I/O. External Memory Address/Data 9. Write control for Parallel Slave Port. ECCP2 PWM Output C. I/O I/O I O ST TTL TTL -- Digital I/O. External Memory Address/Data 10. Chip select control for Parallel Slave Port. ECCP2 PWM Output B. I/O I/O O ST TTL -- Digital I/O. External Memory Address/Data 11. ECCP3 PWM Output C. I/O I/O O ST TTL -- Digital I/O. External Memory Address/Data 12. ECCP3 PWM Output B. I/O I/O O ST TTL -- Digital I/O. External Memory Address/Data 13. ECCP1 PWM Output C. I/O I/O O ST TTL -- Digital I/O. External Memory Address/Data 14. ECCP1 PWM Output B. I/O I/O I/O O ST TTL ST -- Digital I/O. External Memory Address/Data 15. Capture 2 input/Compare 2 output/PWM2 output. ECCP2 PWM Output A. TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode). Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX Configuration bit is set). Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode). Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). 2011 Microchip Technology Inc. DS39762F-page 37 PIC18F97J60 FAMILY TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTF is a bidirectional I/O port. RF0/AN5 RF0 AN5 12 RF1/AN6/C2OUT RF1 AN6 C2OUT 28 RF2/AN7/C1OUT RF2 AN7 C1OUT 23 RF3/AN8 RF3 AN8 22 RF4/AN9 RF4 AN9 21 RF5/AN10/CVREF RF5 AN10 CVREF 20 RF6/AN11 RF6 AN11 19 RF7/SS1 RF7 SS1 18 Legend: Note 1: 2: 3: 4: 5: I/O I ST Analog Digital I/O. Analog Input 5. I/O I O ST Analog -- Digital I/O. Analog Input 6. Comparator 2 output. I/O I O ST Analog -- Digital I/O. Analog Input 7. Comparator 1 output. I/O I ST Analog Digital I/O. Analog Input 8. I/O I ST Analog Digital I/O. Analog Input 9. I/O I O ST Analog -- Digital I/O. Analog Input 10. Comparator reference voltage output. I/O I ST Analog Digital I/O. Analog Input 11. I/O I ST TTL Digital I/O. SPI slave select input. TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode). Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX Configuration bit is set). Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode). Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). DS39762F-page 38 2011 Microchip Technology Inc. PIC18F97J60 FAMILY TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTG is a bidirectional I/O port. RG0/ECCP3/P3A RG0 ECCP3 P3A 71 RG1/TX2/CK2 RG1 TX2 CK2 70 RG2/RX2/DT2 RG2 RX2 DT2 52 RG3/CCP4/P3D RG3 CCP4 P3D 51 RG4/CCP5/P1D RG4 CCP5 P1D 14 I/O I/O O ST ST -- Digital I/O. Capture 3 input/Compare 3 output/PWM3 output. ECCP3 PWM Output A. I/O O I/O ST -- ST Digital I/O. EUSART2 asynchronous transmit. EUSART2 synchronous clock (see related RX2/DT2 pin). I/O I I/O ST ST ST Digital I/O. EUSART2 asynchronous receive. EUSART2 synchronous data (see related TX2/CK2 pin). I/O I/O O ST ST -- Digital I/O. Capture 4 input/Compare 4 output/PWM4 output. ECCP3 PWM Output D. I/O I/O O ST ST -- Digital I/O. Capture 5 input/Compare 5 output/PWM5 output. ECCP1 PWM Output D. RG5 11 I/O ST Digital I/O. RG6 10 I/O ST Digital I/O. RG7 38 I/O ST Digital I/O. Legend: Note 1: 2: 3: 4: 5: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode). Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX Configuration bit is set). Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode). Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). 2011 Microchip Technology Inc. DS39762F-page 39 PIC18F97J60 FAMILY TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTH is a bidirectional I/O port. RH0/A16 RH0 A16 99 RH1/A17 RH1 A17 100 RH2/A18 RH2 A18 1 RH3/A19 RH3 A19 2 RH4/AN12/P3C RH4 AN12 P3C(5) 27 RH5/AN13/P3B RH5 AN13 P3B(5) 26 RH6/AN14/P1C RH6 AN14 P1C(5) 25 RH7/AN15/P1B RH7 AN15 P1B(5) 24 Legend: Note 1: 2: 3: 4: 5: I/O O ST -- Digital I/O. External Memory Address 16. I/O O ST -- Digital I/O. External Memory Address 17. I/O O ST -- Digital I/O. External Memory Address 18. I/O O ST -- Digital I/O. External Memory Address 19. I/O I O ST Analog -- Digital I/O. Analog Input 12. ECCP3 PWM Output C. I/O I O ST Analog -- Digital I/O. Analog Input 13. ECCP3 PWM Output B. I/O I O ST Analog -- Digital I/O. Analog Input 14. ECCP1 PWM Output C. I/O I O ST Analog -- Digital I/O. Analog Input 15. ECCP1 PWM Output B. TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode). Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX Configuration bit is set). Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode). Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). DS39762F-page 40 2011 Microchip Technology Inc. PIC18F97J60 FAMILY TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP Pin Type Buffer Type Description PORTJ is a bidirectional I/O port. RJ0/ALE RJ0 ALE 49 RJ1/OE RJ1 OE 50 RJ2/WRL RJ2 WRL 66 RJ3/WRH RJ3 WRH 61 RJ4/BA0 RJ4 BA0 47 RJ5/CE RJ5 CE 48 RJ6/LB RJ6 LB 58 RJ7/UB RJ7 UB 39 Legend: Note 1: 2: 3: 4: 5: I/O O ST -- Digital I/O. External memory address latch enable. I/O O ST -- Digital I/O. External memory output enable. I/O O ST -- Digital I/O. External memory write low control. I/O O ST -- Digital I/O. External memory write high control. I/O O ST -- Digital I/O. External Memory Byte Address 0 control. I/O O ST -- Digital I/O External memory chip enable control. I/O O ST -- Digital I/O. External memory low byte control. I/O O ST -- Digital I/O. External memory high byte control. TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode). Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX Configuration bit is set). Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode). Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). 2011 Microchip Technology Inc. DS39762F-page 41 PIC18F97J60 FAMILY TABLE 1-6: PIC18F96J60/96J65/97J60 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number TQFP Pin Type Buffer Type NC 9 -- -- No connect. VSS 15, 36, 40, 60, 65, 85 P -- Ground reference for logic and I/O pins. VDD 17, 37, 59, 62, 86 P -- Positive supply for peripheral digital logic and I/O pins. AVSS 31 P -- Ground reference for analog modules. AVDD 30 P -- Positive supply for analog modules. ENVREG 29 I ST Enable for on-chip voltage regulator. VDDCORE/VCAP VDDCORE 16 P -- P -- Core logic power or external filter capacitor connection. Positive supply for microcontroller core logic (regulator disabled). External filter capacitor connection (regulator enabled). P -- Ground reference for Ethernet PHY PLL. Pin Name VCAP Description VSSPLL 82 VDDPLL 81 P -- Positive 3.3V supply for Ethernet PHY PLL. VSSTX 79 P -- Ground reference for Ethernet PHY transmit subsystem. VDDTX 76 P -- Positive 3.3V supply for Ethernet PHY transmit subsystem. VSSRX 72 P -- Ground reference for Ethernet PHY receive subsystem. VDDRX 75 P -- Positive 3.3V supply for Ethernet PHY receive subsystem. RBIAS 80 I TPOUT+ 78 O TPOUT- 77 O TPIN+ 74 I Analog Ethernet differential signal input. 73 I Analog Ethernet differential signal input. TPINLegend: Note 1: 2: 3: 4: 5: Analog Bias current for Ethernet PHY. Must be tied to VSS via a resistor; see Section 19.0 "Ethernet Module" for specification. -- Ethernet differential signal output. -- Ethernet differential signal output. TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode). Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX Configuration bit is set). Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Microcontroller mode). Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). DS39762F-page 42 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 2.0 GUIDELINES FOR GETTING STARTED WITH PIC18FJ MICROCONTROLLERS FIGURE 2-1: RECOMMENDED MINIMUM CONNECTIONS C2(2) * All VDD and VSS pins (see Section 2.2 "Power Supply Pins") * All AVDD and AVSS pins, regardless of whether or not the analog device features are used (see Section 2.2 "Power Supply Pins") * MCLR pin (see Section 2.3 "Master Clear (MCLR) Pin") * ENVREG (if implemented) and VCAP/VDDCORE pins (see Section 2.4 "Voltage Regulator Pins (ENVREG and VCAP/VDDCORE)") VCAP/VDDCORE C1 VSS VDD VDD VSS C3(2) C6(2) C5(2) C4(2) Key (all values are recommendations): * PGC/PGD pins used for In-Circuit Serial ProgrammingTM (ICSPTM) and debugging purposes (see Section 2.5 "ICSP Pins") * OSCI and OSCO pins when an external oscillator source is used (see Section 2.6 "External Oscillator Pins") R1: 10 k Note: C7 PIC18FXXJXX C1 through C6: 0.1 F, 20V ceramic * VREF+/VREF- pins are used when external voltage reference for analog modules is implemented (1) (1) ENVREG MCLR These pins must also be connected if they are being used in the end application: Additionally, the following pins may be required: VSS VDD R2 VSS The following pins must always be connected: R1 VDD Getting started with the PIC18F97J60 family family of 8-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. VDD AVSS Basic Connection Requirements AVDD 2.1 C7: 10 F, 6.3V or greater, tantalum or ceramic R2: 100 to 470 Note 1: 2: See Section 2.4 "Voltage Regulator Pins (ENVREG and VCAP/VDDCORE)" for explanation of ENVREG pin connections. The example shown is for a PIC18F device with five VDD/VSS and AVDD/AVSS pairs. Other devices may have more or less pairs; adjust the number of decoupling capacitors appropriately. The AVDD and AVSS pins must always be connected, regardless of whether any of the analog modules are being used. The minimum mandatory connections are shown in Figure 2-1. 2011 Microchip Technology Inc. DS39762F-page 43 PIC18F97J60 FAMILY 2.2 2.2.1 Power Supply Pins DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS, is required. Consider the following criteria when using decoupling capacitors: * Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device, with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended. * Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is no greater than 0.25 inch (6 mm). * Handling high-frequency noise: If the board is experiencing high-frequency noise (upward of tens of MHz), add a second ceramic type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 F to 0.001 F. Place this second capacitor next to each primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible (e.g., 0.1 F in parallel with 0.001 F). * Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum, thereby reducing PCB trace inductance. 2.2.2 TANK CAPACITORS On boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for integrated circuits, including microcontrollers, to supply a local power source. The value of the tank capacitor should be determined based on the trace resistance that connects the power supply source to the device, and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7 F to 47 F. DS39762F-page 44 2.3 Master Clear (MCLR) Pin The MCLR pin provides two specific device functions: Device Reset, and Device Programming and Debugging. If programming and debugging are not required in the end application, a direct connection to VDD may be all that is required. The addition of other components, to help increase the application's resistance to spurious Resets from voltage sags, may be beneficial. A typical configuration is shown in Figure 2-1. Other circuit designs may be implemented, depending on the application's requirements. During programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R1 and C1 will need to be adjusted based on the application and PCB requirements. For example, it is recommended that the capacitor, C1, be isolated from the MCLR pin during programming and debugging operations by using a jumper (Figure 2-2). The jumper is replaced for normal run-time operations. Any components associated with the MCLR pin should be placed within 0.25 inch (6 mm) of the pin. FIGURE 2-2: EXAMPLE OF MCLR PIN CONNECTIONS VDD R1 R2 JP MCLR PIC18FXXJXX C1 Note 1: R1 10 k is recommended. A suggested starting value is 10 k. Ensure that the MCLR pin VIH and VIL specifications are met. 2: R2 470 will limit any current flowing into MCLR from the external capacitor, C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met. 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 2.4 Voltage Regulator Pins (ENVREG and VCAP/VDDCORE) The on-chip voltage regulator enable pin, ENVREG, must always be connected directly to either a supply voltage or to ground. Tying ENVREG to VDD enables the regulator, while tying it to ground disables the regulator. Refer to Section 25.3 "On-Chip Voltage Regulator" for details on connecting and using the on-chip regulator. Note that the "LF" versions of some low pin count PIC18FJ parts (e.g., the PIC18LF45J10) do not have the ENVREG pin. These devices are provided with the voltage regulator permanently disabled; they must always be provided with a supply voltage on the VDDCORE pin. FIGURE 2-3: When the regulator is enabled, a low-ESR (< 5) capacitor is required on the VCAP/VDDCORE pin to stabilize the voltage regulator output voltage. The VCAP/VDDCORE pin must not be connected to VDD and must use a capacitor of 10 F connected to ground. The type can be ceramic or tantalum. Suitable examples of capacitors are shown in Table 2-1. Capacitors with equivalent specifications can be used. FREQUENCY vs. ESR PERFORMANCE FOR SUGGESTED VCAP 10 ESR () 1 0.1 Designers may use Figure 2-3 to evaluate ESR equivalence of candidate devices. 0.01 It is recommended that the trace length not exceed 0.25 inch (6 mm). Refer to 28.0 "Electrical Characteristics" for additional information. 0.001 0.01 Note: When the regulator is disabled, the VCAP/VDDCORE pin must be tied to a voltage supply at the VDDCORE level. Refer to 28.0 "Electrical Characteristics" for information on VDD and VDDCORE. 0.1 1 10 100 Frequency (MHz) 1000 10,000 Typical data measurement at 25C, 0V DC bias. . TABLE 2-1: SUITABLE CAPACITOR EQUIVALENTS Make Part # Nominal Capacitance Base Tolerance Rated Voltage Temp. Range TDK C3216X7R1C106K 10 F 10% 16V -55 to 125C TDK C3216X5R1C106K 10 F 10% 16V -55 to 85C Panasonic ECJ-3YX1C106K 10 F 10% 16V -55 to 125C Panasonic ECJ-4YB1C106K 10 F 10% 16V -55 to 85C Murata GRM32DR71C106KA01L 10 F 10% 16V -55 to 125C Murata GRM31CR61C106KC31L 10 F 10% 16V -55 to 85C 2011 Microchip Technology Inc. DS39762F-page 45 PIC18F97J60 FAMILY CONSIDERATIONS FOR CERAMIC CAPACITORS In recent years, large value, low-voltage, surface-mount ceramic capacitors have become very cost effective in sizes up to a few tens of microfarad. The low-ESR, small physical size and other properties make ceramic capacitors very attractive in many types of applications. Ceramic capacitors are suitable for use with the VDDCORE voltage regulator of this microcontroller. However, some care is needed in selecting the capacitor to ensure that it maintains sufficient capacitance over the intended operating range of the application. Typical low-cost, 10 F ceramic capacitors are available in X5R, X7R and Y5V dielectric ratings (other types are also available, but are less common). The initial tolerance specifications for these types of capacitors are often specified as 10% to 20% (X5R and X7R), or -20%/+80% (Y5V). However, the effective capacitance that these capacitors provide in an application circuit will also vary based on additional factors, such as the applied DC bias voltage and the temperature. The total in-circuit tolerance is, therefore, much wider than the initial tolerance specification. The X5R and X7R capacitors typically exhibit satisfactory temperature stability (ex: 15% over a wide temperature range, but consult the manufacturer's data sheets for exact specifications). However, Y5V capacitors typically have extreme temperature tolerance specifications of +22%/-82%. Due to the extreme temperature tolerance, a 10 F nominal rated Y5V type capacitor may not deliver enough total capacitance to meet minimum VDDCORE voltage regulator stability and transient response requirements. Therefore, Y5V capacitors are not recommended for use with the VDDCORE regulator if the application must operate over a wide temperature range. In addition to temperature tolerance, the effective capacitance of large value ceramic capacitors can vary substantially, based on the amount of DC voltage applied to the capacitor. This effect can be very significant, but is often overlooked or is not always documented. A typical DC bias voltage vs. capacitance graph for X7R type and Y5V type capacitors is shown in Figure 2-4. FIGURE 2-4: Capacitance Change (%) 2.4.1 DC BIAS VOLTAGE vs. CAPACITANCE CHARACTERISTICS 10 0 -10 16V Capacitor -20 -30 -40 10V Capacitor -50 -60 -70 6.3V Capacitor -80 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 DC Bias Voltage (VDC) When selecting a ceramic capacitor to be used with the VDDCORE voltage regulator, it is suggested to select a high-voltage rating, so that the operating voltage is a small percentage of the maximum rated capacitor voltage. For example, choose a ceramic capacitor rated at 16V for the 2.5V VDDCORE voltage. Suggested capacitors are shown in Table 2-1. 2.5 ICSP Pins The PGC and PGD pins are used for In-Circuit Serial ProgrammingTM (ICSPTM) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of ohms, not to exceed 100. Pull-up resistors, series diodes, and capacitors on the PGC and PGD pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits, and pin input voltage high (VIH) and input low (VIL) requirements. For device emulation, ensure that the "Communication Channel Select" (i.e., PGCx/PGDx pins), programmed into the device, matches the physical connections for the ICSP to the Microchip debugger/emulator tool. For more information on available Microchip development tools connection requirements, refer to Section 27.0 "Development Support". DS39762F-page 46 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 2.6 External Oscillator Pins FIGURE 2-5: Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 3.0 "Oscillator Configurations" for details). The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0.5 inch (12 mm) between the circuit components and the pins. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate it from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. Single-Sided and In-Line Layouts: Copper Pour (tied to ground) For additional information and design guidance on oscillator circuits, please refer to these Microchip Application Notes, available at the corporate web site (www.microchip.com): * AN826, "Crystal Oscillator Basics and Crystal Selection for rfPICTM and PICmicro(R) Devices" * AN849, "Basic PICmicro(R) Oscillator Design" * AN943, "Practical PICmicro(R) Oscillator Analysis and Design" * AN949, "Making Your Oscillator Work" 2.7 Unused I/Os Primary Oscillator Crystal DEVICE PINS Primary Oscillator OSC1 C1 OSC2 GND C2 T1OSO T1OS I Timer1 Oscillator Crystal Layout suggestions are shown in Figure 2-5. In-line packages may be handled with a single-sided layout that completely encompasses the oscillator pins. With fine-pitch packages, it is not always possible to completely surround the pins and components. A suitable solution is to tie the broken guard sections to a mirrored ground layer. In all cases, the guard trace(s) must be returned to ground. In planning the application's routing and I/O assignments, ensure that adjacent port pins, and other signals in close proximity to the oscillator, are benign (i.e., free of high frequencies, short rise and fall times, and other similar noise). SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT T1 Oscillator: C1 T1 Oscillator: C2 Fine-Pitch (Dual-Sided) Layouts: Top Layer Copper Pour (tied to ground) Bottom Layer Copper Pour (tied to ground) OSCO C2 Oscillator Crystal GND C1 OSCI DEVICE PINS Unused I/O pins should be configured as outputs and driven to a logic low state. Alternatively, connect a 1 k to 10 k resistor to VSS on unused pins and drive the output to logic low. 2011 Microchip Technology Inc. DS39762F-page 47 PIC18F97J60 FAMILY NOTES: DS39762F-page 48 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 3.0 3.1 OSCILLATOR CONFIGURATIONS 3.2 Overview 1. 2. HS HSPLL 3. 4. EC ECPLL 5. INTRC Oscillator Types The PIC18F97J60 family of devices can be operated in five different oscillator modes: Devices in the PIC18F97J60 family incorporate an oscillator and microcontroller clock system that differs from standard PIC18FXXJXX devices. The addition of the Ethernet module, with its requirement for a stable 25 MHz clock source, makes it necessary to provide a primary oscillator that can provide this frequency as well as a range of different microcontroller clock speeds. An overview of the oscillator structure is shown in Figure 3-1. 3.2.1 High-Speed Crystal/Resonator High-Speed Crystal/Resonator with Software PLL Control External Clock with FOSC/4 Output External Clock with Software PLL Control Internal 31 kHz Oscillator OSCILLATOR CONTROL The oscillator mode is selected by programming the FOSC<2:0> Configuration bits. FOSC<1:0> bits select the default primary oscillator modes, while FOSC2 selects when INTRC may be invoked. Other oscillator features used in PIC18FXXJXX enhanced microcontrollers, such as the internal RC oscillator and clock switching, remain the same. They are discussed later in this chapter. The OSCCON register (Register 3-2) selects the Active Clock mode. It is primarily used in controlling clock switching in power-managed modes. Its use is discussed in Section 3.7.1 "Oscillator Control Register". The OSCTUNE register (Register 3-1) is used to select the system clock frequency from the primary oscillator source by selecting combinations of prescaler/postscaler settings and enabling the PLL. Its use is described in Section 3.6.1 "PLL Block". FIGURE 3-1: PIC18F97J60 FAMILY CLOCK DIAGRAM PIC18F97J60 Family Primary Oscillator Ethernet Clock OSC2 OSC1 PLL Prescaler 5x PLL T1OSO T1OSI Clock Control PLL Postscaler FOSC<2:0> OSCCON<1:0> EC, HS, ECPLL, HSPLL Secondary Oscillator T1OSCEN Enable Oscillator OSCTUNE<7:5>(1) PLL/Prescaler/Postscaler T1OSC INTRC Source MUX Sleep Peripherals CPU Internal Oscillator IDLEN WDT, PWRT, FSCM and Two-Speed Start-up Clock Source Option for Other Modules Note 1: See Table 3-2 for OSCTUNE register configurations and their corresponding frequencies. 2011 Microchip Technology Inc. DS39762F-page 49 PIC18F97J60 FAMILY 3.3 Crystal Oscillator/Ceramic Resonators (HS Modes) In HS or HSPLL Oscillator modes, a crystal is connected to the OSC1 and OSC2 pins to establish oscillation. Figure 3-2 shows the pin connections. Note 1: Higher capacitance increases the stability of the oscillator but also increases the start-up time. 2: Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. The oscillator design requires the use of a crystal that is rated for parallel resonant operation. Note: FIGURE 3-2: CRYSTAL OSCILLATOR OPERATION (HS OR HSPLL CONFIGURATION) C1(1) OSC1 XTAL C2(1) To Internal Logic RF(3) Sleep OSC2 Note 1: RS(2) PIC18FXXJ6X A series resistor (RS) may be required for crystals with a low drive specification. 3: RF varies with the oscillator mode chosen. TABLE 3-1: HS 4: Always verify oscillator performance over the VDD and temperature range that is expected for the application. 3.4 External Clock Input (EC Modes) The EC and ECPLL Oscillator modes require an external clock source to be connected to the OSC1 pin. There is no oscillator start-up time required after a Power-on Reset or after an exit from Sleep mode. In the EC Oscillator mode, the oscillator frequency, divided by 4, is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. Figure 3-3 shows the pin connections for the EC Oscillator mode. See Table 3-1 for initial values of C1 and C2. 2: Osc Type 3: Rs may be required to avoid overdriving crystals with low drive level specifications. Use of a crystal rated for series resonant operation may give a frequency out of the crystal manufacturer's specifications. CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Crystal Freq. 25 MHz FIGURE 3-3: C2 33 pF 33 pF Capacitor values are for design guidance only. Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. Refer to the following application notes for oscillator specific information: * AN588, "PIC(R) Microcontroller Oscillator Design Guide" * AN826, "Crystal Oscillator Basics and Crystal Selection for rfPIC(R) and PIC(R) Devices" * AN849, "Basic PIC(R) Oscillator Design" * AN943, "Practical PIC(R) Oscillator Analysis and Design" * AN949, "Making Your Oscillator Work" OSC1/CLKI Clock from Ext. System PIC18FXXJ6X FOSC/4 Typical Capacitor Values Tested: C1 EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION) OSC2/CLKO An external clock source may also be connected to the OSC1 pin in the HS mode, as shown in Figure 3-4. In this configuration, the OSC2 pin is left open. Current consumption in this configuration will be somewhat higher than EC mode, as the internal oscillator's feedback circuitry will be enabled (in EC mode, the feedback circuit is disabled). FIGURE 3-4: EXTERNAL CLOCK INPUT OPERATION (HS CONFIGURATION) OSC1 Clock from Ext. System PIC18FXXJ6X (HS Mode) Open OSC2 See the notes following this table for additional information. DS39762F-page 50 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 3.5 Internal Oscillator Block The PIC18F97J60 family of devices includes an internal oscillator source (INTRC) which provides a nominal 31 kHz output. The INTRC is enabled on device power-up and clocks the device during its configuration cycle until it enters operating mode. INTRC is also enabled if it is selected as the device clock source or if any of the following are enabled: * Fail-Safe Clock Monitor * Watchdog Timer * Two-Speed Start-up These features are discussed in greater detail in Section 25.0 "Special Features of the CPU". The INTRC can also be optionally configured as the default clock source on device start-up by setting the FOSC2 Configuration bit. This is discussed in Section 3.7.1 "Oscillator Control Register". 3.6 Ethernet Operation and the Microcontroller Clock Although devices of the PIC18F97J60 family can accept a wide range of crystals and external oscillator inputs, they must always have a 25 MHz clock source when REGISTER 3-1: used for Ethernet applications. No provision is made for internally generating the required Ethernet clock from a primary oscillator source of a different frequency. A frequency tolerance is specified, likely excluding the use of ceramic resonators. See Section 28.0 "Electrical Characteristics", Table 28-6, Parameter 5, for more details. 3.6.1 PLL BLOCK To accommodate a range of applications and microcontroller clock speeds, a separate PLL block is incorporated into the clock system. It consists of three components: * A configurable prescaler (1:2 or 1:3) * A 5x PLL frequency multiplier * A configurable postscaler (1:1, 1:2, or 1:3) The operation of the PLL block's components is controlled by the OSCTUNE register (Register 3-1). The use of the PLL block's prescaler and postscaler, with or without the PLL itself, provides a range of system clock frequencies to choose from, including the unaltered 25 MHz of the primary oscillator. The full range of possible oscillator configurations compatible with Ethernet operation is shown in Table 3-2. OSCTUNE: PLL BLOCK CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 PPST1 PLLEN(1) PPST0 PPRE -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 PPST1: PLL Postscaler Configuration bit 1 = Divide-by-2 0 = Divide-by-3 bit 6 PLLEN: 5x Frequency Multiplier PLL Enable bit(1) 1 = PLL is enabled 0 = PLL is disabled bit 5 PPST0: PLL Postscaler Enable bit 1 = Postscaler is enabled 0 = Postscaler is disabled bit 4 PPRE: PLL Prescaler Configuration bit 1 = Divide-by-2 0 = Divide-by-3 bit 3-0 Unimplemented: Read as `0' Note 1: x = Bit is unknown Available only for ECPLL and HSPLL oscillator configurations; otherwise, this bit is unavailable and is read as `0'. 2011 Microchip Technology Inc. DS39762F-page 51 PIC18F97J60 FAMILY TABLE 3-2: DEVICE CLOCK SPEEDS FOR VARIOUS PLL BLOCK CONFIGURATIONS 5x PLL PLL Prescaler PLL Postscaler PLL Block Configuration (OSCTUNE<7:4>) Clock Frequency (MHz) Disabled x101 (Note 1) 2 1111 31.2500 3 0111 20.8333 2 Enabled Disabled Disabled x100 41.6667 3 2 1110 20.8333 3 0110 13.8889 Disabled(2) Disabled x00x 25 (Default) 2 1011 6.2500 3 0011 4.1667 2 1010 4.1667 3 0010 2.7778 2 3 Legend: x = Don't care Note 1: Reserved configuration; represents a clock frequency beyond the microcontroller's operating range. 2: The prescaler is automatically disabled when the PLL and postscaler are both disabled. 3.7 Clock Sources and Oscillator Switching The PIC18F97J60 family of devices includes a feature that allows the device clock source to be switched from the main oscillator to an alternate clock source. These devices also offer two alternate clock sources. When an alternate clock source is enabled, the various power-managed operating modes are available. Essentially, there are three clock sources for these devices: * Primary oscillators * Secondary oscillators * Internal oscillator block The primary oscillators include the External Crystal and Resonator modes and the External Clock modes. The particular mode is defined by the FOSC<2:0> Configuration bits. The details of these modes are covered earlier in this chapter. DS39762F-page 52 The secondary oscillators are those external sources not connected to the OSC1 or OSC2 pins. These sources may continue to operate even after the controller is placed in a power-managed mode. The PIC18F97J60 family of devices offers the Timer1 oscillator as a secondary oscillator. In all power-managed modes, this oscillator is often the time base for functions such as a Real-Time Clock (RTC). Most often, a 32.768 kHz watch crystal is connected between the RC0/T1OSO/T13CKI and RC1/T1OSI pins. Loading capacitors are also connected from each pin to ground. The Timer1 oscillator is discussed in greater detail in Section 13.3 "Timer1 Oscillator". In addition to being a primary clock source, the internal oscillator is available as a power-managed mode clock source. The INTRC source is also used as the clock source for several special features, such as the WDT and Fail-Safe Clock Monitor. The clock sources for the PIC18F97J60 family devices are shown in Figure 3-1. See Section 25.0 "Special Features of the CPU" for Configuration register details. 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 3.7.1 OSCILLATOR CONTROL REGISTER The OSCCON register (Register 3-2) controls several aspects of the device clock's operation, both in full-power operation and in power-managed modes. The System Clock Select bits, SCS<1:0>, select the clock source. The available clock sources are the primary clock (defined by the FOSC<2:0> Configuration bits), the secondary clock (Timer1 oscillator) and the internal oscillator. The clock source changes after one or more of the bits are changed, following a brief clock transition interval. The OSTS (OSCCON<3>) and T1RUN (T1CON<6>) bits indicate which clock source is currently providing the device clock. The T1RUN bit indicates when the Timer1 oscillator is providing the device clock in secondary clock modes. In power-managed modes, only one of these bits will be set at any time. If neither bit is set, the INTRC source is providing the clock, or the internal oscillator has just started and is not yet stable. REGISTER 3-2: R/W-0 The use of the flag and control bits in the OSCCON register is discussed in more detail in Section 4.0 "Power-Managed Modes". Note 1: The Timer1 oscillator must be enabled to select the secondary clock source. The Timer1 oscillator is enabled by setting the T1OSCEN bit in the Timer1 Control register (T1CON<3>). If the Timer1 oscillator is not enabled, then any attempt to select a secondary clock source will be ignored. 2: It is recommended that the Timer1 oscillator be operating and stable before executing the SLEEP instruction or a very long delay may occur while the Timer1 oscillator starts. OSCCON: OSCILLATOR CONTROL REGISTER U-0 IDLEN The IDLEN bit determines if the device goes into Sleep mode or one of the Idle modes when the SLEEP instruction is executed. -- U-0 -- U-0 R-q U-0 R/W-0 R/W-0 -- OSTS(1) -- SCS1 SCS0 bit 7 bit 0 Legend: q = Value determined by configuration R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 IDLEN: Idle Enable bit 1 = Device enters Idle mode on SLEEP instruction 0 = Device enters Sleep mode on SLEEP instruction bit 6-4 Unimplemented: Read as `0' bit 3 OSTS: Oscillator Status bit(1) 1 = Device is running from oscillator source defined when SCS<1:0> = 00 0 = Device is running from oscillator source defined when SCS<1:0> = 01, 10 or 11 bit 2 Unimplemented: Read as `0' bit 1-0 SCS<1:0>: System Clock Select bits 11 = Internal oscillator 10 = Primary oscillator 01 = Timer1 oscillator When FOSC2 = 1; 00 = Primary oscillator When FOSC2 = 0; 00 = Internal oscillator Note 1: Reset value is `0' when Two-Speed Start-up is enabled and `1' if disabled. 2011 Microchip Technology Inc. DS39762F-page 53 PIC18F97J60 FAMILY 3.7.1.1 System Clock Selection and the FOSC2 Configuration Bit The SCS bits are cleared on all forms of Reset. In the device's default configuration, this means the primary oscillator, defined by FOSC<1:0> (that is, one of the HC or EC modes), is used as the primary clock source on device Resets. The default clock configuration on Reset can be changed with the FOSC2 Configuration bit. This bit affects the clock source selection setting when SCS<1:0> = 00. When FOSC2 = 1 (default), the oscillator source defined by FOSC<1:0> is selected whenever SCS<1:0> = 00. When FOSC2 = 0, the INTRC oscillator is selected whenever SCS<1:0> = 00. Because the SCS bits are cleared on Reset, the FOSC2 setting also changes the default oscillator mode on Reset. Regardless of the setting of FOSC2, INTRC will always be enabled on device power-up. It will serve as the clock source until the device has loaded its configuration values from memory. It is at this point that the FOSC Configuration bits are read and the oscillator selection of operational mode is made. Note that either the primary clock or the internal oscillator will have two bit setting options, at any given time, depending on the setting of FOSC2. 3.7.2 OSCILLATOR TRANSITIONS PIC18F97J60 family devices contain circuitry to prevent clock "glitches" when switching between clock sources. A short pause in the device clock occurs during the clock switch. The length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Clock transitions are discussed in greater detail in Section 4.1.2 "Entering Power-Managed Modes". 3.8 Effects of Power-Managed Modes on the Various Clock Sources When PRI_IDLE mode is selected, the designated primary oscillator continues to run without interruption. For all other power-managed modes, the oscillator using the OSC1 pin is disabled. The OSC1 pin (and OSC2 pin if used by the oscillator) will stop oscillating. In secondary clock modes (SEC_RUN and SEC_IDLE), the Timer1 oscillator is operating and providing the device clock. The Timer1 oscillator may also run in all power-managed modes if required to clock Timer1 or Timer3. In RC_RUN and RC_IDLE modes, the internal oscillator provides the device clock source. The 31 kHz INTRC output can be used directly to provide the clock and may be enabled to support various special features, regardless of the power-managed mode (see Section 25.2 "Watchdog Timer (WDT)" through Section 25.5 "Fail-Safe Clock Monitor" for more information on WDT, Fail-Safe Clock Monitor and Two-Speed Start-up). If the Sleep mode is selected, all clock sources are stopped. Since all the transistor switching currents have been stopped, Sleep mode achieves the lowest current consumption of the device (only leakage currents). Enabling any on-chip feature that will operate during Sleep will increase the current consumed during Sleep. The INTRC is required to support WDT operation. The Timer1 oscillator may be operating to support a Real-Time Clock. Other features may be operating that do not require a device clock source (i.e., MSSP slave, PSP, INTx pins and others). Peripherals that may add significant current consumption are listed in Section 28.2 "DC Characteristics: Power-Down and Supply Current PIC18F97J60 Family (Industrial)" 3.9 Power-up Delays Power-up delays are controlled by two timers, so that no external Reset circuitry is required for most applications. The delays ensure that the device is kept in Reset until the device power supply is stable under normal circumstances, and the primary clock is operating and stable. For additional information on power-up delays, see Section 5.6 "Power-up Timer (PWRT)". The first timer is the Power-up Timer (PWRT), which provides a fixed delay on power-up (Parameter 33, Table 28-12); it is always enabled. The second timer is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable (HS modes). The OST does this by counting 1024 oscillator cycles before allowing the oscillator to clock the device. There is a delay of interval, TCSD (Parameter 38, Table 28-12), following POR, while the controller becomes ready to execute instructions. TABLE 3-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE Oscillator Mode OSC1 Pin OSC2 Pin EC, ECPLL Floating, pulled by external clock At logic low (clock/4 output) HS, HSPLL Feedback inverter is disabled at quiescent voltage level Feedback inverter is disabled at quiescent voltage level Note: See Table 5-2 in Section 5.0 "Reset" for time-outs due to Sleep and MCLR Reset. DS39762F-page 54 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 4.0 4.1.1 POWER-MANAGED MODES CLOCK SOURCES The PIC18F97J60 family devices provide the ability to manage power consumption by simply managing clocking to the CPU and the peripherals. In general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power. For the sake of managing power in an application, there are three primary modes of operation: The SCS<1:0> bits allow the selection of one of three clock sources for power-managed modes. They are: * Run mode * Idle mode * Sleep mode 4.1.2 These modes define which portions of the device are clocked and at what speed. The Run and Idle modes may use any of the three available clock sources (primary, secondary or internal oscillator block); the Sleep mode does not use a clock source. The power-managed modes include several power-saving features offered on previous PIC(R) MCU devices. One is the clock switching feature, offered in other PIC18 devices, allowing the controller to use the Timer1 oscillator in place of the primary oscillator. Also included is the Sleep mode, offered by all PIC MCU devices, where all device clocks are stopped. 4.1 Selecting Power-Managed Modes Selecting a power-managed mode requires two decisions: if the CPU is to be clocked or not and which clock source is to be used. The IDLEN bit (OSCCON<7>) controls CPU clocking, while the SCS<1:0> bits (OSCCON<1:0>) select the clock source. The individual modes, bit settings, clock sources and affected modules are summarized in Table 4-1. TABLE 4-1: ENTERING POWER-MANAGED MODES Switching from one power-managed mode to another begins by loading the OSCCON register. The SCS<1:0> bits select the clock source and determine which Run or Idle mode is to be used. Changing these bits causes an immediate switch to the new clock source, assuming that it is running. The switch may also be subject to clock transition delays. These are discussed in Section 4.1.3 "Clock Transitions and Status Indicators" and subsequent sections. Entry to the power-managed Idle or Sleep modes is triggered by the execution of a SLEEP instruction. The actual mode that results depends on the status of the IDLEN bit. Depending on the current mode and the mode being switched to, a change to a power-managed mode does not always require setting all of these bits. Many transitions may be done by changing the oscillator select bits, or changing the IDLEN bit, prior to issuing a SLEEP instruction. If the IDLEN bit is already configured correctly, it may only be necessary to perform a SLEEP instruction to switch to the desired mode. POWER-MANAGED MODES OSCCON<7,1:0> Mode * The primary clock, as defined by the FOSC<2:0> Configuration bits * The secondary clock (Timer1 oscillator) * The internal oscillator Module Clocking Available Clock and Oscillator Source IDLEN(1) SCS<1:0> CPU Peripherals 0 N/A Off Off PRI_RUN N/A 10 Clocked Clocked SEC_RUN N/A 01 Clocked Clocked Secondary - Timer1 Oscillator RC_RUN N/A 11 Clocked Clocked Internal Oscillator PRI_IDLE 1 10 Off Clocked Primary - HS, EC, HSPLL, ECPLL SEC_IDLE 1 01 Off Clocked Secondary - Timer1 Oscillator RC_IDLE 1 11 Off Clocked Internal Oscillator Sleep Note 1: None - All clocks are disabled Primary - HS, EC, HSPLL, ECPLL; this is the normal, full-power execution mode IDLEN reflects its value when the SLEEP instruction is executed. 2011 Microchip Technology Inc. DS39762F-page 55 PIC18F97J60 FAMILY 4.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Two bits indicate the current clock source and its status: OSTS (OSCCON<3>) and T1RUN (T1CON<6>). In general, only one of these bits will be set while in a given power-managed mode. When the OSTS bit is set, the primary clock is providing the device clock. When the T1RUN bit is set, the Timer1 oscillator is providing the clock. If neither of these bits is set, INTRC is clocking the device. Note: 4.1.4 Executing a SLEEP instruction does not necessarily place the device into Sleep mode. It acts as the trigger to place the controller into either the Sleep mode, or one of the Idle modes, depending on the setting of the IDLEN bit. MULTIPLE SLEEP COMMANDS The power-managed mode that is invoked with the SLEEP instruction is determined by the setting of the IDLEN bit at the time the instruction is executed. If another SLEEP instruction is executed, the device will enter the power-managed mode specified by IDLEN at that time. If IDLEN has changed, the device will enter the new power-managed mode specified by the new setting. 4.2 Run Modes In the Run modes, clocks to both the core and peripherals are active. The difference between these modes is the clock source. 4.2.1 4.2.2 SEC_RUN MODE The SEC_RUN mode is the compatible mode to the "clock switching" feature offered in other PIC18 devices. In this mode, the CPU and peripherals are clocked from the Timer1 oscillator. This gives users the option of lower power consumption while still using a high accuracy clock source. SEC_RUN mode is entered by setting the SCS<1:0> bits to `01'. The device clock source is switched to the Timer1 oscillator (see Figure 4-1), the primary oscillator is shut down, the T1RUN bit (T1CON<6>) is set and the OSTS bit is cleared. Note: The Timer1 oscillator should already be running prior to entering SEC_RUN mode. If the T1OSCEN bit is not set when the SCS<1:0> bits are set to `01', entry to SEC_RUN mode will not occur. If the Timer1 oscillator is enabled, but not yet running, device clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result. On transitions from SEC_RUN mode to PRI_RUN, the peripherals and CPU continue to be clocked from the Timer1 oscillator while the primary clock is started. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see Figure 4-2). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run. PRI_RUN MODE The PRI_RUN mode is the normal, full-power execution mode of the microcontroller. This is also the default mode upon a device Reset unless Two-Speed Start-up is enabled (see Section 25.4 "Two-Speed Start-up" for details). In this mode, the OSTS bit is set. (see Section 3.7.1 "Oscillator Control Register"). DS39762F-page 56 2011 Microchip Technology Inc. PIC18F97J60 FAMILY FIGURE 4-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE Q1 Q2 Q3 Q4 Q1 T1OSI Q2 1 2 3 n-1 Q3 Q4 Q1 Q2 Q3 n Clock Transition OSC1 CPU Clock Peripheral Clock Program Counter PC FIGURE 4-2: PC + 2 PC + 4 TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 T1OSI OSC1 TOST(1) TPLL(1) 1 PLL Clock Output 2 n-1 n Clock Transition CPU Clock Peripheral Clock Program Counter SCS<1:0> bits Changed PC + 2 PC PC + 4 OSTS bit Set Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. 2011 Microchip Technology Inc. DS39762F-page 57 PIC18F97J60 FAMILY 4.2.3 RC_RUN MODE On transitions from RC_RUN mode to PRI_RUN mode, the device continues to be clocked from the INTRC while the primary clock is started. When the primary clock becomes ready, a clock switch to the primary clock occurs (see Figure 4-4). When the clock switch is complete, the OSTS bit is set and the primary clock is providing the device clock. The IDLEN and SCS bits are not affected by the switch. The INTRC source will continue to run if either the WDT or Fail-Safe Clock Monitor is enabled. In RC_RUN mode, the CPU and peripherals are clocked from the internal oscillator; the primary clock is shut down. This mode provides the best power conservation of all the Run modes while still executing code. It works well for user applications which are not highly timing-sensitive or do not require high-speed clocks at all times. This mode is entered by setting SCS<1:0> to `11'. When the clock source is switched to the INTRC (see Figure 4-3), the primary oscillator is shut down and the OSTS bit is cleared. FIGURE 4-3: TRANSITION TIMING TO RC_RUN MODE Q1 Q2 Q3 Q4 Q1 INTRC Q2 1 2 3 n-1 Q3 Q4 Q1 Q2 Q3 n Clock Transition OSC1 CPU Clock Peripheral Clock Program Counter PC FIGURE 4-4: PC + 2 PC + 4 TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE Q1 Q2 Q3 Q4 Q2 Q3 Q4 Q1 Q2 Q3 Q1 INTRC OSC1 TOST(1) TPLL(1) 1 PLL Clock Output 2 n-1 n Clock Transition CPU Clock Peripheral Clock Program Counter SCS<1:0> bits Changed PC PC + 2 PC + 4 OSTS bit Set Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. DS39762F-page 58 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 4.3 Sleep Mode 4.4 The power-managed Sleep mode is identical to the legacy Sleep mode offered in all other PIC MCU devices. It is entered by clearing the IDLEN bit (the default state on device Reset) and executing the SLEEP instruction. This shuts down the selected oscillator (Figure 4-5). All clock source status bits are cleared. Idle Modes The Idle modes allow the controller's CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to `1' when a SLEEP instruction is executed, the peripherals will be clocked from the clock source selected using the SCS<1:0> bits; however, the CPU will not be clocked. The clock source status bits are not affected. Setting IDLEN and executing a SLEEP instruction provides a quick method of switching from a given Run mode to its corresponding Idle mode. Entering the Sleep mode from any other mode does not require a clock switch. This is because no clocks are needed once the controller has entered Sleep. If the WDT is selected, the INTRC source will continue to operate. If the Timer1 oscillator is enabled, it will also continue to run. If the WDT is selected, the INTRC source will continue to operate. If the Timer1 oscillator is enabled, it will also continue to run. When a wake event occurs in Sleep mode (by interrupt, Reset or WDT time-out), the device will not be clocked until the clock source selected by the SCS<1:0> bits becomes ready (see Figure 4-6), or it will be clocked from the internal oscillator if either the Two-Speed Start-up or the Fail-Safe Clock Monitor is enabled (see Section 25.0 "Special Features of the CPU"). In either case, the OSTS bit is set when the primary clock is providing the device clocks. The IDLEN and SCS bits are not affected by the wake-up. Since the CPU is not executing instructions, the only exits from any of the Idle modes are by interrupt, WDT time-out or a Reset. When a wake event occurs, CPU execution is delayed by an interval of TCSD (Parameter 38, Table 28-12) while it becomes ready to execute code. When the CPU begins executing code, it resumes with the same clock source for the current Idle mode. For example, when waking from RC_IDLE mode, the internal oscillator block will clock the CPU and peripherals (in other words, RC_RUN mode). The IDLEN and SCS bits are not affected by the wake-up. While in any Idle mode or Sleep mode, a WDT time-out will result in a WDT wake-up to the Run mode currently specified by the SCS<1:0> bits. FIGURE 4-5: TRANSITION TIMING FOR ENTRY TO SLEEP MODE Q1 Q2 Q3 Q4 Q1 OSC1 CPU Clock Peripheral Clock Sleep Program Counter PC FIGURE 4-6: PC + 2 TRANSITION TIMING FOR WAKE FROM SLEEP MODE (HSPLL) Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 OSC1 PLL Clock Output TOST(1) TPLL(1) CPU Clock Peripheral Clock Program Counter PC Wake Event PC + 2 PC + 4 PC + 6 OSTS bit Set Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. 2011 Microchip Technology Inc. DS39762F-page 59 PIC18F97J60 FAMILY 4.4.1 PRI_IDLE MODE 4.4.2 This mode is unique among the three low-power Idle modes in that it does not disable the primary device clock. For timing-sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to "warm up" or transition from another oscillator. PRI_IDLE mode is entered from PRI_RUN mode by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set IDLEN first, then set the SCS<1:0> bits to `10' and execute SLEEP. Although the CPU is disabled, the peripherals continue to be clocked from the primary clock source specified by the FOSC<1:0> Configuration bits. The OSTS bit remains set (see Figure 4-7). In SEC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the Timer1 oscillator. This mode is entered from SEC_RUN by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set IDLEN first, then set SCS<1:0> to `01' and execute SLEEP. When the clock source is switched to the Timer1 oscillator, the primary oscillator is shut down, the OSTS bit is cleared and the T1RUN bit is set. When a wake event occurs, the peripherals continue to be clocked from the Timer1 oscillator. After an interval of TCSD, following the wake event, the CPU begins executing code being clocked by the Timer1 oscillator. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run (see Figure 4-8). When a wake event occurs, the CPU is clocked from the primary clock source. A delay of interval, TCSD, is required between the wake event and when code execution starts. This is required to allow the CPU to become ready to execute instructions. After the wake-up, the OSTS bit remains set. The IDLEN and SCS bits are not affected by the wake-up (see Figure 4-8). FIGURE 4-7: SEC_IDLE MODE Note: The Timer1 oscillator should already be running prior to entering SEC_IDLE mode. If the T1OSCEN bit is not set when the SLEEP instruction is executed, the SLEEP instruction will be ignored and entry to SEC_IDLE mode will not occur. If the Timer1 oscillator is enabled, but not yet running, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result. TRANSITION TIMING FOR ENTRY TO IDLE MODE Q1 Q4 Q3 Q2 Q1 OSC1 CPU Clock Peripheral Clock Program Counter FIGURE 4-8: PC PC + 2 TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE Q1 Q2 Q3 Q4 OSC1 TCSD CPU Clock Peripheral Clock Program Counter PC Wake Event DS39762F-page 60 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 4.4.3 RC_IDLE MODE In RC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the internal oscillator. This mode allows for controllable power conservation during Idle periods. From RC_RUN mode, RC_IDLE mode is entered by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, first set IDLEN, then clear the SCS bits and execute SLEEP. When the clock source is switched to the INTRC, the primary oscillator is shut down and the OSTS bit is cleared. When a wake event occurs, the peripherals continue to be clocked from the INTRC. After a delay of TCSD following the wake event, the CPU begins executing code being clocked by the INTRC. The IDLEN and SCS bits are not affected by the wake-up. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled. 4.5 Exiting Idle and Sleep Modes An exit from Sleep mode, or any of the Idle modes, is triggered by an interrupt, a Reset or a WDT time-out. This section discusses the triggers that cause exits from power-managed modes. The clocking subsystem actions are discussed in each of the power-managed modes sections (see Section 4.2 "Run Modes", Section 4.3 "Sleep Mode" and Section 4.4 "Idle Modes"). 4.5.1 EXIT BY INTERRUPT Any of the available interrupt sources can cause the device to exit from an Idle mode, or the Sleep mode, to a Run mode. To enable this functionality, an interrupt source must be enabled by setting its enable bit in one of the INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. On all exits from Idle or Sleep modes by interrupt, code execution branches to the interrupt vector if the GIE/GIEH bit (INTCON<7>) is set. Otherwise, code execution continues or resumes without branching (see Section 10.0 "Interrupts"). 4.5.2 EXIT BY WDT TIME-OUT A WDT time-out will cause different actions depending on which power-managed mode the device is in when the time-out occurs. If the device is not executing code (all Idle modes and Sleep mode), the time-out will result in an exit from the power-managed mode (see Section 4.2 "Run Modes" and Section 4.3 "Sleep Mode"). If the device is executing code (all Run modes), the time-out will result in a WDT Reset (see Section 25.2 "Watchdog Timer (WDT)"). The WDT timer and postscaler are cleared by one of the following events: * Executing a SLEEP or CLRWDT instruction * The loss of a currently selected clock source (if the Fail-Safe Clock Monitor is enabled) 4.5.3 EXIT BY RESET Exiting an Idle or Sleep mode by Reset automatically forces the device to run from the INTRC. 4.5.4 EXIT WITHOUT AN OSCILLATOR START-UP TIMER DELAY Certain exits from power-managed modes do not invoke the OST at all. There are two cases: * PRI_IDLE mode, where the primary clock source is not stopped * The primary clock source is either the EC or ECPLL mode In these instances, the primary clock source either does not require an oscillator start-up delay, since it is already running (PRI_IDLE), or normally does not require an oscillator start-up delay (EC). However, a fixed delay of interval, TCSD, following the wake event is still required when leaving the Sleep and Idle modes to allow the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. A fixed delay of interval, TCSD, following the wake event is required when leaving the Sleep and Idle modes. This delay is required for the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. 2011 Microchip Technology Inc. DS39762F-page 61 PIC18F97J60 FAMILY NOTES: DS39762F-page 62 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 5.0 RESET The PIC18F97J60 family of devices differentiates between various kinds of Reset: a) b) c) d) e) f) g) h) i) MCLR Reset during normal operation MCLR Reset during power-managed modes Power-on Reset (POR) Brown-out Reset (BOR) Configuration Mismatch (CM) RESET Instruction Stack Full Reset Stack Underflow Reset Watchdog Timer (WDT) Reset during execution This section discusses Resets generated by hard events (MCLR), power events (POR and BOR) and Configuration Mismatches (CM). It also covers the operation of the various start-up timers. Stack Reset events are covered in Section 6.1.6.4 "Stack Full and Underflow Resets". WDT Resets are covered in Section 25.2 "Watchdog Timer (WDT)". FIGURE 5-1: A simplified block diagram of the on-chip Reset circuit is shown in Figure 5-1. 5.1 RCON Register Device Reset events are tracked through the RCON register (Register 5-1). The lower six bits of the register indicate that a specific Reset event has occurred. In most cases, these bits can only be set by the event and must be cleared by the application after the event. The state of these flag bits, taken together, can be read to indicate the type of Reset that just occurred. This is described in more detail in Section 5.7 "Reset State of Registers". The RCON register also has a control bit for setting interrupt priority (IPEN). Interrupt priority is discussed in Section 10.0 "Interrupts". SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT RESET Instruction Configuration Word Mismatch Stack Pointer Stack Full/Underflow Reset External Reset MCLR ( )_IDLE Sleep WDT Time-out VDD Rise Detect VDD POR Pulse Brown-out Reset(1) S PWRT 32 s PWRT INTRC Note 1: 66 ms 11-Bit Ripple Counter R Q Chip_Reset The ENVREG pin must be tied high to enable Brown-out Reset. The Brown-out Reset is provided by the on-chip voltage regulator when there is insufficient source voltage to maintain regulation. 2011 Microchip Technology Inc. DS39762F-page 63 PIC18F97J60 FAMILY REGISTER 5-1: RCON: RESET CONTROL REGISTER R/W-0 U-0 R/W-1 R/W-1 R-1 R-1 R/W-0 R/W-0 IPEN -- CM RI TO PD POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 Unimplemented: Read as `0' bit 5 CM: Configuration Mismatch Flag bit 1 = A Configuration Mismatch Reset has not occurred 0 = A Configuration Mismatch Reset has occurred (must be set in software after a Configuration Mismatch Reset occurs) bit 4 RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed (set by firmware only) 0 = The RESET instruction was executed causing a device Reset (must be set in software after a Brown-out Reset occurs) bit 3 TO: Watchdog Timer Time-out Flag bit 1 = Set by power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 2 PD: Power-Down Detection Flag bit 1 = Set by power-up or by the CLRWDT instruction 0 = Set by execution of the SLEEP instruction bit 1 POR: Power-on Reset Status bit 1 = A Power-on Reset has not occurred (set by firmware only) 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = A Brown-out Reset has not occurred (set by firmware only) 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Note 1: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent Power-on Resets may be detected. 2: If the on-chip voltage regulator is disabled, BOR remains `0' at all times. See Section 5.4.1 "Detecting BOR" for more information. 3: Brown-out Reset is said to have occurred when BOR is `0' and POR is `1' (assuming that POR was set to `1' by software immediately after a Power-on Reset). DS39762F-page 64 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 5.2 Master Clear (MCLR) FIGURE 5-2: The MCLR pin provides a method for triggering a hard external Reset of the device. A Reset is generated by holding the pin low. PIC18 extended microcontroller devices have a noise filter in the MCLR Reset path which detects and ignores small pulses. 5.3 D(1) C POR events are captured by the POR bit (RCON<1>). The state of the bit is set to `0' whenever a Power-on Reset occurs; it does not change for any other Reset event. POR is not reset to `1' by any hardware event. To capture multiple events, the user manually resets the bit to `1' in software following any Power-on Reset. 5.4 Brown-out Reset (BOR) The PIC18F97J60 family of devices incorporates a simple BOR function when the internal regulator is enabled (ENVREG pin is tied to VDD). Any drop of VDD below VBOR (Parameter D005), for greater than time, TBOR (Parameter 35), will reset the device. A Reset may or may not occur if VDD falls below VBOR for less than TBOR. The chip will remain in Brown-out Reset until VDD rises above VBOR. Once a BOR has occurred, the Power-up Timer will keep the chip in Reset for TPWRT (Parameter 33). If VDD drops below VBOR while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once VDD rises above VBOR, the Power-up Timer will execute the additional time delay. 2011 Microchip Technology Inc. MCLR PIC18FXXJ6X Note 1: External Power-on Reset circuit is required only if the VDD power-up slope is too slow. The diode, D, helps discharge the capacitor quickly when VDD powers down. 2: R < 40 k is recommended to make sure that the voltage drop across R does not violate the device's electrical specification. 3: R1 1 k will limit any current flowing into MCLR from external capacitor, C, in the event of MCLR/VPP pin breakdown, due to Electrostatic Discharge (ESD), or Electrical Overstress (EOS). To take advantage of the POR circuitry, tie the MCLR pin through a resistor (1 k to 10 k) to VDD. This will eliminate external RC components usually needed to create a Power-on Reset delay. A minimum rise rate for VDD is specified (Parameter D004). For a slow rise time, see Figure 5-2. When the device starts normal operation (i.e., exits the Reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. R(2) R1(3) Power-on Reset (POR) A Power-on Reset condition is generated on-chip whenever VDD rises above a certain threshold. This allows the device to start in the initialized state when VDD is adequate for operation. VDD VDD The MCLR pin is not driven low by any internal Resets, including the WDT. EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP) 5.4.1 DETECTING BOR The BOR bit always resets to `0' on any Brown-out Reset or Power-on Reset event. This makes it difficult to determine if a Brown-out Reset event has occurred just by reading the state of BOR alone. A more reliable method is to simultaneously check the state of both POR and BOR. This assumes that the POR bit is reset to `1' in software immediately after any Power-on Reset event. If BOR is `0' while POR is `1', it can be reliably assumed that a Brown-out Reset event has occurred. If the voltage regulator is disabled, Brown-out Reset functionality is disabled. In this case, the BOR bit cannot be used to determine a Brown-out Reset event. The BOR bit is still cleared by a Power-on Reset event. 5.5 Configuration Mismatch (CM) The Configuration Mismatch (CM) Reset is designed to detect and attempt to recover from random, memory corrupting events. These include Electrostatic Discharge (ESD) events which can cause widespread single-bit changes throughout the device and result in catastrophic failure. In PIC18FXXJ Flash devices, the device Configuration registers (located in the configuration memory space) are continuously monitored during operation by comparing their values to complimentary shadow registers. If a mismatch is detected between the two sets of registers, a CM Reset automatically occurs. These events are captured by the CM bit (RCON<5>). The state of the bit is set to `0' whenever a CM event occurs; it does not change for any other Reset event. DS39762F-page 65 PIC18F97J60 FAMILY A CM Reset behaves similarly to a Master Clear Reset, RESET instruction, WDT time-out or Stack Event Reset. As with all hard and power Reset events, the device Configuration Words are reloaded from the Flash Configuration Words in program memory as the device restarts. 5.6 Power-up Timer (PWRT) PIC18F97J60 family of devices incorporates an on-chip Power-up Timer (PWRT) to help regulate the Power-on Reset process. The PWRT is always enabled. The main function is to ensure that the device voltage is stable before code is executed. The Power-up Timer (PWRT) of the PIC18F97J60 family devices is an 11-bit counter which uses the INTRC source as the clock input. This yields an approximate time interval of 2048 x 32 s = 66 ms. While the PWRT is counting, the device is held in Reset. FIGURE 5-3: The power-up time delay depends on the INTRC clock and will vary from chip-to-chip due to temperature and process variation. See DC Parameter 33 for details. 5.6.1 TIME-OUT SEQUENCE The PWRT time-out is invoked after the POR pulse has cleared. The total time-out will vary based on the status of the PWRT. Figure 5-3, Figure 5-4, Figure 5-5 and Figure 5-6 all depict time-out sequences on power-up. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the PWRT will expire. Bringing MCLR high will begin execution immediately (Figure 5-5). This is useful for testing purposes or to synchronize more than one PIC18FXXJ6X device operating in parallel. TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 FIGURE 5-4: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET DS39762F-page 66 2011 Microchip Technology Inc. PIC18F97J60 FAMILY FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET FIGURE 5-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) 3.3V VDD 0V 1V MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET 2011 Microchip Technology Inc. DS39762F-page 67 PIC18F97J60 FAMILY 5.7 TO, PD, POR and BOR) are set or cleared differently in different Reset situations, as indicated in Table 5-1. These bits are used in software to determine the nature of the Reset. Reset State of Registers Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a "Reset state" depending on the type of Reset that occurred. Table 5-2 describes the Reset states for all of the Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets, and WDT wake-ups. Most registers are not affected by a WDT wake-up since this is viewed as the resumption of normal operation. Status bits from the RCON register (CM, RI, TABLE 5-1: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER Condition Program Counter(1) RCON Register STKPTR Register CM RI TO PD POR BOR STKFUL STKUNF Power-on Reset 0000h 1 1 1 1 0 0 0 0 RESET Instruction 0000h u 0 u u u u u u Brown-out Reset 0000h 1 1 1 1 u 0 u u Configuration Mismatch Reset 0000h 0 u u u u u u u MCLR during power-managed Run modes 0000h u u 1 u u u u u MCLR during power-managed Idle modes and Sleep mode 0000h u u 1 0 u u u u MCLR during full-power execution 0000h u u u u u u u u Stack Full Reset (STVREN = 1) 0000h u u u u u u 1 u Stack Underflow Reset (STVREN = 1) 0000h u u u u u u u 1 Stack Underflow Error (not an actual Reset, STVREN = 0) 0000h u u u u u u u 1 WDT time-out during full power or power-managed Run modes 0000h u u 0 u u u u u WDT time-out during power-managed Idle or Sleep modes PC + 2 u u 0 0 u u u u Interrupt exit from power-managed modes PC + 2 u u u 0 u u u u Legend: u = unchanged Note 1: When the wake-up is due to an interrupt, and the GIEH or GIEL bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). DS39762F-page 68 2011 Microchip Technology Inc. PIC18F97J60 FAMILY TABLE 5-2: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS Applicable Devices Power-on Reset, Brown-out Reset MCLR Reset, WDT Reset, RESET Instruction, Stack Resets, CM Reset Wake-up via WDT or Interrupt TOSU PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 0000 ---0 0000 ---0 uuuu(1) TOSH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu(1) TOSL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu(1) STKPTR PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 00-0 0000 uu-0 0000 uu-u uuuu(1) PCLATU PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 0000 ---0 0000 ---u uuuu PCLATH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu PCL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 PC + 2(2) TBLPTRU PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X --00 0000 --00 0000 --uu uuuu TBLPTRH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu TBLPTRL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu TABLAT PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu PRODH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu PRODL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu INTCON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 000x 0000 000u uuuu uuuu(3) INTCON2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1111 1111 1111 uuuu uuuu(3) INTCON3 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1100 0000 1100 0000 uuuu uuuu(3) INDF0 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X N/A N/A N/A POSTINC0 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X N/A N/A N/A POSTDEC0 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X N/A N/A N/A PREINC0 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X N/A N/A N/A PLUSW0 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X N/A N/A N/A FSR0H PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---- xxxx ---- uuuu ---- uuuu FSR0L PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu WREG PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu INDF1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X N/A N/A N/A POSTINC1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X N/A N/A N/A POSTDEC1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X N/A N/A N/A PREINC1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X N/A N/A N/A PLUSW1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X N/A N/A N/A FSR1H PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---- xxxx ---- uuuu ---- uuuu FSR1L PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu BSR PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---- 0000 ---- 0000 ---- uuuu INDF2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X N/A N/A N/A POSTINC2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X N/A N/A N/A POSTDEC2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X N/A N/A N/A PREINC2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X N/A N/A N/A PLUSW2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X N/A N/A N/A FSR2H PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---- xxxx ---- uuuu ---- uuuu PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu FSR2L Legend: Note 1: 2: 3: 4: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). See Table 5-1 for Reset value for specific condition. 2011 Microchip Technology Inc. DS39762F-page 69 PIC18F97J60 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices Power-on Reset, Brown-out Reset MCLR Reset, WDT Reset, RESET Instruction, Stack Resets, CM Reset Wake-up via WDT or Interrupt STATUS PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---x xxxx ---u uuuu ---u uuuu TMR0H PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu TMR0L PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu T0CON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1111 1111 1111 uuuu uuuu OSCCON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0--- q-00 0--- q-00 u--- q-uu ECON1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 00-- 0000 00-- uuuu uu-- WDTCON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---- ---0 ---- ---0 ---- ---u (4) PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0-q1 1100 0-uq qquu u-uu qquu TMR1H PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu TMR1L PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu T1CON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 u0uu uuuu uuuu uuuu TMR2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu PR2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1111 1111 1111 1111 1111 T2CON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X -000 0000 -000 0000 -uuu uuuu SSP1BUF PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu SSP1ADD PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu SSP1STAT PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu SSP1CON1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu SSP1CON2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu ADRESH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu ADRESL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0-00 0000 0-00 0000 u-uu uuuu ADCON1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X --00 0000 --00 0000 --uu uuuu RCON ADCON2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0-00 0000 0-00 0000 u-uu uuuu CCPR1H PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu CCPR1L PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu CCPR2H PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu CCPR2L PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu CCP2CON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu CCPR3H PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu CCPR3L PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu CCP3CON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu ECCP1AS PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu CVRCON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu CMCON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0111 0000 0111 uuuu uuuu TMR3H PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu TMR3L PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu Legend: Note 1: 2: 3: 4: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). See Table 5-1 for Reset value for specific condition. DS39762F-page 70 2011 Microchip Technology Inc. PIC18F97J60 FAMILY TABLE 5-2: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Reset, WDT Reset, RESET Instruction, Stack Resets, CM Reset Wake-up via WDT or Interrupt T3CON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 uuuu uuuu uuuu uuuu PSPCON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 ---- 0000 ---- uuuu ---- SPBRG1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu RCREG1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu TXREG1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu TXSTA1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0010 0000 0010 uuuu uuuu RCSTA1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 000x 0000 000x uuuu uuuu EECON2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---- ---- ---- ---- ---- ---- EECON1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 x00- ---0 x00- ---u uuu- IPR3 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1111 1111 1111 uuuu uuuu PIR3 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu(3) PIE3 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu IPR2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1-11 1111 1-11 uuuu u-uu PIR2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0-00 0000 0-00 uuuu u-uu(3) PIE2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0-00 0000 0-00 uuuu u-uu IPR1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1111 1111 1111 uuuu uuuu PIR1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu(3) PIE1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu MEMCON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0-00 --00 0-00 --00 u-uu --uu OSCTUNE PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 ---- 0000 ---- uuuu ---- TRISJ PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X --11 ---- --11 ---- --uu ---- PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1111 1111 1111 uuuu uuuu PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1111 1111 1111 uuuu uuuu ---u ---- TRISH TRISG TRISF TRISE TRISD PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---1 ---- ---1 ---- PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---1 1111 ---1 1111 ---u uuuu PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1111 1111 1111 uuuu uuuu PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 111- 1111 111- uuuu uuu- PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1111 1111 1111 uuuu uuuu PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X --11 1111 --11 1111 --uu uuuu PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1111 1111 1111 uuuu uuuu PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---- -111 ---- -111 ---- -uuu PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1111 1111 1111 uuuu uuuu TRISC PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1111 1111 1111 uuuu uuuu TRISB PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1111 1111 1111 uuuu uuuu TRISA PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X --11 1111 --11 1111 --uu uuuu LATJ PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X --xx ---- --uu ---- --uu ---- PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu LATH Legend: Note 1: 2: 3: 4: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). See Table 5-1 for Reset value for specific condition. 2011 Microchip Technology Inc. DS39762F-page 71 PIC18F97J60 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register LATG LATF Applicable Devices Power-on Reset, Brown-out Reset MCLR Reset, WDT Reset, RESET Instruction, Stack Resets, CM Reset Wake-up via WDT or Interrupt ---u ---- PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---x ---- ---u ---- PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---x xxxx ---u uuuu ---u uuuu PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxx- uuuu uuu- uuuu uuu- PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X --xx xxxx --uu uuuu --uu uuuu PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---- -xxx ---- -uuu ---- -uuu PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu LATC PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu LATB PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu LATA PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 00xx xxxx 00uu uuuu uuuu uuuu PORTJ PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X --xx ---- --uu ---- --uu ---- PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu PORTH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu PORTG PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---x ---- ---u ---- ---u ---- PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---x xxxx ---u uuuu ---u uuuu PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 111x xxxx 111u uuuu uuuu uuuu PORTF PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X x000 000- x000 000- uuuu uuu- PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X x000 000- x000 000- uuuu uuu- PORTE PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X --xx xxxx --uu uuuu --uu uuuu PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu PORTD PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---- -xxx ---- -uuu ---- -uuu PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu PORTC PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu PORTB PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu PORTA PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0-0x 0000 0-0u 0000 u-uu uuuu LATE LATD SPBRGH1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu BAUDCON1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0100 0-00 0100 0-00 uuuu u-uu SPBRGH2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu BAUDCON2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0100 0-00 0100 0-00 uuuu u-uu ERDPTH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 1010 ---0 1010 ---u uuuu ERDPTL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 0101 1111 0101 uuuu uuuu ECCP1DEL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu TMR4 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu PR4 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1111 1111 1111 1111 1111 T4CON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X -000 0000 -000 0000 -uuu uuuu CCPR4H PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu CCPR4L PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu Legend: Note 1: 2: 3: 4: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). See Table 5-1 for Reset value for specific condition. DS39762F-page 72 2011 Microchip Technology Inc. PIC18F97J60 FAMILY TABLE 5-2: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Reset, WDT Reset, RESET Instruction, Stack Resets, CM Reset Wake-up via WDT or Interrupt CCP4CON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X --00 0000 --00 0000 --uu uuuu CCPR5H PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu CCPR5L PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu CCP5CON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X --00 0000 --00 0000 --uu uuuu SPBRG2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu RCREG2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu TXREG2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu TXSTA2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0010 0000 0010 uuuu uuuu RCSTA2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 000x 0000 000x uuuu uuuu ECCP3AS PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu ECCP3DEL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu ECCP2AS PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu ECCP2DEL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu SSP2BUF PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu SSP2ADD PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu SSP2STAT PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu SSP2CON1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu SSP2CON2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EDATA PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X xxxx xxxx uuuu uuuu uuuu uuuu EIR PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X -000 0-00 -000 0-00 -uuu u-uu ECON2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 100- ---- 100- ---- uuu- ---- ESTAT PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X -0-0 -000 -0-0 -000 -u-u -uuu EIE PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X -000 0-00 -000 0-00 -uuu u-uu EDMACSH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EDMACSL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EDMADSTH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 0000 ---0 0000 ---u uuuu EDMADSTL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EDMANDH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 0000 ---0 0000 ---u uuuu EDMANDL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EDMASTH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 0000 ---0 0000 ---u uuuu EDMASTL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu ERXWRPTH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 0000 ---0 0000 ---u uuuu ERXWRPTL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu ERXRDPTH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 0101 ---0 0101 ---u uuuu ERXRDPTL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1010 1111 1010 uuuu uuuu ERXNDH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---1 1111 ---1 1111 ---u uuuu ERXNDL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1111 1111 1111 uuuu uuuu ERXSTH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 0101 ---0 0101 ---u uuuu ERXSTL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1111 1010 1111 1010 uuuu uuuu Legend: Note 1: 2: 3: 4: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). See Table 5-1 for Reset value for specific condition. 2011 Microchip Technology Inc. DS39762F-page 73 PIC18F97J60 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices Power-on Reset, Brown-out Reset MCLR Reset, WDT Reset, RESET Instruction, Stack Resets, CM Reset Wake-up via WDT or Interrupt ETXNDH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 0000 ---0 0000 ---u uuuu ETXNDL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu ETXSTH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 0000 ---0 0000 ---u uuuu ETXSTL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EWRPTH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 0000 ---0 0000 ---u uuuu EWRPTL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EPKTCNT PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu ERXFCON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 1010 0001 1010 0001 uuuu uuuu EPMOH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 0000 ---0 0000 ---u uuuu EPMOL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EPMCSH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EPMCSL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EPMM7 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EPMM6 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EPMM5 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EPMM4 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EPMM3 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EPMM2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EPMM1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EPMM0 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EHT7 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EHT6 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EHT5 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EHT4 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EHT3 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EHT2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EHT1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EHT0 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu MIRDH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu MIRDL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu MIWRH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu MIWRL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu MIREGADR PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 0000 ---0 0000 ---u uuuu MICMD PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---- --00 ---- --00 ---- --uu MAMXFLH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0110 0000 0110 uuuu uuuu PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu MAMXFLL Legend: Note 1: 2: 3: 4: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). See Table 5-1 for Reset value for specific condition. DS39762F-page 74 2011 Microchip Technology Inc. PIC18F97J60 FAMILY TABLE 5-2: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Reset, WDT Reset, RESET Instruction, Stack Resets, CM Reset Wake-up via WDT or Interrupt MAIPGH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X -000 0000 -000 0000 -uuu uuuu MAIPGL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X -000 0000 -000 0000 -uuu uuuu MABBIPG PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X -000 0000 -000 0000 -uuu uuuu MACON4 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X -000 --00 -000 --00 -uuu --uu MACON3 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu MACON1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---0 0000 ---0 0000 ---u uuuu EPAUSH PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0001 0000 0001 0000 000u uuuu EPAUSL PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu EFLOCON PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---- -000 ---- -000 ---- -uuu MISTAT PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X ---- 0000 ---- 0000 ---- uuuu MAADR2 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu MAADR1 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu MAADR4 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu MAADR3 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu MAADR6 PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu PIC18F6XJ6X PIC18F8XJ6X PIC18F9XJ6X 0000 0000 0000 0000 uuuu uuuu MAADR5 Legend: Note 1: 2: 3: 4: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). See Table 5-1 for Reset value for specific condition. 2011 Microchip Technology Inc. DS39762F-page 75 PIC18F97J60 FAMILY NOTES: DS39762F-page 76 2011 Microchip Technology Inc. PIC18F97J60 FAMILY MEMORY ORGANIZATION There are two types of memory in PIC18 Flash microcontroller devices: * Program Memory * Data RAM As Harvard architecture devices, the data and program memories use separate busses. This allows for concurrent access of the two memory spaces. Additional detailed information on the operation of the Flash program memory is provided in Section 7.0 "Flash Program Memory". FIGURE 6-1: 6.1 Program Memory Organization PIC18 microcontrollers implement a 21-bit program counter which is capable of addressing a 2-Mbyte program memory space. Accessing a location between the upper boundary of the physically implemented memory and the 2-Mbyte address will return all `0's (a NOP instruction). The entire PIC18F97J60 family offers three sizes of on-chip Flash program memory, from 64 Kbytes (up to 32,764 single-word instructions) to 128 Kbytes (65,532 single-word instructions). The program memory maps for individual family members are shown in Figure 6-1. MEMORY MAPS FOR PIC18F97J60 FAMILY DEVICES PC<20:0> CALL, CALLW, RCALL, RETURN, RETFIE, RETLW, ADDULNK, SUBULNK 21 Stack Level 1 Stack Level 31 PIC18FX6J60 PIC18FX6J65 PIC18FX7J60 On-Chip Memory On-Chip Memory On-Chip Memory Config. Words 00FFFFh Config. Words 017FFFh Config. Words Unimplemented Read as `0' 000000h Unimplemented Read as `0' 01FFFFh User Memory Space 6.0 Unimplemented Read as `0' 1FFFFFh Note: Sizes of memory areas are not to scale. Sizes of program memory areas are enhanced to show detail. 2011 Microchip Technology Inc. DS39762F-page 77 PIC18F97J60 FAMILY 6.1.1 HARD MEMORY VECTORS 6.1.2 FLASH CONFIGURATION WORDS All PIC18 devices have a total of three hard-coded return vectors in their program memory space. The Reset vector address is the default value to which the program counter returns on all device Resets; it is located at 0000h. Because the PIC18F97J60 family devices do not have persistent configuration memory, the top four words of on-chip program memory are reserved for configuration information. On Reset, the configuration information is copied into the Configuration registers. PIC18 devices also have two interrupt vector addresses for the handling of high-priority and low-priority interrupts. The high-priority interrupt vector is located at 0008h and the low-priority interrupt vector is at 0018h. Their locations in relation to the program memory map are shown in Figure 6-2. The Configuration Words are stored in their program memory location in numerical order, starting with the lower byte of CONFIG1 at the lowest address and ending with the upper byte of CONFIG4. For these devices, only Configuration Words, CONFIG1 through CONFIG3, are used; CONFIG4 is reserved. The actual addresses of the Flash Configuration Words for devices in the PIC18F97J60 family are shown in Table 6-1. Their location in the memory map is shown with the other memory vectors in Figure 6-2. FIGURE 6-2: HARD VECTOR AND CONFIGURATION WORD LOCATIONS FOR PIC18F97J60 FAMILY DEVICES Reset Vector 0000h High-Priority Interrupt Vector 0008h Low-Priority Interrupt Vector 0018h Additional details on the device Configuration Words are provided in Section 25.1 "Configuration Bits". TABLE 6-1: Device FLASH CONFIGURATION WORDS FOR PIC18F97J60 FAMILY DEVICES Program Memory (Kbytes) Configuration Word Addresses 64 FFF8h to FFFFh 96 17FF8h to 17FFFh 128 1FFF8h to 1FFFFh PIC18F66J60 On-Chip Program Memory PIC18F86J60 PIC18F96J60 PIC18F66J65 PIC18F86J65 PIC18F96J65 Flash Configuration Words (Top of Memory-7) (Top of Memory) PIC18F67J60 PIC18F87J60 PIC18F97J60 Read as `0' 1FFFFFh Legend: (Top of Memory) represents upper boundary of on-chip program memory space (see Figure 6-1 for device-specific values). Shaded area represents unimplemented memory. Areas are not shown to scale. DS39762F-page 78 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 6.1.3 PIC18F9XJ60/9XJ65 PROGRAM MEMORY MODES The 100-pin devices in this family can address up to a total of 2 Mbytes of program memory. This is achieved through the external memory bus. There are two distinct operating modes available to the controllers: * Microcontroller (MC) * Extended Microcontroller (EMC) The program memory mode is determined by setting the EMB Configuration bits (CONFIG3L<5:4>), as shown in Register 6-1. (Also see Section 25.1 "Configuration Bits" for additional details on the device Configuration bits). The program memory modes operate as follows: * The Microcontroller Mode accesses only on-chip Flash memory. Attempts to read above the top of on-chip memory causes a read of all `0's (a NOP instruction). The Microcontroller mode is also the only operating mode available to 64-pin and 80-pin devices. REGISTER 6-1: * The Extended Microcontroller Mode allows access to both internal and external program memories as a single block. The device can access its entire on-chip program memory. Above this, the device accesses external program memory up to the 2-Mbyte program space limit. Execution automatically switches between the two memories as required. The setting of the EMB Configuration bits also controls the address bus width of the external memory bus. This is covered in more detail in Section 8.0 "External Memory Bus". In all modes, the microcontroller has complete access to data RAM. Figure 6-3 compares the memory maps of the different program memory modes. The differences between on-chip and external memory access limitations are more fully explained in Table 6-2. CONFIG3L: CONFIGURATION REGISTER 3 LOW R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 U-0 U-0 U-0 WAIT(1) BW(1) EMB1(1) EMB0(1) EASHFT(1) -- -- -- bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit -n = Value when device is unprogrammed U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared bit 7 WAIT: External Bus Wait Enable bit(1) 1 = Wait states for operations on external memory bus are disabled 0 = Wait states for operations on external memory bus are enabled and selected by MEMCON<5:4> bit 6 BW: Data Bus Width Select bit(1) 1 = 16-Bit Data Width mode 0 = 8-Bit Data Width mode bit 5-4 EMB<1:0>: External Memory Bus Configuration bits(1) 11 = Microcontroller mode, external bus disabled 10 = Extended Microcontroller mode,12-Bit Addressing mode 01 = Extended Microcontroller mode,16-Bit Addressing mode 00 = Extended Microcontroller mode, 20-Bit Addressing mode bit 3 EASHFT: External Address Bus Shift Enable bit(1) 1 = Address shifting is enabled; address on external bus is offset to start at 000000h 0 = Address shifting is disabled; address on external bus reflects the PC value bit 2-0 Unimplemented: Read as `0' Note 1: Implemented on 100-pin devices only. 2011 Microchip Technology Inc. DS39762F-page 79 PIC18F97J60 FAMILY 6.1.4 EXTENDED MICROCONTROLLER MODE AND ADDRESS SHIFTING To avoid this, the Extended Microcontroller mode implements an address shifting option to enable automatic address translation. In this mode, addresses presented on the external bus are shifted down by the size of the on-chip program memory and are remapped to start at 0000h. This allows the complete use of the external memory device's memory space. By default, devices in Extended Microcontroller mode directly present the program counter value on the external address bus for those addresses in the range of the external memory space. In practical terms, this means addresses in the external memory device below the top of on-chip memory are unavailable. FIGURE 6-3: MEMORY MAPS FOR PIC18F97J60 FAMILY PROGRAM MEMORY MODES Microcontroller Mode(1) On-Chip Memory Space Extended Microcontroller Mode(2) External Memory Space On-Chip Memory Space No Access Note 1: 2: 000000h (Top of Memory) (Top of Memory) + 1 External Memory (Top of Memory) (Top of Memory) + 1 External Memory Mapped to External Memory Space Mapped to External Memory Space 1FFFFFh - (Top of Memory) 1FFFFFh 1FFFFFh 1FFFFFh Legend: On-Chip Memory Space On-Chip Program Memory On-Chip Program Memory (Top of Memory) (Top of Memory) + 1 Reads `0's External Memory Space 000000h 000000h On-Chip Program Memory Extended Microcontroller Mode with Address Shifting(2) (Top of Memory) represents upper boundary of on-chip program memory space (see Figure 6-1 for device-specific values). Shaded areas represent unimplemented or inaccessible areas depending on the mode. This mode is the only available mode on 64-pin and 80-pin devices and the default on 100-pin devices. These modes are only available in 100-pin devices. TABLE 6-2: MEMORY ACCESS FOR PIC18F9XJ60/9XJ65 PROGRAM MEMORY MODES Internal Program Memory Operating Mode External Program Memory Execution From Table Read From Table Write To Execution From Table Read From Table Write To Microcontroller Yes Yes Yes No Access No Access No Access Extended Microcontroller Yes Yes Yes Yes Yes Yes DS39762F-page 80 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 6.1.5 PROGRAM COUNTER The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21 bits wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC<15:8> bits; it is not directly readable or writable. Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU. This register contains the PC<20:16> bits; it is also not directly readable or writable. Updates to the PCU register are performed through the PCLATU register. The contents of PCLATH and PCLATU are transferred to the program counter by any operation that writes to the PCL. Similarly, the upper two bytes of the program counter are transferred to PCLATH and PCLATU by an operation that reads PCL. This is useful for computed offsets to the PC (see Section 6.1.8.1 "Computed GOTO"). The PC addresses bytes in the program memory. To prevent the PC from becoming misaligned with word instructions, the Least Significant bit of PCL is fixed to a value of `0'. The PC increments by 2 to address sequential instructions in the program memory. The CALL, RCALL, GOTO and program branch instructions write to the program counter directly. For these instructions, the contents of PCLATH and PCLATU are not transferred to the program counter. 6.1.6 RETURN ADDRESS STACK The return address stack allows any combination of up to 31 program calls and interrupts to occur. The PC is pushed onto the stack when a CALL or RCALL instruction is executed, or an interrupt is Acknowledged. The PC value is pulled off the stack on a RETURN, RETLW or a RETFIE instruction (and on ADDULNK and SUBULNK instructions if the extended instruction set is enabled). PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions. FIGURE 6-4: The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stack space is not part of either program or data space. The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through the Top-of-Stack Special Function Registers. Data can also be pushed to, or popped from the stack, using these registers. A CALL type instruction causes a push onto the stack. The Stack Pointer is first incremented and the location pointed to by the Stack Pointer is written with the contents of the PC (already pointing to the instruction following the CALL). A RETURN type instruction causes a pop from the stack. The contents of the location pointed to by the STKPTR are transferred to the PC and then the Stack Pointer is decremented. The Stack Pointer is initialized to `00000' after all Resets. There is no RAM associated with the location corresponding to a Stack Pointer value of `00000'; this is only a Reset value. Status bits indicate if the stack is full, has overflowed or has underflowed. 6.1.6.1 Top-of-Stack Access Only the top of the return address stack (TOS) is readable and writable. A set of three registers, TOSU:TOSH:TOSL, holds the contents of the stack location pointed to by the STKPTR register (Figure 6-4). This allows users to implement a software stack if necessary. After a CALL, RCALL or interrupt (and ADDULNK and SUBULNK instructions if the extended instruction set is enabled), the software can read the pushed value by reading the TOSU:TOSH:TOSL registers. These values can be placed on a user-defined software stack. At return time, the software can return these values to TOSU:TOSH:TOSL and do a return. The user must disable the Global Interrupt Enable bits while accessing the stack to prevent inadvertent stack corruption. RETURN ADDRESS STACK AND ASSOCIATED REGISTERS Return Address Stack <20:0> Stack Pointer Top-of-Stack Registers TOSU 00h TOSH 1Ah TOSL 34h Top-of-Stack 2011 Microchip Technology Inc. 11111 11110 11101 001A34h 000D58h STKPTR<4:0> 00010 00011 00010 00001 00000 DS39762F-page 81 PIC18F97J60 FAMILY 6.1.6.2 Return Stack Pointer (STKPTR) When the stack has been popped enough times to unload the stack, the next pop returns a value of zero to the PC, and sets the STKUNF bit, while the Stack Pointer remains at zero. The STKUNF bit will remain set until cleared by software or until a POR occurs. The STKPTR register (Register 6-2) contains the Stack Pointer value, the STKFUL (Stack Full) status bit and the STKUNF (Stack Underflow) status bit. The value of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the stack and decrements after values are popped off the stack. On Reset, the Stack Pointer value will be zero. The user may read and write the Stack Pointer value. This feature can be used by a Real-Time Operating System (RTOS) for return stack maintenance. Note: After the PC is pushed onto the stack 31 times (without popping any values off the stack), the STKFUL bit is set. The STKFUL bit is cleared by software or by a POR. 6.1.6.3 PUSH and POP Instructions Since the Top-of-Stack is readable and writable, the ability to push values onto the stack and pull values off the stack, without disturbing normal program execution, is a desirable feature. The PIC18 instruction set includes two instructions, PUSH and POP, that permit the TOS to be manipulated under software control. TOSU, TOSH and TOSL can be modified to place data or a return address on the stack. The action that takes place when the stack becomes full depends on the state of the STVREN (Stack Overflow Reset Enable) Configuration bit. (Refer to Section 25.1 "Configuration Bits" for a description of the device Configuration bits.) If STVREN is set (default), the 31st push will push the (PC + 2) value onto the stack, set the STKFUL bit and reset the device. The STKFUL bit will remain set and the Stack Pointer will be set to zero. The PUSH instruction places the current PC value onto the stack. This increments the Stack Pointer and loads the current PC value onto the stack. If STVREN is cleared, the STKFUL bit will be set on the 31st push and the Stack Pointer will increment to 31. Any additional pushes will not overwrite the 31st push and the STKPTR will remain at 31. REGISTER 6-2: Returning a value of zero to the PC on an underflow has the effect of vectoring the program to the Reset vector, where the stack conditions can be verified and appropriate actions can be taken. This is not the same as a Reset, as the contents of the SFRs are not affected. The POP instruction discards the current TOS by decrementing the Stack Pointer. The previous value pushed onto the stack then becomes the TOS value. STKPTR: STACK POINTER REGISTER R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STKFUL(1) STKUNF(1) -- SP4 SP3 SP2 SP1 SP0 bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 STKFUL: Stack Full Flag bit(1) 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed bit 6 STKUNF: Stack Underflow Flag bit(1) 1 = Stack underflow occurred 0 = Stack underflow did not occur bit 5 Unimplemented: Read as `0' bit 4-0 SP<4:0>: Stack Pointer Location bits Note 1: x = Bit is unknown Bit 7 and bit 6 are cleared by user software or by a POR. DS39762F-page 82 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 6.1.6.4 Stack Full and Underflow Resets Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in Configuration Register 1L. When STVREN is set, a full or underflow condition will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. When STVREN is cleared, a full or underflow condition will set the appropriate STKFUL or STKUNF bit, but not cause a device Reset. The STKFUL or STKUNF bit is cleared by user software or a Power-on Reset. 6.1.7 FAST REGISTER STACK A Fast Register Stack (FSR) is provided for the STATUS, WREG and BSR registers to provide a "fast return" option for interrupts. This stack is only one level deep and is neither readable nor writable. It is loaded with the current value of the corresponding register when the processor vectors for an interrupt. All interrupt sources will push values into the Stack registers. The values in the registers are then loaded back into the working registers if the RETFIE, FAST instruction is used to return from the interrupt. 6.1.8 LOOK-UP TABLES IN PROGRAM MEMORY There may be programming situations that require the creation of data structures, or look-up tables, in program memory. For PIC18 devices, look-up tables can be implemented in two ways: * Computed GOTO * Table Reads 6.1.8.1 Computed GOTO A computed GOTO is accomplished by adding an offset to the program counter. An example is shown in Example 6-2. A look-up table can be formed with an ADDWF PCL instruction and a group of RETLW nn instructions. The W register is loaded with an offset into the table before executing a call to that table. The first instruction of the called routine is the ADDWF PCL instruction. The next instruction executed will be one of the RETLW nn instructions, that returns the value `nn' to the calling function. If both low and high-priority interrupts are enabled, the Stack registers cannot be used reliably to return from low-priority interrupts. If a high-priority interrupt occurs while servicing a low-priority interrupt, the Stack register values stored by the low-priority interrupt will be overwritten. In these cases, users must save the key registers in software during a low-priority interrupt. The offset value (in WREG) specifies the number of bytes that the program counter should advance and should be multiples of 2 (LSb = 0). If interrupt priority is not used, all interrupts may use the Fast Register Stack for returns from interrupt. If no interrupts are used, the Fast Register Stack can be used to restore the STATUS, WREG and BSR registers at the end of a subroutine call. To use the Fast Register Stack for a subroutine call, a CALL label, FAST instruction must be executed to save the STATUS, WREG and BSR registers to the Fast Register Stack. A RETURN, FAST instruction is then executed to restore these registers from the Fast Register Stack. EXAMPLE 6-2: Example 6-1 shows a source code example that uses the Fast Register Stack during a subroutine call and return. EXAMPLE 6-1: CALL SUB1, FAST FAST REGISTER STACK CODE EXAMPLE ;STATUS, WREG, BSR ;SAVED IN FAST REGISTER ;STACK SUB1 RETURN FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK 2011 Microchip Technology Inc. In this method, only one data byte may be stored in each instruction location and room on the return address stack is required. ORG TABLE 6.1.8.2 MOVF CALL nn00h ADDWF RETLW RETLW RETLW . . . COMPUTED GOTO USING AN OFFSET VALUE OFFSET, W TABLE PCL nnh nnh nnh Table Reads A better method of storing data in program memory allows two bytes of data to be stored in each instruction location. Look-up table data may be stored, two bytes per program word, while programming. The Table Pointer (TBLPTR) specifies the byte address and the Table Latch (TABLAT) contains the data that is read from the program memory. Data is transferred from program memory, one byte at a time. Table read operation is discussed further Section 7.1 "Table Reads and Table Writes". in DS39762F-page 83 PIC18F97J60 FAMILY 6.2 6.2.2 PIC18 Instruction Cycle 6.2.1 An "Instruction Cycle" consists of four Q cycles, Q1 through Q4. The instruction fetch and execute are pipelined in such a manner that a fetch takes one instruction cycle, while the decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO), then two cycles are required to complete the instruction (Example 6-3). CLOCKING SCHEME The microcontroller clock input, whether from an internal or external source, is internally divided by four to generate four non-overlapping quadrature clocks (Q1, Q2, Q3 and Q4). Internally, the program counter is incremented on every Q1. The instruction is fetched from the program memory and latched into the Instruction Register (IR) during Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow are shown in Figure 6-5. FIGURE 6-5: INSTRUCTION FLOW/PIPELINING A fetch cycle begins with the Program Counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q2 Q1 Q3 Q4 OSC1 Q1 Q2 Internal Phase Clock Q3 Q4 PC PC PC + 2 PC + 4 OSC2/CLKO (RC mode) Execute INST (PC - 2) Fetch INST (PC) EXAMPLE 6-3: 1. MOVLW 55h 4. BSF Execute INST (PC + 2) Fetch INST (PC + 4) INSTRUCTION PIPELINE FLOW TCY0 TCY1 Fetch 1 Execute 1 2. MOVWF PORTB 3. BRA Execute INST (PC) Fetch INST (PC + 2) SUB_1 PORTA, BIT3 (Forced NOP) 5. Instruction @ address SUB_1 Fetch 2 TCY2 TCY3 TCY4 TCY5 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush (NOP) Fetch SUB_1 Execute SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is "flushed" from the pipeline while the new instruction is being fetched and then executed. DS39762F-page 84 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 6.2.3 INSTRUCTIONS IN PROGRAM MEMORY The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program memory. The Least Significant Byte (LSB) of an instruction word is always stored in a program memory location with an even address (LSb = 0). To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSb will always read `0' (see Section 6.1.5 "Program Counter"). Figure 6-6 shows an example of how instruction words are stored in the program memory. FIGURE 6-6: INSTRUCTIONS IN PROGRAM MEMORY Program Memory Byte Locations 6.2.4 The CALL and GOTO instructions have the absolute program memory address embedded into the instruction. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC<20:1> which accesses the desired byte address in program memory. Instruction #2 in Figure 6-6 shows how the instruction, GOTO 0006h, is encoded in the program memory. Program branch instructions, which encode a relative address offset, operate in the same manner. The offset value stored in a branch instruction represents the number of single-word instructions that the PC will be offset by. Section 26.0 "Instruction Set Summary" provides further details of the instruction set. Instruction 1: Instruction 2: MOVLW GOTO 055h 0006h Instruction 3: MOVFF 123h, 456h TWO-WORD INSTRUCTIONS The standard PIC18 instruction set has four, two-word instructions: CALL, MOVFF, GOTO and LSFR. In all cases, the second word of the instructions always has `1111' as its four Most Significant bits (MSbs); the other 12 bits are literal data, usually a data memory address. The use of `1111' in the 4 MSbs of an instruction specifies a special form of NOP. If the instruction is executed in proper sequence, immediately after the first word, the data in the second word is accessed and EXAMPLE 6-4: LSB = 1 LSB = 0 0Fh EFh F0h C1h F4h 55h 03h 00h 23h 56h Word Address 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h used by the instruction sequence. If the first word is skipped, for some reason, and the second word is executed by itself, a NOP is executed instead. This is necessary for cases when the two-word instruction is preceded by a conditional instruction that changes the PC. Example 6-4 shows how this works. Note: See Section 6.5 "Program Memory and the Extended Instruction Set" for information on two-word instructions in the extended instruction set. TWO-WORD INSTRUCTIONS CASE 1: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word ADDWF REG3 ; continue code 1111 0100 0101 0110 0010 0100 0000 0000 ; Execute this word as a NOP CASE 2: Object Code Source Code 0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0? 1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, execute this word 1111 0100 0101 0110 0010 0100 0000 0000 2011 Microchip Technology Inc. ; 2nd word of instruction ADDWF REG3 ; continue code DS39762F-page 85 PIC18F97J60 FAMILY 6.3 Note: Data Memory Organization The operation of some aspects of data memory is changed when the PIC18 extended instruction set is enabled. See Section 6.6 "Data Memory and the Extended Instruction Set" for more information. The data memory in PIC18 devices is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of addressable memory. The memory space is divided into 16 banks that contain 256 bytes each. All of the PIC18F97J60 family devices implement all available banks and provide 3808 bytes of data memory available to the user. Figure 6-7 shows the data memory organization for the devices. The data memory contains Special Function Registers (SFRs) and General Purpose Registers (GPRs). The SFRs are used for control and status of the controller and peripheral functions, while GPRs are used for data storage and scratchpad operations in the user's application. Any read of an unimplemented location will read as `0's. The instruction set and architecture allow operations across all banks. The entire data memory may be accessed by Direct, Indirect or Indexed Addressing modes. Addressing modes are discussed later in this section. To ensure that commonly used registers (most SFRs and select GPRs) can be accessed in a single cycle, PIC18 devices implement an Access Bank. This is a 256-byte memory space that provides fast access to the majority of SFRs and the lower portion of GPR Bank 0 without using the BSR. Section 6.3.2 "Access Bank" provides a detailed description of the Access RAM. 6.3.1 BANK SELECT REGISTER Large areas of data memory require an efficient addressing scheme to make rapid access to any address possible. Ideally, this means that an entire address does not need to be provided for each read or write operation. For PIC18 devices, this is accomplished with a RAM banking scheme. This divides the memory space into 16 contiguous banks of 256 bytes. Depending on the instruction, each location can be addressed directly by its full 12-bit address, or an 8-bit low-order address and a 4-bit Bank Pointer. Most instructions in the PIC18 instruction set make use of the Bank Pointer, known as the Bank Select Register (BSR). This SFR holds the 4 Most Significant bits of a location's address; the instruction itself includes the 8 Least Significant bits (LSbs). Only the four lower bits of the BSR are implemented (BSR3:BSR0). The upper four bits are unused; they will always read `0' and cannot be written to. The BSR can be loaded directly by using the MOVLB instruction. The value of the BSR indicates the bank in data memory. The 8 bits in the instruction show the location in the bank and can be thought of as an offset from the bank's lower boundary. The relationship between the BSR's value and the bank division in data memory is shown in Figure 6-8. Since up to 16 registers may share the same low-order address, the user must always be careful to ensure that the proper bank is selected before performing a data read or write. For example, writing what should be program data to an 8-bit address of F9h, while the BSR is 0Fh, will end up resetting the program counter. While any bank can be selected, only those banks that are actually implemented can be read or written to. Writes to unimplemented banks are ignored, while reads from unimplemented banks will return `0's. Even so, the STATUS register will still be affected as if the operation was successful. The data memory map in Figure 6-7 indicates which banks are implemented. In the core PIC18 instruction set, only the MOVFF instruction fully specifies the 12-bit address of the source and target registers. This instruction ignores the BSR completely when it executes. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers. DS39762F-page 86 2011 Microchip Technology Inc. PIC18F97J60 FAMILY FIGURE 6-7: DATA MEMORY MAP FOR PIC18F97J60 FAMILY DEVICES When a = 0: BSR<3:0> Data Memory Map 00h = 0000 = 0001 = 0010 = 0011 = 0100 = 0101 = 0110 = 0111 = 1000 = 1001 = 1010 = 1011 = 1100 = 1101 = 1110 = 1111 Bank 0 FFh 00h Bank 1 Access RAM GPR GPR 1FFh 200h FFh 00h Bank 2 GPR FFh 00h Bank 3 2FFh 300h Bank 4 The remaining 160 bytes are Special Function Registers (from Bank 15). When a = 1: The BSR specifies the bank used by the instruction. 3FFh 400h GPR FFh 00h 4FFh 500h GPR Bank 5 FFh 00h 5FFh 600h GPR Bank 6 FFh 00h 6FFh 700h GPR Bank 7 FFh 00h FFh 00h Bank 9 7FFh 800h FFh 00h Bank 10 GPR GPR FFh 00h GPR FFh 00h Bank 12 FFh 00h Bank 13 FFh 00h Bank 14 GPR GPR GPR FFh 00h Ethernet SFR FFh SFR Bank 15 GPR Access Bank Access RAM Low GPR Bank 8 2011 Microchip Technology Inc. The first 96 bytes are general purpose RAM (from Bank 0). GPR FFh 00h Bank 11 000h 05Fh 060h 0FFh 100h The BSR is ignored and the Access Bank is used. 00h 5Fh Access RAM High 60h (SFRs) FFh 8FFh 900h 9FFh A00h AFFh B00h BFFh C00h CFFh D00h DFFh E00h E7Fh E80h EFFh F00h F5Fh F60h FFFh DS39762F-page 87 PIC18F97J60 FAMILY FIGURE 6-8: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) BSR(1) 7 0 0 0 0 0 0 0 Bank Select(2) 1 0 000h Data Memory Bank 0 100h Bank 1 200h 300h Bank 2 00h 7 FFh 00h 11 From Opcode(2) 11 11 11 11 1 0 1 1 FFh 00h FFh 00h Bank 3 through Bank 13 E00h Bank 14 F00h FFFh Note 1: 2: 6.3.2 Bank 15 FFh 00h FFh The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR3:BSR0) to the registers of the Access Bank. The MOVFF instruction embeds the entire 12-bit address in the instruction. ACCESS BANK While the use of the BSR with an embedded 8-bit address allows users to address the entire range of data memory, it also means that the user must always ensure that the correct bank is selected. Otherwise, data may be read from or written to the wrong location. This can be disastrous if a GPR is the intended target of an operation but an SFR is written to instead. Verifying and/or changing the BSR for each read or write to data memory can become very inefficient. To streamline access for the most commonly used data memory locations, the data memory is configured with an Access Bank, which allows users to access a mapped block of memory without specifying a BSR. The Access Bank consists of the first 96 bytes of memory (00h-5Fh) in Bank 0 and the last 160 bytes of memory (60h-FFh) in Bank 15. The lower block is known as the "Access RAM" and is composed of GPRs. The upper block is where the device's SFRs are mapped. These two areas are mapped contiguously in the Access Bank and can be addressed in a linear fashion by an 8-bit address (Figure 6-7). The Access Bank is used by core PIC18 instructions that include the Access RAM bit (the `a' parameter in the instruction). When `a' is equal to `1', the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When `a' is `0', however, the instruction is forced to use the Access Bank address map; the current value of the BSR is ignored entirely. DS39762F-page 88 FFh 00h Using this "forced" addressing allows the instruction to operate on a data address in a single cycle without updating the BSR first. For 8-bit addresses of 60h and above, this means that users can evaluate and operate on SFRs more efficiently. The Access RAM below 60h is a good place for data values that the user might need to access rapidly, such as immediate computational results or common program variables. Access RAM also allows for faster and more code efficient context saving and switching of variables. The mapping of the Access Bank is slightly different when the extended instruction set is enabled (XINST Configuration bit = 1). This is discussed in more detail in Section 6.6.3 "Mapping the Access Bank in Indexed Literal Offset Mode". 6.3.3 GENERAL PURPOSE REGISTER FILE PIC18 devices may have banked memory in the GPR area. This is data RAM which is available for use by all instructions. GPRs start at the bottom of Bank 0 (address 000h) and grow upwards towards the bottom of the SFR area. GPRs are not initialized by a Power-on Reset and are unchanged on all other Resets. 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 6.3.4 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. The main group of SFRs start at the top of data memory (FFFh) and extend downward to occupy more than the top half of Bank 15 (F60h to FFFh). These SFRs can be classified into two sets: those associated with the "core" device functionality (ALU, Resets and interrupts) and those related to the peripheral functions. The TABLE 6-3: Reset and Interrupt registers are described in their respective chapters, while the ALU's STATUS register is described later in this section. Registers related to the operation of the peripheral features are described in the chapter for that peripheral. The SFRs are typically distributed among the peripherals whose functions they control. Unused SFR locations are unimplemented and read as `0's. A list of SFRs is given in Table 6-3; a full description is provided in Table 6-5. SPECIAL FUNCTION REGISTER MAP FOR PIC18F97J60 FAMILY DEVICES Address Name Address FFFh TOSU FDFh Name FFEh TOSH FDEh POSTINC2(1) FBEh FFDh TOSL FDDh POSTDEC2(1) FBDh FFCh STKPTR FDCh PREINC2(1) FBCh FFBh PCLATU FDBh PLUSW2(1) FBBh INDF2(1) Address FBFh Name Address Name Address F9Fh IPR1 F7Fh SPBRGH1 CCPR1L F9Eh PIR1 F7Eh BAUDCON1 CCP1CON F9Dh PIE1 F7Dh SPBRGH2 CCPR2H F9Ch MEMCON(4) F7Ch BAUDCON2 CCPR2L F9Bh OSCTUNE F7Bh ERDPTH F7Ah ERDPTL F79h ECCP1DEL CCPR1H FFAh PCLATH FDAh FSR2H FBAh CCP2CON F9Ah TRISJ(3) FF9h PCL FD9h FSR2L FB9h CCPR3H F99h TRISH(3) Name FF8h TBLPTRU FD8h STATUS FB8h CCPR3L F98h TRISG F78h TMR4 FF7h TBLPTRH FD7h TMR0H FB7h CCP3CON F97h TRISF F77h PR4 FF6h TBLPTRL FD6h TMR0L FB6h ECCP1AS F96h TRISE F76h T4CON FF5h TABLAT FD5h T0CON FB5h CVRCON F95h TRISD F75h CCPR4H FF4h PRODH FD4h --(2) FB4h CMCON F94h TRISC F74h CCPR4L FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB F73h CCP4CON FF2h INTCON FD2h ECON1 FB2h TMR3L F92h TRISA F72h CCPR5H FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h LATJ(3) F71h CCPR5L FF0h INTCON3 FD0h RCON FB0h PSPCON F90h LATH(3) F70h CCP5CON FEFh INDF0(1) FCFh TMR1H FAFh SPBRG1 F8Fh LATG F6Fh SPBRG2 (1) FCEh TMR1L FAEh RCREG1 F8Eh LATF F6Eh RCREG2 FEDh POSTDEC0(1) FCDh T1CON FADh TXREG1 F8Dh LATE F6Dh TXREG2 FEEh POSTINC0 FECh PREINC0(1) FCCh TMR2 FACh TXSTA1 F8Ch LATD F6Ch TXSTA2 FEBh PLUSW0(1) FCBh PR2 FABh RCSTA1 F8Bh LATC F6Bh RCSTA2 FEAh FSR0H FCAh T2CON FAAh --(2) F8Ah LATB F6Ah ECCP3AS FE9h FSR0L FC9h SSP1BUF FA9h --(2) F89h LATA F69h ECCP3DEL FE8h WREG FC8h SSP1ADD FA8h --(2) F88h PORTJ(3) F68h ECCP2AS F87h PORTH(3) F67h ECCP2DEL FE7h INDF1 (1) FC7h SSP1STAT FA7h EECON2 (1) POSTINC1(1) FC6h SSP1CON1 FA6h EECON1 F86h PORTG F66h SSP2BUF FE5h POSTDEC1(1) FC5h SSP1CON2 FA5h IPR3 F85h PORTF F65h SSP2ADD FE6h FE4h PREINC1(1) FC4h ADRESH FA4h PIR3 F84h PORTE F64h SSP2STAT FE3h PLUSW1(1) FC3h ADRESL FA3h PIE3 F83h PORTD F63h SSP2CON1 FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC F62h SSP2CON2 FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB F61h EDATA FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA F60h EIR Note 1: 2: 3: 4: This is not a physical register. Unimplemented registers are read as `0'. This register is not available in 64-pin devices. This register is not available in 64 and 80-pin devices. 2011 Microchip Technology Inc. DS39762F-page 89 PIC18F97J60 FAMILY 6.3.5 ETHERNET SFRs Note: In addition to the standard SFR set in Bank 15, members of the PIC18F97J60 family have a second set of SFRs. This group, associated exclusively with the Ethernet module, occupies the top half of Bank 14 (E80h to EFFh). TABLE 6-4: To improve performance, frequently accessed Ethernet registers are located in the standard SFR bank (F60h through FFFh). A complete list of Ethernet SFRs is given in Table 6-4. All SFRs are fully described in Table 6-5. ETHERNET SFR MAP FOR PIC18F97J60 FAMILY DEVICES Address Name EFFh -- (1) Address Name (1) -- E9Fh --(1) EBEh --(1) E9Eh --(1) EBDh --(1) E9Dh --(1) EBCh -- (1) E9Ch --(1) EBBh --(1) E9Bh --(1) EBAh (1) E9Ah --(1) MIRDH E99h EPAUSH EDEh EFDh ESTAT EDDh --(1) EDCh -- (1) -- Name EBFh ECON2 (1) Address -- EFEh EFCh Name EDFh --(1) (1) Address EFBh EIE EDBh --(1) EFAh -- (1) EDAh (1) EF9h --(2) ED9h EPKTCNT EB9h EF8h --(2) ED8h ERXFCON EB8h MIRDL E98h EPAUSL EF7h EDMACSH ED7h --(1) EB7h MIWRH E97h EFLOCON EF6h EDMACSL ED6h --(1) EB6h MIWRL E96h --(2) EF5h EDMADSTH ED5h EPMOH EB5h --(1) E95h --(2) EF4h EDMADSTL ED4h EPMOL EB4h MIREGADR E94h --(2) ED3h --(2) EB3h --(2) E93h --(2) (2) EB2h MICMD E92h --(2) EB1h --(1) E91h --(2) EB0h --(1) E90h --(2) EAFh -- (2) E8Fh --(2) (1) E8Eh --(2) EF3h EDMANDH EF2h EDMANDL ED2h EF1h EDMASTH ED1h EF0h EEFh EDMASTL ERXWRPTH ED0h ECFh -- -- EPMCSH EPMCSL EPMM7 -- EEEh ERXWRPTL ECEh EPMM6 EAEh -- EEDh ERXRDPTH ECDh EPMM5 EADh --(1) E8Dh --(2) (1) E8Ch --(2) EECh ERXRDPTL ECCh EPMM4 EACh -- EEBh ERXNDH ECBh EPMM3 EABh MAMXFLH E8Bh --(2) EEAh ERXNDL ECAh EPMM2 EAAh MAMXFLL E8Ah MISTAT EE9h ERXSTH EC9h EPMM1 EA9h --(1) E89h --(1) (1) E88h --(1) EE8h ERXSTL EC8h EPMM0 EA8h EE7h ETXNDH EC7h EHT7 EA7h MAIPGH E87h --(1) EE6h ETXNDL EC6h EHT6 EA6h MAIPGL E86h --(1) EE5h ETXSTH EC5h EHT5 EA5h --(2) E85h MAADR2 EE4h ETXSTL EC4h EHT4 EA4h MABBIPG E84h MAADR1 EE3h EWRPTH EC3h EHT3 EA3h MACON4 E83h MAADR4 EE2h EWRPTL EC2h EHT2 EA2h MACON3 E82h MAADR3 EE1h --(1) EC1h EHT1 EA1h --(1) E81h MAADR6 EE0h --(1) EC0h EHT0 EA0h MACON1 E80h MAADR5 Note 1: 2: -- Reserved register location; do not modify. Unimplemented registers are read as `0'. DS39762F-page 90 2011 Microchip Technology Inc. PIC18F97J60 FAMILY TABLE 6-5: File Name TOSU REGISTER FILE SUMMARY (PIC18F97J60 FAMILY) Bit 7 Bit 6 Bit 5 -- -- -- Bit 4 Top-of-Stack Register High Byte (TOS<15:8>) TOSL Top-of-Stack Register Low Byte (TOS<7:0>) STKPTR STKFUL(1) STKUNF(1) -- PCLATU -- -- bit 21(2) Holding Register for PC<15:8> PCL PC Low Byte (PC<7:0>) TBLPTRU -- -- bit 21 Bit 2 Bit 1 Bit 0 Top-of-Stack Register Upper Byte (TOS<20:16>) TOSH PCLATH Bit 3 SP4 SP3 SP2 SP1 SP0 Holding Register for PC<20:16> Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) Values on Details on POR, BOR Page: ---0 0000 69, 81 0000 0000 69, 81 0000 0000 69, 81 00-0 0000 69, 82 ---0 0000 69, 81 0000 0000 69, 81 0000 0000 69, 81 --00 0000 69, 108 TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 69, 108 TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 69, 108 TABLAT Program Memory Table Latch 0000 0000 69, 108 PRODH Product Register High Byte xxxx xxxx 69, 127 PRODL Product Register Low Byte INTCON RBIF xxxx xxxx 69, 127 0000 000x 69, 131 GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 1111 1111 69, 132 INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF 1100 0000 69, 133 INDF0 Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register) N/A 69, 99 POSTINC0 Uses contents of FSR0 to address data memory - value of FSR0 post-incremented (not a physical register) N/A 69, 100 POSTDEC0 Uses contents of FSR0 to address data memory - value of FSR0 post-decremented (not a physical register) N/A 69, 100 PREINC0 Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) N/A 69, 100 PLUSW0 Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) - value of FSR0 offset by W N/A 69, 100 FSR0H ---- xxxx 69, 99 FSR0L Indirect Data Memory Address Pointer 0 Low Byte -- -- -- -- Indirect Data Memory Address Pointer 0 High Byte xxxx xxxx 69, 100 WREG Working Register xxxx xxxx 69 INDF1 Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register) N/A 69, 99 POSTINC1 Uses contents of FSR1 to address data memory - value of FSR1 post-incremented (not a physical register) N/A 69, 100 POSTDEC1 Uses contents of FSR1 to address data memory - value of FSR1 post-decremented (not a physical register) N/A 69, 100 PREINC1 Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) N/A 69, 100 PLUSW1 Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) - value of FSR1 offset by W N/A 69, 100 FSR1H FSR1L BSR -- -- -- -- Indirect Data Memory Address Pointer 1 High Byte Indirect Data Memory Address Pointer 1 Low Byte -- -- -- -- Bank Select Register ---- xxxx 69, 99 xxxx xxxx 69, 99 ---- 0000 69, 99 INDF2 Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register) N/A 69, 99 POSTINC2 Uses contents of FSR2 to address data memory - value of FSR2 post-incremented (not a physical register) N/A 69, 100 POSTDEC2 Uses contents of FSR2 to address data memory - value of FSR2 post-decremented (not a physical register) N/A 69, 100 PREINC2 Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) N/A 69, 100 PLUSW2 Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) - value of FSR2 offset by W N/A 69, 100 FSR2H FSR2L -- -- -- -- Indirect Data Memory Address Pointer 2 Low Byte Indirect Data Memory Address Pointer 2 High Byte ---- xxxx 69, 99 xxxx xxxx 69, 99 Legend: x = unknown; u = unchanged; - = unimplemented, read as `0'; q = value depends on condition; r = reserved bit, do not modify. Shaded cells are unimplemented, read as `0'. Note 1: Bit 7 and bit 6 are cleared by user software or by a POR. 2: Bit 21 of the PC is only available in Serial Programming modes. 3: Reset value is `0' when Two-Speed Start-up is enabled and `1' if disabled. 4: Alternate names and definitions for these bits when the MSSP module is operating in I2CTM Slave mode. 5: These bits and/or registers are only available in 100-pin devices; otherwise, they are unimplemented and read as `0'. Reset values shown apply only to 100-pin devices. 6: These bits and/or registers are only available in 80-pin and 100-pin devices. In 64-pin devices, they are unimplemented and read as `0'. Reset values are shown for 100-pin devices. 7: In Microcontroller mode, the bits in this register are unwritable and read as `0'. 8: PLLEN is only available when either ECPLL or HSPLL Oscillator mode is selected; otherwise, read as `0'. 9: Implemented in 100-pin devices in Microcontroller mode only. 2011 Microchip Technology Inc. DS39762F-page 91 PIC18F97J60 FAMILY TABLE 6-5: File Name STATUS REGISTER FILE SUMMARY (PIC18F97J60 FAMILY) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 -- -- -- N OV Z DC C TMR0H Timer0 Register High Byte TMR0L Timer0 Register Low Byte T0CON TMR0ON T08BIT T0CS T0SE PSA OSCCON IDLEN -- -- -- ECON1 TXRST RXRST DMAST CSUMEN -- -- -- -- -- IPEN -- CM RI TO WDTCON RCON Values on Details on POR, BOR Page: ---x xxxx 70, 97 0000 0000 70, 171 xxxx xxxx 70, 171 1111 1111 70, 171 T0PS2 T0PS1 T0PS0 OSTS(3) -- SCS1 SCS0 0--- q-00 70, 53 TXRTS RXEN -- -- 0000 00-- 70, 227 -- -- SWDTEN --- ---0 70, 368 PD POR BOR 0-q1 1100 70, 64, 143 TMR1H Timer1 Register High Byte xxxx xxxx 70, 175 TMR1L Timer1 Register Low Byte xxxx xxxx 70, 175 T1CON RD16 T1RUN TMR2 Timer2 Register PR2 Timer2 Period Register T2CON -- T2OUTPS3 T1CKPS1 T2OUTPS2 T1CKPS0 T2OUTPS1 T1OSCEN T2OUTPS0 T1SYNC TMR2ON TMR1CS T2CKPS1 TMR1ON T2CKPS0 SSP1BUF MSSP1 Receive Buffer/Transmit Register SSP1ADD MSSP1 Address Register (I2CTM Slave mode), MSSP1 Baud Rate Reload Register (I2C Master mode) 0000 0000 70, 175 0000 0000 70, 180 1111 1111 70, 180 -000 0000 70, 180 xxxx xxxx 70, 279 0000 0000 70, 279 SSP1STAT SMP CKE D/A P S R/W UA BF 0000 0000 70, 270, 280 SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 70, 271, 281 0000 0000 70, 282 SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN GCEN ACKSTAT ADMSK5(4) ADMSK4(4) ADMSK3(4) ADMSK2(4) ADMSK1(4) SEN ADRESH A/D Result Register High Byte xxxx xxxx 70, 347 ADRESL A/D Result Register Low Byte xxxx xxxx 70, 347 ADCON0 ADCAL -- CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 0-00 0000 70, 339 ADCON1 -- -- VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 70, 340 ADFM -- ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 ADCON2 CCPR1H Capture/Compare/PWM Register 1 High Byte CCPR1L Capture/Compare/PWM Register 1 Low Byte CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0-00 0000 70, 341 xxxx xxxx 70, 193 xxxx xxxx 70, 193 0000 0000 70, 198 CCPR2H Capture/Compare/PWM Register 2 High Byte xxxx xxxx 70, 193 CCPR2L Capture/Compare/PWM Register 2 Low Byte xxxx xxxx 70, 193 CCP2CON P2M1 P2M0 DC2B1 DC2B0 CCPR3H Capture/Compare/PWM Register 3 High Byte CCPR3L Capture/Compare/PWM Register 3 Low Byte CCP3CON ECCP1AS CVRCON CMCON P3M1 P3M0 ECCP1ASE ECCP1AS2 CCP2M3 CCP2M2 CCP2M1 CCP2M0 DC3B1 DC3B0 CCP3M3 CCP3M2 CCP3M1 CCP3M0 0000 0000 70, 198 xxxx xxxx 70, 193 xxxx xxxx 70, 193 0000 0000 70, 198 ECCP1AS1 ECCP1AS0 PSS1AC1 PSS1AC0 PSS1BD1 PSS1BD0 0000 0000 70, 212 CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0000 0000 70, 355 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 70, 349 TMR3H Timer3 Register High Byte xxxx xxxx 70, 183 TMR3L Timer3 Register Low Byte xxxx xxxx 70, 183 Legend: x = unknown; u = unchanged; - = unimplemented, read as `0'; q = value depends on condition; r = reserved bit, do not modify. Shaded cells are unimplemented, read as `0'. Note 1: Bit 7 and bit 6 are cleared by user software or by a POR. 2: Bit 21 of the PC is only available in Serial Programming modes. 3: Reset value is `0' when Two-Speed Start-up is enabled and `1' if disabled. 4: Alternate names and definitions for these bits when the MSSP module is operating in I2CTM Slave mode. 5: These bits and/or registers are only available in 100-pin devices; otherwise, they are unimplemented and read as `0'. Reset values shown apply only to 100-pin devices. 6: These bits and/or registers are only available in 80-pin and 100-pin devices. In 64-pin devices, they are unimplemented and read as `0'. Reset values are shown for 100-pin devices. 7: In Microcontroller mode, the bits in this register are unwritable and read as `0'. 8: PLLEN is only available when either ECPLL or HSPLL Oscillator mode is selected; otherwise, read as `0'. 9: Implemented in 100-pin devices in Microcontroller mode only. DS39762F-page 92 2011 Microchip Technology Inc. PIC18F97J60 FAMILY TABLE 6-5: File Name T3CON PSPCON(5) SPBRG1 REGISTER FILE SUMMARY (PIC18F97J60 FAMILY) (CONTINUED) Bit 7 Bit 6 Bit 5 RD16 T3CCP2 IBF OBF Values on Details on POR, BOR Page: Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 IBOV PSPMODE -- -- -- -- 0000 ---- 71, 169 0000 0000 71, 320 EUSART1 Baud Rate Generator Register Low Byte 71, 183 RCREG1 EUSART1 Receive Register 0000 0000 71, 327 TXREG1 EUSART1 Transmit Register xxxx xxxx 71, 329 TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 71, 320 RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 71, 320 ---- ---- 71, 106 EECON2 EECON1 Program Memory Control Register (not a physical register) -- -- -- FREE WRERR WREN WR -- ---0 x00- 71, 107 IPR3 SSP2IP(5) BCL2IP(5) RC2IP(6) TX2IP(6) TMR4IP CCP5IP CCP4IP CCP3IP 1111 1111 71, 142 PIR3 SSP2IF(5) BCL2IF(5) RC2IF(6) TX2IF(6) TMR4IF CCP5IF CCP4IF CCP3IF 0000 0000 71, 136 PIE3 SSP2IE(5) (5) (6) TX2IE(6) TMR4IE CCP5IE CCP4IE CCP3IE 0000 0000 71, 139 IPR2 OSCFIP CMIP ETHIP r BCL1IP -- TMR3IP CCP2IP 1111 1-11 71, 141 PIR2 OSCFIF CMIF ETHIF r BCL1IF -- TMR3IF CCP2IF 0000 0-00 71, 135 PIE2 OSCFIE CMIE ETHIE r BCL1IE -- TMR3IE CCP2IE 0000 0-00 71, 138 IPR1 PSPIP(9) ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 1111 1111 71, 140 PIR1 PSPIF(9) ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 0000 0000 71, 134 PIE1 BCL2IE RC2IE PSPIE(9) ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 0000 0000 71, 137 MEMCON(5,7) EBDIS -- WAIT1 WAIT0 -- -- WM1 WM0 0-00 --00 71, 116 OSCTUNE PPST1 PLLEN(8) PPST0 PPRE -- -- -- -- 0000 ---- 71, 51 TRISJ(6) TRISJ7(5) TRISJ6(5) TRISJ5(6) TRISJ4(6) TRISJ3(5) TRISJ2(5) TRISJ1(5) TRISJ0(5) 1111 1111 71, 167 TRISH(6) TRISH7(6) TRISH6(6) TRISH5(6) TRISH4(6) TRISH3(6) TRISH2(6) TRISH1(6) TRISH0(6) 1111 1111 71, 165 TRISG TRISG7(5) TRISG6(5) TRISG5(5) TRISG4 TRISG3(6) TRISG2(6) TRISG1(6) TRISG0(6) 1111 1111 71, 163 TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0(5) 1111 1111 71, 161 TRISE TRISE7(6) TRISE6(6) TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 1111 1111 71, 159 TRISD TRISD7(5) TRISD6(5) TRISD5(5) TRISD4(5) TRISD3(5) TRISD2 TRISD1 TRISD0 1111 1111 71, 156 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 71, 153 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 71, 150 TRISA -- -- TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 71, 147 LATJ(6) LATJ7(5) LATJ6(5) LATJ5(6) LATJ4(6) LATJ3(5) LATJ2(5) LATJ1(5) LATJ0(5) xxxx xxxx 71, 167 LATH(6) LATH7(6) LATH6(6) LATH5(6) LATH4(6) LATH3(6) LATH2(6) LATH1(6) LATH0(6) xxxx xxxx 71, 165 LATG LATG7(5) LATG6(5) LATG5(5) LATG4 LATG3(6) LATG2(6) LATG1(6) LATG0(6) xxxx xxxx 72, 163 LATF LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0(5) xxxx xxxx 72, 161 LATE LATE7(6) LATE6(6) LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 xxxx xxxx 72, 159 LATD LATD7(5) LATD6(5) LATD5(5) LATD4(5) LATD3(5) LATD2 LATD1 LATD0 xxxx xxxx 72, 156 LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx 72, 153 LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx xxxx 72, 150 LATA RDPU REPU LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 00xx xxxx 72, 147 PORTJ(6) RJ7(5) RJ6(5) RJ5(6) RJ4(6) RJ3(5) RJ2(5) RJ1(5) RJ0(5) xxxx xxxx 72, 167 PORTH(6) RH7(6) RH6(6) RH5(6) RH4(6) RH3(6) RH2(6) RH1(6) RH0(6) 0000 xxxx 72, 165 PORTG RG7(5) RG6(5) RG5(5) RG4 RG3(6) RG2(6) RG1(6) RG0(6) 111x xxxx 72, 163 Legend: x = unknown; u = unchanged; - = unimplemented, read as `0'; q = value depends on condition; r = reserved bit, do not modify. Shaded cells are unimplemented, read as `0'. Note 1: Bit 7 and bit 6 are cleared by user software or by a POR. 2: Bit 21 of the PC is only available in Serial Programming modes. 3: Reset value is `0' when Two-Speed Start-up is enabled and `1' if disabled. 4: Alternate names and definitions for these bits when the MSSP module is operating in I2CTM Slave mode. 5: These bits and/or registers are only available in 100-pin devices; otherwise, they are unimplemented and read as `0'. Reset values shown apply only to 100-pin devices. 6: These bits and/or registers are only available in 80-pin and 100-pin devices. In 64-pin devices, they are unimplemented and read as `0'. Reset values are shown for 100-pin devices. 7: In Microcontroller mode, the bits in this register are unwritable and read as `0'. 8: PLLEN is only available when either ECPLL or HSPLL Oscillator mode is selected; otherwise, read as `0'. 9: Implemented in 100-pin devices in Microcontroller mode only. 2011 Microchip Technology Inc. DS39762F-page 93 PIC18F97J60 FAMILY TABLE 6-5: File Name REGISTER FILE SUMMARY (PIC18F97J60 FAMILY) (CONTINUED) Values on Details on POR, BOR Page: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0(5) 0000 0000 72, 161 PORTE RE7(6) RE6 RE5 RE4 RE3 RE2 RE1 RE0 xxxx xxxx 72, 159 PORTD RD7(5) RD6(5) RD5(5) RD4(5) RD3(5) RD2 RD1 RD0 xxxx xxxx 72, 156 PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 72, 153 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 72, 150 PORTA RJPU(6) -- RA5 RA4 RA3 RA2 RA1 RA0 0-0x 0000 72, 147 0000 0000 72, 320 SPBRGH1 BAUDCON1 SPBRGH2 BAUDCON2 ERDPTH ERDPTL ECCP1DEL (6) EUSART1 Baud Rate Generator Register High Byte ABDOVF RCIDL ABDOVF RCIDL RXDTP -- -- -- TXCKP P1RSEN P1DC6 Timer4 Register PR4 Timer4 Period Register TXCKP -- T4OUTPS3 P1DC5 T4OUTPS2 T4OUTPS1 CCPR4L Capture/Compare/PWM Register 4 Low Byte -- -- DC4B1 DC4B0 CCPR5H Capture/Compare/PWM Register 5 High Byte CCPR5L Capture/Compare/PWM Register 5 Low Byte SPBRG2 BRG16 P1DC4 Capture/Compare/PWM Register 4 High Byte CCP5CON -- WUE ABDEN -- WUE ABDEN Buffer Read Pointer High Byte CCPR4H CCP4CON BRG16 Buffer Read Pointer Low Byte TMR4 T4CON RXDTP EUSART2 Baud Rate Generator Register High Byte -- -- DC5B1 DC5B0 P1DC3 T4OUTPS0 CCP4M3 CCP5M3 P1DC2 TMR4ON CCP4M2 CCP5M2 P1DC1 T4CKPS1 CCP4M1 CCP5M1 P1DC0 T4CKPS0 CCP4M0 CCP5M0 EUSART2 Baud Rate Generator Register Low Byte 0100 0-00 72, 318 0000 0000 72, 320 0100 0-00 72, 318 ---0 0101 72, 223 1111 1010 72, 223 0000 0000 72, 211 0000 0000 72, 187 1111 1111 72, 187 -000 0000 72, 187 xxxx xxxx 72, 193 xxxx xxxx 72, 193 --00 0000 73, 189 xxxx xxxx 73, 193 xxxx xxxx 73, 193 --00 0000 73, 189 0000 0000 73, 320 RCREG2 EUSART2 Receive Register 0000 0000 73, 327 TXREG2 EUSART2 Transmit Register 0000 0000 73, 329 TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 73, 316 RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 73, 317 ECCP3AS1 ECCP3AS0 PSS3AC1 PSS3AC0 PSS3BD1 PSS3BD0 0000 0000 73, 212 P3DC5 P3DC4 P3DC3 P3DC2 P3DC1 P3DC0 0000 0000 73, 211 ECCP2AS1 ECCP2AS0 PSS2AC1 PSS2AC0 PSS2BD1 PSS2BD0 0000 0000 73, 212 P2DC5 P2DC4 P2DC3 P2DC2 P2DC1 P2DC0 ECCP3AS ECCP3DEL ECCP2AS ECCP2DEL ECCP3ASE ECCP3AS2 P3RSEN P3DC6 ECCP2ASE ECCP2AS2 P2RSEN P2DC6 SSP2BUF MSSP2 Receive Buffer/Transmit Register SSP2ADD MSSP2 Address Register (I2CTM Slave mode), MSSP2 Baud Rate Reload Register (I2C Master mode) 0000 0000 73, 211 xxxx xxxx 73, 279 0000 0000 73, 279 SSP2STAT SMP CKE D/A P S R/W UA BF 0000 0000 73, 270 SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 73, 271, 281 0000 0000 73, 282 xxxx xxxx 73, 223 SSP2CON2 EDATA EIR ECON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN GCEN ACKSTAT ADMSK5(4) ADMSK4(4) ADMSK3(4) ADMSK2(4) ADMSK1(4) SEN Ethernet Transmit/Receive Buffer Register (EDATA<7:0>) -- PKTIF DMAIF LINKIF TXIF -- TXERIF RXERIF -000 0-00 73, 241 AUTOINC PKTDEC ETHEN -- -- -- -- -- 100- ---- 73, 228 Legend: x = unknown; u = unchanged; - = unimplemented, read as `0'; q = value depends on condition; r = reserved bit, do not modify. Shaded cells are unimplemented, read as `0'. Note 1: Bit 7 and bit 6 are cleared by user software or by a POR. 2: Bit 21 of the PC is only available in Serial Programming modes. 3: Reset value is `0' when Two-Speed Start-up is enabled and `1' if disabled. 4: Alternate names and definitions for these bits when the MSSP module is operating in I2CTM Slave mode. 5: These bits and/or registers are only available in 100-pin devices; otherwise, they are unimplemented and read as `0'. Reset values shown apply only to 100-pin devices. 6: These bits and/or registers are only available in 80-pin and 100-pin devices. In 64-pin devices, they are unimplemented and read as `0'. Reset values are shown for 100-pin devices. 7: In Microcontroller mode, the bits in this register are unwritable and read as `0'. 8: PLLEN is only available when either ECPLL or HSPLL Oscillator mode is selected; otherwise, read as `0'. 9: Implemented in 100-pin devices in Microcontroller mode only. DS39762F-page 94 2011 Microchip Technology Inc. PIC18F97J60 FAMILY TABLE 6-5: File Name REGISTER FILE SUMMARY (PIC18F97J60 FAMILY) (CONTINUED) Bit 7 Bit 6 Bit 5 ESTAT -- BUFER -- EIE -- PKTIE DMAIE EDMACSH DMA Checksum Register High Byte EDMACSL DMA Checksum Register Low Byte EDMADSTH EDMADSTL EDMANDH EDMANDL EDMASTH EDMASTL ERXWRPTH ERXWRPTL ERXRDPTH ERXRDPTL ERXNDH ERXNDL ERXSTH ERXSTL ETXNDH ETXNDL ETXSTH ETXSTL EWRPTH -- -- -- -- -- -- Bit 1 Bit 0 r -- RXBUSY TXABRT PHYRDY -0-0 -000 LINKIE TXIE -- TXERIE RXERIE -000 0-00 73, 240 0000 0000 73, 265 0000 0000 73, 265 DMA Destination Register High Byte DMA End Register High Byte -- -- DMA Start Register High Byte DMA Start Register Low Byte -- -- -- Receive Buffer Write Pointer High Byte Receive Buffer Write Pointer Low Byte -- -- -- Receive Buffer Read Pointer High Byte Receive Buffer Read Pointer Low Byte -- -- -- Receive End Register High Byte Receive End Register Low Byte -- -- -- Receive Start Register High Byte Receive Start Register Low Byte -- -- -- Transmit End Register High Byte Transmit End Register Low Byte -- -- -- Transmit Start Register High Byte Transmit Start Register Low Byte -- -- -- Buffer Write Pointer Low Byte EPKTCNT Ethernet Packet Count Register EPMOH Bit 2 DMA End Register Low Byte -- UCEN ANDOR CRCEN -- -- -- Values on Details on POR, BOR Page: Bit 3 DMA Destination Register Low Byte EWRPTL ERXFCON Bit 4 Buffer Write Pointer High Byte PMEN MPEN HTEN Pattern Match Offset Register High Byte MCEN BCEN 73, 228 ---0 0000 73, 265 0000 0000 73, 265 ---0 0000 73, 265 0000 0000 73, 265 ---0 0000 73, 265 0000 0000 73, 265 ---0 0000 73, 225 0000 0000 73, 225 ---0 0101 73, 225 1111 1010 73, 225 ---1 1111 73, 225 1111 1111 73, 225 ---0 0101 73, 225 1111 1010 73, 225 ---0 0000 74, 226 0000 0000 74, 226 ---0 0000 74, 226 0000 0000 74, 226 ---0 0000 74, 223 0000 0000 74, 223 0000 0000 74, 252 1010 0001 74, 260 ---0 0000 74, 263 0000 0000 74, 263 EPMOL Pattern Match Offset Register Low Byte EPMCSH Pattern Match Checksum Register High Byte 0000 0000 74, 263 EPMCSL Pattern Match Checksum Register Low Byte 0000 0000 74, 263 EPMM7 Pattern Match Mask Register Byte 7 0000 0000 74, 263 EPMM6 Pattern Match Mask Register Byte 6 0000 0000 74, 263 EPMM5 Pattern Match Mask Register Byte 5 0000 0000 74, 263 EPMM4 Pattern Match Mask Register Byte 4 0000 0000 74, 263 EPMM3 Pattern Match Mask Register Byte 3 0000 0000 74, 263 EPMM2 Pattern Match Mask Register Byte 2 0000 0000 74, 263 EPMM1 Pattern Match Mask Register Byte 1 0000 0000 74, 263 EPMM0 Pattern Match Mask Register Byte 0 0000 0000 74, 263 Legend: x = unknown; u = unchanged; - = unimplemented, read as `0'; q = value depends on condition; r = reserved bit, do not modify. Shaded cells are unimplemented, read as `0'. Note 1: Bit 7 and bit 6 are cleared by user software or by a POR. 2: Bit 21 of the PC is only available in Serial Programming modes. 3: Reset value is `0' when Two-Speed Start-up is enabled and `1' if disabled. 4: Alternate names and definitions for these bits when the MSSP module is operating in I2CTM Slave mode. 5: These bits and/or registers are only available in 100-pin devices; otherwise, they are unimplemented and read as `0'. Reset values shown apply only to 100-pin devices. 6: These bits and/or registers are only available in 80-pin and 100-pin devices. In 64-pin devices, they are unimplemented and read as `0'. Reset values are shown for 100-pin devices. 7: In Microcontroller mode, the bits in this register are unwritable and read as `0'. 8: PLLEN is only available when either ECPLL or HSPLL Oscillator mode is selected; otherwise, read as `0'. 9: Implemented in 100-pin devices in Microcontroller mode only. 2011 Microchip Technology Inc. DS39762F-page 95 PIC18F97J60 FAMILY TABLE 6-5: File Name REGISTER FILE SUMMARY (PIC18F97J60 FAMILY) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on Details on POR, BOR Page: EHT7 Hash Table Register Byte 7 0000 0000 74, 259 EHT6 Hash Table Register Byte 6 0000 0000 74, 259 EHT5 Hash Table Register Byte 5 0000 0000 74, 259 EHT4 Hash Table Register Byte 4 0000 0000 74, 259 EHT3 Hash Table Register Byte 3 0000 0000 74, 259 EHT2 Hash Table Register Byte 2 0000 0000 74, 259 EHT1 Hash Table Register Byte 1 0000 0000 74, 259 EHT0 Hash Table Register Byte 0 0000 0000 74, 259 MIRDH MII Read Data Register High Byte 0000 0000 74, 232 MIRDL MII Read Data Register Low Byte 0000 0000 74, 232 MIWRH MII Write Data Register High Byte 0000 0000 74, 232 MIWRL MII Write Data Register Low Byte 0000 0000 74, 232 ---0 0000 74, 232 MIREGADR -- -- -- MICMD -- -- -- MII Address Register -- -- -- MIISCAN MIIRD ---- --00 74, 231 MAMXFLH Maximum Frame Length Register High Byte 0000 0110 74, 245 MAMXFLL Maximum Frame Length Register Low Byte 0000 0000 74, 245 MAIPGH -- MAC Non Back-to-Back Inter-Packet Gap Register High Byte -000 0000 75, 245 MAIPGL -- MAC Non Back-to-Back Inter-Packet Gap Register Low Byte -000 0000 75, 245 MABBIPG -- BBIPG6 BBIPG5 BBIPG4 BBIPG3 BBIPG2 BBIPG1 BBIPG0 -000 0000 75, 246 MACON4 -- DEFER r r -- -- r r -000 --00 75, 231 MACON3 PADCFG2 PADCFG1 PADCFG0 TXCRCEN PHDREN HFRMEN FRMLNEN FULDPX 0000 0000 75, 230 -- -- -- r TXPAUS RXPAUS PASSALL MARXEN MACON1 EPAUSH Pause Timer Value Register High Byte EPAUSL Pause Timer Value Register Low Byte ---0 0000 75, 229 0001 0000 75, 258 0000 0000 75, 258 EFLOCON -- -- -- -- -- r FCEN1 FCEN0 ---- -000 75, 258 MISTAT -- -- -- -- r NVALID SCAN BUSY ---- 0000 75, 232 MAADR2 MAC Address Register Byte 2 (MAADR<39:32>), OUI Byte 2 0000 0000 75, 245 MAADR1 MAC Address Register Byte 1 (MAADR<47:40>), OUI Byte 1 0000 0000 75, 245 MAADR4 MAC Address Register Byte 4 (MAADR<23:16>) 0000 0000 75, 245 MAADR3 MAC Address Register Byte 3 (MAADR<31:24>), OUI Byte 3 0000 0000 75, 245 MAADR6 MAC Address Register Byte 6 (MAADR<7:0>) 0000 0000 75, 245 MAADR5 MAC Address Register Byte 5 (MAADR<15:8>) 0000 0000 75, 245 Legend: x = unknown; u = unchanged; - = unimplemented, read as `0'; q = value depends on condition; r = reserved bit, do not modify. Shaded cells are unimplemented, read as `0'. Note 1: Bit 7 and bit 6 are cleared by user software or by a POR. 2: Bit 21 of the PC is only available in Serial Programming modes. 3: Reset value is `0' when Two-Speed Start-up is enabled and `1' if disabled. 4: Alternate names and definitions for these bits when the MSSP module is operating in I2CTM Slave mode. 5: These bits and/or registers are only available in 100-pin devices; otherwise, they are unimplemented and read as `0'. Reset values shown apply only to 100-pin devices. 6: These bits and/or registers are only available in 80-pin and 100-pin devices. In 64-pin devices, they are unimplemented and read as `0'. Reset values are shown for 100-pin devices. 7: In Microcontroller mode, the bits in this register are unwritable and read as `0'. 8: PLLEN is only available when either ECPLL or HSPLL Oscillator mode is selected; otherwise, read as `0'. 9: Implemented in 100-pin devices in Microcontroller mode only. DS39762F-page 96 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 6.3.6 STATUS REGISTER The STATUS register, shown in Register 6-3, contains the arithmetic status of the ALU. The STATUS register can be the operand for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, then the write to these five bits is disabled. These bits are set or cleared according to the device logic. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will set the Z bit but leave the other bits unchanged. The STATUS REGISTER 6-3: register then reads back as `000u u1uu'. It is recommended, therefore, that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect the Z, C, DC, OV or N bits in the STATUS register. For other instructions not affecting any Status bits, see the instruction set summaries in Table 26-2 and Table 26-3. Note: The C and DC bits operate as a Borrow and Digit Borrow bit respectively, in subtraction. STATUS REGISTER U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x -- -- -- N OV Z DC(1) C(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as `0' bit 4 N: Negative bit This bit is used for signed arithmetic (2's complement). It indicates whether the result was negative (ALU MSb = 1). 1 = Result was negative 0 = Result was positive bit 3 OV: Overflow bit This bit is used for signed arithmetic (2's complement). It indicates an overflow of the 7-bit magnitude which causes the sign bit (bit 7 of the result) to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is non-zero bit 1 DC: Digit Carry/Borrow bit(1) For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit(2) For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: 2: For Borrow, the polarity is reversed. A subtraction is executed by adding the 2's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register. For Borrow, the polarity is reversed. A subtraction is executed by adding the 2's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. 2011 Microchip Technology Inc. DS39762F-page 97 PIC18F97J60 FAMILY 6.4 Note: Data Addressing Modes The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. See Section 6.6 "Data Memory and the Extended Instruction Set" for more information. While the program memory can be addressed in only one way, through the program counter, information in the data memory space can be addressed in several ways. For most instructions, the addressing mode is fixed. Other instructions may use up to three modes, depending on which operands are used and whether or not the extended instruction set is enabled. The addressing modes are: * Inherent * Literal * Direct * Indirect An additional addressing mode, Indexed Literal Offset, is available when the extended instruction set is enabled (XINST Configuration bit = 1). Its operation is discussed in greater detail in Section 6.6.1 "Indexed Addressing with Literal Offset". 6.4.1 INHERENT AND LITERAL ADDRESSING Many PIC18 control instructions do not need any argument at all. They either perform an operation that globally affects the device, or they operate implicitly on one register. This addressing mode is known as Inherent Addressing. Examples include SLEEP, RESET and DAW. Other instructions work in a similar way, but require an additional explicit argument in the opcode. This is known as Literal Addressing mode because they require some literal value as an argument. Examples include ADDLW and MOVLW, which respectively, add or move a literal value to the W register. Other examples include CALL and GOTO, which include a 20-bit program memory address. 6.4.2 DIRECT ADDRESSING Direct Addressing mode specifies all or part of the source and/or destination address of the operation within the opcode itself. The options are specified by the arguments accompanying the instruction. In the core PIC18 instruction set, bit-oriented and byte-oriented instructions use some version of Direct Addressing by default. All of these instructions include some 8-bit literal address as their Least Significant Byte. This address specifies either a register address in one of the banks of data RAM (Section 6.3.3 "General Purpose Register File") or a location in the Access Bank (Section 6.3.2 "Access Bank") as the data source for the instruction. DS39762F-page 98 The Access RAM bit, `a', determines how the address is interpreted. When `a' is `1', the contents of the BSR (Section 6.3.1 "Bank Select Register") are used with the address to determine the complete 12-bit address of the register. When `a' is `0', the address is interpreted as being a register in the Access Bank. Addressing that uses the Access RAM is sometimes also known as Direct Forced Addressing mode. A few instructions, such as MOVFF, include the entire 12-bit address (either source or destination) in their opcodes. In these cases, the BSR is ignored entirely. The destination of the operation's results is determined by the destination bit, `d'. When `d' is `1', the results are stored back in the source register, overwriting its original contents. When `d' is `0', the results are stored in the W register. Instructions without the `d' argument have a destination that is implicit in the instruction. Their destination is either the target register being operated on or the W register. 6.4.3 INDIRECT ADDRESSING Indirect Addressing mode allows the user to access a location in data memory without giving a fixed address in the instruction. This is done by using File Select Registers (FSRs) as pointers to the locations to be read or written to. Since the FSRs are themselves located in RAM as Special Function Registers, they can also be directly manipulated under program control. This makes FSRs very useful in implementing data structures, such as tables and arrays in data memory. The registers for Indirect Addressing are also implemented with Indirect File Operands (INDFs) that permit automatic manipulation of the pointer value with auto-incrementing, auto-decrementing or offsetting with another value. This allows for efficient code using loops, such as the example of clearing an entire RAM bank in Example 6-5. It also enables users to perform Indexed Addressing and other Stack Pointer operations for program memory in data memory. EXAMPLE 6-5: HOW TO CLEAR RAM (BANK 1) USING INDIRECT ADDRESSING LFSRFSR0, 100h; CLRFPOSTINC0; Clear INDF ; register then ; inc pointer BTFSSFSR0H, 1; All done with ; Bank1? BRA NEXT ; NO, clear next CONTINUE ; YES, continue NEXT 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 6.4.3.1 FSR Registers and the INDF Operand SFR space but are not physically implemented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L. Instructions that use the INDF registers as operands actually use the contents of their corresponding FSR as a pointer to the instruction's target. The INDF operand is just a convenient way of using the pointer. At the core of Indirect Addressing are three sets of registers: FSR0, FSR1 and FSR2. Each represents a pair of 8-bit registers: FSRnH and FSRnL. The four upper bits of the FSRnH register are not used, so each FSR pair holds a 12-bit value. This represents a value that can address the entire range of the data memory in a linear fashion. The FSR register pairs, then, serve as pointers to data memory locations. Because Indirect Addressing uses a full, 12-bit address, data RAM banking is not necessary. Thus, the current contents of the BSR and Access RAM bit have no effect on determining the target address. Indirect Addressing is accomplished with a set of Indirect File Operands: INDF0 through INDF2. These can be thought of as "virtual" registers. They are mapped in the FIGURE 6-9: INDIRECT ADDRESSING 000h Using an instruction with one of the Indirect Addressing registers as the operand.... Bank 0 ADDWF, INDF1, 1 100h Bank 1 200h ...uses the 12-bit address stored in the FSR pair associated with that register.... 300h FSR1H:FSR1L 7 0 x x x x 1 1 1 1 7 Bank 2 0 1 1 0 0 1 1 0 0 Bank 3 through Bank 13 ...to determine the data memory location to be used in that operation. In this case, the FSR1 pair contains FCCh. This means the contents of location FCCh will be added to that of the W register and stored back in FCCh. E00h Bank 14 F00h FFFh Bank 15 Data Memory 2011 Microchip Technology Inc. DS39762F-page 99 PIC18F97J60 FAMILY 6.4.3.2 FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these are "virtual" registers that cannot be indirectly read or written to. Accessing these registers actually accesses the associated FSR register pair, but also performs a specific action on its stored value. They are: * POSTDEC: accesses the FSR value, then automatically decrements it by `1' afterwards * POSTINC: accesses the FSR value, then automatically increments it by `1' afterwards * PREINC: increments the FSR value by `1', then uses it in the operation * PLUSW: adds the signed value of the W register (range of -128 to 127) to that of the FSR and uses the new value in the operation In this context, accessing an INDF register uses the value in the FSR registers without changing them. Similarly, accessing a PLUSW register gives the FSR value offset by the value in the W register; neither value is actually changed in the operation. Accessing the other virtual registers changes the value of the FSR registers. Operations on the FSRs with POSTDEC, POSTINC and PREINC affect the entire register pair; that is, rollovers of the FSRnL register, from FFh to 00h, carry over to the FSRnH register. On the other hand, results of these operations do not change the value of any flags in the STATUS register (e.g., Z, N, OV, etc.). The PLUSW register can be used to implement a form of Indexed Addressing in the data memory space. By manipulating the value in the W register, users can reach addresses that are fixed offsets from pointer addresses. In some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory. 6.4.3.3 Operations by FSRs on FSRs Indirect Addressing operations that target other FSRs, or virtual registers, represent special cases. For example, using an FSR to point to one of the virtual registers will not result in successful operation. As a specific case, assume that the FSR0H:FSR0L pair contains FE7h, the address of INDF1. Attempts to read the value of the INDF1, using INDF0 as an operand, will return 00h. Attempts to write to INDF1, using INDF0 as the operand, will result in a NOP. DS39762F-page 100 On the other hand, using the virtual registers to write to an FSR pair may not occur as planned. In these cases, the value will be written to the FSR pair but without any incrementing or decrementing. Thus, writing to INDF2 or POSTDEC2 will write the same value to the FSR2H:FSR2L pair. Since the FSRs are physical registers mapped in the SFR space, they can be manipulated through all direct operations. Users should proceed cautiously when working on these registers, particularly if their code uses Indirect Addressing. Similarly, operations by Indirect Addressing are generally permitted on all other SFRs. Users should exercise the appropriate caution that they do not inadvertently change settings that might affect the operation of the device. 6.5 Program Memory and the Extended Instruction Set The operation of program memory is unaffected by the use of the extended instruction set. Enabling the extended instruction set adds five additional two-word commands to the existing PIC18 instruction set: ADDFSR, CALLW, MOVSF, MOVSS and SUBFSR. These instructions are executed as described in Section 6.2.4 "Two-Word Instructions". 6.6 Data Memory and the Extended Instruction Set Enabling the PIC18 extended instruction set (XINST Configuration bit = 1) significantly changes certain aspects of data memory and its addressing. Specifically, the use of the Access Bank for many of the core PIC18 instructions is different. This is due to the introduction of a new addressing mode for the data memory space. This mode also alters the behavior of Indirect Addressing using FSR2 and its associated operands. What does not change is just as important. The size of the data memory space is unchanged, as well as its linear addressing. The SFR map remains the same. Core PIC18 instructions can still operate in both Direct and Indirect Addressing mode; inherent and literal instructions do not change at all. Indirect Addressing with FSR0 and FSR1 also remains unchanged. 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 6.6.1 INDEXED ADDRESSING WITH LITERAL OFFSET Enabling the PIC18 extended instruction set changes the behavior of Indirect Addressing using the FSR2 register pair and its associated file operands. Under the proper conditions, instructions that use the Access Bank - that is, most bit-oriented and byte-oriented instructions - can invoke a form of Indexed Addressing using an offset specified in the instruction. This special addressing mode is known as Indexed Addressing with Literal Offset or Indexed Literal Offset mode. When using the extended instruction set, this addressing mode requires the following: * The use of the Access Bank is forced (`a' = 0); and * The file address argument is less than or equal to 5Fh. Under these conditions, the file address of the instruction is not interpreted as the lower byte of an address (used with the BSR in Direct Addressing) or as an 8-bit address in the Access Bank. Instead, the value is interpreted as an offset value to an Address Pointer specified by FSR2. The offset and the contents of FSR2 are added to obtain the target address of the operation. 2011 Microchip Technology Inc. 6.6.2 INSTRUCTIONS AFFECTED BY INDEXED LITERAL OFFSET MODE Any of the core PIC18 instructions that can use Direct Addressing are potentially affected by the Indexed Literal Offset Addressing mode. This includes all byte-oriented and bit-oriented instructions, or almost half of the standard PIC18 instruction set. Instructions that only use Inherent or Literal Addressing modes are unaffected. Additionally, byte-oriented and bit-oriented instructions are not affected if they use the Access Bank (Access RAM bit is `1') or include a file address of 60h or above. Instructions meeting these criteria will continue to execute as before. A comparison of the different possible addressing modes when the extended instruction set is enabled is shown in Figure 6-10. Those who desire to use byte-oriented or bit-oriented instructions in the Indexed Literal Offset mode should note the changes to assembler syntax for this mode. This is described in more detail in Section 26.2.1 "Extended Instruction Syntax". DS39762F-page 101 PIC18F97J60 FAMILY FIGURE 6-10: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff When a = 0 and f 60h: The instruction executes in Direct Forced mode. `f' is interpreted as a location in the Access RAM between 060h and FFFh. This is the same as locations F60h to FFFh (Bank 15) of data memory. Locations below 060h are not available in this addressing mode. 000h 060h Bank 0 100h 00h Bank 1 through Bank 14 60h Valid Range for `f' FFh F00h Access RAM Bank 15 F40h SFRs FFFh Data Memory When a = 0 and f5Fh: The instruction executes in Indexed Literal Offset mode. `f' is interpreted as an offset to the address value in FSR2. The two are added together to obtain the address of the target register for the instruction. The address can be anywhere in the data memory space. Note that in this mode, the correct syntax is now: ADDWF [k], d where `k' is the same as `f'. 000h Bank 0 060h 100h 001001da ffffffff Bank 1 through Bank 14 FSR2H FSR2L F00h Bank 15 F40h SFRs FFFh Data Memory When a = 1 (all values of f): The instruction executes in Direct mode (also known as Direct Long mode). `f' is interpreted as a location in one of the 16 banks of the data memory space. The bank is designated by the Bank Select Register (BSR). The address can be in any implemented bank in the data memory space. BSR 00000000 000h Bank 0 060h 100h Bank 1 through Bank 14 001001da ffffffff F00h Bank 15 F40h SFRs FFFh Data Memory DS39762F-page 102 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 6.6.3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET MODE The use of Indexed Literal Offset Addressing mode effectively changes how the lower part of Access RAM (00h to 5Fh) is mapped. Rather than containing just the contents of the bottom part of Bank 0, this mode maps the contents from Bank 0 and a user-defined "window" that can be located anywhere in the data memory space. The value of FSR2 establishes the lower boundary of the addresses mapped into the window, while the upper boundary is defined by FSR2 plus 95 (5Fh). Addresses in the Access RAM above 5Fh are mapped as previously described (see Section 6.3.2 "Access Bank"). An example of Access Bank remapping in this addressing mode is shown in Figure 6-11. FIGURE 6-11: Remapping of the Access Bank applies only to operations using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is `1') will continue to use Direct Addressing as before. Any indirect or indexed operation that explicitly uses any of the indirect file operands (including FSR2) will continue to operate as standard Indirect Addressing. Any instruction that uses the Access Bank, but includes a register address of greater than 05Fh, will use Direct Addressing and the normal Access Bank map. 6.6.4 BSR IN INDEXED LITERAL OFFSET MODE Although the Access Bank is remapped when the extended instruction set is enabled, the operation of the BSR remains unchanged. Direct Addressing, using the BSR to select the data memory bank, operates in the same manner as previously described. REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET ADDRESSING Example Situation: ADDWF f, d, a FSR2H:FSR2L = 120h 000h 05Fh Locations in the region from the FSR2 Pointer (120h) to the pointer plus 05Fh (17Fh) are mapped to the bottom of the Access RAM (000h-05Fh). 100h 120h 17Fh Bank 0 200h Window Bank 1 00h Bank 1 "Window" 5Fh 60h Special Function Registers at F60h through FFFh are mapped to 60h through FFh, as usual. Bank 0 addresses below 5Fh are not available in this mode. They can still be addressed by using the BSR. Not Accessible Bank 2 through Bank 14 SFRs FFh Access Bank F00h Bank 15 F60h FFFh SFRs Data Memory 2011 Microchip Technology Inc. DS39762F-page 103 PIC18F97J60 FAMILY NOTES: DS39762F-page 104 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 7.0 FLASH PROGRAM MEMORY 7.1 Table Reads and Table Writes The Flash program memory is readable, writable and erasable during normal operation over the entire VDD range. In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM: A read from program memory is executed on one byte at a time. A write to program memory is executed on blocks of 64 bytes at a time. Program memory is erased in blocks of 1024 bytes at a time. A Bulk Erase operation may not be issued from user code. * Table Read (TBLRD) * Table Write (TBLWT) Writing or erasing program memory will cease instruction fetches until the operation is complete. The program memory cannot be accessed during the write or erase, therefore, code cannot execute. An internal programming timer terminates program memory writes and erases. A value written to program memory does not need to be a valid instruction. Executing a program memory location that forms an invalid instruction results in a NOP. The program memory space is 16 bits wide, while the data RAM space is 8 bits wide. Table reads and table writes move data between these two memory spaces through an 8-bit register (TABLAT). Table read operations retrieve data from program memory and place it into the data RAM space. Figure 7-1 shows the operation of a table read with program memory and data RAM. Table write operations store data from the data memory space into holding registers in program memory. The procedure to write the contents of the holding registers into program memory is detailed in Section 7.5 "Writing to Flash Program Memory". Figure 7-2 shows the operation of a table write with program memory and data RAM. Table operations work with byte entities. A table block containing data, rather than program instructions, is not required to be word-aligned. Therefore, a table block can start and end at any byte address. If a table write is being used to write executable code into program memory, program instructions will need to be word-aligned. FIGURE 7-1: TABLE READ OPERATION Instruction: TBLRD* Program Memory Table Pointer(1) TBLPTRU TBLPTRH TBLPTRL Table Latch (8-bit) TABLAT Program Memory (TBLPTR) Note 1: The Table Pointer register points to a byte in program memory. 2011 Microchip Technology Inc. DS39762F-page 105 PIC18F97J60 FAMILY FIGURE 7-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) TBLPTRU TBLPTRH Table Latch (8-bit) TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: 7.2 The Table Pointer actually points to one of 64 holding registers, the address of which is determined by TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section 7.5 "Writing to Flash Program Memory". Control Registers Several control registers are used in conjunction with the TBLRD and TBLWT instructions. These include the: * * * * EECON1 register EECON2 register TABLAT register TBLPTR registers 7.2.1 EECON1 AND EECON2 REGISTERS The EECON1 register (Register 7-1) is the control register for memory accesses. The EECON2 register is not a physical register; it is used exclusively in the memory write and erase sequences. Reading EECON2 will read all `0's. The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The WRERR bit is set in hardware when the WR bit is set, and cleared when the internal programming timer expires and the write operation is complete. Note: During normal operation, the WRERR is read as `1'. This can indicate that a write operation was prematurely terminated by a Reset, or a write operation was attempted improperly. The WR control bit initiates write operations. The bit cannot be cleared, only set, in software; it is cleared in hardware at the completion of the write operation. The FREE bit, when set, will allow a program memory erase operation. When FREE is set, the erase operation is initiated on the next WR command. When FREE is clear, only writes are enabled. DS39762F-page 106 2011 Microchip Technology Inc. PIC18F97J60 FAMILY REGISTER 7-1: EECON1: EEPROM CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0 R/W-x R/W-0 R/S-0 U-0 -- -- -- FREE WRERR WREN WR -- bit 7 bit 0 Legend: S = Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as `0' bit 4 FREE: Flash Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write-only bit 3 WRERR: Flash Program Error Flag bit 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation or an improper write attempt) 0 = The write operation completed bit 2 WREN: Flash Program Write Enable bit 1 = Allows write cycles to Flash program memory 0 = Inhibits write cycles to Flash program memory bit 1 WR: Write Control bit 1 = Initiates a program memory erase cycle or write cycle (The operation is self-timed and the bit is cleared by hardware once the write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle complete bit 0 Unimplemented: Read as `0' 2011 Microchip Technology Inc. DS39762F-page 107 PIC18F97J60 FAMILY 7.2.2 TABLE LATCH REGISTER (TABLAT) 7.2.4 The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 7.2.3 TBLPTR is used in reads, writes and erases of the Flash program memory. When a TBLRD is executed, all 22 bits of the TBLPTR determine which byte is read from program memory into TABLAT. TABLE POINTER REGISTER (TBLPTR) When a TBLWT is executed, the six LSbs of the Table Pointer register (TBLPTR<5:0>) determine which of the 64 program memory holding registers is written to. When the timed write to program memory begins (via the WR bit), the 15 MSbs of the TBLPTR (TBLPTR<20:6>) determine which program memory block of 64 bytes is written to. For more detail, see Section 7.5 "Writing to Flash Program Memory". The Table Pointer (TBLPTR) register addresses a byte within the program memory. The TBLPTR is comprised of three SFR registers: Table Pointer Upper Byte, Table Pointer High Byte and Table Pointer Low Byte (TBLPTRU:TBLPTRH:TBLPTRL). These three registers join to form a 22-bit wide pointer. The low-order 21 bits allow the device to address up to 2 Mbytes of program memory space. The 22nd bit allows access to the Device ID and Configuration bits. When an erase of program memory is executed, the 11 MSbs of the Table Pointer register (TBLPTR<20:10>) point to the 1024-byte block that will be erased. The Least Significant bits (TBLPTR<9:0>) are ignored. The Table Pointer register, TBLPTR, is used by the TBLRD and TBLWT instructions. These instructions can update the TBLPTR in one of four ways based on the table operation. These operations are shown in Table 7-1. The table operations on the TBLPTR only affect the low-order 21 bits. TABLE 7-1: TABLE POINTER BOUNDARIES Figure 7-3 describes the relevant boundaries of TBLPTR based on Flash program memory operations. TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS Example Operation on Table Pointer TBLRD* TBLWT* TBLPTR is not modified TBLRD*+ TBLWT*+ TBLPTR is incremented after the read/write TBLRD*TBLWT*- TBLPTR is decremented after the read/write TBLRD+* TBLWT+* TBLPTR is incremented before the read/write FIGURE 7-3: 21 TABLE POINTER BOUNDARIES BASED ON OPERATION TBLPTRU 16 15 TBLPTRH 8 7 TBLPTRL 0 Table Erase TBLPTR<20:10> Table Write TBLPTR<20:6> Table Read - TBLPTR<21:0> DS39762F-page 108 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 7.3 TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. Reading the Flash Program Memory The TBLRD instruction is used to retrieve data from program memory and places it into data RAM. Table reads from program memory are performed one byte at a time. FIGURE 7-4: The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 7-4 shows the interface between the internal program memory and the TABLAT. READS FROM FLASH PROGRAM MEMORY Program Memory (Even Byte Address) (Odd Byte Address) TBLPTR = xxxxx0 TBLPTR = xxxxx1 Instruction Register (IR) EXAMPLE 7-1: FETCH TBLRD TABLAT Read Register READING A FLASH PROGRAM MEMORY WORD MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; Load TBLPTR with the base ; address of the word READ_WORD TBLRD*+ MOVF MOVWF TBLRD*+ MOVFW MOVF TABLAT, W WORD_EVEN TABLAT, W WORD_ODD 2011 Microchip Technology Inc. ; read into TABLAT and increment ; get data ; read into TABLAT and increment ; get data DS39762F-page 109 PIC18F97J60 FAMILY 7.4 Erasing Flash Program Memory The minimum erase block is 1024 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be Bulk Erased. Word Erase in the Flash array is not supported. When initiating an erase sequence from the microcontroller itself, a block of 1024 bytes of program memory is erased. The Most Significant 11 bits of the TBLPTR<20:10> point to the block being erased. TBLPTR<9:0> are ignored. The EECON1 register commands the erase operation. The WREN bit must be set to enable write operations. The FREE bit is set to select an erase operation. For protection, the write initiate sequence for EECON2 must be used. A long write is necessary for erasing the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. An on-chip timer controls the erase time. The write/erase voltages are generated by an on-chip charge pump, rated to operate over most of the voltage range of the device. See Parameter D132B (VPEW) for specific limits. EXAMPLE 7-2: 7.4.1 FLASH PROGRAM MEMORY ERASE SEQUENCE The sequence of events for erasing a block of internal program memory location is: 1. 2. 3. 4. 5. 6. 7. 8. Load Table Pointer register with the address of row being erased. Set the EECON1 register for the erase operation: * set WREN bit to enable writes; * set FREE bit to enable the erase. Disable interrupts. Write 55h to EECON2. Write 0AAh to EECON2. Set the WR bit. This will begin the Row Erase cycle. The CPU will stall for the duration of the erase. Re-enable interrupts. ERASING A FLASH PROGRAM MEMORY ROW MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; load TBLPTR with the base ; address of the memory block BSF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF EECON1, EECON1, INTCON, 55h EECON2 0AAh EECON2 EECON1, INTCON, ; enable write to memory ; enable Row Erase operation ; disable interrupts ERASE_ROW Required Sequence DS39762F-page 110 WREN FREE GIE ; write 55h WR GIE ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 7.5 An on-chip timer controls the write time. The write/erase voltages are generated by an on-chip charge pump, rated to operate over most of the voltage range of the device. See Parameter D132B (VPEW) for specific limits. Writing to Flash Program Memory The minimum programming block is 32 words or 64 bytes. Word or byte programming is not supported. Table writes are used internally to load the holding registers needed to program the Flash memory. There are 64 holding registers used by the table writes for programming. Note 1: Unlike previous PIC MCU devices, members of the PIC18F97J60 family do not reset the holding registers after a write occurs. The holding registers must be cleared or overwritten before a programming sequence. Since the Table Latch (TABLAT) is only a single byte, the TBLWT instruction may need to be executed 64 times for each programming operation. All of the table write operations will essentially be short writes because only the holding registers are written. At the end of updating the 64 holding registers, the EECON1 register must be written to in order to start the programming operation with a long write. 2: To maintain the endurance of the program memory cells, each Flash byte should not be programmed more than one time between erase operations. Before attempting to modify the contents of the target cell a second time, a Row Erase of the target row, or a Bulk Erase of the entire memory, must be performed. The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. FIGURE 7-5: TABLE WRITES TO FLASH PROGRAM MEMORY TABLAT Write Register 8 8 TBLPTR = xxxxx0 8 TBLPTR = xxxxx1 Holding Register TBLPTR = xxxx3F TBLPTR = xxxxx2 Holding Register 8 Holding Register Holding Register Program Memory 7.5.1 FLASH PROGRAM MEMORY WRITE SEQUENCE The sequence of events for programming an internal program memory location should be: 1. 2. 3. 4. If the section of program memory to be written to has been programmed previously, then the memory will need to be erased before the write occurs (see Section 7.4.1 "Flash Program Memory Erase Sequence"). Write the 64 bytes into the holding registers with auto-increment. Set the WREN bit to enable byte writes. Disable interrupts. 2011 Microchip Technology Inc. 5. 6. 7. 8. 9. 10. Write 55h to EECON2. Write AAh to EECON2. Set the WR bit. This will begin the write cycle. The CPU will stall for the duration of the write. Re-enable interrupts. Verify the memory (table read). An example of the required code is shown in Example 7-3. Note: Before setting the WR bit, the Table Pointer address needs to be within the intended address range of the 64 bytes in the holding register. DS39762F-page 111 PIC18F97J60 FAMILY EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; Load TBLPTR with the base ; address of the memory block BSF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF MOVLW MOVWF EECON1, WREN EECON1, FREE INTCON, GIE 55h EECON2 0AAh EECON2 EECON1, WR INTCON, GIE D'16' WRITE_COUNTER ; enable write to memory ; enable Row Erase operation ; disable interrupts MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF D'64' COUNTER BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L ERASE_BLOCK ; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts ; Need to write 16 blocks of 64 to write ; one erase block of 1024 RESTART_BUFFER ; point to buffer FILL_BUFFER ... ; read the new data from I2C, SPI, ; PSP, USART, etc. WRITE_BUFFER MOVLW MOVWF WRITE_BYTE_TO_HREGS MOVFF MOVWF TBLWT+* D'64 COUNTER ; number of bytes in holding register POSTINC0, WREG TABLAT ; ; ; ; DECFSZ COUNTER ; BRA WRITE_BYTE_TO_HREGS get low byte of buffer data present data to table latch write data, perform a short write to internal TBLWT holding register. loop until buffers are full PROGRAM_MEMORY Required Sequence BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF BCF EECON1, INTCON, 55h EECON2 0AAh EECON2 EECON1, INTCON, EECON1, WREN GIE ; write 55h WR GIE WREN DECFSZ WRITE_COUNTER BRA RESTART_BUFFER DS39762F-page 112 ; enable write to memory ; disable interrupts ; ; ; ; write 0AAh start program (CPU stall) re-enable interrupts disable write to memory ; done with one write cycle ; if not done replacing the erase block 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 7.5.2 WRITE VERIFY 7.5.4 Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. 7.5.3 UNEXPECTED TERMINATION OF WRITE OPERATION If a write is terminated by an unplanned event, such as loss of power or an unexpected Reset, the memory location just programmed should be verified and reprogrammed if needed. If the write operation is interrupted by a MCLR Reset, or a WDT Time-out Reset during normal operation, the user can check the WRERR bit and rewrite the location(s) as needed. TABLE 7-2: PROTECTION AGAINST SPURIOUS WRITES To protect against spurious writes to Flash program memory, the write initiate sequence must also be followed. See Section 25.0 "Special Features of the CPU" for more details. 7.6 Flash Program Operation During Code Protection See Section 25.6 "Program Verification and Code Protection" for details on code protection of Flash program memory. REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY Name Bit 7 Bit 6 Bit 5 TBLPTRU -- -- bit 21 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) Reset Values on Page: 69 TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 69 TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 69 TABLAT 69 Program Memory Table Latch INTCON GIE/GIEH PEIE/GIEL TMR0IE EECON2 EEPROM Control Register 2 (not a physical register) EECON1 -- -- -- INT0IE FREE RBIE WRERR TMR0IF INT0IF RBIF 69 71 WREN WR -- 71 Legend: -- = unimplemented, read as `0'. Shaded cells are not used during Flash/EEPROM access. 2011 Microchip Technology Inc. DS39762F-page 113 PIC18F97J60 FAMILY NOTES: DS39762F-page 114 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 8.0 EXTERNAL MEMORY BUS Note: The external memory bus is not implemented on 64-pin and 80-pin devices. The External Memory Bus (EMB) allows the device to access external memory devices (such as Flash, EPROM, SRAM, etc.) as program or data memory. It supports both 8 and 16-Bit Data Width modes, and three address widths of up to 20 bits. TABLE 8-1: Name The bus is implemented with 28 pins, multiplexed across four I/O ports. Three ports (PORTD, PORTE and PORTH) are multiplexed with the address/data bus for a total of 20 available lines, while PORTJ is multiplexed with the bus control signals. A list of the pins and their functions is provided in Table 8-1. PIC18F96J60/96J65/97J60 EXTERNAL MEMORY BUS - I/O PORT FUNCTIONS Port Bit External Memory Bus Function RD0/AD0 PORTD 0 Address Bit 0 or Data Bit 0 RD1/AD1 PORTD 1 Address Bit 1 or Data Bit 1 RD2/AD2 PORTD 2 Address Bit 2 or Data Bit 2 RD3/AD3 PORTD 3 Address Bit 3 or Data Bit 3 RD4/AD4 PORTD 4 Address Bit 4 or Data Bit 4 RD5/AD5 PORTD 5 Address Bit 5 or Data Bit 5 RD6/AD6 PORTD 6 Address Bit 6 or Data Bit 6 RD7/AD7 PORTD 7 Address Bit 7 or Data Bit 7 RE0/AD8 PORTE 0 Address Bit 8 or Data Bit 8 RE1/AD9 PORTE 1 Address Bit 9 or Data Bit 9 RE2/AD10 PORTE 2 Address Bit 10 or Data Bit 10 RE3/AD11 PORTE 3 Address Bit 11 or Data Bit 11 RE4/AD12 PORTE 4 Address Bit 12 or Data Bit 12 RE5/AD13 PORTE 5 Address Bit 13 or Data Bit 13 RE6/AD14 PORTE 6 Address Bit 14 or Data Bit 14 RE7/AD15 PORTE 7 Address Bit 15 or Data Bit 15 RH0/A16 PORTH 0 Address Bit 16 RH1/A17 PORTH 1 Address Bit 17 RH2/A18 PORTH 2 Address Bit 18 RH3/A19 PORTH 3 Address Bit 19 RJ0/ALE PORTJ 0 Address Latch Enable (ALE) Control bit RJ1/OE PORTJ 1 Output Enable (OE) Control bit RJ2/WRL PORTJ 2 Write Low (WRL) Control bit RJ3/WRH PORTJ 3 Write High (WRH) Control bit RJ4/BA0 PORTJ 4 Byte Address (BA0) Bit 0 RJ5/CE PORTJ 5 Chip Enable (CE) Control bit RJ6/LB PORTJ 6 Lower Byte Enable (LB) Control bit RJ7/UB PORTJ 7 Upper Byte Enable (UB) Control bit Note: For the sake of clarity, only I/O port and external bus assignments are shown here. One or more additional multiplexed features may be available in some pins. 2011 Microchip Technology Inc. DS39762F-page 115 PIC18F97J60 FAMILY 8.1 External Memory Bus Control The operation of the interface is controlled by the MEMCON register (Register 8-1). This register is available in all program memory operating modes, except Microcontroller mode. In this mode, the register is disabled and cannot be written to. The EBDIS bit (MEMCON<7>) controls the operation of the bus and related port functions. Clearing EBDIS enables the interface and disables the I/O functions of the ports, as well as any other functions multiplexed to those pins. Setting the bit enables the I/O ports and other functions, but allows the interface to override everything else on the pins when an external memory operation is required. By default, the external bus is always enabled and disables all other I/Os. REGISTER 8-1: The operation of the EBDIS bit is also influenced by the program memory mode being used. This is discussed in more detail in Section 8.5 "Program Memory Modes and the External Memory Bus". The WAIT bits allow for the addition of Wait states to external memory operations. The use of these bits is discussed in Section 8.3 "Wait States". The WM bits select the particular operating mode used when the bus is operating in 16-Bit Data Width mode. These operating modes are discussed in more detail in Section 8.6 "16-Bit Data Width Modes". The WM bits have no effect when an 8-Bit Data Width mode is selected. MEMCON: EXTERNAL MEMORY BUS CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 EBDIS -- WAIT1 WAIT0 -- -- WM1 WM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 EBDIS: External Bus Disable bit 1 = External bus is enabled when microcontroller accesses external memory; otherwise, all external bus drivers are mapped as I/O ports 0 = External bus is always enabled, I/O ports are disabled bit 6 Unimplemented: Read as `0' bit 5-4 WAIT<1:0>: Table Reads and Writes Bus Cycle Wait Count bits 11 = Table reads and writes will wait 0 TCY 10 = Table reads and writes will wait 1 TCY 01 = Table reads and writes will wait 2 TCY 00 = Table reads and writes will wait 3 TCY bit 3-2 Unimplemented: Read as `0' bit 1-0 WM<1:0>: TBLWT Operation with 16-Bit Data Bus Width Select bits 1x = Word Write mode: WRH is active when TABLAT is written to and TBLPTR contains an odd address. When TBLPTR contains an even address, writing to TABLAT loads a holding latch with the value written. 01 = Byte Select mode: TABLAT data is copied on both MSB and LSB; WRH and (UB or LB) will activate 00 = Byte Write mode: TABLAT data is copied on both MSB and LSB; WRH or WRL will activate DS39762F-page 116 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 8.2 8.2.1 Address and Data Width The PIC18F97J60 family of devices can be independently configured for different address and data widths on the same memory bus. Both address and data widths are set by Configuration bits in the CONFIG3L register. As Configuration bits, this means that these options can only be configured by programming the device and are not controllable in software. The BW bit selects an 8-bit or 16-bit data bus width. Setting this bit (default) selects a data width of 16 bits. The EMB<1:0> bits determine both the program memory operating mode and the address bus width. The available options are 20-bit, 16-bit and 12-bit, as well as the default Microcontroller mode (external bus disabled). Selecting a 16-bit or 12-bit width makes a corresponding number of high-order lines available for I/O functions. These pins are no longer affected by the setting of the EBDIS bit. For example, selecting a 16-Bit Addressing mode (EMB<1:0> = 01) disables A<19:16> and allows the PORTH<3:0> bits to function without interruptions from the bus. Using the smaller address widths allows users to tailor the memory bus to the size of the external memory space for a particular design, while freeing up pins for dedicated I/O operation. Because the EMB bits have the effect of disabling pins for memory bus operations, it is important to always select an address width at least equal to the data width. If a 12-bit address width is used with a 16-bit data width, the upper four bits of data will not be available in the bus. All combinations of address and data widths require multiplexing of address and data information on the same lines. The address and data multiplexing, as well as I/O ports made available by the use of smaller address widths, are summarized in Table 8-2. TABLE 8-2: Data Width By default, the address presented on the external bus is the value of the PC. In practical terms, this means that addresses in the external memory device below the top of on-chip memory are unavailable to the microcontroller. To access these physical locations, the glue logic between the microcontroller and the external memory must somehow translate addresses. To simplify the interface, the external bus offers an extension of Extended Microcontroller mode that automatically performs address shifting. This feature is controlled by the EASHFT Configuration bit. Setting this bit offsets addresses on the bus by the size of the microcontroller's on-chip program memory and sets the bottom address at 0000h. This allows the device to use the entire range of physical addresses of the external memory. 8.2.2 This addressing mode is available in both 8-Bit Data Width and certain 16-Bit Data Width modes. Additional details are provided in Section 8.6.3 "16-Bit Byte Select Mode" and Section 8.7 "8-Bit Data Width Mode". ADDRESS AND DATA LINES FOR DIFFERENT ADDRESS AND DATA WIDTHS Address Width Multiplexed Data and Address Lines (and corresponding ports) 16-bit AD<7:0> (PORTD<7:0>) 20-bit 16-bit 16-bit 21-BIT ADDRESSING As an extension of 20-bit address width operation, the external memory bus can also fully address a 2-Mbyte memory space. This is done by using the Bus Address Bit 0 (BA0) control line as the Least Significant bit of the address. The UB and LB control signals may also be used with certain memory devices to select the upper and lower bytes within a 16-bit wide data word. 12-bit 8-bit ADDRESS SHIFTING ON THE EXTERNAL BUS 20-bit 2011 Microchip Technology Inc. AD<15:0> (PORTD<7:0>, PORTE<7:0>) Address Only Lines (and corresponding ports) Ports Available for I/O AD<11:8> (PORTE<3:0>) PORTE<7:4>, All of PORTH AD<15:8> (PORTE<7:0>) All of PORTH A<19:16>, AD<15:8> (PORTH<3:0>, PORTE<7:0>) -- -- All of PORTH A<19:16> (PORTH<3:0>) -- DS39762F-page 117 PIC18F97J60 FAMILY 8.3 Wait States While it may be assumed that external memory devices will operate at the microcontroller clock rate, this is often not the case. In fact, many devices require longer times to write or retrieve data than the time allowed by the execution of table read or table write operations. To compensate for this, the external memory bus can be configured to add a fixed delay to each table operation using the bus. Wait states are enabled by setting the WAIT Configuration bit. When enabled, the amount of delay is set by the WAIT<1:0> bits (MEMCON<5:4>). The delay is based on multiples of microcontroller instruction cycle time and is added following the instruction cycle when the table operation is executed. The range is from no delay to 3 TCY (default value). 8.4 Port Pin Weak Pull-ups With the exception of the upper address lines, A<19:16>, the pins associated with the external memory bus are equipped with weak pull-ups. The pull-ups are controlled by bits located at LATA<7:6> and PORTA<7>. They are named RDPU, REPU and RJPU and control pull-ups on PORTD, PORTE and PORTJ, respectively. Setting one of these bits enables the corresponding pull-ups for that port. All pull-ups are disabled by default on all device Resets. In Extended Microcontroller mode, the port pull-ups can be useful in preserving the memory state on the external bus while the bus is temporarily disabled (EBDIS = 1). 8.5 Program Memory Modes and the External Memory Bus The PIC18F97J60 family of devices is capable of operating in one of two program memory modes, using combinations of on-chip and external program memory. The functions of the multiplexed port pins depend on the program memory mode selected, as well as the setting of the EBDIS bit. In Microcontroller Mode, the bus is not active and the pins have their port functions only. Writes to the MEMCOM register are not permitted. The Reset value of EBDIS (`0') is ignored and the EMB pins behave as I/O ports. In Extended Microcontroller Mode, the external program memory bus shares I/O port functions on the pins. When the device is fetching, or doing table read/table write operations on the external program memory space, the pins will have the external bus function. If the device is fetching and accessing internal program memory locations only, the EBDIS control bit will change the pins from external memory to I/O port functions. When EBDIS = 0, the pins function as the external bus. When EBDIS = 1, the pins function as I/O ports. DS39762F-page 118 If the device fetches or accesses external memory while EBDIS = 1, the pins will switch to the external bus. If the EBDIS bit is set by a program executing from external memory, the action of setting the bit will be delayed until the program branches into the internal memory. At that time, the pins will change from external bus to I/O ports. If the device is executing out of internal memory when EBDIS = 0, the memory bus address/data and control pins will not be active. They will go to a state where the active address/data pins are tri-state; the CE, OE, WRH, WRL, UB and LB signals are `1', and ALE and BA0 are `0'. Note that only those pins associated with the current address width are forced to tri-state; the other pins continue to function as I/O. In the case of 16-bit address width, for example, only AD<15:0> (PORTD and PORTE) are affected; A<19:16> (PORTH<3:0>) continue to function as I/O. In all external memory modes, the bus takes priority over any other peripherals that may share pins with it. This includes the Parallel Slave Port and serial communication modules, which would otherwise take priority over the I/O port. 8.6 16-Bit Data Width Modes In 16-Bit Data Width mode, the external memory interface can be connected to external memories in three different configurations: * 16-Bit Byte Write * 16-Bit Word Write * 16-Bit Byte Select The configuration to be used is determined by the WM<1:0> bits in the MEMCON register (MEMCON<1:0>). These three different configurations allow the designer maximum flexibility in using both 8-bit and 16-bit devices with 16-bit data. For all 16-Bit Data Width modes, the Address Latch Enable (ALE) pin indicates that the address bits, AD<15:0>, are available in the external memory interface bus. Following the address latch, the Output Enable signal (OE) will enable both bytes of program memory at once to form a 16-bit instruction word. The Chip Enable signal (CE) is active at any time that the microcontroller accesses external memory, whether reading or writing. It is inactive (asserted high) whenever the device is in Sleep mode. In Byte Select mode, JEDEC standard Flash memories will require BA0 for the byte address line and one I/O line to select between Byte and Word mode. The other 16-Bit Data Width modes do not need BA0. JEDEC standard, static RAM memories will use the UB or LB signals for byte selection. 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 8.6.1 16-BIT BYTE WRITE MODE During a TBLWT instruction cycle, the TABLAT data is presented on the upper and lower bytes of the AD<15:0> bus. The appropriate WRH or WRL control line is strobed on the LSb of the TBLPTR. Figure 8-1 shows an example of 16-Bit Byte Write mode for PIC18F97J60 family devices. This mode is used for two separate 8-bit memories connected for 16-bit operation. This generally includes basic EPROM and Flash devices. It allows table writes to byte-wide external memories. FIGURE 8-1: 16-BIT BYTE WRITE MODE EXAMPLE D<7:0> PIC18F97J60 AD<7:0> (MSB) 373 A<19:0> D<15:8> (LSB) A<x:0> A<x:0> D<7:0> D<7:0> CE AD<15:8> 373 OE D<7:0> CE WR (2) OE WR(2) ALE A<19:16>(1) CE OE WRH WRL Address Bus Data Bus Control Lines Note 1: 2: The upper order address lines are used only for 20-bit address widths. This signal only applies to table writes. See Section 7.1 "Table Reads and Table Writes". 2011 Microchip Technology Inc. DS39762F-page 119 PIC18F97J60 FAMILY 8.6.2 16-BIT WORD WRITE MODE Figure 8-2 shows an example of 16-Bit Word Write mode for PIC18F97J60 family devices. This mode is used for word-wide memories, which include some of the EPROM and Flash type memories. This mode allows opcode fetches and table reads from all forms of 16-bit memory, and table writes to any type of word-wide external memories. This method makes a distinction between TBLWT cycles to even or odd addresses. During a TBLWT cycle to an even address (TBLPTR<0> = 0), the TABLAT data is transferred to a holding latch and the external address data bus is tri-stated for the data portion of the bus cycle. No write signals are activated. FIGURE 8-2: During a TBLWT cycle to an odd address (TBLPTR<0> = 1), the TABLAT data is presented on the upper byte of the AD<15:0> bus. The contents of the holding latch are presented on the lower byte of the AD<15:0> bus. The WRH signal is strobed for each write cycle; the WRL pin is unused. The signal on the BA0 pin indicates the LSb of the TBLPTR but it is left unconnected. Instead, the UB and LB signals are active to select both bytes. The obvious limitation to this method is that the table write must be done in pairs on a specific word boundary to correctly write a word location. 16-BIT WORD WRITE MODE EXAMPLE PIC18F97J60 AD<7:0> 373 A<20:1> A<x:0> D<15:0> JEDEC Word EPROM Memory D<15:0> CE AD<15:8> OE WR(2) 373 ALE A<19:16>(1) CE OE WRH Address Bus Data Bus Control Lines Note 1: 2: DS39762F-page 120 The upper order address lines are used only for 20-bit address widths. This signal only applies to table writes. See Section 7.1 "Table Reads and Table Writes". 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 8.6.3 16-BIT BYTE SELECT MODE Figure 8-3 shows an example of 16-Bit Byte Select mode. This mode allows table write operations to word-wide external memories with byte selection capability. This generally includes both word-wide Flash and SRAM devices. During a TBLWT cycle, the TABLAT data is presented on the upper and lower byte of the AD<15:0> bus. The WRH signal is strobed for each write cycle; the WRL pin is not used. The BA0 or UB/LB signals are used to select the byte to be written based on the Least Significant bit of the TBLPTR register. FIGURE 8-3: Flash and SRAM devices use different control signal combinations to implement Byte Select mode. JEDEC standard Flash memories require that a controller I/O port pin be connected to the memory's BYTE/WORD pin to provide the select signal. They also use the BA0 signal from the controller as a byte address. JEDEC standard, static RAM memories, on the other hand, use the UB or LB signals to select the byte. 16-BIT BYTE SELECT MODE EXAMPLE PIC18F97J60 AD<7:0> 373 A<20:1> A<x:1> JEDEC Word FLASH Memory D<15:0> AD<15:8> 138(3) 373 CE A0 BYTE/WORD ALE D<15:0> OE WR(1) A<19:16>(2) OE WRH A<20:1> A<x:1> BA0 JEDEC Word SRAM Memory I/O LB UB CE D<15:0> CE LB UB D<15:0> OE WR(1) Address Bus Data Bus Control Lines Note 1: This signal only applies to table writes. See Section 7.1 "Table Reads and Table Writes". 2: The upper order address lines are used only for 20-bit address width. 3: Demultiplexing is only required when multiple memory devices are accessed. 2011 Microchip Technology Inc. DS39762F-page 121 PIC18F97J60 FAMILY 8.6.4 16-BIT MODE TIMING The presentation of control signals on the external memory bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure 8-4 and Figure 8-5. FIGURE 8-4: EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED MICROCONTROLLER MODE) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 A<19:16> Q3 Q4 Q1 Q2 Q3 Q4 0Ch CF33h AD<15:0> 9256h CE ALE OE Memory Cycle Opcode Fetch TBLRD* from 000100h Opcode Fetch MOVLW 55h from 000102h TBLRD 92h from 199E67h Opcode Fetch ADDLW 55h from 000104h Instruction Execution INST(PC - 2) TBLRD Cycle 1 TBLRD Cycle 2 MOVLW FIGURE 8-5: EXTERNAL MEMORY BUS TIMING FOR SLEEP (EXTENDED MICROCONTROLLER MODE) Q1 Q2 A<19:16> AD<15:0> Q3 Q4 Q1 Q2 00h 3AAAh Q3 Q4 Q1 00h 0003h 3AABh 0E55h CE ALE OE Memory Cycle Opcode Fetch SLEEP from 007554h Opcode Fetch MOVLW 55h from 007556h Instruction Execution INST(PC - 2) SLEEP DS39762F-page 122 Sleep Mode, Bus Inactive 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 8.7 will enable one byte of program memory for a portion of the instruction cycle, then BA0 will change and the second byte will be enabled to form the 16-bit instruction word. The Least Significant bit of the address, BA0, must be connected to the memory devices in this mode. The Chip Enable signal (CE) is active at any time that the microcontroller accesses external memory, whether reading or writing. It is inactive (asserted high) whenever the device is in Sleep mode. 8-Bit Data Width Mode In 8-Bit Data Width mode, the external memory bus operates only in Multiplexed mode; that is, data shares the eight Least Significant bits of the address bus. Figure 8-6 shows an example of 8-Bit Multiplexed mode for 100-pin devices. This mode is used for a single 8-bit memory connected for 16-bit operation. The instructions will be fetched as two 8-bit bytes on a shared data/address bus. The two bytes are sequentially fetched within one instruction cycle (TCY). Therefore, the designer must choose external memory devices according to timing calculations based on 1/2 TCY (2 times the instruction rate). For proper memory speed selection, glue logic propagation delay times must be considered, along with setup and hold times. This process generally includes basic EPROM and Flash devices. It allows table writes to byte-wide external memories. During a TBLWT instruction cycle, the TABLAT data is presented on the upper and lower bytes of the AD<15:0> bus. The appropriate level of the BA0 control line is strobed on the LSb of the TBLPTR. The Address Latch Enable (ALE) pin indicates that the address bits, AD<15:0>, are available in the external memory interface bus. The Output Enable signal (OE) FIGURE 8-6: 8-BIT MULTIPLEXED MODE EXAMPLE D<7:0> PIC18F97J60 AD<7:0> ALE 373 A<19:0> A<x:1> A0 D<15:8> D<7:0> AD<15:8>(1) CE A<19:16>(1) OE WR(2) BA0 CE OE WRL Address Bus Data Bus Control Lines Note 1: 2: The upper order address bits are used only for 20-bit address width. The upper AD byte is used for all address widths except 8-bit. This signal only applies to table writes. See Section 7.1 "Table Reads and Table Writes". 2011 Microchip Technology Inc. DS39762F-page 123 PIC18F97J60 FAMILY 8.7.1 8-BIT MODE TIMING The presentation of control signals on the external memory bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure 8-7 and Figure 8-8. FIGURE 8-7: EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED MICROCONTROLLER MODE) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 0Ch A<19:16> CFh AD<15:8> AD<7:0> 92h 33h CE ALE OE Memory Cycle Opcode Fetch TBLRD* from 000100h Opcode Fetch MOVLW 55h from 000102h TBLRD 92h from 199E67h Opcode Fetch ADDLW 55h from 000104h Instruction Execution INST(PC - 2) TBLRD Cycle 1 TBLRD Cycle 2 MOVLW FIGURE 8-8: EXTERNAL MEMORY BUS TIMING FOR SLEEP (EXTENDED MICROCONTROLLER MODE) Q1 Q2 A<19:16> Q4 Q1 Q2 3Ah AAh 00h Q3 Q4 Q1 00h 00h AD<15:8> AD<7:0> Q3 3Ah 03h ABh 0Eh 55h BA0 CE ALE OE Memory Cycle Opcode Fetch SLEEP from 007554h Opcode Fetch MOVLW 55h from 007556h Instruction Execution INST(PC - 2) SLEEP DS39762F-page 124 Sleep Mode, Bus Inactive 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 8.8 Operation in Power-Managed Modes In alternate power-managed Run modes, the external bus continues to operate normally. If a clock source with a lower speed is selected, bus operations will run at that speed. In these cases, excessive access times for the external memory may result if Wait states have been enabled and added to external memory operations. If operations in a lower power Run mode are anticipated, user applications should provide memory access time adjustments at the lower clock speeds. 2011 Microchip Technology Inc. In Sleep and Idle modes, the microcontroller core does not need to access data; bus operations are suspended. The state of the external bus is frozen, with the address/data pins and most of the control pins holding at the same state they were in when the mode was invoked. The only potential changes are the CE, LB and UB pins, which are held at logic high. DS39762F-page 125 PIC18F97J60 FAMILY NOTES: DS39762F-page 126 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 9.0 8 x 8 HARDWARE MULTIPLIER 9.1 Introduction EXAMPLE 9-1: MOVF MULWF All PIC18 devices include an 8 x 8 hardware multiplier as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL. The multiplier's operation does not affect any flags in the STATUS register. ARG1, W ARG2 EXAMPLE 9-2: Making multiplication a hardware operation allows it to be completed in a single instruction cycle. This has the advantages of higher computational throughput and reduced code size for multiplication algorithms and allows the PIC18 devices to be used in many applications previously reserved for digital signal processors. A comparison of various hardware and software multiply operations, along with the savings in memory and execution time, is shown in Table 9-1. 9.2 8 x 8 UNSIGNED MULTIPLY ROUTINE ; ; ARG1 * ARG2 -> ; PRODH:PRODL 8 x 8 SIGNED MULTIPLY ROUTINE MOVF MULWF ARG1, W ARG2 BTFSC SUBWF ARG2, SB PRODH, F MOVF BTFSC SUBWF ARG2, W ARG1, SB PRODH, F ; ; ; ; ; ARG1 * ARG2 -> PRODH:PRODL Test Sign Bit PRODH = PRODH - ARG1 ; Test Sign Bit ; PRODH = PRODH ; - ARG2 Operation Example 9-1 shows the instruction sequence for an 8 x 8 unsigned multiplication. Only one instruction is required when one of the arguments is already loaded in the WREG register. Example 9-2 shows the sequence to do an 8 x 8 signed multiplication. To account for the sign bits of the arguments, each argument's Most Significant bit (MSb) is tested and the appropriate subtractions are done. TABLE 9-1: PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS Routine 8 x 8 unsigned 8 x 8 signed 16 x 16 unsigned 16 x 16 signed Multiply Method Without hardware multiply Program Memory (Words) Cycles (Max) @ 40 MHz @ 10 MHz @ 4 MHz 13 69 6.9 s 27.6 s 69 s Time Hardware multiply 1 1 100 ns 400 ns 1 s Without hardware multiply 33 91 9.1 s 36.4 s 91 s Hardware multiply 6 6 600 ns 2.4 s 6 s Without hardware multiply 21 242 24.2 s 96.8 s 242 s Hardware multiply 28 28 2.8 s 11.2 s 28 s Without hardware multiply 52 254 25.4 s 102.6 s 254 s Hardware multiply 35 40 4.0 s 16.0 s 40 s 2011 Microchip Technology Inc. DS39762F-page 127 PIC18F97J60 FAMILY Example 9-3 shows the sequence to do a 16 x 16 unsigned multiplication. Equation 9-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0). EQUATION 9-1: RES3:RES0 = = EXAMPLE 9-3: 16 x 16 UNSIGNED MULTIPLICATION ALGORITHM ARG1H:ARG1L ARG2H:ARG2L (ARG1H ARG2H 216) + (ARG1H ARG2L 28) + (ARG1L ARG2H 28) + (ARG1L ARG2L) EQUATION 9-2: RES3:RES0= ARG1H:ARG1L ARG2H:ARG2L = (ARG1H ARG2H 216) + (ARG1H ARG2L 28) + (ARG1L ARG2H 28) + (ARG1L ARG2L) + (-1 ARG2H<7> ARG1H:ARG1L 216) + (-1 ARG1H<7> ARG2H:ARG2L 216) EXAMPLE 9-4: 16 x 16 UNSIGNED MULTIPLY ROUTINE MOVF MULWF ARG1L, W ARG2L MOVFF MOVFF PRODH, RES1 PRODL, RES0 MOVF MULWF ARG1H, W ARG2H MOVFF MOVFF PRODH, RES3 PRODL, RES2 MOVF MULWF ARG1L, W ARG2H MOVF ADDWF MOVF ADDWFC CLRF ADDWFC PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F MOVF MULWF ARG1H, W ARG2L MOVF ADDWF MOVF ADDWFC CLRF ADDWFC PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F ; ARG1L * ARG2L-> ; PRODH:PRODL ; ; ARG1L * ARG2H-> PRODH:PRODL Add cross products ARG1H * ARG2L-> PRODH:PRODL Add cross products Example 9-4 shows the sequence to do a 16 x 16 signed multiply. Equation 9-2 shows the algorithm used. The 32-bit result is stored in four registers (RES3:RES0). To account for the sign bits of the arguments, the MSb for each argument pair is tested and the appropriate subtractions are done. DS39762F-page 128 ARG1L, W ARG2L MOVFF MOVFF PRODH, RES1 PRODL, RES0 MOVF MULWF ARG1H, W ARG2H MOVFF MOVFF PRODH, RES3 PRODL, RES2 MOVF MULWF ARG1L, W ARG2H MOVF ADDWF MOVF ADDWFC CLRF ADDWFC PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F MOVF MULWF ARG1H, W ARG2L MOVF ADDWF MOVF ADDWFC CLRF ADDWFC PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F BTFSS BRA MOVF SUBWF MOVF SUBWFB ARG2H, 7 SIGN_ARG1 ARG1L, W RES2 ARG1H, W RES3 ; ARG2H:ARG2L neg? ; no, check ARG1 ; ; ; ARG1H, 7 CONT_CODE ARG2L, W RES2 ARG2H, W RES3 ; ARG1H:ARG1L neg? ; no, done ; ; ; ; ARG1L * ARG2L -> ; PRODH:PRODL ; ; ; ARG1H * ARG2H -> ; PRODH:PRODL ; ; ; ; ; ; ; ; ; ; ARG1L * ARG2H -> PRODH:PRODL Add cross products ; ; ; ; ; ; ; ; ; ; ; MOVF MULWF ; ; ; ; ; ; ; ; ; ; 16 x 16 SIGNED MULTIPLY ROUTINE ; ; ; ARG1H * ARG2H-> ; PRODH:PRODL ; ; 16 x 16 SIGNED MULTIPLICATION ALGORITHM ; ; ; ; ; ; ; ; ; ARG1H * ARG2L -> PRODH:PRODL Add cross products ; ; SIGN_ARG1 BTFSS BRA MOVF SUBWF MOVF SUBWFB ; CONT_CODE : 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 10.0 INTERRUPTS Members of the PIC18F97J60 family of devices have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high-priority level or a low-priority level. The high-priority interrupt vector is at 0008h and the low-priority interrupt vector is at 0018h. High-priority interrupt events will interrupt any low-priority interrupts that may be in progress. There are thirteen registers which are used to control interrupt operation. These registers are: * * * * * * * RCON INTCON INTCON2 INTCON3 PIR1, PIR2, PIR3 PIE1, PIE2, PIE3 IPR1, IPR2, IPR3 It is recommended that the Microchip header files supplied with MPLAB(R) IDE be used for the symbolic bit names in these registers. This allows the assembler/compiler to automatically take care of the placement of these bits within the specified register. In general, interrupt sources have three bits to control their operation. They are: * Flag bit to indicate that an interrupt event occurred * Enable bit that allows program execution to branch to the interrupt vector address when the flag bit is set * Priority bit to select high priority or low priority The interrupt priority feature is enabled by setting the IPEN bit (RCON<7>). When interrupt priority is enabled, there are two bits which enable interrupts globally. Setting the GIEH bit (INTCON<7>) enables all interrupts that have the priority bit set (high priority). Setting the GIEL bit (INTCON<6>) enables all interrupts that have the priority bit cleared (low priority). When the interrupt flag, enable bit and appropriate Global Interrupt Enable bit are set, the interrupt will vector immediately to address, 0008h or 0018h, depending on the priority bit setting. Individual interrupts can be disabled through their corresponding enable bits. 2011 Microchip Technology Inc. When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are compatible with PIC(R) mid-range devices. In Compatibility mode, the interrupt priority bits for each source have no effect. INTCON<6> is the PEIE bit which enables/disables all peripheral interrupt sources. INTCON<7> is the GIE bit which enables/disables all interrupt sources. All interrupts branch to address, 0008h, in Compatibility mode. When an interrupt is responded to, the Global Interrupt Enable bit is cleared to disable further interrupts. If the IPEN bit is cleared, this is the GIE bit. If interrupt priority levels are used, this will be either the GIEH or GIEL bit. High-priority interrupt sources can interrupt a low-priority interrupt. Low-priority interrupts are not processed while high-priority interrupts are in progress. The return address is pushed onto the stack and the PC is loaded with the interrupt vector address (0008h or 0018h). Once in the Interrupt Service Routine (ISR), the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bits must be cleared in software before re-enabling interrupts to avoid recursive interrupts. The "return from interrupt" instruction, RETFIE, exits the interrupt routine and sets the GIE bit (GIEH or GIEL if priority levels are used) which re-enables interrupts. For external interrupt events, such as the INTx pins or the PORTB input change interrupt, the interrupt latency will be three to four instruction cycles. The exact latency is the same for one or two-cycle instructions. Individual interrupt flag bits are set regardless of the status of their corresponding enable bit or the GIE bit. Note: Do not use the MOVFF instruction to modify any of the interrupt control registers while any interrupt is enabled. Doing so may cause erratic microcontroller behavior. DS39762F-page 129 PIC18F97J60 FAMILY FIGURE 10-1: PIC18F97J60 FAMILY INTERRUPT LOGIC PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:5,3,1:0> PIE2<7:5,3,1:0> IPR2<7:5,3,1:0> Wake-up if in Idle or Sleep modes TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP Interrupt to CPU Vector to Location 0008h GIE/GIEH IPEN IPEN PEIE/GIEL PIR3<7:0> PIE3<7:0> IPR3<7:0> IPEN High-Priority Interrupt Generation Low-Priority Interrupt Generation PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:5,3,1:0> PIE2<7:5,3,1:0> IPR2<7:5,3,1:0> PIR3<7:0> PIE3<7:0> IPR3<7:0> TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP DS39762F-page 130 Interrupt to CPU Vector to Location 0018h IPEN GIE/GIEH PEIE/GIEL 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 10.1 INTCON Registers Note: The INTCON registers are readable and writable registers which contain various enable, priority and flag bits. REGISTER 10-1: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. INTCON: INTERRUPT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 GIE/GIEH: Global Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked interrupts 0 = Disables all interrupts When IPEN = 1: 1 = Enables all high-priority interrupts 0 = Disables all interrupts bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts When IPEN = 1: 1 = Enables all low-priority peripheral interrupts 0 = Disables all low-priority peripheral interrupts bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt bit 4 INT0IE: INT0 External Interrupt Enable bit 1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt bit 3 RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1 INT0IF: INT0 External Interrupt Flag bit 1 = The INT0 external interrupt occurred (must be cleared in software) 0 = The INT0 external interrupt did not occur bit 0 RBIF: RB Port Change Interrupt Flag bit(1) 1 = At least one of the RB<7:4> pins changed state (must be cleared in software) 0 = None of the RB<7:4> pins have changed state Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. 2011 Microchip Technology Inc. DS39762F-page 131 PIC18F97J60 FAMILY REGISTER 10-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 5 INTEDG1: External Interrupt 1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 4 INTEDG2: External Interrupt 2 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 3 INTEDG3: External Interrupt 3 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 INT3IP: INT3 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 RBIP: RB Port Change Interrupt Priority bit 1 = High priority 0 = Low priority Note: x = Bit is unknown Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS39762F-page 132 2011 Microchip Technology Inc. PIC18F97J60 FAMILY REGISTER 10-3: INTCON3: INTERRUPT CONTROL REGISTER 3 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 INT3IE: INT3 External Interrupt Enable bit 1 = Enables the INT3 external interrupt 0 = Disables the INT3 external interrupt bit 4 INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt bit 3 INT1IE: INT1 External Interrupt Enable bit 1 = Enables the INT1 external interrupt 0 = Disables the INT1 external interrupt bit 2 INT3IF: INT3 External Interrupt Flag bit 1 = The INT3 external interrupt occurred (must be cleared in software) 0 = The INT3 external interrupt did not occur bit 1 INT2IF: INT2 External Interrupt Flag bit 1 = The INT2 external interrupt occurred (must be cleared in software) 0 = The INT2 external interrupt did not occur bit 0 INT1IF: INT1 External Interrupt Flag bit 1 = The INT1 external interrupt occurred (must be cleared in software) 0 = The INT1 external interrupt did not occur Note: x = Bit is unknown Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. 2011 Microchip Technology Inc. DS39762F-page 133 PIC18F97J60 FAMILY 10.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Request (Flag) registers (PIR1, PIR2, PIR3). REGISTER 10-4: Note 1: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE (INTCON<7>). 2: User software should ensure the appropriate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt. PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIF(1) ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit(1) 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete bit 5 RC1IF: EUSART1 Receive Interrupt Flag bit 1 = The EUSART1 receive buffer, RCREG1, is full (cleared when RCREG1 is read) 0 = The EUSART1 receive buffer is empty bit 4 TX1IF: EUSART1 Transmit Interrupt Flag bit 1 = The EUSART1 transmit buffer, TXREG1, is empty (cleared when TXREG1 is written) 0 = The EUSART1 transmit buffer is full bit 3 SSP1IF: MSSP1 Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 2 CCP1IF: ECCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode. bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Note 1: Implemented in 100-pin devices in Microcontroller mode only. DS39762F-page 134 2011 Microchip Technology Inc. PIC18F97J60 FAMILY REGISTER 10-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 OSCFIF CMIF ETHIF r BCL1IF -- TMR3IF CCP2IF bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = System oscillator failed, clock input has changed to INTRC (must be cleared in software) 0 = System clock is operating bit 6 CMIF: Comparator Interrupt Flag bit 1 = Comparator input has changed (must be cleared in software) 0 = Comparator input has not changed bit 5 ETHIF: Ethernet Module Interrupt Flag bit 1 = An Ethernet module interrupt event has occurred; query EIR register to resolve source 0 = No Ethernet interrupt event has occurred bit 4 Reserved: Maintain as `0' bit 3 BCL1IF: Bus Collision Interrupt Flag bit (MSSP1 module) 1 = A bus collision occurred (must be cleared in software) 0 = No bus collision occurred bit 2 Unimplemented: Read as `0' bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared in software) 0 = TMR3 register did not overflow bit 0 CCP2IF: ECCP2 Interrupt Flag bit Capture mode: 1 = A TMR1/TMR3 register capture occurred (must be cleared in software) 0 = No TMR1/TMR3 register capture occurred Compare mode: 1 = A TMR1/TMR3 register compare match occurred (must be cleared in software) 0 = No TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. 2011 Microchip Technology Inc. DS39762F-page 135 PIC18F97J60 FAMILY REGISTER 10-6: R/W-0 SSP2IF (1) PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 BCL2IF(1) RC2IF(2) TX2IF(2) TMR4IF CCP5IF CCP4IF CCP3IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 SSP2IF: MSSP2 Interrupt Flag bit(1) 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 6 BCL2IF: Bus Collision Interrupt Flag bit (MSSP2 module)(1) 1 = A bus collision occurred (must be cleared in software) 0 = No bus collision occurred bit 5 RC2IF: EUSART2 Receive Interrupt Flag bit(2) 1 = The EUSART2 receive buffer, RCREG2, is full (cleared when RCREG2 is read) 0 = The EUSART2 receive buffer is empty bit 4 TX2IF: EUSART2 Transmit Interrupt Flag bit(2) 1 = The EUSART2 transmit buffer, TXREG2, is empty (cleared when TXREG2 is written) 0 = The EUSART2 transmit buffer is full bit 3 TMR4IF: TMR4 to PR4 Match Interrupt Flag bit 1 = TMR4 to PR4 match occurred (must be cleared in software) 0 = No TMR4 to PR4 match occurred bit 2 CCP5IF: CCP5 Interrupt Flag bit Capture mode: 1 = A TMR1/TMR3 register capture occurred (must be cleared in software) 0 = No TMR1/TMR3 register capture occurred Compare mode: 1 = A TMR1/TMR3 register compare match occurred (must be cleared in software) 0 = No TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. bit 1 CCP4IF: CCP4 Interrupt Flag bit Capture mode: 1 = A TMR1/TMR3 register capture occurred (must be cleared in software) 0 = No TMR1/TMR3 register capture occurred Compare mode: 1 = A TMR1/TMR3 register compare match occurred (must be cleared in software) 0 = No TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. bit 0 CCP3IF: ECCP3 Interrupt Flag bit Capture mode: 1 = A TMR1/TMR3 register capture occurred (must be cleared in software) 0 = No TMR1/TMR3 register capture occurred Compare mode: 1 = A TMR1/TMR3 register compare match occurred (must be cleared in software) 0 = No TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. Note 1: 2: Implemented in 100-pin devices only. Implemented in 80-pin and 100-pin devices only. DS39762F-page 136 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 10.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Enable registers (PIE1, PIE2, PIE3). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts. REGISTER 10-7: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIE(1) ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit(1) 1 = Enabled 0 = Disabled bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5 RC1IE: EUSART1 Receive Interrupt Enable bit 1 = Enabled 0 = Disabled bit 4 TX1IE: EUSART1 Transmit Interrupt Enable bit 1 = Enabled 0 = Disabled bit 3 SSP1IE: MSSP1 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 2 CCP1IE: ECCP1 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled Note 1: x = Bit is unknown Implemented in 100-pin devices in Microcontroller mode only. 2011 Microchip Technology Inc. DS39762F-page 137 PIC18F97J60 FAMILY REGISTER 10-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 OSCFIE CMIE ETHIE r BCL1IE -- TMR3IE CCP2IE bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CMIE: Comparator Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5 ETHIE: Ethernet Module Interrupt Enable bit 1 = Enabled 0 = Disabled bit 4 Reserved: Maintain as `0' bit 3 BCL1IE: Bus Collision Interrupt Enable bit (MSSP1 module) 1 = Enabled 0 = Disabled bit 2 Unimplemented: Read as `0' bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP2IE: ECCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled DS39762F-page 138 x = Bit is unknown 2011 Microchip Technology Inc. PIC18F97J60 FAMILY REGISTER 10-9: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 SSP2IE(1) BCL2IE(1) RC2IE(2) TX2IE(2) TMR4IE CCP5IE CCP4IE CCP3IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 SSP2IE: MSSP2 Interrupt Enable bit(1) 1 = Enabled 0 = Disabled bit 6 BCL2IE: Bus Collision Interrupt Enable bit (MSSP2 module)(1) 1 = Enabled 0 = Disabled bit 5 RC2IE: EUSART2 Receive Interrupt Enable bit(2) 1 = Enabled 0 = Disabled bit 4 TX2IE: EUSART2 Transmit Interrupt Enable bit(2) 1 = Enabled 0 = Disabled bit 3 TMR4IE: TMR4 to PR4 Match Interrupt Enable bit 1 = Enabled 0 = Disabled bit 2 CCP5IE: CCP5 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 CCP4IE: CCP4 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP3IE: ECCP3 Interrupt Enable bit 1 = Enabled 0 = Disabled Note 1: 2: x = Bit is unknown Implemented in 100-pin devices only. Implemented in 80-pin and 100-pin devices only. 2011 Microchip Technology Inc. DS39762F-page 139 PIC18F97J60 FAMILY 10.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2, IPR3). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set. REGISTER 10-10: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 PSPIP(1) ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit(1) 1 = High priority 0 = Low priority bit 6 ADIP: A/D Converter Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 RC1IP: EUSART1 Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TX1IP: EUSART1 Transmit Interrupt Priority bit x = Bit is unknown 1 = High priority 0 = Low priority bit 3 SSP1IP: MSSP1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 CCP1IP: ECCP1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority Note 1: Implemented in 100-pin devices in Microcontroller mode only. DS39762F-page 140 2011 Microchip Technology Inc. PIC18F97J60 FAMILY REGISTER 10-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 R/W-1 OSCFIP CMIP ETHIP r BCL1IP -- TMR3IP CCP2IP bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 CMIP: Comparator Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 ETHIP: Ethernet Module Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 Reserved: Maintain as `1' bit 3 BCL1IP: Bus Collision Interrupt Priority bit (MSSP1 module) 1 = High priority 0 = Low priority bit 2 Unimplemented: Read as `0' bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: ECCP2 Interrupt Priority bit 1 = High priority 0 = Low priority 2011 Microchip Technology Inc. x = Bit is unknown DS39762F-page 141 PIC18F97J60 FAMILY REGISTER 10-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 SSP2IP(1) BCL2IP(1) RC2IP(2) TX2IP(2) TMR4IP CCP5IP CCP4IP CCP3IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 SSP2IP: MSSP2 Interrupt Priority bit(1) 1 = High priority 0 = Low priority bit 6 BCL2IP: Bus Collision Interrupt Priority bit (MSSP2 module)(1) 1 = High priority 0 = Low priority bit 5 RC2IP: EUSART2 Receive Interrupt Priority bit(2) 1 = High priority 0 = Low priority bit 4 TX2IP: EUSART2 Transmit Interrupt Priority bit(2) x = Bit is unknown 1 = High priority 0 = Low priority bit 3 TMR4IE: TMR4 to PR4 Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 CCP5IP: CCP5 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 CCP4IP: CCP4 Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP3IP: ECCP3 Interrupt Priority bit 1 = High priority 0 = Low priority Note 1: 2: Implemented in 100-pin devices only. Implemented in 80-pin and 100-pin devices only. DS39762F-page 142 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 10.5 RCON Register The RCON register contains bits used to determine the cause of the last Reset or wake-up from Idle or Sleep modes. RCON also contains the bit that enables interrupt priorities (IPEN). REGISTER 10-13: RCON: RESET CONTROL REGISTER R/W-0 U-0 R/W-1 R/W-1 R-1 R-1 R/W-0 R/W-0 IPEN -- CM RI TO PD POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 Unimplemented: Read as `0' bit 5 CM: Configuration Mismatch Flag bit For details of bit operation, see Register 5-1. bit 4 RI: RESET Instruction Flag bit For details of bit operation, see Register 5-1. bit 3 TO: Watchdog Timer Time-out Flag bit For details of bit operation, see Register 5-1. bit 2 PD: Power-Down Detection Flag bit For details of bit operation, see Register 5-1. bit 1 POR: Power-on Reset Status bit(2) For details of bit operation, see Register 5-1. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register 5-1. 2011 Microchip Technology Inc. x = Bit is unknown DS39762F-page 143 PIC18F97J60 FAMILY 10.6 INTx Pin Interrupts 10.7 TMR0 Interrupt External interrupts on the RB0/INT0/FLT0, RB1/INT1, RB2/INT2 and RB3/INT3 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit, INTxIF, is set. This interrupt can be disabled by clearing the corresponding enable bit, INTxIE. Flag bit, INTxIF, must be cleared in software in the Interrupt Service Routine (ISR) before re-enabling the interrupt. In 8-bit mode (which is the default), an overflow in the TMR0 register (FFh 00h) will set flag bit, TMR0IF. In 16-bit mode, an overflow in the TMR0H:TMR0L register pair (FFFFh 0000h) will set TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE (INTCON<5>). Interrupt priority for Timer0 is determined by the value contained in the interrupt priority bit, TMR0IP (INTCON2<2>). See Section 12.0 "Timer0 Module" for further details on the Timer0 module. All external interrupts (INT0, INT1, INT2 and INT3) can wake-up the processor from the power-managed modes if bit, INTxIE, was set prior to going into the power-managed modes. If the Global Interrupt Enable bit, GIE, is set, the processor will branch to the interrupt vector following wake-up. 10.8 Interrupt priority for INT1, INT2 and INT3 is determined by the value contained in the Interrupt Priority bits, INT1IP (INTCON3<6>), INT2IP (INTCON3<7>) and INT3IP (INTCON2<1>). There is no priority bit associated with INT0. It is always a high-priority interrupt source. EXAMPLE 10-1: MOVWF MOVFF MOVFF ; ; USER ; MOVFF MOVF MOVFF PORTB Interrupt-on-Change An input change on PORTB<7:4> sets flag bit, RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit, RBIE (INTCON<3>). Interrupt priority for PORTB interrupt-on-change is determined by the value contained in the interrupt priority bit, RBIP (INTCON2<0>). 10.9 Context Saving During Interrupts During interrupts, the return PC address is saved on the stack. Additionally, the WREG, STATUS and BSR registers are saved on the Fast Return Stack (FSR). If a fast return from interrupt is not used (see Section 6.3 "Data Memory Organization"), the user may need to save the WREG, STATUS and BSR registers on entry to the Interrupt Service Routine. Depending on the user's application, other registers may also need to be saved. Example 10-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. SAVING STATUS, WREG AND BSR REGISTERS IN RAM W_TEMP STATUS, STATUS_TEMP BSR, BSR_TEMP ; W_TEMP is in virtual bank ; STATUS_TEMP located anywhere ; BSR_TMEP located anywhere ISR CODE BSR_TEMP, BSR W_TEMP, W STATUS_TEMP, STATUS DS39762F-page 144 ; Restore BSR ; Restore WREG ; Restore STATUS 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 11.0 I/O PORTS 11.1 I/O Port Pin Capabilities Depending on the device selected and features enabled, there are up to nine ports available. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. When developing an application, the capabilities of the port pins must be considered. Outputs on some pins have higher output drive strength than others. Similarly, some pins can tolerate higher than VDD input levels. Each port has three registers for its operation. These registers are: The output pin drive strengths vary for groups of pins intended to meet the needs for a variety of applications. PORTB and PORTC are designed to drive higher loads, such as LEDs. The external memory interface ports (PORTD, PORTE and PORTJ) are designed to drive medium loads. All other ports are designed for small loads, typically indication only. Table 11-1 summarizes the output capabilities. Refer to Section 28.0 "Electrical Characteristics" for more details. * TRIS register (Data Direction register) * PORT register (reads the levels on the pins of the device) * LAT register (Output Latch register) The Output Latch (LAT register) is useful for read-modify-write operations on the value that the I/O pins are driving. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure 11-1. FIGURE 11-1: GENERIC I/O PORT OPERATION 11.1.1 PIN OUTPUT DRIVE TABLE 11-1: Port OUTPUT DRIVE LEVELS Drive PORTA(1) Description Minimum Intended for indication. (2) PORTF PORTG(2) PORTH(3) RD LAT Data Bus WR LAT or PORT PORTD(2) Sufficient drive levels for external memory interfacing, as well as indication. High Suitable for direct LED drive levels. PORTE D Q PORTJ(3) I/O Pin CK D PORTB PORTC Data Latch WR TRIS Medium Note 1: Q 2: CK TRIS Latch Input Buffer 3: The exceptions are RA<1:0>, which are capable of directly driving LEDs. Partially implemented on 64-pin and 80-pin devices; fully implemented on 100-pin devices. Unimplemented on 64-pin devices. RD TRIS Q D ENEN RD PORT 2011 Microchip Technology Inc. DS39762F-page 145 PIC18F97J60 FAMILY 11.1.2 INPUT PINS AND VOLTAGE CONSIDERATIONS The voltage tolerance of pins used as device inputs is dependent on the pin's input function. Pins that are used as digital only inputs are able to handle DC voltages up to 5.5V, a level typical for digital logic circuits. In contrast, pins that also have analog input functions of any kind can only tolerate voltages up to VDD. Voltage excursions beyond VDD on these pins are always to be avoided. Table 11-2 summarizes the input capabilities. Refer to Section 28.0 "Electrical Characteristics" for more details. TABLE 11-2: INPUT VOLTAGE LEVELS Port or Pin Tolerated Input PORTA<5,3:0> VDD Only VDD input levels tolerated. 5.5V Tolerates input levels above VDD, useful for most standard logic. PORTF<6:1>(1) Description PORTH<7:4>(2) PORTA<4> PORTB<7:0> PORTC<7:0> PORTD<7:0>(1) PORTE<7:0> PORTF<7> PORTG<7:0>(1) The RA4 pin is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. The other PORTA pins are multiplexed with the analog VREF+ and VREF- inputs. The operation of pins, RA<5:0>, as A/D Converter inputs is selected by clearing or setting the PCFG<3:0> control bits in the ADCON1 register. Note: RA5 and RA<3:0> are configured as analog inputs on any Reset and are read as `0'. RA4 is configured as a digital input. The RA4/T0CKI pin is a Schmitt Trigger input. All other PORTA pins have TTL input levels and full CMOS output drivers. The TRISA register controls the direction of the PORTA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. The RA0 and RA1 pins can also be configured as the outputs for the two Ethernet LED indicators. When configured, these two pins are the only pins on PORTA that are capable of high output drive levels. Although the port is only six bits wide, PORTA<7> is implemented as RJPU, the weak pull-up control bit for PORTJ. In a similar fashion, the LATA<7:6> bits are implemented, not as latch bits, but the pull-up control bits, RDPU and REPU, for PORTD and PORTE. Setting these bits enables the pull-ups for the corresponding port. Because their port pins are not used, the TRISA<7:6> bits are not implemented. PORTH<3:0>(2) PORTJ<7:0>(2) Note 1: 2: 11.2 Partially implemented on 64-pin and 80-pin devices; fully implemented on 100-pin devices. Unavailable in 64-pin devices. PORTA, TRISA and LATA Registers PORTA is a 6-bit wide, bidirectional port; it is fully implemented on all devices. The corresponding Data Direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). EXAMPLE 11-1: CLRF CLRF MOVLW MOVWF MOVWF MOVWF MOVLW MOVWF PORTA ; ; ; LATA ; ; ; 07h ; ADCON1 ; 07h ; CMCON ; 0CFh ; ; ; TRISA ; ; INITIALIZING PORTA Initialize PORTA by clearing output data latches Alternate method to clear output data latches Configure A/D for digital inputs Configure comparators for digital input Value used to initialize data direction Set RA<3:0> as inputs RA<5:4> as outputs Reading the PORTA register reads the status of the pins, whereas writing to it, will write to the port latch. The Output Latch register (LATA) is also memory mapped. Read-modify-write operations on the LATA register read and write the latched output value for PORTA. DS39762F-page 146 2011 Microchip Technology Inc. PIC18F97J60 FAMILY TABLE 11-3: PORTA FUNCTIONS Pin Name Function RA0/LEDA/AN0 RA0 RA1/LEDB/AN1 RA2/AN2/VREF- RA3/AN3/VREF+ RA4/T0CKI RA5/AN4 TRIS Setting I/O 0 O DIG LATA<0> data output; not affected by analog input. I TTL PORTA<0> data input; disabled when analog input is enabled. LEDA 0 O DIG Ethernet LEDA output; takes priority over digital data. AN0 1 I ANA A/D Input Channel 0. Default input configuration on POR; does not affect digital output. RA1 0 O DIG LATA<1> data output; not affected by analog input. 1 I TTL PORTA<1> data input; disabled when analog input is enabled. LEDB 0 O DIG Ethernet LEDB output; takes priority over digital data. AN1 1 I ANA A/D Input Channel 1. Default input configuration on POR; does not affect digital output. RA2 0 O DIG LATA<2> data output; not affected by analog input. Disabled when CVREF output is enabled. 1 I TTL PORTA<2> data input. Disabled when analog functions are enabled; disabled when CVREF output is enabled. AN2 1 I ANA A/D Input Channel 2 and Comparator C2+ input. Default input configuration on POR; not affected by analog output. VREF- 1 I ANA A/D and comparator low reference voltage input. RA3 0 O DIG LATA<3> data output; not affected by analog input. 1 I TTL PORTA<3> data input; disabled when analog input is enabled. AN3 1 I ANA A/D Input Channel 3. Default input configuration on POR. VREF+ 1 I ANA A/D high reference voltage input. RA4 0 O DIG LATA<4> data output. 1 I ST PORTA<4> data input; default configuration on POR. Timer0 clock input. T0CKI x I ST RA5 0 O DIG LATA<5> data output; not affected by analog input. 1 I TTL PORTA<5> data input; disabled when analog input is enabled. 1 I ANA A/D Input Channel 4. Default configuration on POR. O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don't care (TRIS bit does not affect port direction or is overridden for this option). TABLE 11-4: Name Description 1 AN4 Legend: I/O Type SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: RJPU(1) -- RA5 RA4 RA3 RA2 RA1 RA0 72 LATA RDPU REPU LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 72 TRISA -- -- TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 71 ADCON1 -- -- VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 70 PORTA Legend: -- = unimplemented, read as `0'. Shaded cells are not used by PORTA. Note 1: Implemented in 80-pin and 100-pin devices only. 2011 Microchip Technology Inc. DS39762F-page 147 PIC18F97J60 FAMILY 11.3 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port; it is fully implemented on all devices. The corresponding Data Direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). All pins on PORTB are digital only and tolerate voltages up to 5.5V. The Output Latch register (LATB) is also memory mapped. Read-modify-write operations on the LATB register read and write the latched output value for PORTB. EXAMPLE 11-2: CLRF PORTB CLRF LATB MOVLW 0CFh MOVWF TRISB INITIALIZING PORTB ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTB by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RB<3:0> as inputs RB<5:4> as outputs RB<7:6> as inputs Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all of the pull-ups. This is performed by clearing bit, RBPU (INTCON2<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on all Resets. DS39762F-page 148 Four of the PORTB pins (RB<7:4>) have an interrupt-on-change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB<7:4> pin configured as an output is excluded from the interrupt-on-change comparison). The input pins (of RB<7:4>) are compared with the old value latched on the last read of PORTB. The "mismatch" outputs of RB<7:4> are ORed together to generate the RB Port Change Interrupt Flag bit, RBIF (INTCON<0>). This interrupt can wake the device from power-managed modes. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) b) Any read or write of PORTB (except with the MOVFF (ANY), PORTB instruction). This will end the mismatch condition. Clear flag bit, RBIF. A mismatch condition will continue to set flag bit, RBIF. Reading PORTB will end the mismatch condition and allow flag bit, RBIF, to be cleared. The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. For 100-pin devices operating in Extended Microcontroller mode, RB3 can be configured as the alternate peripheral pin for the ECCP2 module and Enhanced PWM Output 2A by clearing the CCP2MX Configuration bit. If the devices are in Microcontroller mode, the alternate assignment for ECCP2 is RE7. As with other ECCP2 configurations, the user must ensure that the TRISB<3> bit is set appropriately for the intended operation. 2011 Microchip Technology Inc. PIC18F97J60 FAMILY TABLE 11-5: PORTB FUNCTIONS Pin Name Function TRIS Setting I/O I/O Type RB0/INT0/FLT0 RB0 0 O DIG LATB<0> data output. 1 I TTL PORTB<0> data input; weak pull-up when RBPU bit is cleared. 1 I ST External Interrupt 0 input. INT0 RB1/INT1 RB2/INT2 RB3/INT3/ ECCP2/P2A RB4/KBI0 RB5/KBI1 RB6/KBI2/PGC RB7/KBI3/PGD Legend: Note 1: 2: Description FLT0 1 I ST Enhanced PWM Fault input (ECCP1 module); enabled in software. RB1 0 O DIG LATB<1> data output. 1 I TTL PORTB<1> data input; weak pull-up when RBPU bit is cleared. INT1 1 I ST External Interrupt 1 input. RB2 0 O DIG LATB<2> data output. 1 I TTL PORTB<2> data input; weak pull-up when RBPU bit is cleared. INT2 1 I ST External Interrupt 2 input. RB3 0 O DIG LATB<3> data output. 1 I TTL PORTB<3> data input; weak pull-up when RBPU bit is cleared. INT3 1 I ST External Interrupt 3 input. ECCP2(1) 0 O DIG ECCP2 compare output and PWM output; takes priority over port data. 1 I ST ECCP2 capture input. P2A(1) 0 O DIG ECCP2 Enhanced PWM output, Channel A. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. RB4 0 O DIG LATB<4> data output. 1 I TTL PORTB<4> data input; weak pull-up when RBPU bit is cleared. KBI0 1 I TTL Interrupt-on-pin change. RB5 0 O DIG LATB<5> data output. PORTB<5> data input; weak pull-up when RBPU bit is cleared. 1 I TTL KBI1 1 I TTL Interrupt-on-pin change. RB6 0 O DIG LATB<6> data output. 1 I TTL PORTB<6> data input; weak pull-up when RBPU bit is cleared. KBI2 1 I TTL Interrupt-on-pin change. PGC x I ST Serial execution (ICSPTM) clock input for ICSP and ICD operation.(2) RB7 0 O DIG LATB<7> data output. 1 I TTL PORTB<7> data input; weak pull-up when RBPU bit is cleared. KBI3 1 I TTL Interrupt-on-pin change. PGD x O DIG Serial execution data output for ICSP and ICD operation.(2) x I ST Serial execution data input for ICSP and ICD operation.(2) O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don't care (TRIS bit does not affect port direction or is overridden for this option). Alternate assignment for ECCP2/P2A when the CCP2MX Configuration bit is cleared (100-pin devices in Extended Microcontroller mode). Default assignment is RC1. All other pin functions are disabled when ICSP or ICD is enabled. 2011 Microchip Technology Inc. DS39762F-page 149 PIC18F97J60 FAMILY TABLE 11-6: Name PORTB SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 72 LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 72 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 71 TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 69 INT2IF INT1IF 69 INTCON GIE/GIEH PEIE/GIEL INTCON2 RBPU INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF Legend: Shaded cells are not used by PORTB. DS39762F-page 150 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 11.4 PORTC, TRISC and LATC Registers PORTC is an 8-bit wide, bidirectional port; it is fully implemented on all devices. The corresponding Data Direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). Only PORTC pins, RC2 through RC7, are digital only pins and can tolerate input voltages up to 5.5V. The Output Latch register (LATC) is also memory mapped. Read-modify-write operations on the LATC register read and write the latched output value for PORTC. PORTC is multiplexed with several peripheral functions (Table 11-7). The pins have Schmitt Trigger input buffers. RC1 is normally configured by Configuration bit, CCP2MX, as the default peripheral pin for the ECCP2 module and Enhanced PWM output, P2A (default state, CCP2MX = 1). Note: These pins are configured as digital inputs on any device Reset. The contents of the TRISC register are affected by peripheral overrides. Reading TRISC always returns the current contents, even though a peripheral device may be overriding one or more of the pins. EXAMPLE 11-3: CLRF PORTC CLRF LATC MOVLW 0CFh MOVWF TRISC INITIALIZING PORTC ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTC by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RC<3:0> as inputs RC<5:4> as outputs RC<7:6> as inputs When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. 2011 Microchip Technology Inc. DS39762F-page 151 PIC18F97J60 FAMILY TABLE 11-7: Pin Name RC0/T1OSO/ T13CKI RC1/T1OSI/ ECCP2/P2A PORTC FUNCTIONS Function TRIS Setting I/O I/O Type RC0 0 O DIG 1 I ST T1OSO x O ANA T13CKI 1 I ST Timer1/Timer3 counter input. RC1 0 O DIG LATC<1> data output. 1 I ST T1OSI x I ANA Timer1 oscillator input; enabled when Timer1 oscillator is enabled. Disables digital I/O. ECCP2(1) 0 O DIG ECCP2 compare output and PWM output; takes priority over port data. 1 I ST ECCP2 capture input. 0 O DIG ECCP2 Enhanced PWM output, Channel A. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. 0 O DIG LATC<2> data output. P2A RC2/ECCP1/ P1A RC3/SCK1/ SCL1 (1) RC2 I ST PORTC<2> data input. O DIG ECCP1 compare output and PWM output; takes priority over port data. 1 I ST ECCP1 capture input. P1A 0 O DIG ECCP1 Enhanced PWM output, Channel A. May be configured for tri-state during Enhanced PWM shutdown events. Takes priority over port data. RC3 0 O DIG LATC<3> data output. 1 I ST PORTC<3> data input. 0 O DIG SPI clock output (MSSP1 module); takes priority over port data. 1 I ST SPI clock input (MSSP1 module). 0 O DIG I2CTM clock output (MSSP1 module); takes priority over port data. 1 I ST I2C clock input (MSSP1 module); input type depends on module setting. 0 O DIG LATC<4> data output. 1 I ST PORTC<4> data input. Legend: Note 1: SDI1 1 I ST SPI data input (MSSP1 module). SDA1 1 O DIG I2C data output (MSSP1 module); takes priority over port data. 1 I ST I2C data input (MSSP1 module); input type depends on module setting. 0 O DIG LATC<5> data output. 1 I ST PORTC<5> data input. SDO1 0 O DIG SPI data output (MSSP1 module); takes priority over port data. RC6 0 O DIG LATC<6> data output. 1 I ST PORTC<6> data input. TX1 1 O DIG Synchronous serial data output (EUSART1 module); takes priority over port data. CK1 1 O DIG Synchronous serial data input (EUSART1 module). User must configure as an input. RC5 RC7/RX1/DT1 PORTC<1> data input. 0 RC4 RC6/TX1/CK1 PORTC<0> data input. Timer1 oscillator output; enabled when Timer1 oscillator is enabled. Disables digital I/O. 1 SCL1 RC5/SDO1 LATC<0> data output. ECCP1 SCK1 RC4/SDI1/ SDA1 Description 1 I ST Synchronous serial clock input (EUSART1 module). RC7 0 O DIG LATC<7> data output. 1 I ST PORTC<7> data input. RX1 1 I ST Asynchronous serial receive data input (EUSART1 module). DT1 1 O DIG Synchronous serial data output (EUSART1 module); takes priority over port data. 1 I ST Synchronous serial data input (EUSART1 module). User must configure as an input. O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, x = Don't care (TRIS bit does not affect port direction or is overridden for this option). Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set. DS39762F-page 152 2011 Microchip Technology Inc. PIC18F97J60 FAMILY TABLE 11-8: Name PORTC SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 72 LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 72 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 71 2011 Microchip Technology Inc. DS39762F-page 153 PIC18F97J60 FAMILY 11.5 PORTD, TRISD and LATD Registers PORTD is implemented as a bidirectional port in two ways: * 64-pin and 80-pin devices: 3 bits (RD<2:0>) * 100-pin devices: 8 bits (RD<7:0>) The corresponding Data Direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i.e., put the contents of the output latch on the selected pin). All pins on PORTD are digital only and tolerate voltages up to 5.5V. The Output Latch register (LATD) is also memory mapped. Read-modify-write operations on the LATD register read and write the latched output value for PORTD. All pins on PORTD are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. Note: These pins are configured as digital inputs on any device Reset. On 100-pin devices, PORTD is multiplexed with the system bus as part of the external memory interface. I/O port and other functions are only available when the interface is disabled by setting the EBDIS bit (MEMCON<7>). When the interface is enabled, PORTD is the low-order byte of the multiplexed address/data bus (AD<7:0>). The TRISD bits are also overridden. DS39762F-page 154 Each of the PORTD pins has a weak internal pull-up. A single control bit can turn on all of the pull-ups. This is performed by setting the RDPU bit (LATA<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on all device Resets. On 100-pin devices, PORTD can also be configured to function as an 8-bit wide, parallel microprocessor port by setting the PSPMODE control bit (PSPCON<4>). In this mode, parallel port data takes priority over other digital I/O (but not the external memory interface). When the parallel port is active, the input buffers are TTL. For more information, refer to Section 11.11 "Parallel Slave Port (PSP)". EXAMPLE 11-4: CLRF PORTD CLRF LATD MOVLW 0CFh MOVWF TRISD INITIALIZING PORTD ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTD by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RD<3:0> as inputs RD<5:4> as outputs RD<7:6> as inputs 2011 Microchip Technology Inc. PIC18F97J60 FAMILY TABLE 11-9: PORTD FUNCTIONS Pin Name Function TRIS Setting I/O I/O Type RD0/AD0/PSP0 (RD0/P1B) RD0 0 O DIG LATD<0> data output. 1 I ST PORTD<0> data input; weak pull-up when RDPU bit is set. x O DIG External memory interface, Address/Data Bit 0 output.(2) x I TTL External memory interface, Data Bit 0 input.(2) x O DIG PSP read output data (LATD<0>); takes priority over port data. x I TTL PSP write data input. P1B(3) 0 O DIG ECCP1 Enhanced PWM output, Channel B; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RD1 0 O DIG LATD<1> data output. 1 I ST PORTD<1> data input; weak pull-up when RDPU bit is set. x O DIG External memory interface, Address/Data Bit 1 output.(2) x I TTL External memory interface, Data Bit 1 input.(2) x O DIG PSP read output data (LATD<1>); takes priority over port data. x I TTL PSP write data input. 0 O DIG ECCP3 compare and PWM output; takes priority over port data. AD0(1) PSP0(1) RD1/AD1/PSP1 (RD1/ECCP3/ P3A) AD1(1) PSP1 (1) ECCP3(3) RD2/AD2/PSP2 (RD2/CCP4/ P3D) 1 I ST ECCP3 capture input. P3A(3) 0 O DIG ECCP3 Enhanced PWM output, Channel A; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RD2 0 O DIG LATD<2> data output. 1 I ST PORTD<2> data input; weak pull-up when RDPU bit is set. x O DIG External memory interface, Address/Data Bit 2 output.(2) x I TTL External memory interface, Data Bit 2 input.(2) x O DIG PSP read output data (LATD<2>); takes priority over port data. x I TTL PSP write data input. 0 O DIG CCP4 compare output and PWM output; takes priority over port data. 1 I ST CCP4 capture input. P3D(3) 0 O DIG ECCP3 Enhanced PWM output, Channel D; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RD3(1) 0 O DIG LATD<3> data output. AD2(1) PSP2(1) CCP4(3) RD3/AD3/ PSP3(1) AD3(1) PSP3(1) RD4/AD4/ PSP4/SDO2(1) RD4(1) AD4(1) PSP4 (1) SDO2(1) Legend: Note 1: 2: 3: Description 1 I ST PORTD<3> data input; weak pull-up when RDPU bit is set. x O DIG External memory interface, Address/Data Bit 3 output.(2) x I TTL External memory interface, Data Bit 3 input.(2) x O DIG PSP read output data (LATD<3>); takes priority over port data. x I TTL PSP write data input. 0 O DIG LATD<4> data output. 1 I ST PORTD<4> data input; weak pull-up when RDPU bit is set. x O DIG External memory interface, Address/Data Bit 4 output.(2) x I TTL External memory interface, Data Bit 4 input.(2) x O DIG PSP read output data (LATD<4>); takes priority over port data. x I TTL PSP write data input. 0 O DIG SPI data output (MSSP2 module); takes priority over port data. O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don't care (TRIS bit does not affect port direction or is overridden for this option). These features or port pins are implemented only on 100-pin devices. External memory interface I/O takes priority over all other digital and PSP I/O. These features are implemented on this pin only on 64-pin devices; for all other devices, they are multiplexed with RE6/RH7 (P1B), RG0 (ECCP3/P3A) or RG3 (CCP4/P3D). 2011 Microchip Technology Inc. DS39762F-page 155 PIC18F97J60 FAMILY TABLE 11-9: Pin Name RD5/AD5/ PSP5/SDI2/ SDA2(1) PORTD FUNCTIONS (CONTINUED) Function TRIS Setting I/O I/O Type RD5(1) 0 O DIG LATD<5> data output. AD5(1) PSP5(1) RD6/AD6/ PSP6/SCK2/ SCL2(1) ST PORTD<5> data input; weak pull-up when RDPU bit is set. O DIG External memory interface, Address/Data Bit 5 output.(2) x I TTL External memory interface, Data Bit 5 input.(2) x O DIG PSP read output data (LATD<5>); takes priority over port data. I TTL PSP write data input. 1 I ST SPI data input (MSSP2 module). SDA2(1) 1 O DIG I2CTM data output (MSSP2 module); takes priority over port data. 1 I ST I2C data input (MSSP2 module); input type depends on module setting. 0 O DIG LATD<6> data output. 1 I ST PORTD<6> data input; weak pull-up when RDPU bit is set. x O DIG-3 x I TTL x O DIG PSP read output data (LATD<6>); takes priority over port data. x I TTL PSP write data input. 0 O DIG SPI clock output (MSSP2 module); takes priority over port data. 1 I ST SPI clock input (MSSP2 module). 0 O DIG I2C clock output (MSSP2 module); takes priority over port data. 1 I ST I2C clock input (MSSP2 module); input type depends on module setting. 0 O DIG LATD<7> data output. 1 I ST PORTD<7> data input; weak pull-up when RDPU bit is set. x O DIG External memory interface, Address/Data Bit 7 output.(2) x I TTL External memory interface, Data Bit 7 input.(2) x O DIG PSP read output data (LATD<7>); takes priority over port data. x I TTL PSP write data input. x I TTL Slave select input for MSSP2 module. RD6(1) AD6(1) (1) SCL2(1) RD7(1) AD7(1) PSP7 (1) SS2(1) Note 1: 2: 3: I x x SCK2(1) Legend: 1 SDI2(1) PSP6 RD7/AD7/ PSP7/SS2(1) Description External memory interface, Address/Data Bit 6 output.(2) External memory interface, Data Bit 6 input.(2) O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don't care (TRIS bit does not affect port direction or is overridden for this option). These features or port pins are implemented only on 100-pin devices. External memory interface I/O takes priority over all other digital and PSP I/O. These features are implemented on this pin only on 64-pin devices; for all other devices, they are multiplexed with RE6/RH7 (P1B), RG0 (ECCP3/P3A) or RG3 (CCP4/P3D). TABLE 11-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Name PORTD Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: RD7(1) RD6(1) RD5(1) RD4(1) RD3(1) RD2 RD1 RD0 72 LATD LATD7(1) TRISD TRISD7(1) TRISD6(1) TRISD5(1) TRISD4(1) TRISD3(1) LATA RDPU (1) LATD6 REPU (1) LATD5 LATA5 (1) LATD4 LATA4 (1) LATD3 LATA3 LATD2 LATD1 LATD0 72 TRISD2 TRISD1 TRISD0 71 LATA2 LATA1 LATA0 72 Legend: Shaded cells are not used by PORTD. Note 1: Unimplemented on 64-pin and 80-pin devices; read as `0'. DS39762F-page 156 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 11.6 PORTE, TRISE and LATE Registers PORTE is implemented as a bidirectional port in two different ways: * 64-pin devices: 6 bits wide (RE<5:0>) * 80-pin and 100-pin devices: 8 bits wide (RE<7:0>) The corresponding Data Direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i.e., put the contents of the output latch on the selected pin). All pins on PORTE are digital only and tolerate voltages up to 5.5V. The Output Latch register (LATE) is also memory mapped. Read-modify-write operations on the LATE register read and write the latched output value for PORTE. All pins on PORTE are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. Note: These pins are configured as digital inputs on any device Reset. On 100-pin devices, PORTE is multiplexed with the system bus as part of the external memory interface. I/O port and other functions are only available when the interface is disabled by setting the EBDIS bit (MEMCON<7>). When the interface is enabled, PORTE is the high-order byte of the multiplexed address/data bus (AD<15:8>). The TRISE bits are also overridden. Each of the PORTE pins has a weak internal pull-up. A single control bit can turn on all of the pull-ups. This is performed by setting bit, REPU (LATA<6>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on all device Resets. 2011 Microchip Technology Inc. PORTE is also multiplexed with Enhanced PWM Outputs B and C for ECCP1 and ECCP3 and Outputs B, C and D for ECCP2. For 80-pin and 100-pin devices, their default assignments are on PORTE<6:0>. For 64-pin devices, their default assignments are on PORTE<5:0> and PORTD<0>. On 80-pin and 100-pin devices, the multiplexing for the outputs of ECCP1 and ECCP3 is controlled by the ECCPMX Configuration bit. Clearing this bit reassigns the P1B/P1C and P3B/P3C outputs to PORTH. For 80-pin and 100-pin devices operating in Microcontroller mode, pin, RE7, can be configured as the alternate peripheral pin for the ECCP2 module and Enhanced PWM Output 2A. This is done by clearing the CCP2MX Configuration bit. When the Parallel Slave Port is active on PORTD, three of the PORTE pins (RE0, RE1 and RE2) are configured as digital control inputs for the port. The control functions are summarized in Table 11-11. The reconfiguration occurs automatically when the PSPMODE control bit (PSPCON<4>) is set. Users must still make certain the corresponding TRISE bits are set to configure these pins as digital inputs. EXAMPLE 11-5: CLRF PORTE CLRF LATE MOVLW 03h MOVWF TRISE INITIALIZING PORTE ; ; ; ; ; ; ; ; ; ; ; Initialize PORTE by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RE<1:0> as inputs RE<7:2> as outputs DS39762F-page 157 PIC18F97J60 FAMILY TABLE 11-11: Pin Name PORTE FUNCTIONS Function TRIS Setting I/O I/O Type RE0 0 O DIG LATE<0> data output. RE0/AD8/RD/ P2D AD8(1) RE1/AD9/WR/ P2C ST PORTE<0> data input; weak pull-up when REPU bit is set. O DIG External memory interface, Address/Data Bit 8 output.(2) x I TTL External memory interface, Data bit 8 input.(2) 1 I TTL Parallel Slave Port read enable control input. P2D 0 O DIG ECCP2 Enhanced PWM output, Channel D; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RE1 0 O DIG LATE<1> data output. 1 I ST PORTE<1> data input; weak pull-up when REPU bit is set. x O DIG External memory interface, Address/Data Bit 9 output.(2) x I TTL External memory interface, Data Bit 9 input.(2) 1 I TTL Parallel Slave Port write enable control input. P2C 0 O DIG ECCP2 Enhanced PWM output, Channel C; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RE2 0 O DIG LATE<2> data output. 1 I ST PORTE<2> data input; weak pull-up when REPU bit is set. AD10(1) x O DIG External memory interface, Address/Data Bit 10 output.(2) x I TTL External memory interface, Data Bit 10 input.(2) RE3/AD11/ P3C CS(6) 1 I TTL Parallel Slave Port chip select control input. P2B 0 O DIG ECCP2 Enhanced PWM output, Channel B; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RE3 0 O DIG LATE<3> data output. 1 I ST PORTE<3> data input; weak pull-up when REPU bit is set. x O DIG External memory interface, Address/Data Bit 11 output.(2) AD11(1) x I TTL External memory interface, Data Bit 11 input.(2) P3C(3) 0 O DIG ECCP3 Enhanced PWM output, Channel C; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RE4 0 O DIG LATE<4> data output. 1 I ST PORTE<4> data input; weak pull-up when REPU bit is set. AD12(1) x O DIG External memory interface, Address/Data Bit 12 output.(2) x I TTL External memory interface, Data Bit 12 input.(2) 0 O DIG ECCP3 Enhanced PWM output, channel B; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RE4/AD12/ P3B P3B(3) 6: I x WR(6) RE2/AD10/CS/ P2B Note 1: 2: 3: 4: 5: 1 RD(6) AD9(1) Legend: Description O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don't care (TRIS bit does not affect port direction or is overridden for this option). EMB functions are implemented on 100-pin devices only. External memory interface I/O takes priority over all other digital and PSP I/O. Default assignments for P1B/P1C and P3B/P3C when ECCPMX Configuration bit is set (80-pin and 100-pin devices). Unimplemented on 64-pin devices. Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (80-pin and 100-pin devices in Microcontroller mode). Unimplemented on 64-pin and 80-pin devices. DS39762F-page 158 2011 Microchip Technology Inc. PIC18F97J60 FAMILY TABLE 11-11: Pin Name RE5/AD13/ P1C PORTE FUNCTIONS (CONTINUED) Function TRIS Setting I/O I/O Type RE5 0 O DIG LATE<5> data output. 1 I ST PORTE<5> data input; weak pull-up when REPU bit is set. x O DIG External memory interface, Address/Data Bit 13 output.(2) x I TTL External memory interface, Data Bit 13 input.(2) P1C(3) 0 O DIG ECCP1 Enhanced PWM output, Channel C; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RE6 0 O DIG LATE<6> data output. 1 I ST PORTE<6> data input; weak pull-up when REPU bit is set. x O DIG External memory interface, Address/Data Bit 14 output.(2) x I TTL External memory interface, Data Bit 14 input.(2) 0 O DIG ECCP1 Enhanced PWM output, Channel B; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. 0 O DIG LATE<7> data output. 1 I ST PORTE<7> data input; weak pull-up when REPU bit is set. x O DIG External memory interface, Address/Data Bit 15 output.(2) x I TTL External memory interface, Data Bit 15 input.(2) 0 O DIG ECCP2 compare output and PWM output; takes priority over port data. AD13(1) RE6/AD14/ P1B(4) AD14(1) (3) P1B RE7/AD15/ ECCP2/P2A(4) RE7 AD15(1) ECCP2 (5) P2A(5) Legend: Note 1: 2: 3: 4: 5: 6: Description 1 I ST ECCP2 capture input. 0 O DIG ECCP2 Enhanced PWM output, Channel A; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don't care (TRIS bit does not affect port direction or is overridden for this option). EMB functions are implemented on 100-pin devices only. External memory interface I/O takes priority over all other digital and PSP I/O. Default assignments for P1B/P1C and P3B/P3C when ECCPMX Configuration bit is set (80-pin and 100-pin devices). Unimplemented on 64-pin devices. Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (80-pin and 100-pin devices in Microcontroller mode). Unimplemented on 64-pin and 80-pin devices. TABLE 11-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Name PORTE LATE TRISE LATA Bit 7 Bit 6 RE7(1) RE6(1) RE5 RE4 RE3 RE2 LATE7(1) LATE6(1) LATE5 LATE4 LATE3 LATE2 TRISE6(1) TRISE5 TRISE4 TRISE3 TRISE2 REPU LATA5 LATA4 LATA3 LATA2 TRISE7 (1) RDPU Bit 5 Bit 4 Bit 3 Bit 2 Bit 0 Reset Values on Page: RE1 RE0 72 LATE1 LATE0 72 TRISE1 TRISE0 71 LATA1 LATA0 72 Bit 1 Legend: -- = unimplemented, read as `0'. Shaded cells are not used by PORTE. Note 1: Unimplemented on 64-pin devices; read as `0'. 2011 Microchip Technology Inc. DS39762F-page 159 PIC18F97J60 FAMILY 11.7 PORTF, LATF and TRISF Registers PORTF is implemented as a bidirectional port in two different ways: Note 1: On device Resets, pins, RF<6:1>, are configured as analog inputs and are read as `0'. 2: To configure PORTF as digital I/O, turn off the comparators and set the ADCON1 value. * 64-pin and 80-pin devices: 7 bits wide (RF<7:1>) * 100-pin devices: 8 bits wide (RF<7:0>) The corresponding Data Direction register is TRISF. Setting a TRISF bit (= 1) will make the corresponding PORTF pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISF bit (= 0) will make the corresponding PORTF pin an output (i.e., put the contents of the output latch on the selected pin). Only Pin 7 of PORTF has no analog input; it is the only pin that can tolerate voltages up to 5.5V. The Output Latch register (LATF) is also memory mapped. Read-modify-write operations on the LATF register read and write the latched output value for PORTF. All pins on PORTF are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. PORTF is multiplexed with several analog peripheral functions, including the A/D Converter and comparator inputs, as well as the comparator outputs. Pins, RF1 through RF6, may be used as comparator inputs or outputs by setting the appropriate bits in the CMCON register. To use RF<6:1> as digital inputs, it is also necessary to turn off the comparators. DS39762F-page 160 EXAMPLE 11-6: CLRF CLRF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF PORTF ; ; ; LATF ; ; ; 07h ; CMCON ; 0Fh ; ADCON1 ; 0CEh ; ; ; TRISF ; ; ; INITIALIZING PORTF Initialize PORTF by clearing output data latches Alternate method to clear output data latches Turn off comparators Set PORTF as digital I/O Value used to initialize data direction Set RF3:RF1 as inputs RF5:RF4 as outputs RF7:RF6 as inputs 2011 Microchip Technology Inc. PIC18F97J60 FAMILY TABLE 11-13: PORTF FUNCTIONS Pin Name Function RF0/AN5(1) RF1/AN6/ C2OUT RF2/AN7/ C1OUT RF3/AN8 RF4/AN9 RF5/AN10/ CVREF RF6/AN11 RF7/SS1 TRIS Setting I/O I/O Type 0 O DIG LATF<0> data output; not affected by analog input. 1 I ST PORTF<0> data input; disabled when analog input is enabled. RF0(1) AN5(1) 1 I ANA A/D Input Channel 5. Default configuration on POR. RF1 0 O DIG LATF<1> data output; not affected by analog input. 1 I ST AN6 1 I ANA A/D Input Channel 6. Default configuration on POR. C2OUT 0 O DIG Comparator 2 output; takes priority over port data. RF2 0 O DIG LATF<2> data output; not affected by analog input. Note 1: PORTF<1> data input; disabled when analog input is enabled. 1 I ST AN7 1 I ANA C1OUT 0 O TTL Comparator 1 output; takes priority over port data. RF3 0 O DIG LATF<3> data output; not affected by analog input. PORTF<2> data input; disabled when analog input is enabled. A/D Input Channel 7. Default configuration on POR. 1 I ST AN8 1 I ANA RF4 0 O DIG LATF<4> data output; not affected by analog input. 1 I ST PORTF<4> data input; disabled when analog input is enabled. AN9 1 I ANA A/D Input Channel 9 and Comparator C2- input. Default input configuration on POR; does not affect digital output. RF5 0 O DIG LATF<5> data output; not affected by analog input. Disabled when CVREF output is enabled. 1 I ST PORTF<5> data input; disabled when analog input is enabled. Disabled when CVREF output is enabled. AN10 1 I ANA A/D Input Channel 10 and Comparator C1+ input. Default input configuration on POR. CVREF x O ANA Comparator voltage reference output. Enabling this feature disables digital I/O. RF6 0 O DIG LATF<6> data output; not affected by analog input. 1 I ST PORTF<6> data input; disabled when analog input is enabled. AN11 1 I ANA A/D Input Channel 11 and Comparator C1- input. Default input configuration on POR; does not affect digital output. RF7 0 O DIG LATF<7> data output. 1 I ST PORTF<7> data input. 1 I TTL Slave select input for MSSP1 module. SS1 Legend: Description PORTF<3> data input; disabled when analog input is enabled. A/D Input Channel 8 and Comparator C2+ input. Default input configuration on POR; not affected by analog output. O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input, x = Don't care (TRIS bit does not affect port direction or is overridden for this option). Implemented on 100-pin devices only. TABLE 11-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF Name PORTF LATF TRISF ADCON1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0(1) 72 LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0(1) 72 TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 -- -- VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 TRISF0 (1) 71 PCFG0 70 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 70 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 70 Legend: -- = unimplemented, read as `0'. Shaded cells are not used by PORTF. Note 1: Implemented on 100-pin devices only. 2011 Microchip Technology Inc. DS39762F-page 161 PIC18F97J60 FAMILY 11.8 PORTG, TRISG and LATG Registers Depending on the particular device, PORTG is implemented as a bidirectional port in one of three ways: * 64-pin devices: 1 bit wide (RG<4>) * 80-pin devices: 5 bits wide (RG<4:0>) * 100-pin devices: 8 bits wide (RG<7:0>) The corresponding Data Direction register is TRISG. Setting a TRISG bit (= 1) will make the corresponding PORTG pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISG bit (= 0) will make the corresponding PORTG pin an output (i.e., put the contents of the output latch on the selected pin). All pins on PORTG are digital only and tolerate voltages up to 5.5V. The Output Latch register (LATG) is also memory mapped. Read-modify-write operations on the LATG register read and write the latched output value for PORTG. PORTG is multiplexed with EUSART2 functions on 80-pin and 100-pin devices (Table 11-15). PORTG pins have Schmitt Trigger input buffers. DS39762F-page 162 When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTG pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. The pin override value is not loaded into the TRIS register. This allows read-modify-write of the TRIS register without concern due to peripheral overrides. EXAMPLE 11-7: CLRF PORTG CLRF LATG MOVLW 04h MOVWF TRISG INITIALIZING PORTG ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTG by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RG1:RG0 as outputs RG2 as input RG4:RG3 as inputs 2011 Microchip Technology Inc. PIC18F97J60 FAMILY TABLE 11-15: PORTG FUNCTIONS Pin Name Function TRIS Setting I/O I/O Type RG0/ECCP3/ P3A(1) RG0(1) 0 O DIG LATG<0> data output. 1 I ST PORTG<0> data input. 0 O DIG ECCP3 compare and PWM output; takes priority over port data. ECCP3(1) RG1/TX2/ CK2(1) RG2/RX2/ DT2(1) 1 I ST ECCP3 capture input. P3A(1) 0 O DIG ECCP3 Enhanced PWM output, Channel A; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RG1(1) 0 O DIG LATG<1> data output. 1 I ST PORTG<1> data input. TX2(1) 1 O DIG Synchronous serial data output (EUSART2 module); takes priority over port data. CK2(1) 1 O DIG Synchronous serial data input (EUSART2 module). User must configure as an input. Synchronous serial clock input (EUSART2 module). RG2(1) RX2(1) DT2(1) RG3/CCP4/ P3D(1) RG6(2) RG7(2) Legend: Note 1: 2: I ST 0 O DIG LATG<2> data output. 1 I ST PORTG<2> data input. 1 I ST Asynchronous serial receive data input (EUSART2 module). 1 O DIG Synchronous serial data output (EUSART2 module); takes priority over port data. I ST Synchronous serial data input (EUSART2 module). User must configure as an input. 0 O DIG LATG<3> data output. 1 I ST PORTG<3> data input. 0 O DIG CCP4 compare output and PWM output; takes priority over port data. 1 I ST CCP4 capture input. P3D(1) 0 O DIG ECCP3 Enhanced PWM output, Channel D; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RG4 0 O DIG LATG<4> data output. 1 I ST PORTG<4> data input. 0 O DIG CCP5 compare output and PWM output; takes priority over port data. RG3(1) CCP5 RG5(2) 1 1 CCP4(1) RG4/CCP5/ P1D Description 1 I ST CCP5 capture input. P1D 0 O DIG ECCP1 Enhanced PWM output, Channel D; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RG5(2) 0 O DIG LATG<0> data output. 1 I ST PORTG<0> data input. 0 O DIG LATG<0> data output. 1 I ST PORTG<0> data input. 0 O DIG LATG<0> data output. 1 I ST PORTG<0> data input. RG6(2) RG7(2) O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, x = Don't care (TRIS bit does not affect port direction or is overridden for this option). Implemented on 80-pin and 100-pin devices only. Implemented on 100-pin devices only. TABLE 11-16: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: RG7(1) RG6(1) RG5(1) RG4 RG3(2) RG2(2) RG1(2) RG0(2) 72 LATG LATG7 LATG6(1) LATG5(1) LATG4 LATG3(2) LATG2(2) LATG1(2) LATG0(2) 72 TRISG TRISG7(1) TRISG6(1) TRISG5(1) TRISG4 TRISG3(2) TRISG2(2) TRISG1(2) TRISG0(2) 71 Name PORTG Note 1: 2: (1) Implemented on 100-pin devices only. Implemented on 80-pin and 100-pin devices only. 2011 Microchip Technology Inc. DS39762F-page 163 PIC18F97J60 FAMILY 11.9 Note: PORTH, LATH and TRISH Registers PORTH is available only on 80-pin and 100-pin devices. PORTH is an 8-bit wide, bidirectional I/O port; it is fully implemented on 80-pin and 100-pin devices. The corresponding Data Direction register is TRISH. Setting a TRISH bit (= 1) will make the corresponding PORTH pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISH bit (= 0) will make the corresponding PORTH pin an output (i.e., put the contents of the output latch on the selected pin). PORTH<3:0> pins are digital only and tolerate voltages up to 5.5V. The Output Latch register (LATH) is also memory mapped. Read-modify-write operations on the LATH register, read and write the latched output value for PORTH. All pins on PORTH are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. DS39762F-page 164 When the external memory interface is enabled, four of the PORTH pins function as the high-order address lines for the interface. The address output from the interface takes priority over other digital I/O. The corresponding TRISH bits are also overridden. PORTH pins, RH4 through RH7, are multiplexed with analog converter inputs. The operation of these pins as analog inputs is selected by clearing or setting the PCFG<3:0> control bits in the ADCON1 register. PORTH can also be configured as the alternate Enhanced PWM Output Channels B and C for the ECCP1 and ECCP3 modules. This is done by clearing the ECCPMX Configuration bit. EXAMPLE 11-8: CLRF PORTH CLRF LATH MOVLW MOVWF MOVLW 0Fh ADCON1 0CFh MOVWF TRISH INITIALIZING PORTH ; ; ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTH by clearing output data latches Alternate method to clear output data latches Configure PORTH as digital I/O Value used to initialize data direction Set RH3:RH0 as inputs RH5:RH4 as outputs RH7:RH6 as inputs 2011 Microchip Technology Inc. PIC18F97J60 FAMILY TABLE 11-17: PORTH FUNCTIONS Pin Name RH0/A16 RH1/A17 RH2/A18 RH3/A19 RH4/AN12/P3C Function TRIS Setting I/O I/O Type RH0 0 O DIG 1 I ST PORTH<0> data input. A16(1) x O DIG External memory interface, Address Line 16. Takes priority over port data. RH1 0 O DIG LATH<1> data output. 1 I ST PORTH<1> data input. x O DIG External memory interface, Address Line 17. Takes priority over port data. RH2 0 O DIG LATH<2> data output. 1 I ST PORTH<2> data input. A18(1) x O DIG External memory interface, Address Line 18. Takes priority over port data. RH3 0 O DIG LATH<3> data output. 1 I ST PORTH<3> data input. A19(1) x O DIG External memory interface, Address Line 19. Takes priority over port data. RH4 0 O DIG LATH<4> data output. 1 I ST PORTH<4> data input. I ANA A/D Input Channel 12. Default input configuration on POR; does not affect digital output. P3C(2) 0 O DIG ECCP3 Enhanced PWM output, Channel C; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RH5 0 O DIG LATH<5> data output. 1 I ST PORTH<5> data input. I ANA A/D Input Channel 13. Default input configuration on POR; does not affect digital output. AN13 RH6/AN14/P1C P3B(2) 0 O DIG ECCP3 Enhanced PWM output, Channel B; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RH6 0 O DIG LATH<6> data output. 1 I ST PORTH<6> data input. I ANA A/D Input Channel 14. Default input configuration on POR; does not affect digital output. AN14 RH7/AN15/P1B P1C(2) 0 O DIG ECCP1 Enhanced PWM output, Channel C; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. RH7 0 O DIG LATH<7> data output. 1 I ST PORTH<7> data input. I ANA A/D Input Channel 15. Default input configuration on POR; does not affect digital output. O DIG ECCP1 Enhanced PWM output, Channel B; takes priority over port and PSP data. May be configured for tri-state during Enhanced PWM shutdown events. AN15 P1B(2) Legend: Note 1: 2: LATH<0> data output. A17(1) AN12 RH5/AN13/P3B Description 0 O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, x = Don't care (TRIS bit does not affect port direction or is overridden for this option). Unimplemented on 80-pin devices. Alternate assignments for P1B/P1C and P3B/P3C when ECCPMX Configuration bit is cleared (80-pin and 100-pin devices only). Default assignments are PORTE<6:3>. TABLE 11-18: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH Name PORTH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0 72 LATH LATH7 LATH6 LATH5 LATH4 LATH3 LATH2 LATH1 LATH0 71 TRISH TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 71 2011 Microchip Technology Inc. DS39762F-page 165 PIC18F97J60 FAMILY 11.10 PORTJ, TRISJ and LATJ Registers Note: PORTJ is available only on 80-pin and 100-pin devices. PORTJ is implemented as a bidirectional port in two different ways: * 80-pin devices: 2 bits wide (RJ<5:4>) * 100-pin devices: 8 bits wide (RJ<7:0>) The corresponding Data Direction register is TRISJ. Setting a TRISJ bit (= 1) will make the corresponding PORTJ pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISJ bit (= 0) will make the corresponding PORTJ pin an output (i.e., put the contents of the output latch on the selected pin). All pins on PORTJ are digital only and tolerate voltages up to 5.5V. The Output Latch register (LATJ) is also memory mapped. Read-modify-write operations on the LATJ register read and write the latched output value for PORTJ. All pins on PORTJ are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. Note: When the external memory interface is enabled, all of the PORTJ pins function as control outputs for the interface. This occurs automatically when the interface is enabled by clearing the EBDIS control bit (MEMCON<7>). The TRISJ bits are also overridden. Each of the PORTJ pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by setting bit, RJPU (PORTA<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on all device Resets. EXAMPLE 11-9: CLRF PORTJ CLRF LATJ MOVLW 0CFh MOVWF TRISJ INITIALIZING PORTJ ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTG by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RJ3:RJ0 as inputs RJ5:RJ4 as output RJ7:RJ6 as inputs These pins are configured as digital inputs on any device Reset. DS39762F-page 166 2011 Microchip Technology Inc. PIC18F97J60 FAMILY TABLE 11-19: PORTJ FUNCTIONS Pin Name RJ0/ALE(1) RJ1/OE(1) RJ2/WRL(1) RJ3/WRH(1) RJ4/BA0 RJ5/CE RJ6/LB(1) RJ7/UB(1) Function TRIS Setting I/O I/O Type RJ0(1) 0 O DIG LATJ<0> data output. 1 I ST PORTJ<0> data input; weak pull-up when RJPU bit is set. ALE(1) x O DIG External memory interface address latch enable control output; takes priority over digital I/O. RJ1(1) 0 O DIG LATJ<1> data output. 1 I ST PORTJ<1> data input; weak pull-up when RJPU bit is set. OE(1) x O DIG External memory interface output enable control output; takes priority over digital I/O. RJ2(1) 0 O DIG LATJ<2> data output. 1 I ST PORTJ<2> data input; weak pull-up when RJPU bit is set. WRL(1) x O DIG External memory bus write low byte control; takes priority over digital I/O. RJ3(1) 0 O DIG LATJ<3> data output. 1 I ST PORTJ<3> data input; weak pull-up when RJPU bit is set. WRH(1) x O DIG External memory interface write high byte control output; takes priority over digital I/O. RJ4 0 O DIG LATJ<4> data output. 1 I ST PORTJ<4> data input; weak pull-up when RJPU bit is set. BA0(2) x O DIG External Memory Interface Byte Address 0 control output; takes priority over digital I/O. RJ5 0 O DIG LATJ<5> data output. 1 I ST PORTJ<5> data input; weak pull-up when RJPU bit is set. CE(2) x O DIG External memory interface chip enable control output; takes priority over digital I/O. RJ6(1) 0 O DIG LATJ<6> data output. 1 I ST PORTJ<6> data input; weak pull-up when RJPU bit is set. LB(1) x O DIG External memory interface lower byte enable control output; takes priority over digital I/O. RJ7(1) 0 O DIG LATJ<7> data output. UB(1) Legend: Note 1: 2: Description 1 I ST PORTJ<7> data input; weak pull-up when RJPU bit is set. x O DIG External memory interface upper byte enable control output; takes priority over digital I/O. O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, x = Don't care (TRIS bit does not affect port direction or is overridden for this option). Implemented on 100-pin devices only. EMB functions are implemented on 100-pin devices only. TABLE 11-20: SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: RJ7(1) RJ6(1) RJ5 RJ4 RJ3(1) RJ2(1) RJ1(1) RJ0(1) 72 LATJ LATJ7(1) LATJ6(1) LATJ5 LATJ4 LATJ3(1) LATJ2(1) LATJ1(1) LATJ0(1) 71 TRISJ TRISJ7(1) TRISJ6(1) TRISJ5 TRISJ4 TRISJ3(1) TRISJ2(1) TRISJ1(1) TRISJ0(1) 71 RA5 RA4 Name PORTJ PORTA RJPU -- RA3 RA2 RA1 RA0 72 Legend: -- = unimplemented, read as `0'. Shaded cells are not used by PORTJ. Note 1: Implemented on 100-pin devices only. 2011 Microchip Technology Inc. DS39762F-page 167 PIC18F97J60 FAMILY 11.11 Parallel Slave Port (PSP) Note: PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT) The Parallel Slave Port is only implemented on 100-pin devices. PORTD can also function as an 8-bit wide, Parallel Slave Port, or microprocessor port, when control bit, PSPMODE (PSPCON<4>), is set. It is asynchronously readable and writable by the external world through the RD control input pin, RE0/AD8/RD/P2D and WR control input pin, RE1/AD9//WR/P2C. Note: FIGURE 11-2: The Parallel Slave Port is available only in Microcontroller mode. The PSP can directly interface to an 8-bit microprocessor data bus. The external microprocessor can read or write the PORTD latch as an 8-bit latch. Setting bit, PSPMODE, enables port pin, RE0/AD8/RD/P2D, to be the RD input, RE1/AD9//WR/P2C to be the WR input and RE2/AD10//CS/P2B to be the CS (Chip Select) input. For this functionality, the corresponding data direction bits of the TRISE register (TRISE<2:0>) must be configured as inputs (set). A write to the PSP occurs when both the CS and WR lines are first detected low and ends when either are detected high. The PSPIF and IBF flag bits are both set when the write ends. A read from the PSP occurs when both the CS and RD lines are first detected low. The data in PORTD is read out and the OBF bit is set. If the user writes new data to PORTD to set OBF, the data is immediately read out; however, the OBF bit is not set. When either the CS or RD lines is detected high, the PORTD pins return to the input state and the PSPIF bit is set. User applications should wait for PSPIF to be set before servicing the PSP. When this happens, the IBF and OBF bits can be polled and the appropriate action taken. Data Bus D WR LATD or PORTD Q RDx Pin CK Data Latch Q RD PORTD TTL D ENEN TRIS Latch RD LATD One bit of PORTD Set Interrupt Flag PSPIF (PIR1<7>) Read TTL RD Chip Select TTL CS Write TTL WR The timing for the control signals in Write and Read modes is shown in Figure 11-3 and Figure 11-4, respectively. DS39762F-page 168 2011 Microchip Technology Inc. PIC18F97J60 FAMILY REGISTER 11-1: PSPCON: PARALLEL SLAVE PORT CONTROL REGISTER R-0 R-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 IBF OBF IBOV PSPMODE -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 IBF: Input Buffer Full Status bit 1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received bit 6 OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read bit 5 IBOV: Input Buffer Overflow Detect bit 1 = A write occurred when a previously input word has not been read (must be cleared in software) 0 = No overflow occurred bit 4 PSPMODE: Parallel Slave Port Mode Select bit 1 = Parallel Slave Port mode 0 = General Purpose I/O mode bit 3-0 Unimplemented: Read as `0' FIGURE 11-3: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF 2011 Microchip Technology Inc. DS39762F-page 169 PIC18F97J60 FAMILY FIGURE 11-4: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 11-21: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Name PORTD Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 72 LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 72 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 71 PORTE RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 72 LATE LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 72 TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 71 IBF OBF IBOV PSPMODE -- -- -- -- 71 TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 PSPCON INTCON GIE/GIEH PEIE/GIEL PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 71 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 71 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 71 Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the Parallel Slave Port. DS39762F-page 170 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 12.0 TIMER0 MODULE The Timer0 module incorporates the following features: * Software selectable operation as a timer or counter in both 8-bit or 16-bit modes * Readable and writable registers * Dedicated, 8-bit, software programmable prescaler * Selectable clock source (internal or external) * Edge select for external clock * Interrupt on overflow REGISTER 12-1: The T0CON register (Register 12-1) controls all aspects of the module's operation, including the prescale selection. It is both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 12-1. Figure 12-2 shows a simplified block diagram of the Timer0 module in 16-bit mode. T0CON: TIMER0 CONTROL REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 TMR0ON: Timer0 On/Off Control bit 1 = Enables Timer0 0 = Stops Timer0 bit 6 T08BIT: Timer0 8-Bit/16-Bit Control bit 1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKO) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Timer0 Prescaler Assignment bit 1 = TImer0 prescaler is NOT assigned; Timer0 clock input bypasses prescaler 0 = Timer0 prescaler is assigned; Timer0 clock input comes from prescaler output bit 2-0 T0PS<2:0>: Timer0 Prescaler Select bits 111 = 1:256 Prescale value 110 = 1:128 Prescale value 101 = 1:64 Prescale value 100 = 1:32 Prescale value 011 = 1:16 Prescale value 010 = 1:8 Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value 2011 Microchip Technology Inc. DS39762F-page 171 PIC18F97J60 FAMILY 12.1 Timer0 Operation Timer0 can operate as either a timer or a counter; the mode is selected with the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on every clock by default unless a different prescaler value is selected (see Section 12.3 "Prescaler"). If the TMR0 register is written to, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register. The Counter mode is selected by setting the T0CS bit (= 1). In this mode, Timer0 increments either on every rising or falling edge of pin, RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit, T0SE (T0CON<4>); clearing this bit selects the rising edge. Restrictions on the external clock input are discussed below. An external clock source can be used to drive Timer0; however, it must meet certain requirements to ensure that the external clock can be synchronized with the FIGURE 12-1: internal phase clock (TOSC). There is a delay between synchronization and the onset of incrementing the timer/counter. 12.2 Timer0 Reads and Writes in 16-Bit Mode TMR0H is not the actual high byte of Timer0 in 16-bit mode. It is actually a buffered version of the real high byte of Timer0 which is not directly readable nor writable (refer to Figure 12-2). TMR0H is updated with the contents of the high byte of Timer0 during a read of TMR0L. This provides the ability to read all 16 bits of Timer0 without having to verify that the read of the high and low byte was valid, due to a rollover between successive reads of the high and low byte. Similarly, a write to the high byte of Timer0 must also take place through the TMR0H Buffer register. The high byte is updated with the contents of TMR0H when a write occurs to TMR0L. This allows all 16 bits of Timer0 to be updated at once. TIMER0 BLOCK DIAGRAM (8-BIT MODE) FOSC/4 0 1 1 Programmable Prescaler T0CKI pin T0SE T0CS 0 Sync with Internal Clocks (2 TCY Delay) 8 3 T0PS<2:0> 8 PSA Note: Set TMR0IF on Overflow TMR0L Internal Data Bus Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. FIGURE 12-2: FOSC/4 TIMER0 BLOCK DIAGRAM (16-BIT MODE) 0 1 1 T0CKI pin T0SE T0CS Programmable Prescaler 0 Sync with Internal Clocks TMR0 High Byte TMR0L 8 Set TMR0IF on Overflow (2 TCY Delay) 3 Read TMR0L T0PS<2:0> Write TMR0L PSA 8 8 TMR0H 8 8 Internal Data Bus Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. DS39762F-page 172 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 12.3 12.3.1 Prescaler An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not directly readable or writable. Its value is set by the PSA and T0PS<2:0> bits (T0CON<3:0>) which determine the prescaler assignment and prescale ratio. Clearing the PSA bit assigns the prescaler to the Timer0 module. When it is assigned, prescale values from 1:2 through 1:256, in power-of-2 increments, are selectable. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF TMR0, MOVWF TMR0, BSF TMR0, etc.) clear the prescaler count. Note: Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler count but will not change the prescaler assignment. TABLE 12-1: Name The prescaler assignment is fully under software control and can be changed "on-the-fly" during program execution. 12.4 Timer0 Interrupt The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h in 8-bit mode, or from FFFFh to 0000h in 16-bit mode. This overflow sets the TMR0IF flag bit. The interrupt can be masked by clearing the TMR0IE bit (INTCON<5>). Before re-enabling the interrupt, the TMR0IF bit must be cleared in software by the Interrupt Service Routine. Since Timer0 is shut down in Sleep mode, the TMR0 interrupt cannot awaken the processor from Sleep. REGISTERS ASSOCIATED WITH TIMER0 Bit 7 Bit 6 Bit 5 TMR0L Timer0 Register Low Byte TMR0H Timer0 Register High Byte INTCON GIE/GIEH PEIE/GIEL TMR0IE INTCON2 SWITCHING PRESCALER ASSIGNMENT RBPU Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: 70 70 INT0IE RBIE INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IF INT0IF RBIF 69 TMR0IP INT3IP RBIP 69 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 70 TRISA -- -- TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 71 Legend: -- = unimplemented, read as `0'. Shaded cells are not used by Timer0. 2011 Microchip Technology Inc. DS39762F-page 173 PIC18F97J60 FAMILY NOTES: DS39762F-page 174 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 13.0 TIMER1 MODULE The Timer1 timer/counter module incorporates these features: * Software selectable operation as a 16-bit timer or counter * Readable and writable 8-bit registers (TMR1H and TMR1L) * Selectable clock source (internal or external) with device clock or Timer1 oscillator internal options * Interrupt on overflow * Reset on ECCP Special Event Trigger * Device clock status flag (T1RUN) REGISTER 13-1: R/W-0 The module incorporates its own low-power oscillator to provide an additional clocking option. The Timer1 oscillator can also be used as a low-power clock source for the microcontroller in power-managed operation. Timer1 can also be used to provide Real-Time Clock (RTC) functionality to applications with only a minimal addition of external components and code overhead. Timer1 is controlled through the T1CON Control register (Register 13-1). It also contains the Timer1 Oscillator Enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit, TMR1ON (T1CON<0>). T1CON: TIMER1 CONTROL REGISTER R-0 RD16 A simplified block diagram of the Timer1 module is shown in Figure 13-1. A block diagram of the module's operation in Read/Write mode is shown in Figure 13-2. T1RUN R/W-0 T1CKPS1 R/W-0 T1CKPS0 R/W-0 T1OSCEN R/W-0 R/W-0 R/W-0 T1SYNC TMR1CS TMR1ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 RD16: 16-Bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer1 in one 16-bit operation 0 = Enables register read/write of Timer1 in two 8-bit operations bit 6 T1RUN: Timer1 System Clock Status bit 1 = Device clock is derived from Timer1 oscillator 0 = Device clock is derived from another source bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 T1OSCEN: Timer1 Oscillator Enable bit 1 = Timer1 oscillator is enabled 0 = Timer1 oscillator is shut off The oscillator inverter and feedback resistor are turned off to eliminate power drain. bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit When TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from RC0/T1OSO/T13CKI pin (on the rising edge) 0 = Internal clock (FOSC/4) bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 2011 Microchip Technology Inc. DS39762F-page 175 PIC18F97J60 FAMILY 13.1 cycle (FOSC/4). When the bit is set, Timer1 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled. Timer1 Operation Timer1 can operate in one of these modes: * Timer * Synchronous Counter * Asynchronous Counter When Timer1 is enabled, the RC1/T1OSI and RC0/T1OSO/T13CKI pins become inputs. This means the values of TRISC<1:0> are ignored and the pins are read as `0'. The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). When TMR1CS is cleared (= 0), Timer1 increments on every internal instruction FIGURE 13-1: TIMER1 BLOCK DIAGRAM Timer1 Oscillator Timer1 Clock Input On/Off T1OSO/T13CKI 1 1 FOSC/4 Internal Clock T1OSI T1OSCEN(1) Synchronize Prescaler 1, 2, 4, 8 0 Detect 0 2 Sleep Input TMR1CS Timer1 On/Off T1CKPS<1:0> T1SYNC TMR1ON Clear TMR1 (ECCPx Special Event Trigger) Set TMR1IF on Overflow TMR1 High Byte TMR1L Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. FIGURE 13-2: TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE) Timer1 Clock Input Timer1 Oscillator 1 T1OSO/T13CKI 1 FOSC/4 Internal Clock T1OSI T1OSCEN(1) T1CKPS<1:0> T1SYNC TMR1ON Synchronize Detect Prescaler 1, 2, 4, 8 0 0 2 Sleep Input TMR1CS Clear TMR1 (ECCPx Special Event Trigger) Timer1 On/Off TMR1 High Byte TMR1L 8 Set TMR1IF on Overflow Read TMR1L Write TMR1L 8 8 TMR1H 8 8 Internal Data Bus Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. DS39762F-page 176 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 13.2 Timer1 16-Bit Read/Write Mode Timer1 can be configured for 16-bit reads and writes (see Figure 13-2). When the RD16 control bit (T1CON<7>) is set, the address for TMR1H is mapped to a buffer register for the high byte of Timer1. A read from TMR1L will load the contents of the high byte of Timer1 into the Timer1 High Byte Buffer register. This provides the user with the ability to accurately read all 16 bits of Timer1 without having to determine whether a read of the high byte, followed by a read of the low byte, has become invalid due to a rollover between reads. TABLE 13-1: Oscillator Type Freq. C1 C2 LP 32 kHz 27 pF(1) 27 pF(1) Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit. 2: Higher capacitance increases the stability of the oscillator but also increases the start-up time. A write to the high byte of Timer1 must also take place through the TMR1H Buffer register. The Timer1 high byte is updated with the contents of TMR1H when a write occurs to TMR1L. This allows a user to write all 16 bits to both the high and low bytes of Timer1 at once. The high byte of Timer1 is not directly readable or writable in this mode. All reads and writes must take place through the Timer1 High Byte Buffer register. Writes to TMR1H do not clear the Timer1 prescaler. The prescaler is only cleared on writes to TMR1L. 13.3 The user must provide a software time delay to ensure proper start-up of the Timer1 oscillator. FIGURE 13-3: EXTERNAL COMPONENTS FOR THE TIMER1 OSCILLATOR C1 27 pF PIC18F97J60 T1OSI XTAL 32.768 kHz T1OSO C2 27 pF Note: 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: Capacitor values are for design guidance only. 13.3.1 Timer1 Oscillator An on-chip crystal oscillator circuit is incorporated between pins, T1OSI (input) and T1OSO (amplifier output). It is enabled by setting the Timer1 Oscillator Enable bit, T1OSCEN (T1CON<3>). The oscillator is a low-power circuit rated for 32 kHz crystals. It will continue to run during all power-managed modes. The circuit for a typical LP oscillator is shown in Figure 13-3. Table 13-1 shows the capacitor selection for the Timer1 oscillator. See the Notes with Table 13-1 for additional information about capacitor selection. 2011 Microchip Technology Inc. CAPACITOR SELECTION FOR THE TIMER1 OSCILLATOR(2,3,4) USING TIMER1 AS A CLOCK SOURCE The Timer1 oscillator is also available as a clock source in power-managed modes. By setting the Clock Select bits, SCS<1:0> (OSCCON<1:0>), to `01', the device switches to SEC_RUN mode. Both the CPU and peripherals are clocked from the Timer1 oscillator. If the IDLEN bit (OSCCON<7>) is cleared and a SLEEP instruction is executed, the device enters SEC_IDLE mode. Additional details are available in Section 4.0 "Power-Managed Modes". Whenever the Timer1 oscillator is providing the clock source, the Timer1 system clock status flag, T1RUN (T1CON<6>), is set. This can be used to determine the controller's current clocking mode. It can also indicate the clock source being currently used by the Fail-Safe Clock Monitor. If the Clock Monitor is enabled and the Timer1 oscillator fails while providing the clock, polling the T1RUN bit will indicate whether the clock is being provided by the Timer1 oscillator or another source. 13.3.2 TIMER1 OSCILLATOR LAYOUT CONSIDERATIONS The Timer1 oscillator circuit draws very little power during operation. Due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. The oscillator circuit, shown in Figure 13-3, should be located as close as possible to the microcontroller. There should be no circuits passing within the oscillator circuit boundaries other than VSS or VDD. DS39762F-page 177 PIC18F97J60 FAMILY If a high-speed circuit must be located near the oscillator (such as the ECCP1 pin in Output Compare or PWM mode, or the primary oscillator using the OSC2 pin), a grounded guard ring around the oscillator circuit, as shown in Figure 13-4, may be helpful when used on a single-sided PCB or in addition to a ground plane. FIGURE 13-4: OSCILLATOR CIRCUIT WITH GROUNDED GUARD RING VDD VSS OSC1 OSC2 RC0 RC1 RC2 Note: Not drawn to scale. 13.4 Timer1 Interrupt The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The Timer1 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit, TMR1IF (PIR1<0>). This interrupt can be enabled or disabled by setting or clearing the Timer1 Interrupt Enable bit, TMR1IE (PIE1<0>). 13.5 Resetting Timer1 Using the ECCPx Special Event Trigger If ECCP1 or ECCP2 is configured to use Timer1 and to generate a Special Event Trigger in Compare mode (CCPxM<3:0> = 1011), this signal will reset Timer3. The trigger from ECCP2 will also start an A/D conversion if the A/D module is enabled (see Section 18.2.1 "Special Event Trigger" for more information). The module must be configured as either a timer or a synchronous counter to take advantage of this feature. When used this way, the CCPRxH:CCPRxL register pair effectively becomes a period register for Timer1. If Timer1 is running in Asynchronous Counter mode, this Reset operation may not work. In the event that a write to Timer1 coincides with a Special Event Trigger, the write operation will take precedence. Note: The Special Event Triggers from the ECCPx module will not set the TMR1IF interrupt flag bit (PIR1<0>). DS39762F-page 178 13.6 Using Timer1 as a Real-Time Clock Adding an external LP oscillator to Timer1 (such as the one described in Section 13.3 "Timer1 Oscillator") gives users the option to include RTC functionality to their applications. This is accomplished with an inexpensive watch crystal to provide an accurate time base and several lines of application code to calculate the time. When operating in Sleep mode and using a battery or supercapacitor as a power source, it can completely eliminate the need for a separate RTC device and battery backup. The application code routine, RTCisr, shown in Example 13-1, demonstrates a simple method to increment a counter at one-second intervals using an Interrupt Service Routine. Incrementing the TMR1 register pair to overflow, triggers the interrupt and calls the routine, which increments the seconds counter by one. Additional counters for minutes and hours are incremented as the previous counter overflows. Since the register pair is 16 bits wide, counting up to overflow the register directly from a 32.768 kHz clock would take 2 seconds. To force the overflow at the required one-second intervals, it is necessary to preload it. The simplest method is to set the MSb of TMR1H with a BSF instruction. Note that the TMR1L register is never preloaded or altered; doing so may introduce cumulative error over many cycles. For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> = 1), as shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times. 13.7 Considerations in Asynchronous Counter Mode Following a Timer1 interrupt and an update to the TMR1 registers, the Timer1 module uses a falling edge on its clock source to trigger the next register update on the rising edge. If the update is completed after the clock input has fallen, the next rising edge will not be counted. If the application can reliably update TMR1 before the timer input goes low, no additional action is needed. Otherwise, an adjusted update can be performed following a later Timer1 increment. This can be done by monitoring TMR1L within the interrupt routine until it increments, and then updating the TMR1H:TMR1L register pair while the clock is low, or one-half of the period of the clock source. Assuming that Timer1 is being used as a Real-Time Clock, the clock source is a 32.768 kHz crystal oscillator. In this case, one-half period of the clock is 15.25 s. The Real-Time Clock application code in Example 13-1 shows a typical ISR for Timer1, as well as the optional code required if the update cannot be done reliably within the required interval. 2011 Microchip Technology Inc. PIC18F97J60 FAMILY EXAMPLE 13-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE RTCinit MOVLW MOVWF CLRF MOVLW MOVWF CLRF CLRF MOVLW MOVWF BSF RETURN 80h ; TMR1H ; TMR1L b'00001111' ; T1CON ; secs ; mins ; .12 hours PIE1, TMR1IE ; Preload TMR1 register pair for 1 second overflow Configure for external clock, Asynchronous operation, external oscillator Initialize timekeeping registers Enable Timer1 interrupt RTCisr BTFSC BRA BTFSS BRA BSF BCF INCF MOVLW CPFSGT RETURN CLRF INCF MOVLW CPFSGT RETURN CLRF INCF MOVLW CPFSGT RETURN CLRF RETURN TABLE 13-2: Name INTCON ; ; TMR1L,0 ; $-2 ; TMR1L,0 ; $-2 ; ; ; TMR1H, 7 ; PIR1, TMR1IF ; secs, F ; .59 ; secs ; secs ; mins, F ; .59 ; mins ; mins ; hours, F ; .23 ; hours ; hours ; ; Insert the next 4 lines of code when TMR1 can not be reliably updated before clock pulse goes low wait for TMR1L to become clear (may already be clear) wait for TMR1L to become set TMR1 has just incremented If TMR1 update can be completed before clock pulse goes low Start ISR here Preload for 1 sec overflow Clear interrupt flag Increment seconds 60 seconds elapsed? No, done Clear seconds Increment minutes 60 minutes elapsed? No, done clear minutes Increment hours 24 hours elapsed? No, done Reset hours Done REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Bit 7 Bit 6 GIE/GIEH PEIE/GIEL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 71 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 71 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 71 TMR1L Timer1 Register Low Byte 70 TMR1H Timer1 Register High Byte 70 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 70 Legend: Shaded cells are not used by the Timer1 module. 2011 Microchip Technology Inc. DS39762F-page 179 PIC18F97J60 FAMILY 14.0 TIMER2 MODULE 14.1 The Timer2 timer module incorporates the following features: * 8-Bit Timer and Period registers (TMR2 and PR2, respectively) * Readable and writable (both registers) * Software programmable prescaler (1:1, 1:4 and 1:16) * Software programmable postscaler (1:1 through 1:16) * Interrupt on TMR2 to PR2 match * Optional use as the shift clock for the MSSPx modules This module is controlled through the T2CON register (Register 14-1) which enables or disables the timer and configures the prescaler and postscaler. Timer2 can be shut off by clearing control bit, TMR2ON (T2CON<2>), to minimize power consumption. A simplified block diagram of the module is shown in Figure 14-1. Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (FOSC/4). A 4-bit counter/prescaler on the clock input gives direct input, divide-by-4 and divide-by-16 prescale options. These options are selected by the prescaler control bits, T2CKPS<1:0> (T2CON<1:0>). The value of TMR2 is compared to that of the Period register, PR2, on each clock cycle. When the two values match, the comparator generates a match signal as the timer output. This signal also resets the value of TMR2 to 00h on the next cycle and drives the output counter/postscaler (see Section 14.2 "Timer2 Interrupt"). The TMR2 and PR2 registers are both directly readable and writable. The TMR2 register is cleared on any device Reset, while the PR2 register initializes at FFh. Both the prescaler and postscaler counters are cleared on the following events: * A write to the TMR2 register * A write to the T2CON register * Any device Reset (Power-on Reset, MCLR Reset, Watchdog Timer Reset or Brown-out Reset) TMR2 is not cleared when T2CON is written. REGISTER 14-1: T2CON: TIMER2 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 Unimplemented: Read as `0' bit 6-3 T2OUTPS<3:0>: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale * * * 1111 = 1:16 Postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 DS39762F-page 180 x = Bit is unknown 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 14.2 Timer2 Interrupt 14.3 Timer2 can also generate an optional device interrupt. The Timer2 output signal (TMR2 to PR2 match) provides the input for the 4-bit output counter/postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF (PIR1<1>). The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE (PIE1<1>). Timer2 Output The unscaled output of TMR2 is available primarily to the CCP modules, where it is used as a time base for operations in PWM mode. Timer2 can be optionally used as the shift clock source for the MSSPx modules operating in SPI mode. Additional information is provided in Section 20.0 "Master Synchronous Serial Port (MSSP) Module". A range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, T2OUTPS<3:0> (T2CON<6:3>). FIGURE 14-1: TIMER2 BLOCK DIAGRAM 4 T2OUTPS<3:0> T2CKPS<1:0> TMR2 Output (to PWM or MSSPx) TMR2/PR2 Match Reset TMR2 Comparator 8 Name PR2 8 8 Internal Data Bus TABLE 14-1: Set TMR2IF 2 1:1, 1:4, 1:16 Prescaler FOSC/4 1:1 to 1:16 Postscaler REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 71 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 71 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 71 TMR2 T2CON PR2 Timer2 Register -- T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON 70 T2CKPS1 T2CKPS0 Timer2 Period Register 70 70 Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the Timer2 module. 2011 Microchip Technology Inc. DS39762F-page 181 PIC18F97J60 FAMILY NOTES: DS39762F-page 182 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 15.0 TIMER3 MODULE The Timer3 timer/counter module incorporates these features: * Software selectable operation as a 16-bit timer or counter * Readable and writable 8-bit registers (TMR3H and TMR3L) * Selectable clock source (internal or external) with device clock or Timer1 oscillator internal options * Interrupt on overflow * Module Reset on CCPx/ECCPx Special Event Trigger REGISTER 15-1: A simplified block diagram of the Timer3 module is shown in Figure 15-1. A block diagram of the module's operation in Read/Write mode is shown in Figure 15-2. The Timer3 module is controlled through the T3CON register (Register 15-1). It also selects the clock source options for the CCPx and ECCPx modules; see Section 17.1.1 "CCPx/ECCPx Modules and Timer Resources" for more information. T3CON: TIMER3 CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 RD16: 16-Bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer3 in one 16-bit operation 0 = Enables register read/write of Timer3 in two 8-bit operations bit 6,3 T3CCP<2:1>: Timer3 and Timer1 to CCPx/ECCPx Enable bits 11 = Timer3 and Timer4 are the clock sources for all CCPx/ECCPx modules 10 = Timer3 and Timer4 are the clock sources for ECCP3, CCP4 and CCP5; Timer1 and Timer2 are the clock sources for ECCP1 and ECCP2 01 = Timer3 and Timer4 are the clock sources for ECCP2, ECCP3, CCP4 and CCP5; Timer1 and Timer2 are the clock sources for ECCP1 00 = Timer1 and Timer2 are the clock sources for all CCPx/ECCPx modules bit 5-4 T3CKPS<1:0>: Timer3 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 2 T3SYNC: Timer3 External Clock Input Synchronization Select bit (not usable if the device clock comes from Timer1/Timer3) When TMR3CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR3CS = 0: This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0. bit 1 TMR3CS: Timer3 Clock Source Select bit 1 = External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first falling edge) 0 = Internal clock (FOSC/4) bit 0 TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 2011 Microchip Technology Inc. DS39762F-page 183 PIC18F97J60 FAMILY 15.1 The operating mode is determined by the clock select bit, TMR3CS (T3CON<1>). When TMR3CS is cleared (= 0), Timer3 increments on every internal instruction cycle (FOSC/4). When the bit is set, Timer3 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled. Timer3 Operation Timer3 can operate in one of three modes: * Timer * Synchronous Counter * Asynchronous Counter FIGURE 15-1: As with Timer1, the RC1/T1OSI and RC0/T1OSO/T13CKI pins become inputs when the Timer1 oscillator is enabled. This means the values of TRISC<1:0> are ignored and the pins are read as `0'. TIMER3 BLOCK DIAGRAM Timer1 Oscillator Timer1 Clock Input 1 T1OSO/T13CKI 1 FOSC/4 Internal Clock T1OSI T1OSCEN(1) Synchronize Detect Prescaler 1, 2, 4, 8 0 0 2 Sleep Input TMR3CS Timer3 On/Off T3CKPS<1:0> T3SYNC TMR3ON Clear TMR3 ECCPx Special Event Trigger ECCPx Select from T3CON<6,3> Set TMR3IF on Overflow TMR3 High Byte TMR3L Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. FIGURE 15-2: TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE) Timer1 Clock Input Timer1 Oscillator 1 T1OSO/T13CKI 1 FOSC/4 Internal Clock T1OSI (1) T1OSCEN T3CKPS<1:0> T3SYNC TMR3ON Synchronize Detect Prescaler 1, 2, 4, 8 0 2 Sleep Input TMR3CS ECCPx Special Event Trigger ECCPx Select from T3CON<6,3> 0 Clear TMR3 Timer3 On/Off Set TMR3IF on Overflow TMR3 High Byte TMR3L 8 Read TMR1L Write TMR1L 8 8 TMR3H 8 8 Internal Data Bus Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. DS39762F-page 184 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 15.2 Timer3 16-Bit Read/Write Mode 15.4 Timer3 Interrupt Timer3 can be configured for 16-bit reads and writes (see Figure 15-2). When the RD16 control bit (T3CON<7>) is set, the address for TMR3H is mapped to a buffer register for the high byte of Timer3. A read from TMR3L will load the contents of the high byte of Timer3 into the Timer3 High Byte Buffer register. This provides the user with the ability to accurately read all 16 bits of Timer1 without having to determine whether a read of the high byte, followed by a read of the low byte, has become invalid due to a rollover between reads. The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh, and overflows to 0000h. The Timer3 interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit, TMR3IF (PIR2<1>). This interrupt can be enabled or disabled by setting or clearing the Timer3 Interrupt Enable bit, TMR3IE (PIE2<1>). A write to the high byte of Timer3 must also take place through the TMR3H Buffer register. The Timer3 high byte is updated with the contents of TMR3H when a write occurs to TMR3L. This allows a user to write all 16 bits to both the high and low bytes of Timer3 at once. If ECCP1 or ECCP2 is configured to use Timer3 and to generate a Special Event Trigger in Compare mode (CCPxM<3:0> = 1011), this signal will reset Timer3. The trigger from ECCP2 will also start an A/D conversion if the A/D module is enabled (see Section 18.2.1 "Special Event Trigger" for more information). The high byte of Timer3 is not directly readable or writable in this mode. All reads and writes must take place through the Timer3 High Byte Buffer register. Writes to TMR3H do not clear the Timer3 prescaler. The prescaler is only cleared on writes to TMR3L. 15.3 Using the Timer1 Oscillator as the Timer3 Clock Source The Timer1 internal oscillator may be used as the clock source for Timer3. The Timer1 oscillator is enabled by setting the T1OSCEN (T1CON<3>) bit. To use it as the Timer3 clock source, the TMR3CS bit must also be set. As previously noted, this also configures Timer3 to increment on every rising edge of the oscillator source. 15.5 Resetting Timer3 Using the ECCPx Special Event Trigger The module must be configured as either a timer or synchronous counter to take advantage of this feature. When used this way, the CCPRxH:CCPRxL register pair effectively becomes a Period register for Timer3. If Timer3 is running in Asynchronous Counter mode, the Reset operation may not work. In the event that a write to Timer3 coincides with a Special Event Trigger from an ECCPx module, the write will take precedence. Note: The Special Event Triggers from the ECCPx module will not set the TMR3IF interrupt flag bit (PIR2<1>). The Timer1 oscillator is described in Section 13.0 "Timer1 Module". TABLE 15-1: Name INTCON REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER Bit 7 Bit 6 GIE/GIEH PEIE/GIEL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 PIR2 OSCFIF CMIF ETHIF r BCL1IF -- TMR3IF CCP2IF 71 PIE2 OSCFIE CMIE ETHIE r BCL1IE -- TMR3IE CCP2IE 71 IPR2 OSCFIP CMIP ETHIP r BCL1IP -- TMR3IP CCP2IP 71 TMR3L Timer3 Register Low Byte 70 TMR3H Timer3 Register High Byte 70 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 70 T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 TMR3CS TMR3ON 71 T3CCP1 T3SYNC Legend: -- = unimplemented, read as `0', r = reserved. Shaded cells are not used by the Timer3 module. 2011 Microchip Technology Inc. DS39762F-page 185 PIC18F97J60 FAMILY NOTES: DS39762F-page 186 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 16.0 TIMER4 MODULE 16.1 The Timer4 module has the following features: * * * * * * 8-Bit Timer register (TMR4) 8-Bit Period register (PR4) Readable and writable (both registers) Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Interrupt on TMR4 match of PR4 Timer4 has a control register, shown in Register 16-1. Timer4 can be shut off by clearing control bit, TMR4ON (T4CON<2>), to minimize power consumption. The prescaler and postscaler selection of Timer4 is also controlled by this register. Figure 16-1 is a simplified block diagram of the Timer4 module. Timer4 Operation Timer4 can be used as the PWM time base for the PWM mode of the CCP module. The TMR4 register is readable and writable, and is cleared on any device Reset. The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits, T4CKPS<1:0> (T4CON<1:0>). The match output of TMR4 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR4 interrupt, latched in flag bit, TMR4IF (PIR3<3>). The prescaler and postscaler counters are cleared when any of the following occurs: * A write to the TMR4 register * A write to the T4CON register * Any device Reset (Power-on Reset, MCLR Reset, Watchdog Timer Reset or Brown-out Reset) TMR4 is not cleared when T4CON is written. REGISTER 16-1: T4CON: TIMER4 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 Unimplemented: Read as `0' bit 6-3 T4OUTPS<3:0>: Timer4 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale * * * 1111 = 1:16 Postscale bit 2 TMR4ON: Timer4 On bit 1 = Timer4 is on 0 = Timer4 is off bit 1-0 T4CKPS<1:0>: Timer4 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 2011 Microchip Technology Inc. x = Bit is unknown DS39762F-page 187 PIC18F97J60 FAMILY 16.2 Timer4 Interrupt 16.3 The Timer4 module has an 8-Bit Period register, PR4, which is both readable and writable. Timer4 increments from 00h until it matches PR4 and then resets to 00h on the next increment cycle. The PR4 register is initialized to FFh upon Reset. FIGURE 16-1: Output of TMR4 The output of TMR4 (before the postscaler) is used only as a PWM time base for the CCPx/ECCPx modules. It is not used as a baud rate clock for the MSSPx modules as is the Timer2 output. TIMER4 BLOCK DIAGRAM 4 T4OUTPS<3:0> Set TMR4IF 2 T4CKPS<1:0> TMR4 Output (to PWM) TMR4/PR4 Match Reset 1:1, 1:4, 1:16 Prescaler FOSC/4 1:1 to 1:16 Postscaler TMR4 PR4 Comparator 8 8 8 Internal Data Bus TABLE 16-1: Name REGISTERS ASSOCIATED WITH TIMER4 AS A TIMER/COUNTER Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 71 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 71 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 71 PIE3 TMR4 T4CON PR4 Timer4 Register -- 72 T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 Timer4 Period Register 72 72 Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the Timer4 module. DS39762F-page 188 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 17.0 register. For the sake of clarity, all CCPx module operation in the following sections is described with respect to CCP4, but is equally applicable to CCP5. CAPTURE/COMPARE/PWM (CCP) MODULES Members of the PIC18F97J60 family of devices all have a total of five CCP (Capture/Compare/PWM) modules. Two of these (CCP4 and CCP5) implement standard Capture, Compare and Pulse-Width Modulation (PWM) modes and are discussed in this section. The other three modules (ECCP1, ECCP2, ECCP3) implement standard Capture and Compare modes, as well as Enhanced PWM modes. These are discussed in Section 18.0 "Enhanced Capture/Compare/PWM (ECCP) Modules". Each CCPx/ECCPx module contains a 16-bit register which can operate as a 16-Bit Capture register, a 16-Bit Compare register or a PWM Master/Slave Duty Cycle REGISTER 17-1: Capture and Compare operations described in this chapter apply to all standard and Enhanced CCPx modules. The operations of PWM mode, described in Section 17.4 "PWM Mode", apply to CCP4 and CCP5 only. Note: Throughout this section and Section 18.0 "Enhanced Capture/Compare/PWM (ECCP) Modules", references to register and bit names that may be associated with a specific CCP module are referred to generically by the use of `x' or `y' in place of the specific module number. Thus, "CCPxCON" might refer to the control register for ECCP1, ECCP2, ECCP3, CCP4 or CCP5. CCPxCON: CCPx CONTROL REGISTER (CCP4 AND CCP5) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as `0' bit 5-4 DCxB<1:0>: CCPx Module PWM Duty Cycle Bit 1 and Bit 0 Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two Least Significant bits (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight Most Significant bits (DCxB<9:2>) of the duty cycle are found in CCPRxL. bit 3-0 CCPxM<3:0>: CCPx Module Mode Select bits 0000 = Capture/Compare/PWM disabled (resets CCPx module) 0001 = Reserved 0010 = Compare mode; toggle output on match (CCPxIF bit is set) 0011 = Reserved 0100 = Capture mode; every falling edge 0101 = Capture mode; every rising edge 0110 = Capture mode; every 4th rising edge 0111 = Capture mode; every 16th rising edge 1000 = Compare mode; initialize CCPx pin low; on compare match, force CCPx pin high (CCPxIF bit is set) 1001 = Compare mode; initialize CCPx pin high; on compare match, force CCPx pin low (CCPxIF bit is set) 1010 = Compare mode; generate software interrupt on compare match (CCPxIF bit is set, CCPx pin reflects I/O state) 1011 = Reserved 11xx = PWM mode 2011 Microchip Technology Inc. DS39762F-page 189 PIC18F97J60 FAMILY 17.1 CCPx Module Configuration Each Capture/Compare/PWM module is associated with a control register (generically, CCPxCON) and a data register (CCPRx). The data register, in turn, is comprised of two 8-bit registers: CCPRxL (low byte) and CCPRxH (high byte). All registers are both readable and writable. 17.1.1 17.1.2 CCPx/ECCPx MODULES AND TIMER RESOURCES The CCPx/ECCPx modules utilize Timers 1, 2, 3 or 4, depending on the mode selected. Timer1 and Timer3 are available to modules in Capture or Compare modes, while Timer2 and Timer4 are available for modules in PWM mode. TABLE 17-1: CCPx/ECCPx MODE - TIMER RESOURCE CCPx/ECCPx Mode Timer Resource Capture Compare PWM Timer1 or Timer3 Timer1 or Timer3 Timer2 or Timer4 FIGURE 17-1: The assignment of a particular timer to a module is determined by the timer to CCPx enable bits in the T3CON register (Register 15-1, page 183). Depending on the configuration selected, up to four timers may be active at once, with modules in the same configuration (Capture/Compare or PWM) sharing timer resources. The possible configurations are shown in Figure 17-1. ECCP2 PIN ASSIGNMENT The pin assignment for ECCP2 (Capture input, Compare and PWM output) can change based on device configuration. The CCP2MX Configuration bit determines which pin ECCP2 is multiplexed to. By default, it is assigned to RC1 (CCP2MX = 1). If the Configuration bit is cleared, ECCP2 is multiplexed with RE7 on 80-pin and 100-pin devices in Microcontroller mode and RB3 on 100-pin devices in Extended Microcontroller mode. Changing the pin assignment of ECCP2 does not automatically change any requirements for configuring the port pin. Users must always verify that the appropriate TRIS register is configured correctly for ECCP2 operation, regardless of where it is located. CCPx/ECCPx AND TIMER INTERCONNECT CONFIGURATIONS T3CCP<2:1> = 00 T3CCP<2:1> = 01 T3CCP<2:1> = 10 T3CCP<2:1> = 11 TMR1 TMR1 TMR1 TMR1 TMR3 TMR3 ECCP1 ECCP1 TMR3 TMR3 ECCP1 ECCP1 ECCP2 ECCP2 ECCP2 ECCP2 ECCP3 ECCP3 ECCP3 ECCP3 CCP4 CCP4 CCP4 CCP4 CCP5 CCP5 CCP5 CCP5 TMR2 TMR4 Timer1 is used for all Capture and Compare operations for all CCPx modules. Timer2 is used for PWM operations for all CCPx modules. Modules may share either timer resource as a common time base. Timer3 and Timer4 are not available. DS39762F-page 190 TMR2 TMR4 Timer1 and Timer2 are used for Capture and Compare or PWM operations for ECCP1 only (depending on selected mode). All other modules use either Timer3 or Timer4. Modules may share either timer resource as a common time base if they are in Capture/Compare or PWM modes. TMR2 TMR4 Timer1 and Timer2 are used for Capture and Compare or PWM operations for ECCP1 and ECCP2 only (depending on the mode selected for each module). Both modules may use a timer as a common time base if they are both in Capture/Compare or PWM modes. TMR2 TMR4 Timer3 is used for all Capture and Compare operations for all CCPx modules. Timer4 is used for PWM operations for all CCPx modules. Modules may share either timer resource as a common time base. Timer1 and Timer2 are not available. The other modules use either Timer3 or Timer4. Modules may share either timer resource as a common time base if they are in Capture/Compare or PWM modes. 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 17.2 17.2.3 Capture Mode When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit clear to avoid false interrupts. The interrupt flag bit, CCPxIF, should also be cleared following any such change in operating mode. In Capture mode, the CCPRxH:CCPRxL register pair captures the 16-bit value of the TMR1 or TMR3 registers when an event occurs on the corresponding CCPx pin. An event is defined as one of the following: * * * * Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge 17.2.4 Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared; therefore, the first capture may be from a non-zero prescaler. Example 17-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the "false" interrupt. CCPx PIN CONFIGURATION In Capture mode, the appropriate CCPx pin should be configured as an input by setting the corresponding TRIS direction bit. Note: 17.2.2 If RG4/CCP5/P1D is configured as an output, a write to the port can cause a capture condition. EXAMPLE 17-1: TIMER1/TIMER3 MODE SELECTION CLRF MOVLW The timers that are to be used with the capture feature (Timer1 and/or Timer3) must be running in Timer mode or Synchronized Counter mode. In Asynchronous Counter mode, the capture operation will not work. The timer to be used with each CCPx module is selected in the T3CON register (see Section 17.1.1 "CCPx/ECCPx Modules and Timer Resources"). FIGURE 17-2: CCPx PRESCALER There are four prescaler settings in Capture mode. They are specified as part of the operating mode selected by the mode select bits (CCPxM<3:0>). Whenever the CCPx module is turned off or Capture mode is disabled, the prescaler counter is cleared. This means that any Reset will clear the prescaler counter. The event is selected by the mode select bits, CCPxM<3:0> (CCPxCON<3:0>). When a capture is made, the interrupt request flag bit, CCPxIF, is set; it must be cleared in software. If another capture occurs before the value in register, CCPRx, is read, the old captured value is overwritten by the new captured value. 17.2.1 SOFTWARE INTERRUPT MOVWF CHANGING BETWEEN CAPTURE PRESCALERS (CCP5 SHOWN) CCP5CON ; Turn CCP module off NEW_CAPT_PS ; Load WREG with the ; new prescaler mode ; value and CCP ON CCP5CON ; Load CCP5CON with ; this value CAPTURE MODE OPERATION BLOCK DIAGRAM TMR3H Set CCP4IF T3CCP2 CCP4 Pin Prescaler 1, 4, 16 and Edge Detect CCP4CON<3:0> Q1:Q4 CCP5CON<3:0> 4 4 Set CCP5IF CCPR4L TMR1 Enable TMR1H TMR1L TMR3H TMR3L 4 T3CCP1 T3CCP2 CCP5 Pin Prescaler 1, 4, 16 TMR3 Enable CCPR4H T3CCP2 TMR3L and Edge Detect TMR3 Enable CCPR5H CCPR5L TMR1 Enable T3CCP2 T3CCP1 2011 Microchip Technology Inc. TMR1H TMR1L DS39762F-page 191 PIC18F97J60 FAMILY 17.3 Compare Mode Note: In Compare mode, the 16-bit CCPRx register value is constantly compared against either the TMR1 or TMR3 register pair value. When a match occurs, the CCPx pin: * * * * Can be driven high Can be driven low Can be toggled (high-to-low or low-to-high) Remains unchanged (that is, reflects the state of the I/O latch) 17.3.2 CCPx PIN CONFIGURATION The user must configure the CCPx pin as an output by clearing the appropriate TRIS bit. FIGURE 17-3: TIMER1/TIMER3 MODE SELECTION Timer1 and/or Timer3 must be running in Timer mode or Synchronized Counter mode if the CCPx module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. The action on the pin is based on the value of the mode select bits (CCPxM<3:0>). At the same time, the interrupt flag bit, CCPxIF, is set. 17.3.1 Clearing the CCP5CON register will force the RG4 compare output latch (depending on device configuration) to the default low level. This is not the PORTB or PORTC I/O data latch. 17.3.3 SOFTWARE INTERRUPT MODE When the Generate Software Interrupt mode is chosen (CCPxM<3:0> = 1010), the corresponding CCPx pin is not affected. Only a CCPx interrupt is generated, if enabled, and the CCPxIE bit is set. COMPARE MODE OPERATION BLOCK DIAGRAM CCPR4H Set CCP4IF CCPR4L CCP4 Pin Comparator Output Logic Compare Match S Q R TRIS Output Enable 4 CCP4CON<3:0> 0 TMR1H TMR1L 0 1 TMR3H TMR3L 1 T3CCP1 T3CCP2 Set CCP5IF Comparator CCPR5H CCPR5L Compare Match CCP5 Pin Output Logic 4 S Q R TRIS Output Enable CCP5CON<3:0> DS39762F-page 192 2011 Microchip Technology Inc. PIC18F97J60 FAMILY TABLE 17-2: Name INTCON REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Bit 7 Bit 6 Bit 5 GIE/GIEH PEIE/GIEL TMR0IE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: INT0IE RBIE TMR0IF INT0IF RBIF 69 RCON IPEN -- CM RI TO PD POR BOR 70 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 71 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 71 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 71 PIR2 OSCFIF CMIF ETHIF r BCL1IF -- TMR3IF CCP2IF 71 PIE2 OSCFIE CMIE ETHIE r BCL1IE -- TMR3IE CCP2IE 71 IPR2 OSCFIP CMIP ETHIP r BCL1IP -- TMR3IP CCP2IP 71 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 71 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 71 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 71 TRISG4 TRISG3(1) TRISG2 TRISG1 TRISG0 71 TRISG TRISG7 TRISG6 TRISG5 TMR1L Timer1 Register Low Byte 70 TMR1H Timer1 Register High Byte 70 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR3H Timer3 Register High Byte TMR3L Timer3 Register Low Byte T3CON RD16 TMR1CS TMR1ON 70 70 70 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 71 CCPR4L Capture/Compare/PWM Register 4 Low Byte 72 CCPR4H Capture/Compare/PWM Register 4 High Byte 72 CCPR5L Capture/Compare/PWM Register 5 Low Byte 73 CCPR5H Capture/Compare/PWM Register 5 High Byte 73 CCP4CON -- -- DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 73 CCP5CON -- -- DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 73 Legend: -- = unimplemented, read as `0', r = reserved. Shaded cells are not used by Capture/Compare, Timer1 or Timer3. Note 1: This bit is only available in 80-pin and 100-pin devices; otherwise, it is unimplemented and reads as `0'. 2011 Microchip Technology Inc. DS39762F-page 193 PIC18F97J60 FAMILY 17.4 17.4.1 PWM Mode In Pulse-Width Modulation (PWM) mode, the CCPx pin produces up to a 10-bit resolution PWM output. Since the CCP4 and CCP5 pins are multiplexed with a PORTG data latch, the appropriate TRISG bit must be cleared to make the CCP4 or CCP5 pin an output. Clearing the CCP4CON or CCP5CON register will force the RG3 or RG4 output latch (depending on device configuration) to the default low level. This is not the PORTG I/O data latch. Note: Figure 17-4 shows a simplified block diagram of the CCPx module in PWM mode. For a step-by-step procedure on how to set up a CCPx module for PWM operation, see Section 17.4.3 "Setup for PWM Operation". FIGURE 17-4: SIMPLIFIED PWM BLOCK DIAGRAM The PWM period is specified by writing to the PR2 (PR4) register. The PWM period can be calculated using Equation 17-1: EQUATION 17-1: PWM Period = [(PR2) + 1] * 4 * TOSC * (TMR2 Prescale Value) PWM frequency is defined as 1/[PWM period]. When TMR2 (TMR4) is equal to PR2 (PR4), the following three events occur on the next increment cycle: * TMR2 (TMR4) is cleared * The CCPx pin is set (exception: if PWM duty cycle = 0%, the CCPx pin will not be set) * The PWM duty cycle is latched from CCPRxL into CCPRxH Note: Duty Cycle Register 9 0 CCPxCON<5:4> CCPRxL Latch Duty Cycle (1) CCPRxH S Comparator R Reset CCPx Pin TMRx TMRx = PRx Match 17.4.2 Q 2 LSbs Latched From Q clocks Comparator PRx TRIS Output Enable Set CCPx pin Note 1: The two LSbs of the Duty Cycle register are held by a 2-bit latch that is part of the module's hardware. It is physically separate from the CCPRx registers. A PWM output (Figure 17-5) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period). FIGURE 17-5: PWM OUTPUT PWM PERIOD The Timer2 and Timer4 postscalers (see Section 14.0 "Timer2 Module" and Section 16.0 "Timer4 Module") are not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPRxL register and to the CCPxCON<5:4> bits. Up to 10-bit resolution is available. The CCPRxL contains the eight MSbs and the CCPxCON<5:4> contains the two LSbs. This 10-bit value is represented by CCPRxL:CCPxCON<5:4>. Equation 17-2 is used to calculate the PWM duty cycle in time. EQUATION 17-2: PWM Duty Cycle = (CCPRXL:CCPXCON<5:4>) * TOSC * (TMRx Prescale Value) CCPRxL and CCPxCON<5:4> can be written to at any time, but the duty cycle value is not latched into CCPRxH until after a match between PR2 (PR4) and TMR2 (TMR4) occurs (i.e., the period is complete). In PWM mode, CCPRxH is a read-only register. Period Duty Cycle TMR2 (TMR4) = PR2 (PR4) TMR2 (TMR4) = Duty Cycle TMR2 (TMR4) = PR2 (TMR4) DS39762F-page 194 2011 Microchip Technology Inc. PIC18F97J60 FAMILY The CCPRxH register and a 2-bit internal latch are used to double-buffer the PWM duty cycle. This double-buffering is essential for glitchless PWM operation. When the CCPRxH and 2-bit latch match TMR2 (TMR4), concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 (TMR4) prescaler, the CCPx pin is cleared. The maximum PWM resolution (bits) for a given PWM frequency is given by Equation 17-3: 17.4.3 The following steps should be taken when configuring the CCPx module for PWM operation: 1. 2. 3. 4. EQUATION 17-3: FOSC log FPWM PWM Resolution (max) = log(2) ( Note: ) SETUP FOR PWM OPERATION 5. Set the PWM period by writing to the PR2 (PR4) register. Set the PWM duty cycle by writing to the CCPRxL register and CCPxCON<5:4> bits. Make the CCPx pin an output by clearing the appropriate TRIS bit. Set the TMR2 (TMR4) prescale value, then enable Timer2 (Timer4) by writing to T2CON (T4CON). Configure the CCPx module for PWM operation. bits If the PWM duty cycle value is longer than the PWM period, the CCPx pin will not be cleared. TABLE 17-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency Timer Prescaler (1, 4, 16) PR2 Value Maximum Resolution (bits) 2011 Microchip Technology Inc. 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz 16 4 1 1 1 1 FFh FFh FFh 3Fh 1Fh 17h 10 10 10 8 7 6.58 DS39762F-page 195 PIC18F97J60 FAMILY TABLE 17-4: Name INTCON REGISTERS ASSOCIATED WITH PWM, TIMER2 AND TIMER4 Bit 7 Bit 6 GIE/GIEH PEIE/GIEL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 IPEN -- CM RI TO PD POR BOR 70 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 71 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 71 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 71 RCON PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 71 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 71 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 71 TRISG TRISG7 TRISG6 TRISG5 TRISG4 TRISG3(1) TRISG2 TRISG1 TRISG0 71 TMR2 Timer2 Register 70 PR2 Timer2 Period Register 70 T2CON -- T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 70 TMR4 Timer4 Register 72 PR4 Timer4 Period Register 72 T4CON -- T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 72 CCPR4L Capture/Compare/PWM Register 4 Low Byte 72 CCPR4H Capture/Compare/PWM Register 4 High Byte 72 CCPR5L Capture/Compare/PWM Register 5 Low Byte 73 CCPR5H Capture/Compare/PWM Register 5 High Byte 73 CCP4CON -- -- DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 73 CCP5CON -- -- DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 73 Legend: -- = unimplemented, read as `0'. Shaded cells are not used by PWM, Timer2 or Timer4. Note 1: This bit is only available in 80-pin and 100-pin devices; otherwise, it is unimplemented and reads as `0'. DS39762F-page 196 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 18.0 ENHANCED CAPTURE/COMPARE/PWM (ECCP) MODULES In the PIC18F97J60 family of devices, three of the CCP modules are implemented as standard CCP modules with Enhanced PWM capabilities. These include the provision for 2 or 4 output channels, user-selectable polarity, dead-band control and automatic shutdown and restart. The Enhanced features are discussed in detail in Section 18.4 "Enhanced PWM Mode". Capture, Compare and single output PWM functions of the ECCPx modules are the same as described for the standard CCPx modules. 2011 Microchip Technology Inc. The control register for the Enhanced CCPx module is shown in Register 18-1. It differs from the CCP4CON/CCP5CON registers in that the two Most Significant bits are implemented to control PWM functionality. In addition to the expanded range of modes available through the Enhanced CCPxCON register, the ECCPx modules each have two additional registers associated with Enhanced PWM operation and auto-shutdown features. They are: * ECCPxDEL (Dead-Band Delay) * ECCPxAS (Auto-Shutdown Configuration) DS39762F-page 197 PIC18F97J60 FAMILY REGISTER 18-1: CCPxCON: ENHANCED CCPx CONTROL REGISTER (ECCP1/ECCP2/ECCP3) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PxM1 PxM0 DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-6 PxM<1:0>: Enhanced PWM Output Configuration bits If CCPxM<3:2> = 00, 01, 10: xx = PxA assigned as Capture/Compare input/output; PxB, PxC, PxD assigned as port pins If CCPxM<3:2> = 11: 00 = Single output: PxA modulated; PxB, PxC, PxD assigned as port pins 01 = Full-bridge output forward: P1D modulated; P1A active; P1B, P1C inactive 10 = Half-bridge output: P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins 11 = Full-bridge output reverse: P1B modulated; P1C active; P1A, P1D inactive bit 5-4 DCxB<1:0>: ECCPx Module PWM Duty Cycle Bit 1 and Bit 0 Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the 2 LSbs of the 10-bit PWM duty cycle. The 8 MSbs of the duty cycle are found in CCPRxL. bit 3-0 CCPxM<3:0>: ECCPx Module Mode Select bits 0000 = Capture/Compare/PWM disabled (resets ECCPx module) 0001 = Reserved 0010 = Compare mode; toggle output on match 0011 = Capture mode 0100 = Capture mode; every falling edge 0101 = Capture mode; every rising edge 0110 = Capture mode; every 4th rising edge 0111 = Capture mode; every 16th rising edge 1000 = Compare mode; initialize ECCPx pin low; set output on compare match (set CCPxIF) 1001 = Compare mode; initialize ECCPx pin high; clear output on compare match (set CCPxIF) 1010 = Compare mode; generate software interrupt only, ECCPx pin reverts to I/O state) 1011 = Compare mode; trigger special event (ECCPx resets TMR1 or TMR3, sets CCPxIF bit, ECCPx trigger also starts A/D conversion if A/D module is enabled)(1) 1100 = PWM mode; PxA, PxC active-high; PxB, PxD active-high 1101 = PWM mode; PxA, PxC active-high; PxB, PxD active-low 1110 = PWM mode; PxA, PxC active-low; PxB, PxD active-high 1111 = PWM mode; PxA, PxC active-low; PxB, PxD active-low Note 1: Implemented only for ECCP1 and ECCP2; same as `1010' for ECCP3. DS39762F-page 198 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 18.1 ECCPx Outputs and Configuration Each of the Enhanced CCPx modules may have up to four PWM outputs, depending on the selected operating mode. These outputs, designated PxA through PxD, are multiplexed with various I/O pins. Some ECCPx pin assignments are constant, while others change based on device configuration. For those pins that do change, the controlling bits are: * CCP2MX Configuration bit (80-pin and 100-pin devices only) * ECCPMX Configuration bit (80-pin and 100-pin devices only) * Program memory operating mode set by the EMB Configuration bits (100-pin devices only) The pin assignments for the Enhanced CCPx modules are summarized in Table 18-1, Table 18-2 and Table 18-3. To configure the I/O pins as PWM outputs, the proper PWM mode must be selected by setting the PxMx and CCPxMx bits (CCPxCON<7:6> and <3:0>, respectively). The appropriate TRIS direction bits for the corresponding port pins must also be set as outputs. 18.1.1 ECCP1/ECCP3 OUTPUTS AND PROGRAM MEMORY MODE In 100-pin devices, the use of Extended Microcontroller mode has an indirect effect on the ECCP1 and ECCP3 pins in Enhanced PWM modes. By default, PWM outputs, P1B/P1C and P3B/P3C, are multiplexed to PORTE pins, along with the high-order byte of the external memory bus. When the bus is active in Extended Microcontroller mode, it overrides the Enhanced CCPx outputs and makes them unavailable. Because of this, ECCP1 and ECCP3 can only be used in compatible (single output) PWM modes when the device is in Extended Microcontroller mode with default pin configuration. An exception to this configuration is when a 12-bit address width is selected for the external bus (EMB<1:0> Configuration bits = 10). In this case, the upper pins of PORTE continue to operate as digital I/O, even when the external bus is active. P1B/P1C and P3B/P3C remain available for use as Enhanced PWM outputs. 18.1.2 ECCP2 OUTPUTS AND PROGRAM MEMORY MODES For 100-pin devices, the Program Memory mode of the device (Section 6.1.3 "PIC18F9XJ60/9XJ65 Program Memory Modes") also impacts pin multiplexing for the module. The ECCP2 input/output (ECCP2/P2A) can be multiplexed to one of three pins. The default assignment (CCP2MX Configuration bit is set) for all devices is RC1. Clearing CCP2MX reassigns ECCP2/P2A to RE7 in 80-pin and 100-pin devices. An additional option exists for 100-pin devices. When these devices are operating in Microcontroller mode, the multiplexing options described above still apply. In Extended Microcontroller mode, clearing CCP2MX reassigns ECCP2/P2A to RB3. 18.1.3 USE OF CCP4 AND CCP5 WITH ECCP1 AND ECCP3 Only the ECCP2 module has four dedicated, output pins that are available for use. Assuming that the I/O ports or other multiplexed functions on those pins are not needed, they may be used without interfering with any other CCPx module. ECCP1 and ECCP3, on the other hand, only have three dedicated output pins: ECCPx/PxA, PxB and PxC. Whenever these modules are configured for Quad PWM mode, the pin normally used for CCP4 or CCP5 becomes the PxD output pin for ECCP3 and ECCP1, respectively. The CCP4 and CCP5 modules remain functional but their outputs are overridden. 18.1.4 ECCPx MODULES AND TIMER RESOURCES Like the standard CCPx modules, the ECCPx modules can utilize Timers 1, 2, 3 or 4, depending on the mode selected. Timer1 and Timer3 are available for modules in Capture or Compare modes, while Timer2 and Timer4 are available for modules in PWM mode. Additional details on timer resources are provided in Section 17.1.1 "CCPx/ECCPx Modules and Timer Resources". If an application requires the use of additional PWM outputs during Extended Microcontroller mode, the P1B/P1C and P3B/P3C outputs can be reassigned to the upper bits of PORTH. This is done by clearing the ECCPMX Configuration bit. 2011 Microchip Technology Inc. DS39762F-page 199 PIC18F97J60 FAMILY TABLE 18-1: PIN CONFIGURATIONS FOR ECCP1 CCP1CON Configuration ECCP Mode RC2 RD0 or RE6(1) RE5 RG4 RH7(2) RH6(2) 64-Pin Devices; 80-Pin Devices, ECCPMX = 1; 100-Pin Devices, ECCPMX = 1, Microcontroller mode or Extended Microcontroller mode with 12-Bit Address Width: Compatible CCP 00xx 11xx ECCP1 RD0/RE6 RE5 RG4/CCP5 RH7/AN15 RH6/AN14 Dual PWM 10xx 11xx P1A P1B RE5 RG4/CCP5 RH7/AN15 RH6/AN14 Quad PWM x1xx 11xx P1A P1B P1C P1D RH7/AN15 RH6/AN14 80-Pin Devices, ECCPMX = 0; 100-Pin Devices, ECCPMX = 0, All Program Memory modes: Compatible CCP 00xx 11xx ECCP1 RD0/RE6 RE5/AD13 RG4/CCP5 RH7/AN15 RH6/AN14 Dual PWM 10xx 11xx P1A RD0/RE6 RE5/AD13 RG4/CCP5 P1B RH6/AN14 Quad PWM(3) x1xx 11xx P1A RD0/RE6 RE5/AD13 P1D P1B P1C 100-Pin Devices, ECCPMX = 1, Extended Microcontroller mode with 16-Bit or 20-Bit Address Width: Compatible CCP Legend: Note 1: 2: 3: 00xx 11xx ECCP1 RD0/RE6 RE5/AD13 RG4/CCP5 RH7/AN15 RH6/AN14 x = Don't care. Shaded cells indicate pin assignments not used by ECCP1 in a given mode. P1B is multiplexed with RD0 in 64-pin devices, and RE6 on 80-pin and 100-pin devices. These pin options are not available in 64-pin devices. With ECCP1 in Quad PWM mode, the CCP5 pin's output is overridden by P1D; otherwise, CCP5 is fully operational. TABLE 18-2: PIN CONFIGURATIONS FOR ECCP2 ECCP Mode CCP2CON Configuration Compatible CCP 00xx 11xx RB3/INT3 ECCP2 RE7 RE2 Dual PWM 10xx 11xx RB3/INT3 P2A RE7 Quad PWM x1xx 11xx RB3/INT3 P2A RE7 Compatible CCP 00xx 11xx RB3/INT3 RC1/T1OS1 ECCP2 RE2 Dual PWM 10xx 11xx RB3/INT3 RC1/T1OS1 P2A P2B RE1 RE0 Quad PWM x1xx 11xx RB3/INT3 RC1/T1OS1 P2A P2B P2C P2D RB3 RC1 RE7 RE2 RE1 RE0 RE1 RE0 P2B RE1 RE0 P2B P2C P2D RE1 RE0 All Devices, CCP2MX = 1, All Program Memory modes: 80-Pin and 100-Pin Devices, CCP2MX = 0, Microcontroller mode: 100-Pin Devices, CCP2MX = 0, Extended Microcontroller mode: Compatible CCP 00xx 11xx ECCP2 RC1/T1OS1 RE7/AD15 RE2/CS RE1/WR RE0/RD Dual PWM 10xx 11xx P2A RC1/T1OS1 RE7/AD15 P2B RE1/WR RE0/RD Quad PWM x1xx 11xx P2A RC1/T1OS1 RE7/AD15 P2B P2C P2D Legend: x = Don't care. Shaded cells indicate pin assignments not used by ECCP2 in a given mode. DS39762F-page 200 2011 Microchip Technology Inc. PIC18F97J60 FAMILY TABLE 18-3: ECCP Mode PIN CONFIGURATIONS FOR ECCP3 CCP3CON Configuration RD1 or RG0(1) RE4 RE3 RD2 or RG3(1) RH5(2) RH4(2) 64-Pin Devices; 80-Pin Devices, ECCPMX = 1; 100-Pin Devices, ECCPMX = 1, Microcontroller mode: Compatible CCP 00xx 11xx ECCP3 RE4 RE3 RD2/RG3 RH5/AN13 RH4/AN12 Dual PWM 10xx 11xx P3A P3B RE3 RD2/RG3 RH5/AN13 RH4/AN12 Quad PWM x1xx 11xx P3A P3B P3C P3D RH5/AN13 RH4/AN12 80-Pin Devices, ECCPMX = 0; 100-Pin Devices, ECCPMX = 0, All Program Memory modes: Compatible CCP 00xx 11xx ECCP3 RE6/AD14 RE5/AD13 RD2/RG3 RH5/AN13 RH4/AN12 Dual PWM 10xx 11xx P3A RE6/AD14 RE5/AD13 RD2/RG3 P3B RH4/AN12 Quad PWM(3) x1xx 11xx P3A RE6/AD14 RE5/AD13 P3D P3B P3C 100-Pin Devices, ECCPMX = 1, Extended Microcontroller with 12-Bit Address Width: Compatible CCP 00xx 11xx ECCP3 RE4/AD12 RE3/AD11 RD2/RG3 RH5/AN13 RH4/AN12 Dual PWM 10xx 11xx P3A P3B RE3/AD11 RD2/RG3 RH5/AN13 RH4/AN12 100-Pin Devices, ECCPMX = 1, Extended Microcontroller mode with 16-Bit or 20-Bit Address Width: Compatible CCP Legend: Note 1: 2: 3: 00xx 11xx ECCP3 RE6/AD14 RE5/AD13 RD2/RG3 RH5/AN13 RH4/AN12 x = Don't care. Shaded cells indicate pin assignments not used by ECCP3 in a given mode. ECCP3/P3A and CCP4/P3D are multiplexed with RD1 and RD2 in 64-pin devices, and RG0 and RG3 in 80-pin and 100-pin devices. These pin options are not available in 64-pin devices. With ECCP3 in Quad PWM mode, the CCP4 pin's output is overridden by P3D; otherwise, CCP4 is fully operational. 2011 Microchip Technology Inc. DS39762F-page 201 PIC18F97J60 FAMILY 18.2 Capture and Compare Modes Except for the operation of the Special Event Trigger discussed below, the Capture and Compare modes of the ECCPx modules are identical in operation to that of CCP4. These are discussed in detail in Section 17.2 "Capture Mode" and Section 17.3 "Compare Mode". 18.2.1 Special Event Triggers are not implemented for ECCP3, CCP4 or CCP5. Selecting the Special Event Trigger mode for these modules has the same effect as selecting the Compare with Software Interrupt mode (CCPxM<3:0> = 1010). Note: The Special Event Trigger from ECCP2 will not set the Timer1 or Timer3 interrupt flag bits. SPECIAL EVENT TRIGGER ECCP1 and ECCP2 incorporate an internal hardware trigger that is generated in Compare mode on a match between the CCPRx register pair and the selected timer. This can be used, in turn, to initiate an action. This mode is selected by setting CCPxCON<3:0> to `1011'. The Special Event Trigger output of either ECCP1 or ECCP2 resets the TMR1 or TMR3 register pair, depending on which timer resource is currently selected. This allows the CCPRx register to effectively be a 16-Bit Programmable Period register for Timer1 or Timer3. In addition, the ECCP2 Special Event Trigger will also start an A/D conversion if the A/D module is enabled. DS39762F-page 202 18.3 Standard PWM Mode When configured in Single Output mode, the ECCPx modules function identically to the standard CCPx modules in PWM mode, as described in Section 17.4 "PWM Mode". Sometimes this is also referred to as "Compatible CCP" mode, as in Tables 18-1 through 18-3. Note: When setting up single output PWM operations, users are free to use either of the processes described in Section 17.4.3 "Setup for PWM Operation" or Section 18.4.9 "Setup for PWM Operation". The latter is more generic but will work for either single or multi-output PWM. 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 18.4 Enhanced PWM Mode The Enhanced PWM mode provides additional PWM output options for a broader range of control applications. The module is a backward compatible version of the standard CCPx modules and offers up to four outputs, designated PxA through PxD. Users are also able to select the polarity of the signal (either active-high or active-low). The module's output mode and polarity are configured by setting the PxM<1:0> and CCPxM<3:0> bits of the CCPxCON register (CCPxCON<7:6> and <3:0>, respectively). For the sake of clarity, Enhanced PWM mode operation is described generically throughout this section with respect to ECCP1 and TMR2 modules. Control register names are presented in terms of ECCP1. All three Enhanced modules, as well as the two timer resources, can be used interchangeably and function identically. TMR2 or TMR4 can be selected for PWM operation by selecting the proper bits in T3CON. Figure 18-1 shows a simplified block diagram of PWM operation. All control registers are double-buffered and are loaded at the beginning of a new PWM cycle (the period boundary when Timer2 resets) in order to prevent glitches on any of the outputs. The exception is the ECCP1 Dead-Band Delay register, ECCP1DEL, which is loaded at either the duty cycle boundary or the boundary period (whichever comes first). Because of the buffering, the module waits until the assigned timer resets instead of starting immediately. This means that FIGURE 18-1: Enhanced PWM waveforms do not exactly match the standard PWM waveforms, but are instead, offset by one full instruction cycle (4 TOSC). As before, the user must manually configure the appropriate TRIS bits for output. 18.4.1 PWM PERIOD The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following equation: EQUATION 18-1: PWM Period = [(PR2) + 1] * 4 * TOSC * (TMR2 Prescale Value) PWM frequency is defined as 1/[PWM period]. When TMR2 is equal to PR2, the following three events occur on the next increment cycle: * TMR2 is cleared * The ECCP1 pin is set (if PWM duty cycle = 0%, the ECCP1 pin will not be set) * The PWM duty cycle is copied from CCPR1L into CCPR1H Note: The Timer2 postscaler (see Section 14.0 "Timer2 Module") is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE Duty Cycle Registers CCP1CON<5:4> CCP1M<3:0> 4 P1M1<1:0> 2 CCPR1L ECCP1/P1A ECCP1/P1A TRISx<x> CCPR1H (Slave) P1B R Comparator Q Output Controller P1B TRISx<x> P1C TMR2 (Note 1) P1D Comparator PR2 P1C TRISx<x> S Clear Timer, set ECCP1 pin and latch D.C. P1D TRISx<x> ECCP1DEL Note: The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base. 2011 Microchip Technology Inc. DS39762F-page 203 PIC18F97J60 FAMILY 18.4.2 PWM DUTY CYCLE Note: The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> bits contain the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The PWM duty cycle is calculated by the equation: 18.4.3 PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) * TOSC * (TMR2 Prescale Value) CCPR1L and CCP1CON<5:4> can be written to at any time, but the duty cycle value is not copied into CCPR1H until a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register. The CCPR1H register and a 2-bit internal latch are used to double-buffer the PWM duty cycle. This double-buffering is essential for glitchless PWM operation. When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or two bits of the TMR2 prescaler, the ECCP1 pin is cleared. The maximum PWM resolution (bits) for a given PWM frequency is given by the following equation: PWM OUTPUT CONFIGURATIONS The P1M<1:0> bits in the CCP1CON register allow one of four configurations: * * * * EQUATION 18-2: If the PWM duty cycle value is longer than the PWM period, the ECCP1 pin will not be cleared. Single Output Half-Bridge Output Full-Bridge Output, Forward mode Full-Bridge Output, Reverse mode The Single Output mode is the standard PWM mode discussed in Section 18.4 "Enhanced PWM Mode". The Half-Bridge and Full-Bridge Output modes are covered in detail in the sections that follow. The general relationship of the outputs in all configurations is summarized in Figure 18-2. EQUATION 18-3: ( log FOSC FPWM PWM Resolution (max) = log(2) TABLE 18-4: ) bits EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency Timer Prescaler (1, 4, 16) PR2 Value Maximum Resolution (bits) DS39762F-page 204 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz 16 4 1 1 1 1 FFh FFh FFh 3Fh 1Fh 17h 10 10 10 8 7 6.58 2011 Microchip Technology Inc. PIC18F97J60 FAMILY FIGURE 18-2: PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) 0 CCP1CON<7:6> SIGNAL PR2 + 1 Duty Cycle Period 00 (Single Output) P1A Modulated Delay(1) Delay(1) P1A Modulated 10 (Half-Bridge) P1B Modulated P1A Active 01 (Full-Bridge, Forward) P1B Inactive P1C Inactive P1D Modulated P1A Inactive 11 (Full-Bridge, Reverse) P1B Modulated P1C Active P1D Inactive Relationships: * Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) * Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) * Delay = 4 * TOSC * (ECCP1DEL<6:0>) Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section 18.4.6 "Programmable Dead-Band Delay"). 2011 Microchip Technology Inc. DS39762F-page 205 PIC18F97J60 FAMILY FIGURE 18-3: PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) CCP1CON<7:6> SIGNAL Duty Cycle 0 PR2 + 1 Period 00 (Single Output) P1A Modulated P1A Modulated 10 (Half-Bridge) P1B Modulated Delay(1) Delay(1) P1A Active 01 (Full-Bridge, Forward) P1B Inactive P1C Inactive P1D Modulated P1A Inactive 11 (Full-Bridge, Reverse) P1B Modulated P1C Active P1D Inactive Relationships: * Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) * Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) * Delay = 4 * TOSC * (ECCP1DEL<6:0>) Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section 18.4.6 "Programmable Dead-Band Delay"). DS39762F-page 206 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 18.4.4 HALF-BRIDGE MODE FIGURE 18-4: In the Half-Bridge Output mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the P1A pin, while the complementary PWM output signal is output on the P1B pin (Figure 18-4). This mode can be used for half-bridge applications, as shown in Figure 18-5, or for full-bridge applications, where four power switches are being modulated with two PWM signals. HALF-BRIDGE PWM OUTPUT Period Period Duty Cycle P1A(2) td td P1B(2) In Half-Bridge Output mode, the programmable dead-band delay can be used to prevent shoot-through current in half-bridge power devices. The value of bits, P1DC<6:0>, sets the number of instruction cycles before the output is driven active. If the value is greater than the duty cycle, the corresponding output remains inactive during the entire cycle. See Section 18.4.6 "Programmable Dead-Band Delay" for more details on dead-band delay operations. (1) (1) (1) td = Dead Band Delay Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high. Since the P1A and P1B outputs are multiplexed with the PORTC<2> and PORTE<6> data latches, the TRISC<2> and TRISE<6> bits must be cleared to configure P1A and P1B as outputs. FIGURE 18-5: EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS V+ Standard Half-Bridge Circuit ("Push-Pull") PIC18F97J60 FET Driver + V - P1A Load FET Driver + V - P1B V- Half-Bridge Output Driving a Full-Bridge Circuit V+ PIC18F97J60 FET Driver FET Driver P1A FET Driver Load FET Driver P1B V- 2011 Microchip Technology Inc. DS39762F-page 207 PIC18F97J60 FAMILY 18.4.5 FULL-BRIDGE MODE In Full-Bridge Output mode, four pins are used as outputs; however, only two outputs are active at a time. In the Forward mode, pin, P1A, is continuously active and pin, P1D, is modulated. In the Reverse mode, pin, P1C, is continuously active and pin, P1B, is modulated. These are illustrated in Figure 18-6. FIGURE 18-6: P1A, P1B, P1C and P1D outputs are multiplexed with the data latches of the port pins listed in Table 18-1 and Table 18-3. The corresponding TRIS bits must be cleared to make the P1A, P1B, P1C and P1D pins outputs. FULL-BRIDGE PWM OUTPUT Forward Mode Period P1A(2) Duty Cycle P1B(2) P1C(2) P1D(2) (1) (1) Reverse Mode Period Duty Cycle P1A(2) P1B(2) P1C(2) P1D(2) (1) (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as active-high. DS39762F-page 208 2011 Microchip Technology Inc. PIC18F97J60 FAMILY FIGURE 18-7: EXAMPLE OF FULL-BRIDGE APPLICATION V+ PIC18F97J60 FET Driver QC QA FET Driver P1A Load P1B FET Driver P1C FET Driver QD QB VP1D 18.4.5.1 Direction Change in Full-Bridge Mode In the Full-Bridge Output mode, the P1M1 bit in the CCP1CON register allows users to control the forward/reverse direction. When the application firmware changes this direction control bit, the module will assume the new direction on the next PWM cycle. Just before the end of the current PWM period, the modulated outputs (P1B and P1D) are placed in their inactive state, while the unmodulated outputs (P1A and P1C) are switched to drive in the opposite direction. This occurs in a time interval of (4 TOSC * (Timer2 Prescale Value) before the next PWM period begins. The Timer2 prescaler will be either 1, 4 or 16, depending on the value of the T2CKPS bits (T2CON<1:0>). During the interval from the switch of the unmodulated outputs to the beginning of the next period, the modulated outputs (P1B and P1D) remain inactive. This relationship is shown in Figure 18-8. Note that in Full-Bridge Output mode, the ECCP1 module does not provide any dead-band delay. In general, since only one output is modulated at all times, dead-band delay is not required. However, there is a situation where a dead-band delay might be required. This situation occurs when both of the following conditions are true: 2011 Microchip Technology Inc. 1. 2. The direction of the PWM output changes when the duty cycle of the output is at or near 100%. The turn-off time of the power switch, including the power device and driver circuit, is greater than the turn-on time. Figure 18-9 shows an example where the PWM direction changes from forward to reverse at a near 100% duty cycle. At time, t1, the outputs, P1A and P1D, become inactive, while output, P1C, becomes active. In this example, since the turn-off time of the power devices is longer than the turn-on time, a shoot-through current may flow through power devices, QC and QD (see Figure 18-7), for the duration of `t'. The same phenomenon will occur to power devices, QA and QB, for PWM direction change from reverse to forward. If changing PWM direction at high duty cycle is required for an application, one of the following requirements must be met: 1. 2. Reduce PWM for a PWM period before changing directions. Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. DS39762F-page 209 PIC18F97J60 FAMILY FIGURE 18-8: PWM DIRECTION CHANGE Period(1) SIGNAL Period P1A (Active-High) P1B (Active-High) DC P1C (Active-High) (Note 2) P1D (Active-High) DC Note 1: The direction bit in the ECCP1 Control register (CCP1CON<7>) is written at any time during the PWM cycle. 2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervals of 4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value. The modulated P1B and P1D signals are inactive at this time. FIGURE 18-9: PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period P1A(1) P1B(1) DC P1C(1) P1D(1) DC tON(2) External Switch C(1) tOFF(3) External Switch D(1) Potential Shoot-Through Current(1) t = tOFF - tON(2,3) Note 1: All signals are shown as active-high. 2: tON is the turn-on delay of power switch, QC, and its driver. 3: tOFF is the turn-off delay of power switch, QD, and its driver. DS39762F-page 210 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 18.4.6 PROGRAMMABLE DEAD-BAND DELAY In half-bridge applications, where all power switches are modulated at the PWM frequency at all times, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on and the other turned off), both switches may be on for a short period of time until one switch completely turns off. During this brief interval, a very high current (shoot-through current) may flow through both power switches, shorting the bridge supply. To avoid this potentially destructive shoot-through current from flowing during switching, turning on either of the power switches is normally delayed to allow the other switch to completely turn off. In the Half-Bridge Output mode, a digitally programmable dead-band delay is available to avoid shoot-through current from destroying the bridge power switches. The delay occurs at the signal transition from the non-active state to the active state. See Figure 18-4 for the illustration. The lower seven bits of the ECCP1DEL register (Register 18-2) set the delay period in terms of microcontroller instruction cycles (TCY or 4 TOSC). 18.4.7 ENHANCED PWM AUTO-SHUTDOWN When the ECCP1 is programmed for any of the Enhanced PWM modes, the active output pins may be configured for auto-shutdown. Auto-shutdown immediately places the Enhanced PWM output pins into a defined shutdown state when a shutdown event occurs. REGISTER 18-2: A shutdown event can be caused by either of the two comparator modules or the FLT0 pin (or any combination of these three sources). The comparators may be used to monitor a voltage input proportional to a current being monitored in the bridge circuit. If the voltage exceeds a threshold, the comparator switches state and triggers a shutdown. Alternatively, a low-level digital signal on the FLT0 pin can also trigger a shutdown. The auto-shutdown feature can be disabled by not selecting any auto-shutdown sources. The auto-shutdown sources to be used are selected using the ECCP1AS<2:0> bits (ECCP1AS<6:4>). When a shutdown occurs, the output pins are asynchronously placed in their shutdown states, specified by the PSS1AC<1:0> and PSS1BD<1:0> bits (ECCP1AS<3:0>). Each pin pair (P1A/P1C and P1B/P1D) may be set to drive high, drive low or be tri-stated (not driving). The ECCP1ASE bit (ECCP1AS<7>) is also set to hold the Enhanced PWM outputs in their shutdown states. The ECCP1ASE bit is set by hardware when a shutdown event occurs. If automatic restarts are not enabled, the ECCP1ASE bit is cleared by firmware when the cause of the shutdown clears. If automatic restarts are enabled, the ECC1PASE bit is automatically cleared when the cause of the auto-shutdown has cleared. If the ECCP1ASE bit is set when a PWM period begins, the PWM outputs remain in their shutdown state for that entire PWM period. When the ECCP1ASE bit is cleared, the PWM outputs will return to normal operation at the beginning of the next PWM period. Note: Writing to the ECCP1ASE bit is disabled while a shutdown condition is active. ECCP1DEL: ECCP1 DEAD-BAND DELAY REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 P1RSEN P1DC6 P1DC5 P1DC4 P1DC3 P1DC2 P1DC1 P1DC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 P1RSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCP1ASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, ECCP1ASE must be cleared in software to restart the PWM bit 6-0 P1DC<6:0>: PWM Delay Count bits Delay time, in number of FOSC/4 (4 * TOSC) cycles, between the scheduled time and actual time for a PWM signal to transition to active. 2011 Microchip Technology Inc. DS39762F-page 211 PIC18F97J60 FAMILY REGISTER 18-3: ECCP1AS: ECCP1 AUTO-SHUTDOWN CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0 PSS1AC1 PSS1AC0 PSS1BD1 PSS1BD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 ECCP1ASE: ECCP1 Auto-Shutdown Event Status bit 0 = ECCP1 outputs are operating 1 = A shutdown event has occurred; ECCP1 outputs are in shutdown state bit 6-4 ECCP1AS<2:0>: ECCP1 Auto-Shutdown Source Select bits 000 = Auto-shutdown is disabled 001 = Comparator 1 output 010 = Comparator 2 output 011 = Either Comparator 1 or 2 100 = FLT0 101 = FLT0 or Comparator 1 110 = FLT0 or Comparator 2 111 = FLT0 or Comparator 1 or Comparator 2 bit 3-2 PSS1AC<1:0>: A and C Pins Shutdown State Control bits 00 = Drive A and C pins to `0' 01 = Drive A and C pins to `1' 1x = A and C pins tri-state bit 1-0 PSS1BD<1:0>: B and D Pins Shutdown State Control bits 00 = Drive B and D pins to `0' 01 = Drive B and D pins to `1' 1x = B and D pins tri-state DS39762F-page 212 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 18.4.7.1 Auto-Shutdown and Automatic Restart 18.4.8 The auto-shutdown feature can be configured to allow automatic restarts of the module following a shutdown event. This is enabled by setting the P1RSEN bit of the ECCP1DEL register (ECCP1DEL<7>). In Shutdown mode with P1RSEN = 1 (Figure 18-10), the ECCP1ASE bit will remain set for as long as the cause of the shutdown continues. When the shutdown condition clears, the ECCP1ASE bit is cleared. If P1RSEN = 0 (Figure 18-11), once a shutdown condition occurs, the ECCP1ASE bit will remain set until it is cleared by firmware. Once ECCP1ASE is cleared, the Enhanced PWM will resume at the beginning of the next PWM period. Note: Writing to the ECCP1ASE bit is disabled while a shutdown condition is active. Independent of the P1RSEN bit setting, if the auto-shutdown source is one of the comparators, the shutdown condition is a level. The ECCP1ASE bit cannot be cleared as long as the cause of the shutdown persists. The Auto-Shutdown mode can be forced by writing a `1' to the ECCP1ASE bit. FIGURE 18-10: START-UP CONSIDERATIONS When the ECCP1 module is used in the PWM mode, the application hardware must use the proper external pull-up and/or pull-down resistors on the PWM output pins. When the microcontroller is released from Reset, all of the I/O pins are in the high-impedance state. The external circuits must keep the power switch devices in the OFF state until the microcontroller drives the I/O pins with the proper signal levels, or activates the PWM output(s). The CCP1M<1:0> bits (CCP1CON<1:0>) allow the user to choose whether the PWM output signals are active-high or active-low for each pair of PWM output pins (P1A/P1C and P1B/P1D). The PWM output polarities must be selected before the PWM pins are configured as outputs. Changing the polarity configuration while the PWM pins are configured as outputs is not recommended since it may result in damage to the application circuits. The P1A, P1B, P1C and P1D output latches may not be in the proper states when the PWM module is initialized. Enabling the PWM pins for output at the same time as the ECCP1 module may cause damage to the application circuit. The ECCP1 module must be enabled in the proper Output mode and complete a full PWM cycle before configuring the PWM pins as outputs. The completion of a full PWM cycle is indicated by the TMR2IF bit being set as the second PWM period begins. PWM AUTO-SHUTDOWN (P1RSEN = 1, AUTO-RESTART ENABLED) PWM Period Shutdown Event ECCP1ASE bit PWM Activity Normal PWM Start of PWM Period FIGURE 18-11: Shutdown Shutdown Event Occurs Event Clears PWM Resumes PWM AUTO-SHUTDOWN (P1RSEN = 0, AUTO-RESTART DISABLED) PWM Period Shutdown Event ECCP1ASE bit PWM Activity Normal PWM Start of PWM Period 2011 Microchip Technology Inc. ECCP1ASE Cleared by Shutdown Shutdown Firmware PWM Event Occurs Event Clears Resumes DS39762F-page 213 PIC18F97J60 FAMILY 18.4.9 SETUP FOR PWM OPERATION The following steps should be taken when configuring the ECCP1 module for PWM operation: 1. 2. 3. 4. 5. 6. 7. Configure the PWM pins, P1A and P1B (and P1C and P1D, if used), as inputs by setting the corresponding TRIS bits. Set the PWM period by loading the PR2 (PR4) register. Configure the ECCP1 module for the desired PWM mode and configuration by loading the CCP1CON register with the appropriate values: * Select one of the available output configurations and direction with the P1M<1:0> bits. * Select the polarities of the PWM output signals with the CCP1M<3:0> bits. Set the PWM duty cycle by loading the CCPR1L register and the CCP1CON<5:4> bits. For auto-shutdown: * Disable auto-shutdown; ECCP1ASE = 0 * Configure auto-shutdown source * Wait for Run condition For Half-Bridge Output mode, set the dead-band delay by loading ECCP1DEL<6:0> with the appropriate value. If auto-shutdown operation is required, load the ECCP1AS register: * Select the auto-shutdown sources using the ECCP1AS<2:0> bits. * Select the shutdown states of the PWM output pins using PSS1AC<1:0> and PSS1BD<1:0> bits. * Set the ECCP1ASE bit (ECCP1AS<7>). DS39762F-page 214 8. If auto-restart operation is required, set the P1RSEN bit (ECCP1DEL<7>). 9. Configure and start TMR2 (TMR4): * Clear the TMRx interrupt flag bit by clearing the TMRxIF bit (PIR1<1> for Timer2 or PIR3<3> for Timer4). * Set the TMRx prescale value by loading the TxCKPS bits (T2CON<1:0> for Timer2 or T4CON<1:0> for Timer4). * Enable Timer2 (or Timer4) by setting the TMRxON bit (T2CON<2> for Timer2 or T4CON<2> for Timer4). 10. Enable PWM outputs after a new PWM cycle has started: * Wait until TMR2 (TMR4) overflows (TMRxIF bit is set). * Enable the ECCP1/P1A, P1B, P1C and/or P1D pin outputs by clearing the respective TRIS bits. * Clear the ECCP1ASE bit (ECCP1AS<7>). 18.4.10 EFFECTS OF A RESET Both Power-on Reset and subsequent Resets will force all ports to Input mode and the CCPx/ECCPx registers to their Reset states. This forces the Enhanced CCPx modules to reset to a state compatible with the standard CCPx modules. 2011 Microchip Technology Inc. PIC18F97J60 FAMILY TABLE 18-5: Name INTCON REGISTERS ASSOCIATED WITH ECCPx MODULES AND TIMER1 TO TIMER4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 RCON IPEN -- CM RI TO PD POR BOR 70 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 71 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 71 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 71 PIR2 OSCFIF CMIF ETHIF r BCL1IF -- TMR3IF CCP2IF 71 PIE2 OSCFIE CMIE ETHIE r BCL1IE -- TMR3IE CCP2IE 71 IPR2 OSCFIP CMIP ETHIP r BCL1IP -- TMR3IP CCP2IP 71 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 71 PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 71 IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 71 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 71 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 71 71 (1) TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 TRISE TRISE7(2) TRISE6(2) TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 71 TRISG TRISG7 TRISG6 TRISG5 TRISG4 TRISG3(2) TRISG2 TRISG1 TRISG0(2) 71 TRISH(2) TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 71 TMR1L Timer1 Register Low Byte TMR1H Timer1 Register High Byte T1CON T1RUN 70 T1OSCEN T1SYNC TMR1CS TMR1ON 70 T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 70 RD16 TMR2 70 T1CKPS1 T1CKPS0 Timer2 Register -- T2CON 70 PR2 Timer2 Period Register 70 TMR3L Timer3 Register Low Byte 70 TMR3H Timer3 Register High Byte RD16 T3CON TMR4 T3CCP2 70 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON Timer4 Register -- T4CON 71 72 T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 72 PR4 Timer4 Period Register 72 CCPRxL(3) Capture/Compare/PWM Register x Low Byte 70 CCPRxH(3) Capture/Compare/PWM Register x High Byte 70 CCPxCON(3) ECCPxAS(3) ECCPxDEL(3) Legend: Note 1: 2: 3: PxM1 PxM0 DCxB1 DCxB0 ECCPXASE ECCPXAS2 ECCPXAS1 ECCPXAS0 PxRSEN PxDC6 PxDC5 PxDC4 CCPxM3 CCPxM2 CCPxM1 CCPxM0 70 PSSXAC1 PSSXAC0 PSSXBD1 PSSXBD0 70, 73 PxDC3 PxDC2 PxDC1 PxDC0 73 -- = unimplemented, read as `0', r = reserved. Shaded cells are not used during ECCPx operation. Applicable in 64-pin devices only. Registers and/or specific bits are unimplemented in 64-pin devices. Generic term for all of the identical registers of this name for all Enhanced CCPx modules, where `x' identifies the individual module (ECCP1, ECCP2 or ECCP3). Bit assignments and Reset values for all registers of the same generic name are identical. 2011 Microchip Technology Inc. DS39762F-page 215 PIC18F97J60 FAMILY NOTES: DS39762F-page 216 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 19.0 ETHERNET MODULE All members of the PIC18F97J60 family of devices feature an embedded Ethernet controller module. This is a complete connectivity solution, including full implementations of both Media Access Control (MAC) and Physical Layer (PHY) transceiver modules. Two pulse transformers and a few passive components are all that are required to connect the microcontroller directly to an Ethernet network. The Ethernet module meets all of the IEEE 802.3TM specifications for 10-BaseT connectivity to a twisted-pair network. It incorporates a number of packet filtering schemes to limit incoming packets. It also provides an internal DMA module for fast data throughput and hardware assisted IP checksum calculations. Provisions are also made for two LED outputs to indicate link and network activity. The Ethernet module consists of five major functional blocks: 1. 2. 3. 4. 5. A simple block diagram of the module is shown in Figure 19-1. FIGURE 19-1: The PHY transceiver module that encodes and decodes the analog data that is present on the twisted-pair interface and sends or receives it over the network. The MAC module that implements IEEE 802.3 compliant MAC logic and provides Media Independent Interface Management (MIIM) to control the PHY. An independent, 8-Kbyte RAM buffer for storing packets that have been received and packets that are to be transmitted. An arbiter to control access to the RAM buffer when requests are made from the microcontroller core, DMA, transmit and receive blocks. The register interface that functions as an interpreter of commands and internal status signals between the module and the microcontroller's SFRs. ETHERNET MODULE BLOCK DIAGRAM RX MAC RXBM 8-Kbyte Ethernet RAM Buffer PHY Arbiter ch0 RXF (Filter) MII Interface ch1 ch0 ch2 TX TPOUT+ TPOUT- DMA and IP Checksum TPIN+ TX ch1 RX TXBM Ethernet Buffer Addresses Flow Control Ethernet Data MIIM Interface TPIN- RBIAS Host Interface Ethernet Buffer Pointers EDATA Ethernet Control MIRD/MIWR PHY Register Data PHY Register Addresses MIREGADR Microcontroller SFRs 8 2011 Microchip Technology Inc. LEDA/LEDB Control Microcontroller Data Bus DS39762F-page 217 PIC18F97J60 FAMILY 19.1 19.1.1 Physical Interfaces and External Connections SIGNAL AND POWER INTERFACES PIC18F97J60 family devices all provide a dedicated 4-pin signal interface for the Ethernet module. No other microcontroller or peripheral functions are multiplexed with these pins, so potential device configuration conflicts do not need to be considered. The pins are: * * * * TPIN+: Differential plus twisted-pair input TPIN-: Differential minus twisted-pair input TPOUT+: Differential plus twisted-pair output TPOUT-: Differential minus twisted-pair output No provisions are made for providing or receiving digital Ethernet data from an external Ethernet PHY. In addition to the signal connections, the Ethernet module has its own independent voltage source and ground connections for the PHY module. Separate connections are provided for the receiver (VDDRX and VSSRX), the transmitter (VDDTX and VSSTX) and the transmitter's internal PLL (VDDPLL and VSSPLL). Although the voltage requirements are the same as VDD and VSS for the microcontroller, the pins are not internally connected. For the Ethernet module to operate properly, supply voltage and ground must be connected to these pins. All of the microcontroller's power and ground supply pins should be externally connected to the same power source or ground node, with no inductors or other filter components between the microcontroller and Ethernet module's VDD pins. Besides the independent voltage connections, the PHY module has a separate bias current input pin, RBIAS. A bias current, derived from an external resistor, must be applied to RBIAS for proper transceiver operation. 19.1.2 LED CONFIGURATION The PHY module provides separate outputs to drive the standard Ethernet indicators, LEDA and LEDB. The LED outputs are multiplexed with PORTA pins, RA0 and RA1. Their use as LED outputs is enabled by setting the Configuration bit, ETHLED (Register 25-6, CONFIG3H<2>). When configured as LED outputs, RA0/LEDA and RA1/LEDB have sufficient drive capacity (up to 25 mA) to directly power the LEDs. The pins must always be configured to supply (source) current to the LEDs. Users must also configure the pins as outputs by clearing TRISA<1:0>. DS39762F-page 218 The LEDs can be individually configured to automatically display link status, RX/TX activity, etc. A configurable stretch capability prolongs the LED blink duration for short events, such as a single packet transmit, allowing human perception. The options are controlled by the PHLCON register (Register 19-13). Typical values for blink stretch are listed in Table 19-1. TABLE 19-1: LED BLINK STRETCH LENGTH Stretch Length Typical Stretch (ms) TNSTRCH (normal) 40 TMSTRCH (medium) 70 TLSTRCH (long) 140 19.1.3 OSCILLATOR REQUIREMENTS The Ethernet module is designed to operate at 25 MHz. This is provided by the primary microcontroller clock, either with a 25 MHz crystal connected to the OSC1 and OSC2 pins or an external clock source connected to the OSC1 pin. No provision is made to clock the module from a different source. To maintain the required clock frequency, the microcontroller can operate only from the primary oscillator source (PRI_RUN or PRI_IDLE modes) while the Ethernet module is enabled. Using any other power-managed mode will require that the Ethernet module be disabled. 19.1.3.1 Start-up Timer The Ethernet module contains a start-up timer, independent of the microcontroller's OST, to ensure that the PHY module's PLL has stabilized before operation. Clearing the module enable bit, ETHEN (ECON2<5>), clears the PHYRDY status bit (ESTAT<0>). Setting the ETHEN bit causes this start-up timer to start counting. When the timer expires, after 1 ms, the PHYRDY bit will be automatically set. After enabling the module by setting the ETHEN bit, the application software should always poll PHYRDY to determine when normal Ethernet operation can begin. 2011 Microchip Technology Inc. PIC18F97J60 FAMILY MAGNETICS, TERMINATION AND OTHER EXTERNAL COMPONENTS To complete the Ethernet interface, the Ethernet module requires several standard components to be installed externally. These components should be connected, as shown in Figure 19-2. The internal analog circuitry in the PHY module requires that an external resistor (2.26 k) be attached from RBIAS to ground. The resistor influences the TPOUT+/signal amplitude. It should be placed as close as possible to the chip with no immediately adjacent signal traces to prevent noise capacitively coupling into the pin and affecting the transmit behavior. It is recommended that the resistor be a surface mount type. On the TPIN+/TPIN- and TPOUT+/TPOUT- pins, 1:1 center-tapped pulse transformers, rated for Ethernet operations (10/100 or 10/100/1000), are required. When the Ethernet module is enabled, current is continually sunk through both TPOUT pins. When the PHY is actively transmitting, a differential voltage is created on the Ethernet cable by varying the relative current sunk by TPOUT+ compared to TPOUT-. A common-mode choke on the PHY side of the interface (i.e., between the microcontrollers's TPOUT pins and the Ethernet transformer) is not recommend. If a All power supply pins must be externally connected to the same power source. Similarly, all ground references must be externally connected to the same ground node. Each VDD and VSS pin pair should have a 0.1 F ceramic bypass capacitor placed as close to the pins as possible. Since relatively high currents are necessary to operate the twisted-pair interface, all wires should be kept as short as possible. Reasonable wire widths should be used on power wires to reduce resistive loss. If the differential data lines cannot be kept short, they should be routed in such a way as to have a 100 characteristic impedance. EXTERNAL COMPONENTS REQUIRED FOR ETHERNET OPERATION 1 PIC18FXXJ6X 120(1) C1 OSC1 25 MHz TPOUTTPIN+ C2 120(1) 56pF(1) 5% (3) 1 49.9, 1% 49.9, 1% 3 1:1 CT CMC(2) 4 49.9, 1% OSC2 49.9, 1% 5 0.1 F 1:1 CT TPIN- LEDA 2 0.1 F(1) LEDB RBIAS 2.26 k, 1% 6 7 75(1,4) 56pF(1) 5% (3) RJ-45 CMC(2) 75(1, 4) TPOUT+ 3.3V 75(1,4) FIGURE 19-2: common-mode choke is used to reduce EMI emissions, it should be placed between the Ethernet transformer and Pins 1 and 2, of the RJ-45 connector. Many Ethernet transformer modules include common-mode chokes inside the same device package. The transformers should have at least the isolation rating specified in Table 28-28 to protect against static voltages and meet IEEE 802.3 isolation requirements (see Section 28.5 "Ethernet Specifications and Requirements" for specific transformer requirements). Both transmit and receive interfaces additionally require two resistors and a capacitor to properly terminate the transmission line, minimizing signal reflections. 75(1,4) 19.1.4 8 1 nF, 2 kV(1) Note 1: These components are installed for EMI reduction purposes. See Section 19.1.5 for more information. 2: Recommended insertion point for Common-Mode Chokes (CMCs) if required for EMI reduction. 3: See Section 3.3 "Crystal Oscillator/Ceramic Resonators (HS Modes)" for recommended values. 4: Power over Ethernet applications require capacitors in series with these resistors. 2011 Microchip Technology Inc. DS39762F-page 219 PIC18F97J60 FAMILY 19.1.5 EMI EMISSIONS CONSIDERATIONS Most locales have limits on unintentional EMI or EMC emissions that govern the amount of electromagnetic energy that may be radiated into the environment across a range of test frequencies. Ethernet applications normally do not include intentional radio frequency emissions sources. They may experience occasional regulatory failures though, due to the relative ease at which high-frequency noise may radiate out of a long attached Ethernet cable. Long cables can act as unintentional antennas. The PIC18F97J60 family Ethernet module transmit engine internally operates by stepping the 25 MHz base Ethernet clock up to a high frequency via a PLL embedded in the PHY module. Then, the high frequency is used to turn on/turn off small current sinks on the TPOUT+ and TPOUT- pins. This current-mode drive technique allows the PHY to generate an Ethernet TX waveform that resembles an analog signal, with most spectral energy at or below 20 MHz. However, while low in amplitude, the high frequency used to synthesize the waveform can, in some application circuits, radiate out of the circuit and result in regulatory emissions compliance failures. Such failures caused by the Ethernet module will normally be exhibited as excess emissions at 200 MHz and occasionally 400 MHz. To minimize the chance of failure, the use of the LC low-pass filter is recommended on the TPOUT+ and TPOUT- pins, as shown Figure 19-2. In this circuit, 120 ohm ferrite beads are used along with 56 pF5% capacitors to form a low-pass filter with a -3dB breakpoint that is above 20 MHz, but below 200 MHz. 10Base-T Ethernet signaling requires only about 20 MHz of spectral bandwidth, so minimal distortion is done to the Ethernet signal by using these filters. However, noise at 200 MHz or 400 MHz, generated by the PHY, is reduced by several decibels before having a chance to radiate out of the application and cause a regulatory failure. In this circuit, the ferrite beads must have a saturation current rating of at least 100 mA. If EMI emissions regulations are stringent in your locale, additional care should be taken when selecting the Ethernet magnetics to further minimize unintentionally radiating common-mode signals out of the Ethernet cable. Ethernet magnetics with a high differential to common-mode rejection ratio should be used. The differential to common-mode rejection parameter is normally expressed in magnetics manufacturers' data sheets, in units of negative decibels across a test frequency range. In the absence of test data indicating otherwise, a more negative specification at higher frequencies is recommended for the PIC18F97J60 family Ethernet module. For example, a device rated for -40 dB @ 100 MHz is likely preferable to -33 dB @ 100 MHz, even if the performance at 30 MHz is similar or better on the -33 dB @ 100MHz magnetics. DS39762F-page 220 Often, the use of "5-core" magnetics, or magnetics involving a center tapped inductor or auto-transformer on the TX path, is also desirable for EMI emissions reasons. 19.1.6 AUTOMATIC RX POLARITY DETECTION AND CORRECTION 10Base-T Ethernet signaling is performed on the Ethernet cable as a differentially encoded Manchester data stream. This signaling is polarized; therefore, it is required that the RX+ Ethernet signal on the Ethernet cable reach the TPIN+ pin, and the RX- Ethernet signal reach the TPIN- pin. Connecting RX+ to TPIN- and RXto TPIN+ (by way of Ethernet isolation transformers) will cause the PIC18F97J60 family Ethernet module to successfully link with the remote partner. However, all receive data will be corrupted by the polarity mismatch and will be internally discarded by the PHY as if it were noise on the wire. Higher speed 100Base-TX and 1000Base-T Ethernet technologies uses different signaling schemes. They use Multi-Level Transition 3 (MLT3) and Five-Level Pulse Amplitude Modulation (PAM5) encoding on the wire, respectively. These encodings are non-polarized. Therefore, swapping the differential wires will have no impact on the Ethernet controller's ability to communicate with the remote node. A limited number of modern 3rd party 10/100 and 10/100/1000 rated Ethernet devices (switches, routers and end devices) connect their TX+ and TX- signals to the incorrect pins on their RJ-45 Ethernet jack. These devices are not IEEE Standard 802.3 compliant. However, because 100Base-TX and 1000Base-T communications continue to work without correct polarization, some 3rd party vendors mistakenly release their products to production without catching these polarization errors. Due to these circumstances, current revisions of the Ethernet controller in the PIC18F97J60 family of devices are not compatible with a limited number of 3rd party Ethernet devices. The PIC18FXXJXX devices will link up with the partner and the PHY RX activity LED (if enabled) will blink whenever a packet is transmitted to the PIC18FXXJXX device. However, no packets will be successfully received and written in the Ethernet SRAM buffer when the polarity is incorrect. To eliminate this problem, and obtain maximum interoperability with 3rd party devices, it is possible to externally add an RX polarity swapping circuit to PIC18F97J60 family applications. Figure 19-3 demonstrates the use of bus switches to facilitate the swapping of the RX signals. In Figure 19-3, a general purpose output pin is used to select the polarity of the RX signals. When the select line is held low, the A ports of the switches will connect with the B0 ports, leaving the B1 ports disconnected. This will allow the TPIN+ pin to be connected to Pin 3 of the RJ-45 jack while TPIN- is connected to Pin 6. These connections accommodate the IEEE Standard 802.3 specified polarity. 2011 Microchip Technology Inc. PIC18F97J60 FAMILY When the select line is raised high, the A ports of the switches will connect with the B1 ports, leaving the B0 ports disconnected. This will swap the RX polarity and route the TPIN+ pin to the signal on RJ-45 Jack Pin 6. TPIN- will connect to RJ-45 Pin 3. This swapped polarity can correct an incorrectly wired signal generated at the remote link partner or in the intermediate cabling. immediate response. This method requires the use of a protocol that results in a response packet from the network. In many networks, Dynamic Host Configuration Protocol (DHCP) discovery packets may be used to resolve the correct TPIN polarity quickly. Care should be taken when selecting the bus switches to ensure that they are capable of passing the Ethernet signals without distortion. The TPIN pins will weakly bias the RX common-mode voltage to approximately VDD/2, and the Ethernet RX waveform will add up to 1.4V onto this common-mode voltage. Therefore, the switches must be capable of passing signals of at least 3.05V. In the MCU, software must be written to toggle the select line state to the correct level based on the connected link partner. This is best achieved by periodically toggling the select line at low frequency (<5 Hz), while watching for a successful packet reception event. When the correct polarity is found, the select line should stop toggling and remain static until the Ethernet link is removed. Additionally, the bus switches should have low capacitance to minimize the signal loss and impedance discontinuity that may affect the RX signal. The switches, rated -3dB bandwidth, must be well above 20 MHz. In some cases, rather than periodically toggling the polarity select at a low frequency to receive a packet, faster determination of the correct polarity may be determined by transmitting a packet and looking for an FIGURE 19-3: RX POLARITY CORRECTION CIRCUIT (TX CONNECTIONS NOT SHOWN) PIC18FXXJ6X GPIO RJ-45 and Magnetics 1 2 3 TPIN+ TX RX 0.1 F 4x 75 ohm 1 2 3 6 5 4 NC7SB3157 2011 Microchip Technology Inc. +3.3V NC7SB3157 49.9 49.9 TPIN- 6 5 4 +3.3V 1000 pF 2kV 100K DS39762F-page 221 PIC18F97J60 FAMILY 19.2 Ethernet Buffer and Register Spaces The Ethernet module uses three independent memory spaces for its operations: * An Ethernet RAM buffer which stores packet data as it is received and being prepared for transmission. * A set of 8-bit Special Function Registers (SFRs), used to control the module, and pass data back and forth between the module and microcontroller core. * A separate set of 16-bit PHY registers used specifically for PHY control and status reporting. FIGURE 19-4: The Ethernet buffer and PHY Control registers are contained entirely within the Ethernet module and cannot be accessed directly by the microcontroller. Data is transferred between the Ethernet and microcontroller by using buffer and pointer registers mapped in the microcontroller's SFR space. The relationships between the SFRs and the Ethernet module's memory spaces are shown in Figure 19-4. RELATIONSHIP BETWEEN MICROCONTROLLER AND ETHERNET MEMORY SPACES Microcontroller SFRs Ethernet Module Ethernet Buffer EDATA ERDPT(H:L) EWRPT(H:L) ETXST(H:L) ETXND(H:L) ERXST(H:L) ERXND(H:L) ERXRDPT(H:L) ERXWRPT(H:L) 1FFFh Buffer Address PHY Registers PHY Register Data (In/Out) MIRD(H:L) MIWR(H:L) MIREGADR Note: 0000h Ethernet Data 00h 1Fh PHY Register Address Microcontroller SFRs are not shown in the order of their placement in the data memory space. Memory areas are not shown to scale. DS39762F-page 222 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 19.2.1 ETHERNET BUFFER AND BUFFER POINTER REGISTERS The Ethernet buffer contains the transmit and receive memory used by the Ethernet controller. The entire buffer is 8 Kbytes, divided into separate receive and transmit buffer spaces. The sizes and locations of transmit and receive memory are fully definable using the pointers in the Ethernet SFR space. The organization of the memory space and the relationships of the pointers are shown in Figure 19-5. The buffer is always accessible through the EDATA and Ethernet Pointer SFRs, regardless of whether or not the Ethernet module is enabled. This makes the buffer potentially useful for applications requiring large amounts of RAM and that do not require Ethernet communication. In these instances, disabling the Ethernet module reduces overall power usage but does not prevent buffer access. 19.2.1.1 Reading and Writing to the Buffer The Ethernet buffer contents are accessed through the EDATA register, which acts as a window from the microcontroller data bus into the buffer. The location of that window is determined by either the ERDPT or EWRPT Pointers, depending on the operation being performed. For example, writing to EDATA causes a write to the Ethernet buffer at the address currently indicated by the EWRPT register pair. Similarly, moving the contents of EDATA to another register actually moves the buffer contents at the address indicated by the ERDPT Pointer. When the AUTOINC bit (ECON2<7>) is set, the associated Read or Write Pointer increments by one address following each read or write operation. This eliminates the need to constantly update a pointer after each read or write, simplifying multiple sequential operations. By default, the AUTOINC bit is set. While sequentially reading from the receive buffer, a wrapping condition will occur at the end of the receive buffer. A read of EDATA, from the address programmed 2011 Microchip Technology Inc. into the ERXND Pointers, will cause the ERDPT registers to be incremented to the value contained in the ERXST Pointers. Writing to the buffer, on the other hand, does not result in automatic wrapping. By design, the Ethernet memory buffer is unable to support a set of operations where EDATA is used as both an operand and a data destination. Failure to observe these restrictions will result in a corrupted read or write. Also, due to the read-modify-write architecture of the processor core, single-cycle instructions, which write to the EDATA register, will have a side effect of automatically incrementing the ERDPT registers when AUTOINC is set. Using double-cycle MOVFF, MOVSF and MOVSS instructions to write to EDATA will not affect the Read Pointer. See the following note for examples. Note: Any single instruction that performs both a read and write to the EDATA SFR register will result in a corrupted operation. Unsupported examples: INCF XORWF MOVFF MOVFF EDATA, EDATA, EDATA, INDF0, F F EDATA EDATA; (FSR0 = F61h) Instructions that only perform one read or one write are permitted. Supported examples: INCF MOVF MOVFF EDATA, W EDATA, W INDF0, EDATA; (FSR0 != F61h) Single-cycle, write-only instructions, while valid, will have a side effect of also incrementing the ERDPT registers when AUTOINC is enabled. Examples incrementing both ERDPT and EWRPT: CLRF SETF MOVWF EDATA EDATA EDATA DS39762F-page 223 PIC18F97J60 FAMILY FIGURE 19-5: ETHERNET BUFFER ORGANIZATION Transmit Buffer Start (ETXSTH:ETXSTL) Buffer Write Pointer (EWRPTH:EWRPTL) Transmit Buffer End (ETXNDH:ETXNDL) Receive Buffer Start (ERXSTH:ERXSTL) 0000h Write Buffer Data (data AAh moved to EDATA) AAh Transmit Buffer Receive Buffer (Circular FIFO) Buffer Read Pointer (ERDPTH:ERDPTL) Receive Buffer End (ERXNDH:ERXNDL) DS39762F-page 224 Read Buffer Data (data 55h moved out of EDATA) 55h 1FFFh 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 19.2.1.2 Receive Buffer The receive buffer constitutes a circular FIFO buffer managed by hardware. The register pairs, ERXSTH:ERXSTL and ERXNDH:ERXNDL, serve as pointers to define the buffer's size and location within the memory. The byte pointed to by the ERXST pair and the byte pointed to by the ERXND pair are both included in the FIFO buffer. As bytes of data are received from the Ethernet interface, they are written into the receive buffer sequentially. However, after the memory pointed to by the ERXND Pointers is written to, the hardware will automatically write the next byte of received data to the memory pointed to by the ERXST pair. As a result, the receive hardware will never write outside the boundaries of the FIFO. The user may program the ERXST and ERXND Pointers while the receive logic is disabled. The pointers must not be modified while the receive logic is enabled (ERXEN (ECON1<2>) is set). The buffer hardware uses an Internal Pointer (not mapped to any user-accessible registers) to determine where unvalidated incoming data is to be written. When a packet has been completely received and validated, FIGURE 19-6: the read-only ERXWRPTH:ERXWRPTL registers are updated with the Internal Pointer's value. Thus, the ERXWRPT registers define the general area in the receive buffer where data is currently being written. This makes it useful for determining how much free space is available within the FIFO. The ERXRDPT registers define a location within the FIFO where the receive hardware is forbidden to write to. In normal operation, the receive hardware will write data up to, but not including, the memory pointed to by the ERXRDPT registers. If the FIFO fills up with data and new data continues to arrive, the hardware will not overwrite the previously received data. Instead, the incoming data will be thrown away and the old data will be preserved. In order to continuously receive new data, the application must periodically advance this pointer whenever it finishes processing some, or all, of the old received data. An example of how the Receive Buffer Pointers and packet data are related in the circular buffer scheme is shown in Figure 19-6. Note that while four packets are shown in this example, the actual number of packets may be greater or lesser. CIRCULAR FIFO BUFFER AND THE RELATIONSHIPS OF THE POINTERS ERXST ERXRDPT: Sets boundary that Internal Write Pointer cannot advance beyond. Prevents Internal Write Pointer from moving into Packet 1's data space. ERDPT: Data being read out to application. ERXND PB Internal Write Hardware Pointer points to the buffer location being written (packet data is still being received). Unused Buffer (may contain old data) Packet 1 (being processed by application) PB Packet 4 (currently being received) Packet 2 ERXWRPT: Shows the end of the last complete received packet. Packet 3 PB PB Direction of reading and writing data (lower to higher buffer addresses). 2011 Microchip Technology Inc. PB: Packet Boundary, as defined by the Next Packet Pointers that precede each packet. DS39762F-page 225 PIC18F97J60 FAMILY 19.2.1.3 Transmit Buffer Any space within the 8-Kbyte memory which is not programmed as part of the receive FIFO buffer is considered to be the transmit buffer. The responsibility of managing where packets are located in the transmit buffer belongs to the application. Whenever the application decides to transmit a packet, the ETXST and ETXND Pointers are programmed with addresses specifying where, within the transmit buffer, the particular packet to transmit is located. The hardware does not check that the start and end addresses do not overlap with the receive buffer. To prevent buffer corruption, the firmware must not transmit a packet while the ETXST and ETXND Pointers are overlapping the receive buffer, or while the ETXND Pointers are too close to the receive buffer. See Section 19.5.2 "Transmitting Packets" for more information. 19.2.1.4 Buffer Arbiter and Access Arbitration The Ethernet buffer is clocked at one-half of the microcontroller clock rate. Varying amounts of memory access bandwidth are available depending on the clock speed. The total bandwidth available, in bytes per second, is equal to twice the instruction rate (2 * FCY or FOSC/2). For example, at a system clock speed of 41.667 MHz, the total available memory bandwidth that is available is 20.834 Mbyte/s. At an Ethernet signaling rate of 10 Mbit/s, the Ethernet RX engine requires 1.25 Mbyte/s of buffer memory bandwidth to operate without causing an overrun. If Full-Duplex mode is used, an additional 1.25 Mbyte/s is required to allow for simultaneous RX and TX activity. Because of the finite available memory bandwidth, a three-channel arbiter is used to allocate bandwidth between the RX engine, the TX and DMA engines, and the microcontroller's CPU (i.e., the application access- TABLE 19-2: ing EDATA). The arbiter gives the EDATA register accesses first priority, while all remaining bandwidth is shared between the RX and TX/DMA blocks. With arbitration, bandwidth limitations require that some care be taken in balancing the needs of the module's hardware with that of the application. Accessing the EDATA register too often may result in the RX or TX blocks causing a buffer overrun or underrun, respectively. If such a memory access failure occurs, the BUFER bit (ESTAT<6>), and either the TXERIF or RXERIF interrupt flag, becomes set, and a TX or RX interrupt occurs (if enabled). In either case, the current packet will be lost or aborted. To eliminate the risk of lost packets, run the microcontroller core at higher speeds. Following the arbitration restrictions, shown in Table 19-2, will prevent memory access failures from occurring. Also, avoid using segments of application code which perform back-to-back accesses of the EDATA register. Instead, insert one or more instructions (including NOP instructions) between each read or write to EDATA. 19.2.1.5 DMA Access to the Buffer The integrated DMA controller must read from the buffer when calculating a checksum, and it must read and write to the buffer when copying memory. The DMA follows the same wrapping rules as previously described for the receive buffer. While it sequentially reads, it will be subject to a wrapping condition at the end of the receive buffer. All writes it does will not be subject to any wrapping conditions. See Section 19.9 "Direct Memory Access Controller" for more information. BUFFER ARBITRATION RESTRICTIONS VS. CLOCK SPEED FOSC (MHz) FCY (MHz) 41.667 Available Bandwidth (Mbyte/s) Application Restrictions to Prevent Underrun/Overrun Total After RX After TX 10.42 20.83 19.58 18.33 31.250 7.81 15.63 14.38 13.13 Access EDATA no more than once every 2 TCY 25.000 6.25 12.50 11.25 10.00 Access EDATA no more than once every 2 TCY 20.833 5.21 10.42 9.17 7.92 Access EDATA no more than once every 2 TCY 13.889 3.47 6.94 5.69 4.44 Access EDATA no more than once every 2 TCY Access EDATA no more than once every 2 TCY 12.500 3.13 6.25 5.00 3.75 Access EDATA no more than once every 2 TCY 8.333 2.08 4.17 2.92 1.67 Access EDATA no more than once every 3 TCY 6.250 1.56 3.13 1.88 0.63 Access EDATA no more than once every 5 TCY 4.167 1.04 2.08 0.83 <0 Do not use DMA, do not use full duplex, access EDATA no more than once every 3 TCY 2.778 0.69 1.39 0.14 <0 Do not use DMA, do not use full duplex, access EDATA no more than once every 10 TCY DS39762F-page 226 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 19.2.2 SFRs AND THE ETHERNET MODULE Like other peripherals, direct control of the Ethernet module is accomplished through a set of SFRs. Because of their large number, the majority of these registers is located in the bottom half of Bank 14 of the microcontroller's data memory space. Five key SFRs for the Ethernet module are located in the microcontroller's regular SFR area in Bank 15, where fast access is possible. They are: * * * * ECON1 EDATA EIR The Ethernet Buffer Read Pointer Pair (ERDPTH and ERDPTL) ECON1 is described along with other Ethernet control registers in the following section. EDATA and ERDPTH:ERDPTL are the Ethernet Data Buffer registers and its pointers during read operations (see Section 19.2.1 "Ethernet Buffer and Buffer Pointer Registers"). EIR is part of the Ethernet interrupt structure and is described in Section 19.3 "Ethernet Interrupts". REGISTER 19-1: Many of the Ethernet SFRs in Bank 14 serve as pointer registers to indicate addresses within the dedicated Ethernet buffer for storage and retrieval of packet data. Others store information for packet pattern masks or checksum operations. Several are used for controlling overall module operations, as well as specific MAC and PHY functions. 19.2.3 ETHERNET CONTROL REGISTERS The ECON1 register (Register 19-1) is used to control the main functions of the module. Receive enable, transmit request and DMA control bits are all located here. The ECON2 register (Register 19-2) is used to control other top level functions of the module. The ESTAT register (Register 19-3) is used to report the high-level status of the module and Ethernet communications. The Ethernet SFRs with the `E' prefix are always accessible, regardless of whether or not the module is enabled. ECON1: ETHERNET CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 TXRST RXRST DMAST CSUMEN TXRTS RXEN -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 TXRST: Transmit Logic Reset bit 1 = Transmit logic is held in Reset 0 = Normal operation bit 6 RXRST: Receive Logic Reset bit 1 = Receive logic is held in Reset 0 = Normal operation bit 5 DMAST: DMA Start and Busy Status bit 1 = DMA copy or checksum operation is in progress (set by software, cleared by hardware or software) 0 = DMA hardware is Idle bit 4 CSUMEN: DMA Checksum Enable bit 1 = DMA hardware calculates checksums 0 = DMA hardware copies buffer memory bit 3 TXRTS: Transmit Request to Send bit 1 = The transmit logic is attempting to transmit a packet (set by software, cleared by hardware or software) 0 = The transmit logic is Idle bit 2 RXEN: Receive Enable bit 1 = Packets which pass the current filter configuration will be written into the receive buffer 0 = All packets received will be discarded by hardware bit 1-0 Unimplemented: Read as `0' 2011 Microchip Technology Inc. DS39762F-page 227 PIC18F97J60 FAMILY REGISTER 19-2: ECON2: ETHERNET CONTROL REGISTER 2 R/W-1 R/W-0(1) R/W-0 U-0 U-0 U-0 U-0 U-0 AUTOINC PKTDEC ETHEN -- -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 AUTOINC: Automatic Buffer Pointer Increment Enable bit 1 = Automatically increment ERDPT or EWRPT registers on reading from, or writing to, EDATA 0 = Do not automatically change ERDPT and EWRPT registers after EDATA is accessed bit 6 PKTDEC: Packet Decrement bit(1) 1 = Decrement the EPKTCNT register by one 0 = Leave EPKTCNT unchanged bit 5 ETHEN: Ethernet Module Enable bit 1 = Ethernet module is enabled 0 = Ethernet module is disabled bit 4-0 Unimplemented: Read as `0' Note 1: This bit is automatically cleared once it is set. REGISTER 19-3: ESTAT: ETHERNET STATUS REGISTER U-0 R/C-0 U-0 R/C-0 U-0 R-0 R/C-0 R-0 -- BUFER -- r -- RXBUSY TXABRT PHYRDY bit 7 bit 0 Legend: r = Reserved bit R = Readable bit C = Clearable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as `0' bit 6 BUFER: Ethernet Buffer Error Status bit 1 = An Ethernet read or write has generated a buffer error (overrun or underrun) 0 = No buffer error has occurred bit 5 Unimplemented: Read as `0' bit 4 Reserved: Write as `0' bit 3 Unimplemented: Read as `0' bit 2 RXBUSY: Receive Busy bit 1 = Receive logic is receiving a data packet 0 = Receive logic is Idle bit 1 TXABRT: Transmit Abort Error bit 1 = The transmit request was aborted 0 = No transmit abort error bit 0 PHYRDY: Ethernet PHY Clock Ready bit 1 = Ethernet PHY start-up timer has expired; PHY is ready 0 = Ethernet PHY start-up timer is still counting; PHY is not ready DS39762F-page 228 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 19.2.4 MAC AND MII REGISTERS Note 1: Do not access the MAC and MII SFRs unless the Ethernet module is enabled (ETHEN = 1). These SFRs are used to control the operations of the MAC, and through the MIIM, the PHY. The MAC and MII registers occupy data addresses, E80h-E85h, E8Ah and EA0h through EB9h. Although MAC and MII registers appear in the general memory map of the microcontroller, these registers are embedded inside the MAC module. Host interface logic translates the microcontroller data/address bus data to be able to access these registers. The host interface logic imposes restrictions on how firmware is able to access the MAC and MII SFRs. See the following notes. REGISTER 19-4: 2: Back-to-back accesses of MAC or MII registers are not supported. Between any instruction which addresses a MAC or MII register, at least one NOP or other instruction must be executed. The three MACON registers control specific MAC operations and packet configuration operations. They are shown in Register 19-4 through Register 19-6. The MII registers are used to control the MIIM interface and serve as the communication channel with the PHY registers. They are shown in Register 19-7 and Register 19-8. MACON1: MAC CONTROL REGISTER 1 U-0 U-0 U-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- -- r TXPAUS RXPAUS PASSALL MARXEN bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as `0' bit 4 Reserved: Do not use bit 3 TXPAUS: Pause Control Frame Transmission Enable bit 1 = Allow the MAC to transmit pause control frames (needed for flow control in full duplex) 0 = Disallow pause frame transmissions bit 2 RXPAUS: Pause Control Frame Reception Enable bit 1 = Inhibit transmissions when pause control frames are received (normal operation) 0 = Ignore pause control frames which are received bit 1 PASSALL: Pass All Received Frames Enable bit 1 = Control frames received by the MAC will be written into the receive buffer if not filtered out 0 = Control frames will be discarded after being processed by the MAC (normal operation) bit 0 MARXEN: MAC Receive Enable bit 1 = Enable packets to be received by the MAC 0 = Disable packet reception 2011 Microchip Technology Inc. DS39762F-page 229 PIC18F97J60 FAMILY REGISTER 19-5: MACON3: MAC CONTROL REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PADCFG2 PADCFG1 PADCFG0 TXCRCEN PHDREN HFRMEN FRMLNEN FULDPX bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-5 PADCFG<2:0>: Automatic Pad and CRC Configuration bits 111 = All short frames are zero-padded to 64 bytes and a valid CRC will then be appended 110 = No automatic padding of short frames 101 = MAC automatically detects VLAN protocol frames which have a 8100h type field and automatically pad to 64 bytes. If the frame is not a VLAN frame, it is padded to 60 bytes. After padding, a valid CRC is appended. 100 = No automatic padding of short frames 011 = All short frames are zero-padded to 64 bytes and a valid CRC is appended 010 = No automatic padding of short frames 001 = All short frames are zero-padded to 60 bytes and a valid CRC is appended 000 = No automatic padding of short frames bit 4 TXCRCEN: Transmit CRC Enable bit 1 = MAC appends a valid CRC to all frames transmitted, regardless of the PADCFG<2:0> bits. TXCRCEN must be set if the PADCFG bits specify that a valid CRC is appended. 0 = MAC does not append a CRC. The last 4 bytes are checked and if it is an invalid CRC, it is reported in the transmit status vector. bit 3 PHDREN: Proprietary Header Enable bit 1 = Frames presented to the MAC contain a 4-byte proprietary header which is not used when calculating the CRC 0 = No proprietary header is present; the CRC covers all data (normal operation) bit 2 HFRMEN: Huge Frame Enable bit 1 = Jumbo frames and frames of any illegal size are allowed to be transmitted and received 0 = Frames bigger than MAMXFL are truncated when transmitted or received bit 1 FRMLNEN: Frame Length Checking Enable bit 1 = The type/length field of transmitted and received frames is checked. If it represents a length, the frame size is compared and mismatches are reported in the transmit/receive status vector. 0 = Frame lengths are not compared with the type/length field bit 0 FULDPX: MAC Full-Duplex Enable bit 1 = MAC operates in Full-Duplex mode; application must also set PDPXMD (PHCON1<8>) 0 = MAC operates in Half-Duplex mode; application must also clear PDPXMD DS39762F-page 230 2011 Microchip Technology Inc. PIC18F97J60 FAMILY REGISTER 19-6: MACON4: MAC CONTROL REGISTER 4 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R-0 R-0 -- DEFER r r -- -- r r bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as `0' bit 6 DEFER: Defer Transmission Enable bit (applies to half duplex only) 1 = When the medium is occupied, the MAC waits indefinitely for it to become free when attempting to transmit (use this setting for IEE 802.3 compliance) 0 = When the medium is occupied, the MAC aborts the transmission after the excessive deferral limit is reached bit 5-4 Reserved: Maintain as `0' bit 3-2 Unimplemented: Read as `0' bit 1-0 Reserved: Maintain as `0' REGISTER 19-7: MICMD: MII COMMAND REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 -- -- -- -- -- -- MIISCAN MIIRD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-2 Unimplemented: Read as `0' bit 1 MIISCAN: MII Scan Enable bit 1 = PHY register at MIREGADR is continuously read and the data is placed in the MIRD registers 0 = No MII Management scan operation is in progress bit 0 MIIRD: MII Read Enable bit 1 = PHY register at MIREGADR is read once and the data is placed in the MIRD registers 0 = No MII Management read operation is in progress 2011 Microchip Technology Inc. DS39762F-page 231 PIC18F97J60 FAMILY REGISTER 19-8: MISTAT: MII STATUS REGISTER U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 -- -- -- -- r NVALID SCAN BUSY bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Read as `0' bit 3 Reserved: Do not use bit 2 NVALID: MII Management Read Data Not Valid bit 1 = The contents of the MIRD registers are not valid yet 0 = The MII Management read cycle has completed and the MIRD registers have been updated bit 1 SCAN: MII Management Scan Operation bit 1 = MII Management scan operation is in progress 0 = No MII Management scan operation is in progress bit 0 BUSY: MII Management Busy bit 1 = A PHY register is currently being read, or written to. For internal synchronization, the hardware will delay setting this bit for two TCY following a firmware command, which sets the MIISCAN or MIIRD bits, or writes to the MIWRH register. 0 = The MII Management interface is Idle 19.2.5 PHY REGISTERS The PHY registers provide configuration and control of the PHY module, as well as status information about its operation. All PHY registers are 16 bits in width. PHY registers are accessed with a 5-bit address, for a total of 32 possible registers; of these, only 7 addresses are implemented. The implemented registers are listed in Table 19-3. The main PHY Control registers are described in Register 19-9 through Register 19-13. The other PHY Control and Status registers are described later in this chapter. Unimplemented registers must never be written to. Reading these locations will return indeterminate data. Within implemented registers, all reserved bit locations that are listed as writable must always be written with the value provided in the register description. When read, these reserved bits can be ignored. Thy PHY registers are only accessible through the MII Management interface. They must not be read or written to until the PHY start-up timer has expired and the PHYRDY bit (ESTAT<0>) is set. 19.2.5.1 The PHSTAT1 register (Register 19-10) contains the LLSTAT bit. The bit clears and latches low if the physical layer link has gone down since the last read of the register. The application can periodically poll LLSTAT to determine exactly when the link fails. It may be particularly useful if the link change interrupt is not used. The PHSTAT2 register (Register 19-12) contains status bits which report if the PHY module is linked to the network and whether or not it is transmitting or receiving. 19.2.5.2 Accessing PHY Registers As already mentioned, the PHY registers exist in a different memory space and are not directly accessible by the microcontroller. Instead, they are addressed through a special set of MII registers in the Ethernet SFR bank that implement a Media Independent Interface Management (MIIM). Access is similar to that of the Ethernet buffer, but uses separate read and write buffers (MIRDH:MIRDL and MIWRH:MIWRL) and a 5-bit address register (MIREGADR). In addition, the MICMD and MISTAT registers are used to control read and write operations. PHSTAT Registers The PHSTAT1 and PHSTAT2 registers contain read-only bits that show the current status of the PHY module's operations, particularly the conditions of the communications link to the rest of the network. DS39762F-page 232 2011 Microchip Technology Inc. PIC18F97J60 FAMILY To read from a PHY register: 1. 2. 3. 4. 5. Write the address of the PHY register to be read into the MIREGADR register. Set the MIIRD bit (MICMD<0>). The read operation begins and the BUSY bit (MISTAT<0>) is set after two TCY. Wait 10.24 s, then poll the BUSY bit to be certain that the operation is complete. When the MAC has obtained the register contents, the BUSY bit will clear itself. While BUSY is set, the user application should not start any MIISCAN operations or write to the MIWRH register. Clear the MIIRD bit. Read the entire 16 bits of the PHY register from the MIRDL and MIRDH registers. To write to a PHY register: 1. 2. 3. Write the address of the PHY register to be written into the MIREGADR register. Write the lower 8 bits of data to write into the MIWRL register. Write the upper 8 bits of data to write into the MIWRH register. Writing to this register automatically begins the MII transaction, so it must be written to after MIWRL. The BUSY bit is set automatically after two TCY. The PHY register is written after the MII operation completes, which takes 10.24 s. When the write operation has completed, the BUSY bit will clear itself. The application should not start any MII scan or read operations while busy. When a PHY register is written to, the entire 16 bits are written at once; selective bit and/or byte writes are not implemented. If it is necessary to reprogram only select bits in the register, the controller must first read the PHY register, modify the resulting data and then write the data back to the PHY register. 2011 Microchip Technology Inc. The MAC can also be configured to perform automatic back-to-back read operations on a PHY register. To perform this scan operation: 1. 2. Write the address of the PHY register to be scanned into the MIREGADR register. Set the MIISCAN bit (MICMD<1>). The scan operation begins and the BUSY bit is set after two TCY. After MIISCAN is set, the NVALID (MISTAT<2>), SCAN and BUSY bits are also set. The first read operation will complete after 10.24 s. Subsequent reads will be done and the MIRDL and MIRDH registers will be continuously updated automatically at the same interval until the operation is cancelled. The NVALID bit may be polled to determine when the first read operation is complete. There is no status information which can be used to determine when the MIRD registers are updated. Since only one MII register can be read at a time, it must not be assumed that the values of MIRDL and MIRDH were read from the PHY at exactly the same time during a scan operation. MIISCAN should remain set as long as the scan operation is desired. The BUSY and SCAN bits are automatically cleared after MIISCAN is set to `0' and the last read sequence is completed. MIREGADR should not be updated while MIISCAN is set. Starting new PHY operations, such as a read operation or writing to the MIWRH register, must not be done while a scan is underway. The operation can be cancelled by clearing the MIISCAN bit and then polling the BUSY bit. New operations may be started after the BUSY bit is cleared. DS39762F-page 233 Addr PIC18F97J60 FAMILY PHY REGISTER SUMMARY Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values 00h PHCON1 r r -- -- r r -- PDPXMD r -- -- -- -- -- -- -- 00-- 00-0 0--- ---- 01h PHSTAT1 -- -- -- r r -- -- -- -- -- -- -- -- LLSTAT r -- ---1 1--- ---- -00- 10h PHCON2 -- FRCLNK r r r r r HDLDIS r r r RXAPDIS r r r r -000 0000 0000 0000 11h PHSTAT2 -- -- LSTAT r -- -- -- r -- -- -- -- -- --00 00x- --0- ---- 12h PHIE r r r r r r r r r r r PLNKIE r r PGEIE r xxxx xxxx xx00 xx00 13h PHIR r r r r r r r r r r r PLNKIF r PGIF r r xxxx xxxx xx00 00x0 14h PHLCON r r r r LFRQ1 LFRQ0 STRCH r 0011 0100 0010 001x TXSTAT RXSTAT COLSTAT LACFG3 LACFG2 LACFG1 LACFG0 LBCFG3 LBCFG2 LBCFG1 LBCFG0 Legend: x = unknown, u = unchanged, - = unimplemented, read as `0', r = reserved, do not modify. Shaded cells are unimplemented, read as `0'. PIC18F97J60 FAMILY DS39762F-page 234 TABLE 19-3: 2011 Microchip Technology Inc. PIC18F97J60 FAMILY REGISTER 19-9: PHCON1: PHY CONTROL REGISTER 1 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 R/W-0 r r -- -- r r -- PDPXMD bit 15 bit 8 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 r -- -- -- -- -- -- -- bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-14 Reserved: Write as `0' bit 13-12 Unimplemented: Read as `0' bit 11-10 Reserved: Write as `0' bit 9 Unimplemented: Read as `0' bit 8 PDPXMD: PHY Duplex Mode bit 1 = PHY operates in Full-Duplex mode; application must also set FULDPX (MACON3<0>) 0 = PHY operates in Half-Duplex mode, application must also clear FULDP bit 7 Reserved: Maintain as `0' bit 6-0 Unimplemented: Read as `0' REGISTER 19-10: PHSTAT1: PHYSICAL LAYER STATUS REGISTER 1 U-0 U-0 U-0 R-1 R-1 U-0 U-0 U-0 -- -- -- r r -- -- -- bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/LL-0 R/LH-0 U-0 -- -- -- -- -- LLSTAT r -- bit 7 bit 0 Legend: `1' = Bit is set r = Reserved bit R = Read-only bit `0' = Bit is cleared U = Unimplemented bit, read as `0' -n = Value at POR R/L = Read-Only Latch bit LL = Latches Low bit LH = Latches High bit bit 15-13 Unimplemented: Read as `0' bit 12-11 Reserved: Read as `1' bit 10-3 Unimplemented: Read as `0' bit 2 LLSTAT: PHY Latching Link Status bit 1 = Link is up and has been up continously since PHSTAT1 was last read 0 = Link is down or was down for a period since PHSTAT1 was last read bit 1 Reserved: Ignore on read bit 0 Unimplemented: Read as `0' 2011 Microchip Technology Inc. DS39762F-page 235 PIC18F97J60 FAMILY REGISTER 19-11: PHCON2: PHY CONTROL REGISTER 2 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- FRCLNK r r r r r HDLDIS bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 r r r RXAPDIS r r r r bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as `0' bit 14 FRCLNK: PHY Force Linkup bit 1 = Force linkup even when no link partner is detected (transmission is always allowed) 0 = Normal operation (PHY blocks transmission attempts unless a link partner is attached) bit 13-9 Reserved: Write as `0' bit 8 HDLDIS: PHY Half-Duplex Loopback Disable bit 1 = Normal PHY operation 0 = Reserved bit 7-5 Reserved: Write as `0' bit 4 RXAPDIS: RX+/RX- Operating mode bit 1 = Normal operation 0 = Reserved bit 3-0 Reserved: Write as `0' Note: Improper Ethernet operation may result if HDLDIS or RXAPDIS is cleared, which is the Reset default. Always initialize these bits set before using the Ethernet module. DS39762F-page 236 2011 Microchip Technology Inc. PIC18F97J60 FAMILY REGISTER 19-12: PHSTAT2: PHYSICAL LAYER STATUS REGISTER 2 U-0 U-0 R-0 R-0 R-0 R-0 R-x U-0 -- -- TXSTAT RXSTAT COLSTAT LSTAT r -- bit 15 bit 8 U-0 U-0 R-0 U-0 U-0 U-0 U-0 U-0 -- -- r -- -- -- -- -- bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as `0' bit 13 TXSTAT: PHY Transmit Status bit 1 = PHY is transmitting data 0 = PHY is not transmitting data bit 12 RXSTAT: PHY Receive Status bit 1 = PHY is receiving data 0 = PHY is not receiving data bit 11 COLSTAT: PHY Collision Status bit 1 = A collision is occuring (PHY is both transmitting and receiving while in Half-Duplex mode) 0 = A collision is not occuring bit 10 LSTAT: PHY Collision Status bit 1 = Link is up 0 = Link is down bit 9 Reserved: Ignore on read bit 8-6 Unimplemented: Read as `0' bit 5 Reserved: Ignore on read bit 4-0 Unimplemented: Read as `0' 2011 Microchip Technology Inc. DS39762F-page 237 PIC18F97J60 FAMILY REGISTER 19-13: PHLCON: PHY MODULE LED CONTROL REGISTER R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-1 R/W-0 R/W-0 r r r r LACFG3 LACFG2 LACFG1 LACFG0 bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-1 R/W-x LBCFG3 LBCFG2 LBCFG1 LBCFG0 LFRQ1 LFRQ0 STRCH r bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15-14 x = Bit is unknown Reserved: Write as `0' bit 13-12 Reserved: Write as `1' bit 11-8 LACFG<3:0>: LEDA Configuration bits 0000 = Reserved 0001 = Display transmit activity (stretchable) 0010 = Display receive activity (stretchable) 0011 = Display collision activity (stretchable) 0100 = Display link status 0101 = Display duplex status 0110 = Reserved 0111 = Display transmit and receive activity (stretchable) 1000 = On 1001 = Off 1010 = Blink fast 1011 = Blink slow 1100 = Display link status and receive activity (always stretched) 1101 = Display link status and transmit/receive activity (always stretched) 111x = Reserved bit 7-4 LBCFG<3:0>: LEDB Configuration bits 0000 = Reserved 0001 = Display transmit activity (stretchable) 0010 = Display receive activity (stretchable) 0011 = Display collision activity (stretchable) 0100 = Display link status 0101 = Display duplex status 0110 = Reserved 0111 = Display transmit and receive activity (stretchable) 1000 = On 1001 = Off 1010 = Blink fast 1011 = Blink slow 1100 = Display link status and receive activity (always stretched) 1101 = Display link status and transmit/receive activity (always stretched) 111x = Reserved bit 3-2 LFRQ<1:0>: LED Pulse Stretch Time Configuration bits (see Table 19-1) 11 = Reserved 10 = Stretch LED events by TLSTRCH 01 = Stretch LED events by TMSTRCH 00 = Stretch LED events by TNSTRCH bit 1 STRCH: LED Pulse Stretching Enable bit 1 = Stretchable LED events will cause lengthened LED pulses based on LFRQ<1:0> configuration 0 = Stretchable LED events will only be displayed while they are occurring bit 0 Reserved: Write as `0' DS39762F-page 238 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 19.3 Ethernet Interrupts Note: The Ethernet module can generate multiple interrupt conditions. To accommodate all of these sources, the module has its own interrupt logic structure, similar to that of the microcontroller. Separate sets of registers are used to enable and flag different interrupt conditions. The EIE register contains the individual interrupt enable bits for each source, while the EIR register contains the corresponding interrupt flag bits. When an interrupt occurs, the interrupt flag is set. If the interrupt is enabled in the EIE register, and the corresponding ETHIE Global Interrupt Enable bit is set, the microcontroller's master Ethernet Interrupt Flag (ETHIF) is set, as appropriate (see Figure 19-7). FIGURE 19-7: 19.3.1 Except for the LINKIF interrupt flag, interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the associated global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. CONTROL INTERRUPT (ETHIE) The four registers associated with the control interrupts are shown in Register 19-14 through Register 19-17. ETHERNET MODULE INTERRUPT LOGIC PKTIF PKTIE DMAIF PLNKIF PLNKIE PGIF PGEIE DMAIE LINKIF LINKIE Set ETHIF TXIF TXIE TXERIF ETHIE TXERIE RXERIF RXERIE 2011 Microchip Technology Inc. DS39762F-page 239 PIC18F97J60 FAMILY REGISTER 19-14: EIE: ETHERNET INTERRUPT ENABLE REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 -- PKTIE DMAIE LINKIE TXIE -- TXERIE RXERIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 Unimplemented: Read as `0' bit 6 PKTIE: Receive Packet Pending Interrupt Enable bit 1 = Enable receive packet pending interrupt 0 = Disable receive packet pending interrupt bit 5 DMAIE: DMA Interrupt Enable bit 1 = Enable DMA interrupt 0 = Disable DMA interrupt bit 4 LINKIE: Link Status Change Interrupt Enable bit 1 = Enable link change interrupt from the PHY 0 = Disable link change interrupt bit 3 TXIE: Transmit Enable bit 1 = Enable transmit interrupt 0 = Disable transmit interrupt bit 2 Unimplemented: Read as `0' bit 1 TXERIE: Transmit Error Interrupt Enable bit 1 = Enable transmit error interrupt 0 = Disable transmit error interrupt bit 0 RXERIE: Receive Error Interrupt Enable bit 1 = Enable receive error interrupt 0 = Disable receive error interrupt DS39762F-page 240 x = Bit is unknown 2011 Microchip Technology Inc. PIC18F97J60 FAMILY REGISTER 19-15: EIR: ETHERNET INTERRUPT REQUEST (FLAG) REGISTER U-0 R-0 R/C-0 R-0 R/C-0 U-0 R/C-0 R/C-0 -- PKTIF DMAIF LINKIF TXIF -- TXERIF RXERIF bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as `0' bit 6 PKTIF: Receive Packet Pending Interrupt Flag bit 1 = Receive buffer contains one or more unprocessed packets; cleared only when EPKTCNT is decremented to 0 by setting PKTDEC (ECON2<6>) 0 = Receive buffer is empty bit 5 DMAIF: DMA Interrupt Flag bit 1 = DMA copy or checksum calculation has completed 0 = No DMA interrupt is pending bit 4 LINKIF: Link Change Interrupt Flag bit 1 = PHY reports that the link status has changed; read PHIR register to clear 0 = Link status has not changed bit 3 TXIF: Transmit Interrupt Flag bit 1 = Transmit request has ended 0 = No transmit interrupt is pending bit 2 Unimplemented: Read as `0' bit 1 TXERIF: Transmit Error Interrupt Flag bit 1 = A transmit error has occurred 0 = No transmit error has occurred bit 0 RXERIF: Receive Error Interrupt Flag bit 1 = A packet was aborted because there is insufficient buffer space, or a buffer overrun has occurred 0 = No receive error interrupt is pending 2011 Microchip Technology Inc. DS39762F-page 241 PIC18F97J60 FAMILY REGISTER 19-16: PHIE: PHY INTERRUPT ENABLE REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 r r r r r r r r bit 15 bit 8 R-0 R-0 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 r r r PLNKIE r r PGEIE r bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15-6 Reserved: Write as `0', ignore on read bit 5 Reserved: Maintain as `0' bit 4 PLNKIE: PHY Link Change Interrupt Enable bit 1 = PHY link change interrupt is enabled 0 = PHY link change interrupt is disabled bit 3-2 Reserved: Write as `0', ignore on read bit 1 PGEIE: PHY Global Interrupt Enable bit 1 = PHY interrupts are enabled 0 = PHY interrupts are disabled bit 0 Reserved: Maintain as `0' x = Bit is unknown REGISTER 19-17: PHIR: PHY INTERRUPT REQUEST (FLAG) REGISTER R-x R-x R-x R-x R-x R-x R-x R-x r r r r r r r r bit 15 bit 8 R-x R-x R-0 R/SC-0 R-0 R/SC-0 R-x R-0 r r r PLNKIF r PGIF r r bit 7 bit 0 Legend: r = Reserved bit R = Readable bit SC = Self-Clearable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-6 Reserved: Ignore on read bit 5 Reserved: Read as `0' bit 4 PLNKIF: PHY Link Change Interrupt Flag bit 1 = PHY link status has changed since PHIR was last read; resets to `0' when read 0 = PHY link status has not changed since PHIR was last read bit 3 Reserved: Read as `0' bit 2 PGIF: PHY Global Interrupt Flag bit 1 = One or more enabled PHY interrupts have occurred since PHIR was last read; resets to `0' when read 0 = No PHY interrupts have occurred bit 1 Reserved: Ignore on read bit 0 Reserved: Read as `0' DS39762F-page 242 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 19.3.1.1 Receive Error Interrupt (RXERIF) 4. The receive error interrupt is used to indicate that a packet being received was aborted due to an error condition. Three errors are possible: 1. 2. 3. No buffer space is available to store the incoming packet (buffer overflow); Receiving another packet would cause the EPKTCNT counter to overflow, because it already contains the value, 255; or The Ethernet RX hardware was not allocated enough memory bandwidth to write the incoming data to the buffer. When a packet is being received and the receive error occurs, the packet being received will be aborted (permanently lost) and the RXERIF bit will be set to `1'. Once set, RXERIF can only be cleared by firmware or by a Reset condition. If the receive error interrupt and Ethernet interrupt are enabled (both RXERIE and ETHIE are set), an Ethernet interrupt is generated. If the receive error interrupt is not enabled (either RXERIE or ETHIE is cleared), the application may poll RXERIF and take appropriate action. Normally, upon the first two receive error conditions (buffer overflow or potential EPKTCNT overflow), the application would process any packets pending from the receive buffer, and then make additional room for future packets by advancing the ERXRDPT registers (low byte first) and decrementing the EPKTCNT register. See Section 19.5.3.3 "Freeing Receive Buffer Space" for more information on processing packets. Once processed, the application should clear the RXERIF bit. The third condition (insufficient RX memory bandwidth) can be identified by checking if the BUFER bit (ESTAT<6>) has been set. Memory access errors that set BUFER are generally transient in nature, and do not require run-time resolution. Adjustments to the application and its allocation of buffer memory bandwidth may be necessary if BUFER errors are frequent or persistent. 19.3.1.2 Transmit Error Interrupt (TXERIF) The transmit error interrupt is used to indicate that a transmit abort has occurred. An abort can occur because of any of the following conditions: 1. 2. 3. More than 15 collisions occurred while attempting to transmit a given packet. A late collision (collision after 64 bytes of a packet had been transmitted) has occurred. The transmission was unable to gain an opportunity to transmit the packet because the medium was constantly occupied for too long. The deferral limit was reached and the DEFER bit (MACON4<6>) was clear. 2011 Microchip Technology Inc. 5. An attempt to transmit a packet larger than the maximum frame length, defined by the MAMXFL registers, was made without setting the HFRMEN bit (MACON3<2>) or per-packet POVERRIDE and PHUGEEN bits. The Ethernet buffer did not have enough memory bandwidth to maintain the required 10 Mbit/s transfer rate (buffer underrun). Upon any of these conditions, the TXERIF flag is set to `1'. Once set, it can only be cleared by firmware or by a Reset condition. If the transmit error interrupt is enabled (TXERIE and ETHIE are both set), an Ethernet interrupt is generated. If the transmit error interrupt is not enabled (either TXERIE or ETHIE is cleared), the application may poll TXERIF and take appropriate action. Once the interrupt is processed, the flag bit should be cleared. After a transmit abort, the TXRTS bit (ECON1<3>) will be cleared, the TXABRT bit (ESTAT<1>) becomes set and the transmit status vector will be written at the ETXND registers + 1. The MAC will not automatically attempt to retransmit the packet. The application may wish to read the transmit status vector and BUFER bit to determine the cause of the abort. After determining the problem and solution, the application should clear the BUFER (if set) and TXABRT bits so that future aborts can be detected accurately. In Full-Duplex mode, Conditions 4 and 5 are the only ones that should cause this interrupt. Condition 5 can be further distinguished as it also sets the BUFER bit. Collisions and other problems related to sharing the network are not possible on full-duplex networks. The conditions, which cause the transmit error interrupt, meet the requirements of the transmit interrupt. As a result, when this interrupt occurs, TXIF will also be simultaneously set. 19.3.1.3 Transmit Interrupt (TXIF) The transmit interrupt is used to indicate that the requested packet transmission has ended (the TXRTS bit has transitioned from `1' to `0'). Upon transmission completion, abort, or transmission cancellation by the application, the TXIF flag will be set to `1'. If the application did not clear the TXRTS bit, and the TXABRT bit is not set, the packet was successfully transmitted. Once TXIF is set, it can only be cleared in software or by a Reset condition. If the transmit interrupt is enabled (TXIE and ETHIE are both set), an interrupt is generated. If the transmit interrupt is not enabled (either TXIE or ETHIE is cleared), the application may poll the TXIF bit and take appropriate action. DS39762F-page 243 PIC18F97J60 FAMILY 19.3.1.4 Link Change Interrupt (LINKIF) The LINKIF indicates that the link status has changed. The actual current link status can be obtained from the LLSTAT (PHSTAT1<2>) or LSTAT (PHSTAT2<10>) bits (see Register 19-10 and Register 19-12). Unlike other interrupt sources, the link status change interrupt is created in the integrated PHY module; additional steps must be taken to enable it. By Reset default, LINKIF is never set for any reason. To receive it, both the PLNKIE and PGEIE bits must be set. When the interrupt is enabled, the LINKIF bit will shadow the contents of the PGIF bit. The PHY only supports one interrupt, so the PGIF bit will always be the same as the PLNKIF bit (when both PHY enable bits are set). Once LINKIF is set, it can only be cleared in software or by a Reset. If the link change interrupt is enabled (LINKIE, PLNKIE, PGEIE and ETHIE are all set), an interrupt is generated. If the link change interrupt is not enabled (LINKIE, PLNKIE, PGEIE or ETHIE are cleared), the user application may poll the PLNKIF flag and take appropriate action. The LINKIF bit is read-only. Because reading PHY registers requires a non-negligible period of time, the application may instead set PLNKIE and PGEIE, then poll the LINKIF flag bit. Performing an MII read on the PHIR register will clear the LINKIF, PGIF and PLNKIF bits automatically, and allow for future link status change interrupts. See Section 19.2.5 "PHY Registers" for information on accessing the PHY registers. 19.3.1.5 The PKTIF bit can only be cleared indirectly in software, by decrementing the EPKTCNT register to `0', or by a Reset condition. See Section 19.5.3 "Receiving Packets" for more information about clearing the EPKTCNT register. When the last data packet in the receive buffer is processed, EPKTCNT becomes zero and the PKTIF bit is automatically cleared. 19.3.2 Receive Packet Pending Interrupt (PKTIF) The receive packet pending interrupt is used to indicate the presence of one or more data packets in the receive buffer and to provide a notification means for the arrival of new packets. When the receive buffer has at least one packet in it, the PKTIF flag bit is set. In other words, this interrupt flag will be set any time the Ethernet Packet Count register (EPKTCNT) is non-zero. DS39762F-page 244 ETHERNET INTERRUPTS AND WAKE-ON-LAN The Ethernet interrupt structure implements a version of Wake-on-LAN, also called Remote Wake-up, using a Magic Packet data packet. This allows the application to conserve power in Idle mode, and then return to full-power operation only when a specific wake-up packet is received. For Remote Wake-up to work, the Ethernet module must remain enabled at all times. It is also necessary to configure the receive filters to select for Magic Packets. For more information on filter configuration, see Section 19.8 "Receive Filters". To configure the microcontroller for Remote Wake-up: 1. DMA Interrupt (DMAIF) The DMA interrupt indicates that the DMA module has completed its memory copy or checksum calculation (the DMAST bit has transitioned from `1' to `0'). Additionally, this interrupt will be caused if the application cancels a DMA operation by manually clearing the DMAST bit. Once set, DMAIF can only be cleared by the firmware or by a Reset condition. If the DMA interrupt is enabled, an Ethernet interrupt is generated. If the DMA interrupt is not enabled, the user application may poll the DMAIF flag status and take appropriate action. Once processed, the flag bit should be cleared. 19.3.1.6 When the receive packet pending interrupt is enabled (both PKTIE and ETHIE are set), an Ethernet interrupt is generated whenever a new packet is successfully received and written into the receive buffer. If the receive packet pending interrupt is not enabled (either PKTIE or ETHIE is cleared), the user application may poll the PKTIF bit and take appropriate action. 2. 3. 4. With the Ethernet module enabled and in normal operating configuration, enable the CRC post-filter and Magic Packets filter (ERXFCON<5,3> = 1). Finish processing any pending packets in the Ethernet buffer. Enable Ethernet interrupts at the microcontroller level (PIE2<5> = 1) and the receive packet pending interrupt at the module level (EIE<6> = 1). Place the microcontroller in PRI_IDLE mode (with the primary clock source selected and OSCCON<7> = 1, execute the SLEEP instruction). In this configuration, the receipt of a Magic Packet data packet will cause a receive packet pending interrupt. This, in turn, will cause the microcontroller to wake-up from the interrupt. 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 19.4 Module Initialization Before the Ethernet module can be used to transmit and receive packets, certain device settings must be initialized. Depending on the application, some configuration options may need to be changed. Normally, these tasks may be accomplished once after Reset and do not need to be changed thereafter. Before any other configuration actions are taken, it is recommended that the module be enabled by setting the ETHEN bit (ECON2<5>). This reduces the Idle time that might otherwise result while waiting for the PHYRDY flag to become set. 19.4.1 RECEIVE BUFFER Before receiving any packets, the receive buffer must be initialized by setting the ERXST and ERXND Pointers. All memory between and including the ERXST and ERXND addresses will be dedicated to the receive hardware. The ERXST Pointers must be programmed with an even address while the ERXND Pointers must be programmed with an odd address. 19.4.4 If the initialization procedure is being executed immediately after enabling the module (setting the ETHEN bit to `1'), the PHYRDY bit should be polled to make certain that enough time (1 ms) has elapsed before proceeding to modify the PHY registers. For more information on the PHY start-up timer, see Section 19.1.3.1 "Start-up Timer". 19.4.5 19.4.2 1. 2. 19.4.3 3. 4. 5. TRANSMISSION BUFFER All memory which is not used by the receive buffer is considered to be the transmission buffer. Data which is to be transmitted should be written into any unused space. After a packet is transmitted, however, the hardware will write a 7-byte status vector into memory after the last byte in the packet. Therefore, the application should leave at least 7 bytes between each packet and the beginning of the receive buffer. RECEIVE FILTERS MAC INITIALIZATION SETTINGS Several of the MAC registers require configuration during initialization. This only needs to be done once during initialization; the order of programming is unimportant. Applications expecting large amounts of data and frequent packet delivery may wish to allocate most of the memory as the receive buffer. Applications that may need to save older packets, or have several packets ready for transmission, should allocate less memory. When programming the ERXST or ERXND Pointers, the ERXWRPT Pointer registers will automatically be updated with the value in the ERXST registers. The address in the ERXWRPT registers will be used as the starting location when the receive hardware begins writing received data. When the ERXST and ERXND Pointers are initialized, the ERXRDPT registers should additionally be programmed with the value of the ERXND registers. To program the ERXRDPT registers, write to ERXRDPTL first, followed by ERXRDPTH. See Section 19.5.3.3 "Freeing Receive Buffer Space" for more information. WAITING FOR THE PHY START-UP TIMER 6. 7. 8. Set the MARXEN bit (MACON1<0>) to enable the MAC to receive frames. If using full duplex, most applications should also set TXPAUS and RXPAUS to allow IEEE defined flow control to function. Configure the PADCFG<2:0>, TXCRCEN and FULDPX bits in the MACON3 register. Most applications should enable automatic padding to at least 60 bytes and always append a valid CRC. For convenience, many applications may wish to set the FRMLNEN bit as well to enable frame length status reporting. The FULDPX bit should be set if the application will be connected to a full-duplex configured remote node; otherwise leave it clear. Configure the bits in MACON4. For maintaining compliance with IEEE 802.3, be certain to set the DEFER bit (MACON4<6>). Program the MAMXFL registers with the maximum frame length to be permitted to be received or transmitted. Normal network nodes are designed to handle packets that are 1518 bytes or less; larger packets are not supported by IEEE 802.3. Configure the MAC Back-to-Back Inter-Packet Gap register, MABBIPG, with 15h (when Full-Duplex mode is used) or 12h (when Half-Duplex mode is used). Refer to Register 19-18 for a more detailed description of configuring the inter-packet gap. Configure the MAC Non Back-to-Back Inter-Packet Gap Low Byte register, MAIPGL, with 12h. If half duplex is used, configure the MAC Non Back-to-Back Inter-Packet Gap High Byte register, MAIPGH, with 0Ch. Program the local MAC address into the MAADR1:MAADR6 registers. The appropriate receive filters should be enabled or disabled by writing to the ERXFCON register. See Section 19.8 "Receive Filters" for information on how to configure it. 2011 Microchip Technology Inc. DS39762F-page 245 PIC18F97J60 FAMILY REGISTER 19-18: MABBIPG: MAC BACK-TO-BACK INTER-PACKET GAP REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- BBIPG6 BBIPG5 BBIPG4 BBIPG3 BBIPG2 BBIPG1 BBIPG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as `0' bit 6-0 BBIPG<6:0>: Back-to-Back Inter-Packet Gap Delay Time bits When FULDPX (MACON3<0>) = 1: Nibble time offset delay between the end of one transmission and the beginning of the next in a back-to-back sequence. The register value should be programmed to the desired period in nibble times minus 3. The recommended setting is 15h which represents the minimum IEEE specified Inter-Packet Gap (IPG) of 9.6 s. When FULDPX (MACON3<0>) = 0: Nibble time offset delay between the end of one transmission and the beginning of the next in a back-to-back sequence. The register value should be programmed to the desired period in nibble times minus 6. The recommended setting is 12h which represents the minimum IEEE specified Inter-Packet Gap (IPG) of 9.6 s. 19.4.6 PHY INITIALIZATION SETTINGS Depending on the application, bits in three of the PHY module's registers may also require configuration. The PDPXMD bit (PHCON1<8>) controls the PHY half/full-duplex configuration. The application must program the bit properly, along with the FULDPX bit (MACON3<0>). The HDLDIS bit (PHCON2<8>) disables automatic loopback of data. For proper operation, always set both HDLDIS and RXAPDIS (PHCON2<4>). The PHY register, PHLCON (Register 19-13), controls the outputs of LEDA and LEDB. If an application requires a LED configuration other than the default, alter this register to match the new requirements. The settings for LED operation are discussed in Section 19.1.2 "LED Configuration". 19.4.7 There may be circumstances during which the Ethernet module is not needed for prolonged periods. For example, in situations where the application only needs to transmit or receive Ethernet packets on the occurrence of a particular event. In these cases, the module can be selectively powered down. To selectively disable the module: 1. 2. 3. 4. DS39762F-page 246 DISABLING THE ETHERNET MODULE Turn off packet reception by clearing the RXEN bit. Wait for any in-progress packets to finish being received by polling the RXBUSY bit (ESTAT<2>). This bit should be clear before proceeding. Wait for any current transmissions to end by confirming that the TXRTS bit (ECON1<3>) is clear. Clear the ETHEN bit. This removes power and clock sources from the module, and makes the PHY registers inaccessible. The PHYRDY bit is also cleared automatically. 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 19.5 Transmitting and Receiving Data The Ethernet protocol (IEEE Standard 802.3) provides an extremely detailed description of the 10 Mbps, frame-based serial communications system. Before discussing the actual use of the Ethernet module, a brief review of the structure of a typical Ethernet data frame may be appropriate. It is assumed that users already have some familiarity with IEEE 802.3. Those requiring more information should refer to the official standard, or other Ethernet reference texts, for a more comprehensive explanation. 19.5.1 PACKET FORMAT Normal IEEE 802.3 compliant Ethernet frames are between 64 and 1518 bytes long. They are made up of five or six different fields: a destination MAC address, a source MAC address, a type/length field, data payload, an optional padding field and a Cyclic Redundancy Check (CRC). Additionally, when transmitted on the FIGURE 19-8: Ethernet medium, a 7-byte preamble field and Start-of-Frame (SOF) delimiter byte are appended to the beginning of the Ethernet packet. Thus, traffic seen on the twisted-pair cabling will appear as shown in Figure 19-8. 19.5.1.1 Preamble/Start-of-Frame Delimiter When transmitting and receiving data with the Ethernet module, the preamble and Start-of-Frame delimiter bytes are automatically generated, or stripped from the packets, when they are transmitted or received. It can also automatically generate CRC fields and padding as needed on transmission, and verify CRC data on reception. The user application does not need to create or process these fields, or manually verify CRC data. However, the padding and CRC fields are written into the receive buffer when packets arrive, so they may be evaluated by the user application as needed. ETHERNET PACKET FORMAT Number of Bytes Field Comments 7 Preamble Filtered Out by the Module 1 SFD Start-of-Frame Delimiter (filtered out by the module) 6 DA Destination Address, such as Multicast, Broadcast or Unicast 6 SA Source Address 2 Type/Length Used in the Calculation of the FCS Type of Packet or the Length of the Packet Data Packet Payload (with optional padding) 46-1500 Padding 4 Note 1: FCS(1) Frame Check Sequence - CRC The FCS is transmitted starting with bit 31 and ending with bit 0. 2011 Microchip Technology Inc. DS39762F-page 247 PIC18F97J60 FAMILY 19.5.1.2 Destination Address The destination address field is a 6-byte field filled with the MAC address of the device that the packet is directed to. If the Least Significant bit in the first byte of the MAC address is set, the address is a Multicast destination. For example, 01-00-00-00-F0-00 and 33-45-67-89-AB-CD are Multicast addresses, while 00-00-00-00-F0-00 and 32-45-67-89-AB-CD are not. Packets with Multicast destination addresses are designed to arrive and be important to a selected group of Ethernet nodes. If the destination address field is the reserved Multicast address, FF-FF-FF-FF-FF-FF, the packet is a Broadcast packet and it will be directed to everyone sharing the network. If the Least Significant bit in the first byte of the MAC address is clear, the address is a Unicast address and will be designed for usage by only the addressed node. The Ethernet module incorporates receive filters which can be used to discard or accept packets with Multicast, Broadcast and/or Unicast destination addresses. When transmitting packets, the application is responsible for writing the desired destination address into the transmit buffer. 19.5.1.3 Source Address The source address field is a 6-byte field filled with the MAC address of the node which created the Ethernet packet. Users of the Ethernet module must generate a unique MAC address for each and every microcontroller used. MAC addresses consist of two portions. The first three bytes are known as the Organizationally Unique Identifier (OUI). OUIs are distributed by the IEEE. The last three bytes are address bytes at the discretion of the company that purchased the OUI. When transmitting packets, the assigned source MAC address must be written into the transmit buffer by the application. The module will not automatically transmit the contents of the MAADR registers which are used for the Unicast receive filter. 19.5.1.4 Type/Length The type/length field is a 2-byte field which defines which protocol the following packet data belongs to. Alternately, if the field is filled with the contents of 05DCh (1500) or any smaller number, the field is considered a length field, and it specifies the amount of non-padding data which follows in the data field. Users implementing proprietary networks may choose to treat this field as a length field, while applications implementing protocols, such as the Internet Protocol (IP) or Address Resolution Protocol (ARP), should program this field with the appropriate type defined by the protocol's specification when transmitting packets. DS39762F-page 248 19.5.1.5 Data The data field is a variable length field anywhere from 0 to 1500 bytes. Larger data packets will violate Ethernet standards and will be dropped by most Ethernet nodes. The Ethernet module, however, is capable of transmitting and receiving larger packets when the Huge Frame Enable bit, HFRMEN, is set (MACON3<2> = 1). 19.5.1.6 Padding The padding field is a variable length field added to meet IEEE 802.3 specification requirements when small data payloads are used. The destination, source, type, data and padding of an Ethernet packet must be no smaller than 60 bytes. Adding the required 4-byte CRC field, packets must be no smaller than 64 bytes. If the data field is less than 46 bytes long, a padding field is required. When transmitting packets, the Ethernet module automatically generates zero-padding if the PADCFG<2:0> bits (MACON3<7:5>) are configured for this. Otherwise, the user application will need to add any padding to the packet before transmitting it. The module will not prevent the transmission of undersized packets should the application command such an action. When receiving packets, the module automatically rejects packets which are less than 18 bytes. All packets, 18 bytes and larger, will be subject to the standard receive filtering criteria and may be accepted as normal traffic. Since the module only rejects packets smaller than 18 bytes, it is important that the firmware check the length of every received packet and reject packets which are smaller than 64 bytes to meet IEEE 802.3 specification requirements. 19.5.1.7 CRC The CRC field is a 4-byte field which contains an industry standard, 32-bit CRC, calculated with the data from the destination, source, type, data and padding fields. It provides a way of detecting corrupted Ethernet frames, as well as junk data fragments resulting from packet collisions or another host's aborted transmissions. When receiving packets, the Ethernet module will check the CRC of each incoming packet. If the CRCEN bit is set, packets with invalid CRCs will automatically be discarded. If CRCEN is clear and the packet meets all other receive filtering criteria, the packet will be written into the receive buffer and the application will be able to determine if the CRC was valid by reading the receive status vector (see Section 19.5.3 "Receiving Packets"). When transmitting packets, the module automatically generates a valid CRC and transmits it if the PADCFG<2:0> bits are configured for this. Otherwise, the user application must generate the CRC and place it in the transmit buffer. Given the complexity of calculating a CRC, it is highly recommended to allow the module to automatically calculate and include the CRC. 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 19.5.2 TRANSMITTING PACKETS The Ethernet module's MAC will automatically generate the preamble and Start-of-Frame (SOF) delimiter fields when transmitting. Additionally, the MAC can generate any padding (if needed) and the CRC if configured to do so. The application must generate and write all other frame fields into the buffer memory for transmission. FIGURE 19-9: -- In addition, the Ethernet module requires a single per-packet control byte to precede the packet for transmission. The control byte is organized as shown in Figure 19-9. Before transmitting packets, the MAC registers, which alter the transmission characteristics, should be initialized as documented in Section 19.4 "Module Initialization". FORMAT FOR PER-PACKET CONTROL BYTES -- -- -- PHUGEEN PPADN bit 7 PCRCEN POVERRIDE bit 0 bit 7-4 Unimplemented: Read as `0' bit 3 PHUGEEN: Per-Packet Huge Frame Enable bit When POVERRIDE = 1: 1 = The packet will be transmitted in whole 0 = The MAC will transmit up to the number of bytes specified by the MAMXFL registers. If the packet is larger than the bytes specified, it will be aborted after the MAMXFL registers specification is reached. When POVERRIDE = 0: This bit is ignored. bit 2 PPADN: Per-Packet Padding Enable bit When POVERRIDE = 1: 1 = The packet will be zero-padded to 60 bytes if it is less than 60 bytes 0 = The packet will be transmitted without adding any padding bytes When POVERRIDE = 0: This bit is ignored. bit 1 PCRCEN: Per-Packet CRC Enable bit When POVERRIDE = 1: 1 = A valid CRC will be calculated and attached to the frame 0 = No CRC will be appended. The last 4 bytes of the frame will be checked for validity as a CRC. When POVERRIDE = 0: This bit is ignored. bit 0 POVERRIDE: Per-Packet Override bit 1 = The values of PCRCEN, PPADN and PHUGEEN will override the configuration defined by MACON3 0 = The values in MACON3 will be used to determine how the packet will be transmitted 2011 Microchip Technology Inc. DS39762F-page 249 PIC18F97J60 FAMILY An example of how the entire assembled transmit packet looks in memory is shown in Figure 19-10. To construct and transmit a packet in this fashion: 1. 2. 3. 4. 5. Set the ETXST Pointers to an appropriate unused location in the buffer. This will be the location of the per-packet control byte. In the example, it would be 0120h. It is recommended that an even address be used for the ETXST Pointers. Using EDATA and the EWRPT registers, sequentially write the packet data to the Ethernet buffer. In order, write the data for the per-packet control byte, the destination address, the source MAC address, the type/length and the data payload. Set the ETXND Pointers to point to the last byte in the data payload. In the example, it would be programmed to 0156h. Clear the TXIF flag bit (EIR<3>), and set the TXIE (EIE<3>) and ETHIE bits to enable an interrupt when done (if desired). Start the transmission process by setting the TXRTS bit (ECON1<3>). If a DMA operation was in progress while the TXRTS bit was set, the module will wait until the DMA operation is complete before attempting to transmit the packet. This possible delay is required because the DMA and FIGURE 19-10: While the transmission is in progress, the ETXST and ETXND Pointers should not be modified. If it is necessary to cancel the transmission, clear the TXRTS bit. When the packet is finished transmitting, or was aborted due to an error/cancellation, several things occur: * The TXRTS bit is cleared. * A 7-byte transmit status vector is written to the buffer at the location pointed to by the ETXND Pointers + 1. * The TXIF flag is set. * An interrupt will be generated (if enabled). * The ETXST and ETXND Pointers will not be modified. To check if the packet was successfully transmitted, read the TXABRT bit. If it has been set, poll the BUFER bit in addition to the various fields in the transmit status vector to determine the cause. The transmit status vector is organized as shown in Table 19-4. Multi-byte fields are written in little-endian format. SAMPLE TRANSMIT PACKET LAYOUT Buffer Pointers Address Memory ETXST = 0120h 0120h 0Eh 0121h data[1] data[2] 0122h ETXND = 0156h 0156h 0157h 0158h 0159h 015Ah 015Bh 015Ch 015Dh 015Eh DS39762F-page 250 transmission engine share the same memory arbiter channel. Similarly, if the DMAST bit is set after TXRTS is already set, the DMA will wait until the TXRTS bit becomes clear before doing anything. Description Control Data Packet Destination Address, Source Address, Type/Length and Data Status Vector Status Vector Written by the Hardware data[m] tsv[7:0] tsv[15:8] tsv[23:16] tsv[31:24] tsv[39:32] tsv[47:40] tsv[55:48] PHUGEEN, PPADN, PCRCEN and POVERRIDE Start of the Next Packet 2011 Microchip Technology Inc. PIC18F97J60 FAMILY TABLE 19-4: Bit 55-52 TRANSMIT STATUS VECTORS Field Description Zero 0 51 Transmit VLAN Tagged Frame Frame's length/type field contained 8100h which is the VLAN protocol identifier. 50 Backpressure Applied Reserved, do not use. 49 Transmit Pause Control Frame The frame transmitted was a control frame with a valid pause opcode. 48 Transmit Control Frame The frame transmitted was a control frame. Total Bytes Transmitted on Wire Total bytes transmitted on the wire for the current packet, including all bytes from collided attempts. 31 Transmit Underrun The transmission was aborted due to insufficient buffer memory bandwidth to sustain the 10 Mbit/s transmit rate. 30 Transmit Giant Byte count for frame was greater than the MAMXFL registers. 29 Transmit Late Collision Collision occurred after 64 bytes had already been transmitted. 28 Transmit Excessive Collision Packet was aborted after the number of collisions exceeded 15, the retransmission maximum. 27 Transmit Excessive Defer Packet was deferred in excess of 24,287 bit times (2.4287 ms), due to a continuously occupied medium. 26 Transmit Packet Defer Packet was deferred for at least one attempt, but less than an excessive defer. 25 Transmit Broadcast Packet's destination address was a Broadcast address. 24 Transmit Multicast Packet's destination address was a Multicast address. 23 Transmit Done Transmission of the packet was completed successfully. 22 Transmit Length Out of Range Indicates that frame type/length field was larger than 1500 bytes (type field). 21 Transmit Length Check Error Indicates that the frame length field value in the packet does not match the actual data byte length and is not a type field. The FRMLNEN bit (MACON3<1>) must be set to get this error. 20 Transmit CRC Error The attached CRC in the packet did not match the internally generated CRC. 19-16 Transmit Collision Count Number of collisions the current packet incurred during transmission attempts. It applies to successfully transmitted packets, and as such, will not show the possible maximum count of 16 collisions. 15-0 Transmit Byte Count Total bytes in frame, not counting collided bytes. 47-32 2011 Microchip Technology Inc. DS39762F-page 251 PIC18F97J60 FAMILY 19.5.3 RECEIVING PACKETS Assuming that the receive buffer has been initialized, the MAC has been properly configured and the receive filters have been configured, the application should perform these steps to receive Ethernet packets: 1. 2. 3. Set the PKTIE and ETHIE bits to generate an Ethernet interrupt whenever a packet is received (if desired). Clear the RXERIF flag and set both RXERIE and ETHIE to generate an interrupt whenever a packet is dropped, due to insufficient buffer space or memory access bandwidth (if desired). Enable reception by setting the RXEN bit (ECON1<2>). After setting RXEN, the Duplex mode and the Receive Buffer Start and End Pointers should not be modified. Additionally, to prevent unexpected packets from arriving, it is recommended that RXEN be cleared before altering the receive filter configuration (ERXFCON) and MAC address. After reception is enabled, packets which are not filtered out will be written into the circular receive buffer. Any packet which does not meet the necessary filter FIGURE 19-11: criteria will be discarded and the application will not have any means of identifying that a packet was thrown away. When a packet is accepted and completely written into the buffer: * * * * The EPKTCNT register is incremented The PKTIF bit is set An interrupt is generated (if enabled) The Hardware Write Pointers, ERXWRPT, are automatically advanced 19.5.3.1 Receive Packet Layout Figure 19-11 shows the layout of a received packet. The packets are preceded by a 6-byte header which contains a Next Packet Pointer in addition to a receive status vector which contains receive statistics, including the packet's size. The receive status vectors are shown in Table 19-5. If the last byte in the packet ends on an odd value address, the hardware will automatically add a padding byte when advancing the Hardware Write Pointer. As such, all packets will start on an even boundary. SAMPLE RECEIVE PACKET LAYOUT Address Memory Description Packet N - 1 End of the Previous Packet 101Fh 1020h 1021h 1022h 1023h 1024h 1025h 1026h 1027h 5Eh 10h rsv[7:0] rsv[15:8] rsv[23:16] rsv[30:24] data[1] data[2] Low Byte High Byte status[7:0] status[15:8] status[23:16] status[31:24] Next Packet Pointer Receive Status Vector Packet N 1059h 105Ah 105Bh 105Ch 105Dh 105Eh Packet N + 1 DS39762F-page 252 data[m-3] data[m-2] data[m-1] data[m] crc[31:24] crc[23:16] crc[15:8] crc[7:0] Packet Data: Destination Address, Source Address, Type/Length, Data, Padding, CRC Byte Skipped to Ensure Even Buffer Address Start of the Next Packet 2011 Microchip Technology Inc. PIC18F97J60 FAMILY TABLE 19-5: RECEIVE STATUS VECTORS Bit Field Description 31 Zero `0' 30 Receive VLAN Type Detected Current frame was recognized as a VLAN tagged frame. 29 Receive Unknown Opcode Current frame was recognized as a control frame, but it contained an unknown opcode. 28 Receive Pause Control Frame Current frame was recognized as a control frame containing a valid pause frame opcode and a valid destination address. 27 Receive Control Frame Current frame was recognized as a control frame for having a valid type/length designating it as a control frame. 26 Dribble Nibble Indicates that after the end of this packet, an additional 1 to 7 bits were received. The extra bits were thrown away. 25 Receive Broadcast Packet Indicates packet received had a valid Broadcast address. 24 Receive Multicast Packet Indicates packet received had a valid Multicast address. 23 Received OK Indicates that the packet had a valid CRC and no symbol errors. 22 Length Out of Range Indicates that frame type/length field was larger than 1500 bytes (type field). 21 Length Check Error Indicates that frame length field value in the packet does not match the actual data byte length. 20 CRC Error Indicates that the frame CRC field value does not match the CRC calculated by the MAC. 19 Reserved 18 Carrier Event Previously Seen 17 Reserved 16 Long Event/Drop Event Indicates a packet over 50,000 bit times occurred or that a packet was dropped since the last receive. Received Byte Count Indicates length of the received frame. This includes the destination address, source address, type/length, data, padding and CRC fields. This field is stored in little-endian format. 15-0 19.5.3.2 Indicates that at some time since the last receive, a carrier event was detected. The carrier event is not associated with this packet. A carrier event is activity on the receive channel that does not result in a packet receive attempt being made. Reading Received Packets To process the packet, an application will normally start reading from the beginning of the Next Packet Pointer. The application will save the Next Packet Pointer, any necessary bytes from the receive status vector, and then proceed to read the actual packet contents. If the AUTOINC bit is set, it will be able to sequentially read the entire packet without ever modifying the ERDPT registers. The Read Pointer would automatically wrap at the end of the circular receive buffer to the beginning. EQUATION 19-1: In the event that the application needed to randomly access the packet, it would be necessary to manually calculate the proper ERDPT registers, taking care to not exceed the end of the receive buffer if the packet spans the ERXND to ERXST buffer boundary. In other words, given the packet start address and a desired offset, the application should follow the logic shown in Equation 19-1. RANDOM ACCESS ADDRESS CALCULATION If Packet Start Address + Offset > ERXND, then ERDPT = Packet Start Address + Offset - (ERXND - ERXST + 1) else: ERDPT = Packet Start Address + Offset 2011 Microchip Technology Inc. DS39762F-page 253 PIC18F97J60 FAMILY 19.5.3.3 Freeing Receive Buffer Space After the user application has processed a packet (or part of the packet) and needs to free the occupied buffer space used by the processed data, it must advance the Receive Buffer Read Pointer pair, ERXRDPT. The module always writes up to, but not over, the memory pointed to by the ERXRDPT registers. If an attempt to overwrite the Receive Buffer Read Pointer location occurs, the packet in progress is aborted, the RXERIF flag is set and an interrupt is generated (if enabled). In this manner, the hardware will never overwrite unprocessed packets. Normally, the ERXRDPT pair is advanced close to a value pointed to by the Next Packet Pointer, which precedes the receive status vector for the current packet. Because only one pointer is available to control buffer area ownership, the application must process packets in the order they are received. If a packet is to be saved and processed later, the application should copy the packet to an unused location in memory. This can be done efficiently using the integrated DMA controller (see Section 19.9 "Direct Memory Access Controller"). 19.5.3.4 At any time the application needs to know how much receive buffer space is remaining, it should read the Hardware Write Pointers (ERXWRPT registers) and compare it with the ERXRDPT registers. Combined with the known size of the receive buffer, the free space can be derived. The Receive Buffer Read Pointer Low Byte (ERXRDPTL register) is internally buffered to prevent the pointer from moving when only one byte is updated. To move the ERXRDPT pair, the application must write to ERXRDPTL first. The write will update the internal buffer but will not affect the register. When the application writes to ERXRDPTH, the internally buffered low byte will be loaded into the ERXRDPTL register at the same time. The ERXRDPT bytes can be read in any order. When they are read, the actual value of the registers will be returned. As a result, the buffered low byte is not readable. In addition to advancing the Receive Buffer Read Pointer, after each packet is fully processed, the application must set the PKTDEC bit (ECON2<6>). This causes the EPKTCNT register to decrement by 1. After decrementing, if EPKTCNT is `0', the PKTIF flag bit is automatically cleared. Otherwise, it remains set, indicating that additional packets are in the receive buffer and are waiting to be processed. Attempting to decrement EPKTCNT below 0 does not cause an underflow to 255, but may cause an unintentional interrupt. The application should avoid decrementing EPKTCNT in this situation. Additionally, if the EPKTCNT register ever maximizes at 255, all new packets which are received will be aborted, even if buffer space is available. To indicate the error, the RXERIF is set and an interrupt is generated (if enabled). To prevent this condition, the user application must properly decrement the counter whenever a packet is processed. EQUATION 19-2: Receive Buffer Free Space Note: The ERXWRPT registers only update when a packet has been successfully received. If the application reads it just before another packet is to be successfully completed, the value returned could be stale and off by the maximum frame length permitted (MAMXFLH:MAMXFLL) plus 8. Furthermore, as the application reads one byte of the ERXWRPT registers, a new packet may arrive and update the 13-bit pointer before the application has an opportunity to read the other byte of the ERXWRPT registers. When reading the ERXWRPT registers with the receive hardware enabled, special care must be taken to ensure the low and high bytes are read as a matching set. To be assured that a matching set is obtained: 1. 2. 3. 4. Read the EPKTCNT register and save its contents. Read ERXWRPTL and ERXWRPTH. Read the EPKTCNT register again. Compare the two packet counts. If they are not the same, go back to Step 2. With the Hardware Write Pointers obtained, the free space can be calculated as shown in Equation 19-2. The hardware prohibits moving the Write Pointer to the same value occupied by the ERXRDPT registers, so at least one byte will always go unused in the buffer. The Equation 19-2 calculation reflects the lost byte. RECEIVE BUFFER FREE SPACE CALCULATION If ERXWRPT > ERXRDPT, then Free Space = (ERXND - ERXST) - (ERXWRPT - ERXRDPT) else: if ERXWRPT = ERXRDPT, then Free Space = (ERXND - ERXST) else: Free Space = ERXRDPT - ERXWRPT - 1 DS39762F-page 254 2011 Microchip Technology Inc. PIC18F97J60 FAMILY TABLE 19-6: Register Name SUMMARY OF REGISTERS ASSOCIATED WITH PACKET TRANSMISSION Reset Values on Page: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EIE -- PKTIE DMAIE LINKIE TXIE -- TXERIE RXERIE 73 EIR -- PKTIF DMAIF LINKIF TXIF -- TXERIF RXERIF 73 ESTAT -- BUFER -- r -- RXBUSY TXABRT PHYRDY 73 TXRST RXRST DMAST CSUMEN TXRTS RXEN -- -- 70 ECON1 ETXSTL Transmit Start Register Low Byte (ETXST<7:0>) -- ETXSTH ETXNDL -- -- 74 Transmit Start Register High Byte (ETXST<12:8>) 74 Transmit End Register Low Byte (ETXND<7:0>) ETXNDH MACON1 MACON3 -- -- -- -- -- -- r PADCFG2 PADCFG1 PADCFG0 TXCRCEN MACON4 -- 74 Transmit End Register High Byte (ETXND<12:8>) 74 TXPAUS RXPAUS PASSALL MARXEN 75 PHDREN HFRMEN FRMLNEN FULDPX 75 DEFER r r -- -- r r 75 BBIPG6 BBIPG5 BBIPG4 BBIPG3 BBIPG2 BBIPG1 BBIPG0 75 MABBIPG -- MAIPGL -- MAC Non Back-to-Back Inter-Packet Gap Register Low Byte (MAIPGL<6:0>) 75 MAIPGH -- MAC Non Back-to-Back Inter-Packet Gap Register High Byte (MAIPGH<6:0>) 75 MAMXFLL Maximum Frame Length Register Low Byte (MAMXFL<7:0>) 74 MAMXFLH Maximum Frame Length Register High Byte (MAMXFL<15:8>) 74 Legend: -- = unimplemented, r = reserved bit. Shaded cells are not used. TABLE 19-7: Register Name SUMMARY OF REGISTERS ASSOCIATED WITH PACKET RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: EIE -- PKTIE DMAIE LINKIE TXIE -- TXERIE RXERIE 73 EIR -- PKTIF DMAIF LINKIF TXIF -- TXERIF RXERIF 73 ESTAT -- BUFER -- r -- RXBUSY TXABRT PHYRDY 73 ECON2 AUTOINC PKTDEC ETHEN -- -- -- -- -- 73 ECON1 TXRST RXRST DMAST CSUMEN TXRTS RXEN -- -- 70 ERXSTL Receive Start Register Low Byte (ERXST<7:0>) -- ERXSTH ERXNDL -- -- 74 Receive Start Register High Byte (ERXST<12:8>) 74 Receive End Register Low Byte (ERXND<7:0>) -- ERXNDH -- -- 74 Receive End Register High Byte (ERXND<12:8>) 74 ERXRDPTL Receive Buffer Read Pointer Low Byte (ERXRDPT<7:0>) ERXRDPTH ERXFCON EPKTCNT MACON1 -- -- -- UCEN ANDOR CRCEN 73 Receive Buffer Read Pointer High Byte (ERXRDPT<12:8>) PMEN MPEN HTEN MCEN BCEN r TXPAUS RXPAUS PASSALL MARXEN 75 PHDREN HFRMEN FRMLNEN FULDPX 75 Ethernet Packet Count Register -- -- -- 73 74 74 MACON3 PADCFG2 PADCFG1 PADCFG0 TXCRCEN MAMXFLL Maximum Frame Length Register Low Byte (MAMXFL<7:0>) 74 Maximum Frame Length Register High Byte (MAMXFL<15:8>) 74 MAMXFLH Legend: -- = unimplemented, r = reserved bit. Shaded cells are not used. 2011 Microchip Technology Inc. DS39762F-page 255 PIC18F97J60 FAMILY 19.6 Duplex Mode Configuration and Negotiation The Ethernet module does not support Automatic Duplex mode negotiation. If it is connected to an automatic duplex negotiation-enabled network switch or Ethernet controller, the module will be detected as a half-duplex device. To communicate in full duplex, the module and the remote node (switch, router or Ethernet controller) must be manually configured for full-duplex operation. 19.6.1 HALF-DUPLEX OPERATION The Ethernet module operates in Half-Duplex mode when the FULDPX (MACON3<0>) and PDPXMD (PHCON1<8>) bits are cleared (= 0). If only one of these two bits is set, the module will be in an indeterminate state and not function correctly. Since switching between Full and Half-Duplex modes may result in this indeterminate state, it is recommended that the application not transmit any packets (maintain the TXRTS bit clear), and disable packet reception (maintain the RXEN bit clear) during this period. In Half-Duplex mode, only one Ethernet controller may be transmitting on the physical medium at any time. If the application requests a packet to be transmitted by setting the TXRTS bit while another Ethernet controller is already transmitting, the Ethernet module will delay, waiting for the remote transmitter to stop. When it stops, the module will attempt to transmit its packet. Should another Ethernet controller start transmitting at approximately the same time, the data on the wire will become corrupt and a collision will occur. The hardware will handle this condition in one of two ways. If the collision occurs before 64 bytes have been transmitted, the following events occur: 1. 2. 3. 4. If the number of retransmission attempts reaches 15 and another collision occurs, the packet is aborted and the TXRTS bit is cleared. The application will then be responsible for taking appropriate action. The application will be able to determine that the packet was aborted instead of being successfully transmitted by reading the TXABRT flag. For more information, see Section 19.5.2 "Transmitting Packets". If the collision occurs after 64 bytes have already been transmitted, the packet is immediately aborted without any retransmission attempts. Ordinarily, in IEEE 802.3 compliant networks which are properly configured, this late collision will not occur. User intervention may be required to correct the issue. This problem may occur as a result of a full-duplex node attempting to transmit on the half-duplex medium. Alternately, the module may be attempting to operate in Half-Duplex mode while it may be connected to a full-duplex network. Excessively long cabling and network size may also be a possible cause of late collisions. 19.6.2 FULL-DUPLEX OPERATION The Ethernet module operates in Full-Duplex mode when the FULDPX (MACON3<0>) and PDPXMD (PHCON1<8>) bits are both set (= 1). If only one of these two bits is clear, the module will be in an indeterminate state and not function correctly. Again, since switching between Full and Half-Duplex modes may result in this indeterminate state, it is recommended that the application not transmit any packets and should disable packet reception during this period. In Full-Duplex mode, packets will be transmitted while simultaneously packets may be received. Given this, it is impossible to cause any collisions when transmitting packets. The TXRTS bit remains set The transmit error interrupt does not occur A random exponential backoff delay elapses, as defined by the IEEE 802.3 specification A new attempt to transmit the packet from the beginning occurs. The application does not need to intervene. DS39762F-page 256 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 19.7 Flow Control The Ethernet module implements hardware flow control for both Full and Half-Duplex modes. The operation of this feature differs depending on which mode is being used. 19.7.1 HALF-DUPLEX MODE In Half-Duplex mode, setting the FCEN0 bit (EFLOCON<0>) causes flow control to be enabled. When FCEN0 is set, a continuous preamble pattern of alternating `1's and `0's (55h) will automatically be transmitted on the Ethernet medium. Any connected nodes will see the transmission and either not transmit anything, waiting for the transmission to end, or will attempt to transmit and immediately cause a collision. Because a collision will always occur, no nodes on the network will be able to communicate with each other and no new packets will arrive. When the application causes the module to transmit a packet by setting the TXRTS bit, the preamble pattern will stop being transmitted. An inter-packet delay will pass as configured by register, MABBIPG, and then the module will attempt to transmit its packet. After the inter-packet delay, other nodes may begin to transmit. Because all traffic was jammed previously, several nodes may begin transmitting and a series of collisions may occur. When the module successfully finishes transmitting its packet or aborts it, the transmission of the preamble pattern will automatically restart. When the application wishes to no longer jam the network, it should clear the FCEN0 bit. The preamble transmission will cease and normal network operation will resume. used to initialize an internal timer. The timer will automatically decrement every 512 bit times, or 51.2 s. While the timer is counting down, reception of packets is still enabled. If new pause frames arrive, the timer will be re-initialized with the new pause timer value. When the timer reaches zero, or was sent a frame with a zero pause timer value, the MAC that received the pause frame will resume transmitting any pending packets. To prevent a pause frame from stopping all traffic on the entire network, Ethernet switches and routers do not propagate pause control frames in Full-Duplex mode. The pause operation only applies to the direct recipient. A sample network is shown in Figure 19-12. If Computer A were to be transmitting too much data to the microcontroller-based application in Full-Duplex mode, the Ethernet module could transmit a pause control frame to stop the data which is being sent to it. The Ethernet switch would take the pause frame and stop sending data to the application. If Computer A continues to send data, the Ethernet switch will buffer the data so it can be transmitted later when its pause timer expires. If the Ethernet switch begins to run out of buffer space, it will likely transmit a pause control frame of its own to Computer A. If, for some reason the Ethernet switch does not generate a pause control frame of its own, or one of the nodes does not properly handle the pause frame it receives, then packets will inevitably be dropped. In any event, any communication between Computer A and Computer B will always be completely unaffected. FIGURE 19-12: SAMPLE FULL-DUPLEX NETWORK Given the detrimental network effects that are possible and lack of effectiveness, it is not recommended that half-duplex flow control be used unless the application will be in a closed network environment with proper testing. 19.7.2 FULL-DUPLEX MODE In Full-Duplex mode (MACON3<0> = 1), hardware flow control is implemented by means of transmitting pause control frames, as defined by the IEEE 802.3 specification. Pause control frames are 64-byte frames consisting of the reserved Multicast destination address of 01-80-C2-00-00-01, the source address of the sender, a special pause opcode, a 2-byte pause timer value and padding/CRC. Normally, when a pause control frame is received by a MAC, the MAC will finish the packet it is transmitting and then stop transmitting any new frames. The pause timer value will be extracted from the control frame and 2011 Microchip Technology Inc. DS39762F-page 257 PIC18F97J60 FAMILY To enable flow control in Full-Duplex mode, set the TXPAUS and RXPAUS bits in the MACON1 register. Then, at any time that the receiver buffer is running out of space, set the Flow Control Enable bits, FCEN<1:0> (EFLOCON<1:0>). The module will automatically finish transmitting anything that was in progress and then send a valid pause frame, loaded with the selected pause timer value. Depending on the mode selected, the application may need to eventually clear Flow Control mode by again writing to the FCEN bits. When the RXPAUS bit is set and a valid pause frame arrives with a non-zero pause timer value, the module will automatically inhibit transmissions. If the TXRTS bit becomes set to send a packet, the hardware will simply wait until the pause timer expires before attempting to send the packet and subsequently, clearing the TXRTS bit. Normally, this is transparent to the microcontroller, and it will never know that a pause frame had been received. Should it be desirable to know when the MAC is paused or not, the user should set the PASSALL bit (MACON1<1>), then manually interpret the pause control frames which may arrive. REGISTER 19-19: EFLOCON: ETHERNET FLOW CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 R-0 R/W-0 R/W-0 -- -- -- -- -- r FCEN1 FCEN0 bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-3 Unimplemented: Read as `0' bit 2 Reserved: Do not use bit 1-0 FCEN<1:0>: Flow Control Enable bits When FULDPX (MACON3<0>) = 1: 11 = Send one pause frame with a `0' timer value and then turn flow control off 10 = Send pause frames periodically 01 = Send one pause frame then turn flow control off 00 = Flow control off When FULDPX (MACON3<0>) = 0: x1 = Flow control on x0 = Flow control off TABLE 19-8: Register Name SUMMARY OF REGISTERS USED WITH FLOW CONTROL Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: -- -- 70 TXRST RXRST DMAST CSUMEN TXRTS RXEN MACON1 -- -- -- r TXPAUS RXPAUS MABBIPG -- BBIPG6 BBIPG5 BBIPG4 BBIPG3 BBIPG2 BBIPG1 BBIPG0 75 EFLOCON -- -- -- -- -- r FCEN1 FCEN0 75 ECON1 PASSALL MARXEN 75 EPAUSL Pause Timer Value Register Low Byte (EPAUS<7:0>) 75 EPAUSH Pause Timer Value Register High Byte (EPAUS<15:8>) 75 Legend: -- = unimplemented, r = reserved bit. Shaded cells are not used. DS39762F-page 258 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 19.8 Receive Filters 19.8.4 HASH TABLE FILTER To minimize microcontroller processing overhead, the Ethernet module incorporates a range of different receive filters which can automatically reject packets which are not needed. Six different types of packet filters are implemented: The Hash Table receive filter is typically used to receive traffic sent to a specific Multicast group address. Because it checks the specific destination address of packets, it is capable of filtering out more unwanted packets than the Multicast filter. * * * * * * The filter performs a 32-bit CRC over the six destination address bytes in the packet, using the polynomial, 4C11DB7h. From the resulting 32-bit binary number, a 6-bit value is derived from bits<28:23>. This value, in turn, points to a location in a table formed by the Ethernet Hash Table registers, ETH0 through ETH7. If the bit in that location is set, the packet meets the Hash Table filter criteria and is accepted. The specific pointer values for each bit location in the table are shown in Table 19-9. Unicast Multicast Broadcast Pattern Match Magic PacketTM Hash Table The individual filters are all configured by the ERXFCON register (Register 19-20). More than one filter can be active at any given time. Additionally, the filters can be configured by the ANDOR bit to either logically AND or logically OR the tests of several filters. In other words, the filters may be set so that only packets accepted by all active filters are accepted, or a packet accepted by any one filter is accepted. The flowcharts in Figure 19-13 and Figure 19-14 show the effect that each of the filters will have, depending on the setting of ANDOR. The device can enter Promiscuous mode and receive all legal packets by setting the ERXFCON register to 20h (enabling only the CRC filter for valid packets). The proper setting of the register will depend on the application requirements. 19.8.1 UNICAST FILTER The Unicast receive filter checks the destination address of all incoming packets. If the destination address exactly matches the contents of the MAADR registers, the packet meets the Unicast filter criteria. 19.8.2 MULTICAST FILTER The Multicast receive filter checks the destination address of all incoming packets. If the Least Significant bit of the first byte of the destination address is set, the packet meets the Multicast filter criteria. 19.8.3 BROADCAST FILTER The Broadcast receive filter checks the destination address of all incoming packets. If the destination address is FF-FF-FF-FF-FF-FF, the packet meets the Broadcast filter criteria. An example of the Hash Table operation is shown in Example 19-1. In this case, the destination address, 01-00-00-00-01-2C, produces a Table Pointer value of 34h, which points to bit 4 of ETH6. If this bit is `1', the packet will be accepted. By extension, clearing every bit in the Hash Table registers means that the filter criteria will never be met. Similarly, if every bit in the Hash Table is set, the filter criteria will always be met. TABLE 19-9: Register EHT0 EHT1 EHT2 EHT3 EHT4 EHT5 EHT6 EHT7 BIT ASSIGNMENTS IN HASH TABLE REGISTERS Bit Number in Hash Table 7 6 5 4 3 2 1 0 07 0F 17 1F 27 2F 37 3F 06 0E 16 1E 26 2E 36 3E 05 0D 15 1D 25 2D 35 3D 04 0C 14 1C 24 2C 34 3C 03 0B 13 1B 23 2B 33 3B 02 0A 12 1A 22 2A 32 3A 01 09 11 19 21 29 31 39 00 08 10 18 20 28 30 38 EXAMPLE 19-1: DERIVING A HASH TABLE LOCATION Packet Destination Address: 01-00-00-00-01-2C (hex) Result of CRC-32 with 4C11DB7h: 1101 1010 0000 1011 0100 0101 0111 0101 (binary) Pointer Derived from bits<28:23> of CRC Result: 110100 (binary) or 34 (hex) Corresponding Hash Table Location: ETH6<4> 2011 Microchip Technology Inc. DS39762F-page 259 PIC18F97J60 FAMILY REGISTER 19-20: ERXFCON: ETHERNET RECEIVE FILTER CONTROL REGISTER R/W-1 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 UCEN ANDOR CRCEN PMEN MPEN HTEN MCEN BCEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 UCEN: Unicast Filter Enable bit When ANDOR = 1: 1 = Packets not having a destination address matching the local MAC address will be discarded 0 = Filter is disabled When ANDOR = 0: 1 = Packets with a destination address matching the local MAC address will be accepted 0 = Filter is disabled bit 6 ANDOR: AND/OR Filter Select bit 1 = AND: Packets will be rejected unless all enabled filters accept the packet 0 = OR: Packets will be accepted unless all enabled filters reject the packet bit 5 CRCEN: Post-Filter CRC Check Enable bit 1 = All packets with an invalid CRC will be discarded 0 = The CRC validity will be ignored bit 4 PMEN: Pattern Match Filter Enable bit When ANDOR = 1: 1 = Packets must meet the Pattern Match criteria or they will be discarded 0 = Filter is disabled When ANDOR = 0: 1 = Packets which meet the Pattern Match criteria will be accepted 0 = Filter is disabled bit 3 MPEN: Magic Packet Filter Enable bit When ANDOR = 1: 1 = Packets must be Magic Packets for the local MAC address or they will be discarded 0 = Filter is disabled When ANDOR = 0: 1 = Magic Packets for the local MAC address will be accepted 0 = Filter is disabled bit 2 HTEN: Hash Table Filter Enable bit When ANDOR = 1: 1 = Packets must meet the Hash Table criteria or they will be discarded 0 = Filter is disabled When ANDOR = 0: 1 = Packets which meet the Hash Table criteria will be accepted 0 = Filter is disabled bit 1 MCEN: Multicast Filter Enable bit When ANDOR = 1: 1 = The LSb of the first byte of the packet's destination address must be set or it will be discarded 0 = Filter is disabled When ANDOR = 0: 1 = Packets which have the LSb of the first byte in the destination address set will be accepted 0 = Filter is disabled bit 0 BCEN: Broadcast Filter Enable bit When ANDOR = 1: 1 = Packets must have a destination address of FF-FF-FF-FF-FF-FF or they will be discarded 0 = Filter is disabled When ANDOR = 0: 1 = Packets which have a destination address of FF-FF-FF-FF-FF-FF will be accepted 0 = Filter is disabled DS39762F-page 260 2011 Microchip Technology Inc. PIC18F97J60 FAMILY FIGURE 19-13: RECEIVE FILTERING USING OR LOGIC Packet Detected on Wire, ANDOR = 0 (OR) UCEN, PMEN, MPEN, HTEN, MCEN and BCEN all clear? Yes No UCEN set? Yes No PMEN set? Unicast packet? Yes No Pattern matches? No Yes No Yes CRCEN set? Yes CRCEN valid? Yes Accept Packet No No Reject Packet MPEN set? Yes No HTEN set? Yes Hash table bit set? Yes No Yes No BCEN set? Yes No No MCEN set? Magic PacketTM for us? Multicast destination? Yes No Yes No 2011 Microchip Technology Inc. Broadcast destination? Yes No DS39762F-page 261 PIC18F97J60 FAMILY FIGURE 19-14: RECEIVE FILTERING USING AND LOGIC Packet Detected on Wire, ANDOR = 1 (AND) UCEN set? Yes No Unicast packet? No Yes PMEN set? Yes No Pattern Matches? No Yes MPEN set? Yes Magic PacketTM for us? No No Yes HTEN set? Yes No Hash Table bit set? No Yes MCEN set? Yes Multicast destination? No No Yes BCEN set? Yes Broadcast destination? No No Yes No CRCEN set? Yes CRC valid? No Yes Accept Packet DS39762F-page 262 Reject Packet 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 19.8.5 PATTERN MATCH FILTER The Pattern Match Checksum registers should be programmed to the checksum which is expected for the selected bytes. The checksum is calculated in the same manner that the DMA module calculates checksums (see Section 19.9.2 "Checksum Calculations"). Data bytes which have corresponding mask bits programmed to `0' are completely removed for purposes of calculating the checksum, as opposed to treating the data bytes as zero. The Pattern Match filter selects up to 64 bytes from the incoming packet and calculates an IP checksum of the bytes. The checksum is then compared to the EPMCS registers. The packet meets the Pattern Match filter criteria if the calculated checksum matches the EPMCS registers. The Pattern Match filter may be useful for filtering packets which have expected data inside them. To use the Pattern Match filter, the application must program the Pattern Match offset (EPMOH:EPMOL), all of the Pattern Match mask bytes (EPMM0:EPMM7) and the Pattern Match Checksum register pair (EPMCSH:EPMCSL). The Pattern Match offset should be loaded with the offset from the beginning of the destination address field to the 64-byte window which will be used for the checksum computation. Within the 64-byte window, each individual byte can be selectively included or excluded from the checksum computation by setting or clearing the respective bit in the Pattern Match mask. If a packet is received which would cause the 64-byte window to extend past the end of the CRC, the filter criteria will immediately not be met, even if the corresponding mask bits are all `0'. Note: As an example, if the application wished to filter all packets having a particular source MAC address of 00-04-A3-FF-FF-FF, it could program the Pattern Match offset to 0000h and then set bits 6 and 7 of EPMM0 and bits 0, 1, 2 and 3 of EPMM1 (assuming all other mask bits are `0'). The proper checksum to program into the EPMCS registers would be 5BFCh. As an alternative configuration, it could program the offset to 0006h and set bits 0, 1, 2, 3, 4 and 5 of EPMM0. The checksum would still be 5BFCh. However, the second case would be less desirable as packets less than 70 bytes long could never meet the Pattern Match criteria, even if they would generate the proper checksum given the mask configuration. Another example of a Pattern Match filter is illustrated in Figure 19-15. In all cases, the value of the Pattern Match offset must be even for proper operation. Programming the EMPO register pair with an odd value will cause unpredictable results. FIGURE 19-15: SAMPLE PATTERN MATCH FORMAT Input Configuration: EMPOH:EPMOL = 0006h EPMM7:EPMM0 = 0000000000001F0Ah EPMCSH:EPMCSL = 563Fh Field DA SA Type/Length Data FCS Received Data 11 22 33 44 55 66 77 88 99 AA BB CC 00 5A 09 0A 0B 0C 0D . . . 40 . . . FE 45 23 01 Byte # 0 1 2 3 4 5 14 15 16 17 18 . . . 70 . . . 6 7 8 9 10 11 12 13 Bytes Used for Checksum Computation 64-Byte Window Used for Pattern Match Values Used for Checksum Computation = {88h, AAh, 09h, 0Ah, 0Bh, 0Ch, 0Dh, 00h} (00h padding byte added by hardware) Note: Received data is shown in hexadecimal. Byte numbers are shown in decimal format. 2011 Microchip Technology Inc. DS39762F-page 263 PIC18F97J60 FAMILY 19.8.6 MAGIC PACKET FILTER The Magic Packet pattern consists of a sync pattern of 6 FFh bytes, followed by 16 repeats of the destination address (Figure 19-16). The Magic Packet filter checks the destination address and data fields of all incoming packets. If the destination address matches the MAADR registers and the data field holds a valid Magic Packet pattern someplace within it, then the packet will meet the Magic Packet filter criteria. FIGURE 19-16: SAMPLE MAGIC PACKETTM FORMAT Received Data 00 11 22 33 44 55 77 88 99 AA BB CC 00 FE 09 0A 0B 0C 0D 0E FF FF FF FF FF 00 Field Comments DA SA Type/Length Destination MAC Address Source MAC Address Header Optional Application Data or Protocol Header Sync Pattern FF FF FF FF FF FF 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 Magic Packet Pattern 16 Repeats of the Destination MAC Address Footer Optional Application Data or Protocol Footer 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 19 1A 1B 1C 1D 1E EF 54 32 10 DS39762F-page 264 FCS 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 19.9 Direct Memory Access Controller The Ethernet module incorporates a dual purpose DMA controller, which can be used to copy data between locations within the 8-Kbyte memory buffer. It can also be used to calculate a 16-bit checksum which is compatible with various industry standard communication protocols, including TCP, UDP, IP, ICMP, etc. The DMA is controlled using three pointers and several status/control bits: * EDMASTH:EDMASTL: Source Start Address * EDMANDH:EDMANDL: Source End Address * EDMADSTH:EDMADSTL: Destination Start Address * DMAST and CSUMEN (ECON1<5,4>): DMA Start/Busy and Checksum Enable bits * DMAIE and DMAIF (EIE<5> and EIR<5>): DMA Interrupt Enable and Flag bits The Source and End Pointers define what data will be copied or checksumed. The Destination Pointer, used only when copying data, defines where copied data will be placed. All three pointers are with respect to the 8-Kbyte Ethernet memory and cannot be used to access memory in the PIC(R) microcontroller data memory space. When a DMA operation begins, the EDMAST register pair is copied into an Internal Source Pointer. The DMA will execute on one byte at a time and then increment the Internal Source Pointer. However, if a byte is processed and the Internal Source Pointer is equal to the Receive Buffer End Pointer pair, ERXND, the Source Pointer will not be incremented. Instead, the Internal Source Pointer will be loaded with the Receive Buffer Start Pointer pair, ERXST. In this way, the DMA will follow the circular FIFO structure of the receive buffer and received packets can be processed using one operation. The DMA operation will end when the Internal Source Pointer matches the EDMAND Pointers. While any DMA operation is in progress, the DMA Pointers and the CSUMEN bit (ECON1<4>) should not be modified. The DMA operation can be canceled at any time by clearing the DMAST bit (ECON1<5>). No registers will change; however, some memory bytes may already have been copied if a DMA copy was in progress. Some operational requirements must always be kept in mind when using the DMA. Failure to observe these requirements may result in a loss of Ethernet buffer data, or even complete failure of Ethernet operation: * If the EDMAND Pointers cannot be reached because of the receive buffer wrapping behavior, the DMA operation will never end. * By design, the DMA module cannot be used to copy or calculate a checksum over only one byte (EDMAST = EDMAND). An attempt to do so may overwrite all memory in the buffer and never end. 2011 Microchip Technology Inc. * After termination of a DMA operation (DMAST is cleared by hardware or firmware), the application must not set DMAST again within 4 instruction cycles. * To ensure reliable operation, avoid having the application access EDATA during a DMA copy operation. EDATA may be safely accessed during DMA checksum operations. 19.9.1 COPYING MEMORY To copy memory within the buffer: 1. Program the EDMAST, EDMAND and EDMADST register pairs with the appropriate start, end and destination addresses. The EDMAST registers should point to the first byte to copy from, the EDMAND registers should point to the last byte to copy and the EDMADST registers should point to the first byte in the destination range. The destination range will always be linear, never wrapping at any values except from 8191 to 0 (the 8-Kbyte memory boundary). Extreme care should be taken when calculating the End Pointer to prevent a never ending DMA operation which would overwrite the entire 8-Kbyte buffer. 2. If desired, set the DMAIE (EIE<5>) and ETHIE (PIE2<5>) bits, and clear the DMAIF (EIR<5>) flag bit to enable an interrupt at the end of the copy process. 3. Clear the CSUMEN (ECON1<4>) bit. 4. Start the DMA copy by setting the DMAST (ECON1<5>) bit. If a transmit operation is in progress (TXRTS bit is set) while the DMAST bit is set, the module will wait until the transmit operation is complete before attempting to do the DMA copy. This possible delay is required because the DMA and transmission engine are unable to access the buffer at the same time. When the copy is complete, the DMA hardware will clear the DMAST bit, set the DMAIF bit and generate an interrupt (if enabled). The pointers and the EDMACS registers will not be modified. After the DMA module has been initialized and has begun its copy, one instruction cycle (TCY) will be required for each byte copied. However, if the Ethernet receive hardware accumulates one byte of data, the DMA will stall that cycle, yielding to the higher priority operation. If a maximum size, 1518-byte packet was copied while no other memory bandwidth was being used, the DMA module would require slightly more than 145.7 s to complete at a core frequency of 41.667 MHz. The time required to copy a minimum size packet of 64 bytes would be approximately 6.2 s (at 41.667 MHz), plus register configuration time. DS39762F-page 265 PIC18F97J60 FAMILY 19.9.2 CHECKSUM CALCULATIONS When the checksum is finished being calculated, the hardware will clear the DMAST bit, set the DMAIF bit and an interrupt will be generated, if enabled. The DMA Pointers will not be modified and no memory will be written to. The EDMACSH and EDMACSL registers will contain the calculated checksum. The application may write this value into a packet, compare this value with zero (to validate a received block of data containing a checksum field in it), or compare it with some other checksum, such as a pseudo header checksum used in various protocols (TCP, UDP, etc.). The checksum calculation logic treats the source data as a series of 16-bit big-endian integers. If the source range contains an odd number of bytes, a padding byte of 00h is effectively added to the end of the series for purposes of calculating the checksum. The calculated checksum is the 16-bit, one's complement of the one's complement sum of all 16-bit integers. For example, if the bytes included in the checksum were {89h, ABh, CDh}, the checksum would begin by computing: 89ABh + CD00h. A carry out of the 16th bit would occur in the example, so in 16-bit one's complement arithmetic, it would be added back to the first bit. The resulting value of 56ACh would finally be complemented to achieve a checksum of A953h. When operating the DMA in Checksum mode, it takes one instruction cycle (TCY) for every byte included in the checksum. As a result, if a checksum over 1446 bytes was performed, the DMA module would require slightly more than 138.8 s to complete the operation at 41.667 MHz. To calculate a checksum: 1. Set the EDMAST and EDMAND register pairs to point to the first and last bytes of buffer data to be included in the checksum. Care should be taken when programming these pointers to prevent a never-ending checksum calculation due to receive buffer wrapping. To generate an optional interrupt when the checksum calculation is done, set the DMAIE (EIE<5>) and ETHIE (PIE2<5>) bits and clear the DMAIF (EIR<5>) bit. Start the calculation by setting the CSUMEN (ECON1<4>) and DMAST (ECON1<5>) bits. 2. 3. At the same frequency, a small 20-byte header field would take approximately 1.9 s plus DMA setup time to calculate a sum. These estimated times assume that the Ethernet receive hardware does not need memory access bandwidth and the CPU does not issue any reads or writes to the EDATA register while the DMA is computing. Like the DMA Copy mode, the checksum operation will not start until the TXRTS bit (ECON1<3>) is clear. This may considerably increase the checksum calculation time if the application transmits a large packet and immediately attempts to validate a checksum on a received packet. TABLE 19-10: SUMMARY OF REGISTERS ASSOCIATED WITH THE DMA CONTROLLER Register Name Reset Values on Page Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EIE -- PKTIE DMAIE LINKIE TXIE -- TXERIE RXERIE 73 EIR -- PKTIF DMAIF LINKIF TXIF -- TXERIF RXERIF 73 TXRST RXRST DMAST CSUMEN TXRTS RXEN -- -- 70 ECON1 ERXNDL Receive End Register Low Byte (ERXND<7:0>) -- ERXNDH EDMASTL 73 Receive End Register High Byte (ERXND<12:8>) -- -- -- -- -- -- DMA Start Register High Byte (EDMAST<12:8>) -- -- -- 73 73 DMA End Register High Byte (EDMAND<12:8>) DMA Destination Register Low Byte (EDMADST<7:0>) EDMADSTH 73 73 DMA End Register Low Byte (EDMAND<7:0>) EDMANDH EDMADSTL -- DMA Start Register Low Byte (EDMAST<7:0>) EDMASTH EDMANDL -- 73 73 DMA Destination Register High Byte (EDMADST<12:8>) 73 EDMACSL DMA Checksum Register Low Byte (EDMACS<7:0>) 73 EDMACSH DMA Checksum Register High Byte (EDMACS<15:8>) 73 Legend: -- = unimplemented. Shaded cells are not used. DS39762F-page 266 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 19.10 Module Resets 19.10.2 The Ethernet module provides selective module Resets: The Transmit Only Reset is performed by writing a `1' to the TXRST bit (ECON1<7>). This resets the transmit logic only. Other register and control blocks, such as buffer management and host interface, are not affected by a Transmit Only Reset event. To return to normal operation, the TXRST bit must be cleared in software. After clearing TXRST, firmware must not write to any Ethernet module SFRs for at least 1.6 s. After the delay, normal operation can resume. * Transmit Only Reset * Receive Only Reset 19.10.1 MICROCONTROLLER RESETS Following any standard Reset event, the Ethernet module returns to a known state. The contents of the Ethernet buffer memory are unknown. All SFR and PHY registers are loaded with their specified Reset values, depending on the type of Reset event. However, the PHY registers must not be accessed until the PHY start-up timer has expired and the PHYRDY bit (ESTAT<0>) becomes set, or at least 1 ms has passed since the ETHEN bit was set. For more details, see Section 19.1.3.1 "Start-up Timer". 2011 Microchip Technology Inc. 19.10.3 TRANSMIT ONLY RESET RECEIVE ONLY RESET The Receive Only Reset is performed by writing a `1' to the RXRST bit (ECON1<6>). This action resets receive logic only. Other register and control blocks, such as the buffer management and host interface blocks, are not affected by a Receive Only Reset event. To return to normal operation, the RXRST bit is cleared in software. After clearing RXRST, firmware must not write to any Ethernet module SFRs for at least 1.6 s. After the delay, normal operation can resume. DS39762F-page 267 PIC18F97J60 FAMILY NOTES: DS39762F-page 268 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 20.0 20.1 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE Master SSP (MSSP) Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D Converters, etc. The MSSP module can operate in one of two modes: * Serial Peripheral Interface (SPI) * Inter-Integrated Circuit (I2CTM) - Full Master mode - Slave mode (with general address call) 2 The I C interface supports the following modes in hardware: * Master mode * Multi-Master mode * Slave mode 20.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four modes of SPI are supported. To accomplish communication, typically three pins are used: * Serial Data Out (SDOx) - RC5/SDO1 (or RD4/SDO2 for 100-pin devices) * Serial Data In (SDIx) - RC4/SDI1/SDA1 (or RD5/SDI2/SDA2 for 100-pin devices) * Serial Clock (SCKx) - RC3/SCK1/SCL1 (or RD6/SCK2/SCL2 for 100-pin devices) Additionally, a fourth pin may be used when in a Slave mode of operation: * Slave Select (SSx) - RF7/SS1 (or RD7/SS2 for 100-pin devices) Figure 20-1 shows the block diagram of the MSSP module when operating in SPI mode. FIGURE 20-1: Internal Data Bus The 64-pin and 80-pin devices of the PIC18F97J60 family have one MSSP module, designated as MSSP1. The 100-pin devices have two MSSP modules, designated as MSSP1 and MSSP2. Each module operates independently of the other. Note: 20.2 Throughout this section, generic references to an MSSP module in any of its operating modes may be interpreted as being equally applicable to MSSP1 or MSSP2. Register names and module I/O signals use the generic designator, `x', to indicate the use of a numeral to distinguish a particular module when required. Control bit names are not individuated. Read SDIx SSPxSR reg SDOx SSx In devices with more than one MSSP module, it is very important to pay close attention to the SSPxCON register names. SSP1CON1 and SSP1CON2 control different operational aspects of the same module, while SSP1CON1 and SSP2CON1 control the same features for two different modules. 2011 Microchip Technology Inc. Shift Clock bit 0 SSx Control Enable Edge Select Each MSSP module has three associated control registers. These include a status register (SSPxSTAT) and two control registers (SSPxCON1 and SSPxCON2). The use of these registers and their individual configuration bits differ significantly depending on whether the MSSP module is operating in SPI or I2C mode. Note: Write SSPxBUF reg Control Registers Additional details are provided under the individual sections. MSSP BLOCK DIAGRAM (SPI MODE) 2 Clock Select SSPM<3:0> SCKx SMP:CKE 4 2 Edge Select (TMR22Output) Prescaler TOSC 4, 16, 64 Data to TXx/RXx in SSPxSR TRIS bit DS39762F-page 269 PIC18F97J60 FAMILY 20.3.1 REGISTERS SSPxSR is the shift register used for shifting data in or out. SSPxBUF is the buffer register to which data bytes are written to or read from. Each MSSP module has four registers for SPI mode operation. These are: In receive operations, SSPxSR and SSPxBUF together create a double-buffered receiver. When SSPxSR receives a complete byte, it is transferred to SSPxBUF and the SSPxIF interrupt is set. * MSSPx Control Register 1 (SSPxCON1) * MSSPx Status Register (SSPxSTAT) * Serial Receive/Transmit Buffer Register (SSPxBUF) * MSSPx Shift Register (SSPxSR) - Not directly accessible During transmission, the SSPxBUF is not double-buffered. A write to SSPxBUF will write to both SSPxBUF and SSPxSR. SSPxCON1 and SSPxSTAT are the control and status registers in SPI mode operation. The SSPxCON1 register is readable and writable. The lower 6 bits of the SSPxSTAT are read-only. The upper two bits of the SSPxSTAT are read/write. REGISTER 20-1: R/W-0 SMP SSPxSTAT: MSSPx STATUS REGISTER (SPI MODE) R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 (1) D/A P S R/W UA BF CKE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 SMP: Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode. bit 6 CKE: SPI Clock Select bit(1) 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state bit 5 D/A: Data/Address bit Used in I2C mode only. bit 4 P: Stop bit Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared. bit 3 S: Start bit Used in I2C mode only. bit 2 R/W: Read/Write Information bit Used in I2C mode only. bit 1 UA: Update Address bit Used in I2C mode only bit 0 BF: Buffer Full Status bit (Receive mode only) 1 = Receive complete, SSPxBUF is full 0 = Receive not complete, SSPxBUF is empty Note 1: Polarity of clock state is set by the CKP bit (SSPxCON1<4>). DS39762F-page 270 2011 Microchip Technology Inc. PIC18F97J60 FAMILY REGISTER 20-2: R/W-0 SSPxCON1: MSSPx CONTROL REGISTER 1 (SPI MODE) R/W-0 WCOL SSPOV (1) R/W-0 (2) SSPEN R/W-0 CKP R/W-0 SSPM3 (3) R/W-0 SSPM2 (3) R/W-0 SSPM1 (3) R/W-0 SSPM0(3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit (Transmit mode only) 1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit(1) SPI Slave mode: 1 = A new byte is received while the SSPxBUF register is still holding the previous data. In case of overflow, the data in SSPxSR is lost. Overflow can only occur in Slave mode. The user must read the SSPxBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software). 0 = No overflow bit 5 SSPEN: Master Synchronous Serial Port Enable bit(2) 1 = Enables serial port and configures SCKx, SDOx, SDIx and SSx as serial port pins 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level bit 3-0 SSPM<3:0>: Master Synchronous Serial Port Mode Select bits(3) 0101 = SPI Slave mode, Clock = SCKx pin, SSx pin control disabled, SSx can be used as I/O pin 0100 = SPI Slave mode, Clock = SCKx pin, SSx pin control enabled 0011 = SPI Master mode, Clock = TMR2 output/2 0010 = SPI Master mode, Clock = FOSC/64 0001 = SPI Master mode, Clock = FOSC/16 0000 = SPI Master mode, Clock = FOSC/4 Note 1: 2: 3: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register. When this bit is enabled, these pins must be properly configured as input or output. Bit combinations not specifically listed here are either reserved or implemented in I2CTM mode only. 2011 Microchip Technology Inc. DS39762F-page 271 PIC18F97J60 FAMILY 20.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>). These control bits allow the following to be specified: * * * * Master mode (SCKx is the clock output) Slave mode (SCKx is the clock input) Clock Polarity (Idle state of SCKx) Data Input Sample Phase (middle or end of data output time) * Clock Edge (output data on rising/falling edge of SCKx) * Clock Rate (Master mode only) * Slave Select mode (Slave mode only) Each MSSP module consists of a transmit/receive shift register (SSPxSR) and a buffer register (SSPxBUF). The SSPxSR shifts the data in and out of the device, MSb first. The SSPxBUF holds the data that was written to the SSPxSR until the received data is ready. Once the 8 bits of data have been received, that byte is moved to the SSPxBUF register. Then, the Buffer Full detect bit, BF (SSPxSTAT<0>), and the interrupt flag bit, SSPxIF, are set. This double-buffering of the received data (SSPxBUF) allows the next byte to start reception before reading the data that was just EXAMPLE 20-1: LOOP received. Any write to the SSPxBUF register during transmission/reception of data will be ignored and the Write Collision detect bit, WCOL (SSPxCON1<7>), will be set. User software must clear the WCOL bit so that it can be determined if the following write(s) to the SSPxBUF register completed successfully. When the application software is expecting to receive valid data, the SSPxBUF should be read before the next byte of data to transfer is written to the SSPxBUF. The Buffer Full bit, BF (SSPxSTAT<0>), indicates when SSPxBUF has been loaded with the received data (transmission is complete). When the SSPxBUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally, the MSSP interrupt is used to determine when the transmission/reception has completed. The SSPxBUF must be read and/or written. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. Example 20-1 shows the loading of the SSP1BUF (SSP1SR) for data transmission. The SSPxSR is not directly readable or writable and can only be accessed by addressing the SSPxBUF register. Additionally, the SSPxSTAT register indicates the various status conditions. LOADING THE SSP1BUF (SSP1SR) REGISTER BTFSS BRA MOVF SSP1STAT, BF LOOP SSP1BUF, W MOVWF RXDATA ;Save in user RAM, if data is meaningful MOVF MOVWF TXDATA, W SSP1BUF ;W reg = contents of TXDATA ;New data to xmit DS39762F-page 272 ;Has data been received (transmit complete)? ;No ;WREG reg = contents of SSP1BUF 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 20.3.3 ENABLING SPI I/O To enable the serial port, MSSP Enable bit, SSPEN (SSPxCON1<5>), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, reinitialize the SSPxCON registers and then set the SSPEN bit. This configures the SDIx, SDOx, SCKx and SSx pins as serial port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the TRIS register) appropriately programmed as follows: * SDIx is automatically controlled by the SPI module * SDOx must have TRISC<5> (or TRISD<4>) bit cleared * SCKx (Master mode) must have TRISC<3> (or TRISD<6>) bit cleared * SCKx (Slave mode) must have TRISC<3> (or TRISD<6>) bit set * SSx must have TRISF<7> (or TRISD<7>) bit set FIGURE 20-2: Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. 20.3.4 TYPICAL CONNECTION Figure 20-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCKx signal. Data is shifted out of both shift registers on their programmed clock edge and latched on the opposite edge of the clock. Both processors should be programmed to the same Clock Polarity (CKP), then both controllers would send and receive data at the same time. Whether the data is meaningful (or dummy data) depends on the application software. This leads to three scenarios for data transmission: * Master sends data-Slave sends dummy data * Master sends data-Slave sends data * Master sends dummy data-Slave sends data SPI MASTER/SLAVE CONNECTION SPI Master SSPM<3:0> = 00xxb SPI Slave SSPM<3:0> = 010xb SDOx SDIx Serial Input Buffer (SSPxBUF) SDIx Shift Register (SSPxSR) MSb Serial Input Buffer (SSPxBUF) LSb 2011 Microchip Technology Inc. Shift Register (SSPxSR) MSb SCKx PROCESSOR 1 SDOx Serial Clock LSb SCKx PROCESSOR 2 DS39762F-page 273 PIC18F97J60 FAMILY 20.3.5 MASTER MODE The master can initiate the data transfer at any time because it controls the SCKx. The master determines when the slave (Processor 2, Figure 20-2) will broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPxBUF register is written to. If the SPI is only going to receive, the SDOx output could be disabled (programmed as an input). The SSPxSR register will continue to shift in the signal present on the SDIx pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPxBUF register as if a normal received byte (interrupts and status bits appropriately set). This could be useful in receiver applications as a "Line Activity Monitor" mode. FIGURE 20-3: The clock polarity is selected by appropriately programming the CKP bit (SSPxCON1<4>). This then, would give waveforms for SPI communication as shown in Figure 20-3, Figure 20-5 and Figure 20-6, where the MSB is transmitted first. In Master mode, the SPI clock rate (bit rate) is user-programmable to be one of the following: * * * * FOSC/4 (or TCY) FOSC/16 (or 4 * TCY) FOSC/64 (or 16 * TCY) Timer2 output/2 This allows a maximum data rate (at 40 MHz) of 10.00 Mbps. Figure 20-3 shows the waveforms for Master mode. When the CKE bit is set, the SDOx data is valid before there is a clock edge on SCKx. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPxBUF is loaded with the received data is shown. SPI MODE WAVEFORM (MASTER MODE) Write to SSPxBUF SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) 4 Clock Modes SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) SDOx (CKE = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDOx (CKE = 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDIx (SMP = 0) bit 0 bit 7 Input Sample (SMP = 0) SDIx (SMP = 1) bit 7 bit 0 Input Sample (SMP = 1) SSPxIF SSPxSR to SSPxBUF DS39762F-page 274 Next Q4 Cycle after Q2 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 20.3.6 SLAVE MODE In Slave mode, the data is transmitted and received as the external clock pulses appear on SCKx. When the last bit is latched, the SSPxIF interrupt flag bit is set. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCKx pin. The Idle state is determined by the CKP bit (SSPxCON1<4>). While in Slave mode, the external clock is supplied by the external clock source on the SCKx pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. While in Sleep mode, the slave can transmit/receive data. When a byte is received, the device will wake-up from Sleep. 20.3.7 SLAVE SELECT SYNCHRONIZATION The SSx pin allows a Synchronous Slave mode. The SPI must be in Slave mode with SSx pin control enabled (SSPxCON1<3:0> = 04h). When the SSx pin is low, transmission and reception are enabled and the FIGURE 20-4: SDOx pin is driven. When the SSx pin goes high, the SDOx pin is no longer driven, even if in the middle of a transmitted byte, and becomes a floating output. External pull-up/pull-down resistors may be desirable depending on the application. Note 1: When the SPI is in Slave mode with SSx pin control enabled (SSPxCON1<3:0> = 0100), the SPI module will reset if the SSx pin is set to VDD. 2: If the SPI is used in Slave mode with CKE set, then the SSx pin control must be enabled. When the SPI module resets, the bit counter is forced to `0'. This can be done by either forcing the SSx pin to a high level or clearing the SSPEN bit. To emulate two-wire communication, the SDOx pin can be connected to the SDIx pin. When the SPI needs to operate as a receiver, the SDOx pin can be configured as an input. This disables transmissions from the SDOx. The SDIx can always be left as an input (SDIx function) since it cannot create a bus conflict. SLAVE SYNCHRONIZATION WAVEFORM SSx SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF SDOx SDIx (SMP = 0) bit 7 bit 6 bit 7 bit 0 bit 0 bit 7 bit 7 Input Sample (SMP = 0) SSPxIF Interrupt Flag SSPxSR to SSPxBUF 2011 Microchip Technology Inc. Next Q4 Cycle after Q2 DS39762F-page 275 PIC18F97J60 FAMILY FIGURE 20-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SSx Optional SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF SDOx SDIx (SMP = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 bit 7 Input Sample (SMP = 0) SSPxIF Interrupt Flag Next Q4 Cycle after Q2 SSPxSR to SSPxBUF FIGURE 20-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SSx Not Optional SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) Write to SSPxBUF SDOx SDIx (SMP = 0) bit 7 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 Input Sample (SMP = 0) SSPxIF Interrupt Flag SSPxSR to SSPxBUF DS39762F-page 276 Next Q4 Cycle after Q2 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 20.3.8 OPERATION IN POWER-MANAGED MODES In SPI Master mode, module clocks may be operating at a different speed than when in full-power mode. In the case of Sleep mode, all clocks are halted. In Idle modes, a clock is provided to the peripherals. That clock should be from the primary clock source, the secondary clock (Timer1 oscillator at 32.768 kHz) or the INTRC source. See Section 3.7 "Clock Sources and Oscillator Switching" for additional information. 20.3.10 Table 20-1 shows the compatibility between the standard SPI modes and the states of the CKP and CKE control bits. TABLE 20-1: If the Sleep mode is selected, all module clocks are halted and the transmission/reception will remain in that state until the devices wakes. After the device returns to Run mode, the module will resume transmitting and receiving data. In SPI Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in any power-managed mode and data to be shifted into the SPI Transmit/Receive Shift register. When all 8 bits have been received, the MSSP interrupt flag bit will be set, and if enabled, will wake the device. 20.3.9 SPI BUS MODES Control Bits State Standard SPI Mode Terminology CKP CKE 0, 0 0 1 0, 1 0 0 1, 0 1 1 1, 1 1 0 In most cases, the speed that the master clocks SPI data is not important; however, this should be evaluated for each system. If MSSP interrupts are enabled, they can wake the controller from Sleep mode, or one of the Idle modes, when the master completes sending data. If an exit from Sleep or Idle mode is not desired, MSSP interrupts should be disabled. BUS MODE COMPATIBILITY There is also an SMP bit which controls when the data is sampled. 20.3.11 SPI CLOCK SPEED AND MODULE INTERACTIONS Because MSSP1 and MSSP2 are independent modules, they can operate simultaneously at different data rates. Setting the SSPM<3:0> bits of the SSPxCON1 register determines the rate for the corresponding module. An exception is when both modules use Timer2 as a time base in Master mode. In this instance, any changes to the Timer2 operation will affect both MSSP modules equally. If different bit rates are required for each module, the user should select one of the other three time base options for one of the modules. EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. 2011 Microchip Technology Inc. DS39762F-page 277 PIC18F97J60 FAMILY TABLE 20-2: Name INTCON REGISTERS ASSOCIATED WITH SPI OPERATION Bit 7 Bit 6 Bit 5 Bit 4 GIE/GIEH PEIE/GIEL TMR0IE Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: INT0IE RBIE TMR0IF INT0IF RBIF 69 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 71 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 71 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 71 PIR3 SSP2IF(1) BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 71 PIE3 SSP2IE(1) BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 71 IPR3 SSP2IP(1) BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 71 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 71 TRISD TRISD7(1) TRISD3 TRISD2 TRISD1 TRISD0 71 TRISF3 TRISF2 TRISF1 TRISF0 TRISF SSP1BUF TRISF7 (1) TRISD6 TRISF6 TRISD5 (1) TRISF5 TRISD4 (1) TRISF4 MSSP1 Receive Buffer/Transmit Register 71 70 SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 70 SSP1STAT SMP CKE D/A P S R/W UA BF 70 SSP2BUF MSSP2 Receive Buffer/Transmit Register 73 SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 73 SSP2STAT SMP CKE D/A P S R/W UA BF 73 Legend: Shaded cells are not used by the MSSP module in SPI mode. Note 1: These bits are only available in 100-pin devices; otherwise, they are unimplemented and read as `0'. DS39762F-page 278 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 20.4 I2C Mode 20.4.1 The MSSP module in I 2C mode fully implements all master and slave functions (including general call support) and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing. Two pins are used for data transfer: * Serial clock (SCLx) - RC3/SCK1/SCL1 (or RD6/SCK2/SCL2 for 100-pin devices) * Serial data (SDAx) - RC4/SDI1/SDA1 (or RD5/SDI2/SDA2 for 100-pin devices) The user must configure these pins as inputs by setting the TRISC<4:3> or TRISD<5:4> bits. FIGURE 20-7: MSSP BLOCK DIAGRAM (I2CTM MODE) Internal Data Bus Read Write SSPxBUF reg SCLx SDAx SSPxSR reg LSb Match Detect Addr Match SSPxADD reg 2011 Microchip Technology Inc. * * * * MSSPx Control Register 1 (SSPxCON1) MSSPx Control Register 2 (SSPxCON2) MSSPx Status Register (SSPxSTAT) MSSPx Receive Buffer/Transmit Register (SSPxBUF) * MSSPx Shift Register (SSPxSR) - Not directly accessible * MSSPx Address Register (SSPxADD) SSPxCON1, SSPxCON2 and SSPxSTAT are the control and status registers in I2C mode operation. The SSPxCON1 and SSPxCON2 registers are readable and writable. The lower 6 bits of the SSPxSTAT are read-only. The upper two bits of the SSPxSTAT are read/write. Many of the bits in SSPxCON2 assume different functions, depending on whether the module is operating in Master or Slave mode. SSPxCON2<5:1> also assume different names in Slave mode. The different aspects of SSPxCON2 are shown in Register 20-5 (for Master mode) and Register 20-6 (Slave mode). The SSPxADD register holds the slave device address when the MSSP is configured in I2C Slave mode. When the MSSP is configured in Master mode, the lower seven bits of SSPxADD act as the Baud Rate Generator reload value. In receive operations, SSPxSR and SSPxBUF together, create a double-buffered receiver. When SSPxSR receives a complete byte, it is transferred to SSPxBUF and the SSPxIF interrupt is set. Address Mask Start and Stop bit Detect The MSSP module has six registers for I2C operation. These are: SSPxSR is the shift register used for shifting data in or out. SSPxBUF is the buffer register to which data bytes are written to or read from. Shift Clock MSb REGISTERS Set, Reset S, P bits (SSPxSTAT reg) During transmission, the SSPxBUF is not double-buffered. A write to SSPxBUF will write to both SSPxBUF and SSPxSR. DS39762F-page 279 PIC18F97J60 FAMILY REGISTER 20-3: R/W-0 SSPxSTAT: MSSPx STATUS REGISTER (I2CTM MODE) R/W-0 SMP CKE R-0 R-0 R-0 D/A (1) (1) P S R-0 R/W (2,3) R-0 R-0 UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control is disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control is enabled for High-Speed mode (400 kHz) bit 6 CKE: SMBus Select bit In Master or Slave mode: 1 = Enable SMBus-specific inputs 0 = Disable SMBus-specific inputs bit 5 D/A: Data/Address bit In Master mode: Reserved. In Slave mode: 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit(1) 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last bit 3 S: Start bit(1) 1 = Indicates that a Start bit has been detected last 0 = Start bit was not detected last bit 2 R/W: Read/Write Information bit (I2C mode only)(2,3) In Slave mode: 1 = Read 0 = Write In Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress bit 1 UA: Update Address bit (10-Bit Slave mode only) 1 = Indicates that the user needs to update the address in the SSPxADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit In Transmit mode: 1 = SSPxBUF is full 0 = SSPxBUF is empty In Receive mode: 1 = SSPxBUF is full (does not include the ACK and Stop bits) 0 = SSPxBUF is empty (does not include the ACK and Stop bits) Note 1: 2: 3: This bit is cleared on Reset and when SSPEN is cleared. This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit. ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Active mode. DS39762F-page 280 2011 Microchip Technology Inc. PIC18F97J60 FAMILY REGISTER 20-4: SSPxCON1: MSSPx CONTROL REGISTER 1 (I2CTM MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPxBUF register was attempted while the I2C conditions were not valid for a transmission to be started (must be cleared in software) 0 = No collision In Slave Transmit mode: 1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision In Receive mode (Master or Slave modes): This is a "don't care" bit. bit 6 SSPOV: Receive Overflow Indicator bit In Receive mode: 1 = A byte is received while the SSPxBUF register is still holding the previous byte (must be cleared in software) 0 = No overflow In Transmit mode: This is a "don't care" bit in Transmit mode. bit 5 SSPEN: Master Synchronous Serial Port Enable bit 1 = Enables the serial port and configures the SDAx and SCLx pins as the serial port pins(1) 0 = Disables serial port and configures these pins as I/O port pins(1) bit 4 CKP: SCKx Release Control bit In Slave mode: 1 = Releases clock 0 = Holds clock low (clock stretch); used to ensure data setup time In Master mode: Unused in this mode. bit 3-0 SSPM<3:0>: Master Synchronous Serial Port Mode Select bits 1111 = I2C Slave mode, 10-bit addressing with Start and Stop bit interrupts enabled(2) 1110 = I2C Slave mode, 7-bit addressing with Start and Stop bit interrupts enabled(2) 1011 = I2C Firmware Controlled Master mode (slave Idle)(2) 1000 = I2C Master mode, Clock = FOSC/(4 * (SSPADD + 1))(2) 0111 = I2C Slave mode, 10-bit addressing(2) 0110 = I2C Slave mode, 7-bit addressing(2) Note 1: 2: When enabled, the SDAx and SCLx pins must be configured as inputs. Bit combinations not specifically listed here are either reserved or implemented in SPI mode only. 2011 Microchip Technology Inc. DS39762F-page 281 PIC18F97J60 FAMILY REGISTER 20-5: SSPxCON2: MSSPx CONTROL REGISTER 2 (I2CTM MASTER MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT(1) ACKEN(2) RCEN(2) PEN(2) RSEN(2) SEN(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit (Slave mode only) Unused in Master mode. bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only) 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave bit 5 ACKDT: Acknowledge Data bit (Master Receive mode only)(1) 1 = Not Acknowledged 0 = Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit(2) 1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence Idle bit 3 RCEN: Receive Enable bit (Master Receive mode only)(2) 1 = Enables Receive mode for I2C 0 = Receive Idle bit 2 PEN: Stop Condition Enable bit(2) 1 = Initiate Stop condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Stop condition Idle bit 1 RSEN: Repeated Start Condition Enable bit(2) 1 = Initiate Repeated Start condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle bit 0 SEN: Start Condition Enable/Stretch Enable bit(2) 1 = Initiate Start condition on SDAx and SCLx pins. Automatically cleared by hardware. 0 = Start condition Idle Note 1: 2: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. If the I2C module is active, these bits may not be set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled). DS39762F-page 282 2011 Microchip Technology Inc. PIC18F97J60 FAMILY REGISTER 20-6: SSPxCON2: MSSPx CONTROL REGISTER 2 (I2CTM SLAVE MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ADMSK5 ADMSK4 ADMSK3 ADMSK2 ADMSK1 SEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPxSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit Unused in Slave mode. bit 5-2 ADMSK5:ADMSK2: Slave Address Mask Select bits 1 = Masking of corresponding bits of SSPxADD is enabled 0 = Masking of corresponding bits of SSPxADD is disabled bit 1 ADMSK1: Slave Address Least Significant Mask Select bit In 7-Bit Addressing mode: 1 = Masking of SSPxADD<1> is only enabled 0 = Masking of SSPxADD<1> is only disabled In 10-Bit Addressing mode: 1 = Masking of SSPxADD<1:0> is enabled 0 = Masking of SSPxADD<1:0> is disabled bit 0 SEN: Stretch Enable bit(1) 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled Note 1: If the I2C module is active, this bit may not be set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled). 2011 Microchip Technology Inc. DS39762F-page 283 PIC18F97J60 FAMILY 20.4.2 OPERATION The MSSP module functions are enabled by setting the MSSP Enable bit, SSPEN (SSPxCON1<5>). The SSPxCON1 register allows control of the I 2C operation. Four mode selection bits (SSPxCON1<3:0>) allow one of the following I 2C modes to be selected: 2 * I C Master mode, clock = (FOSC/4) x (SSPxADD + 1) * I 2C Slave mode (7-bit addressing) * I 2C Slave mode (10-bit addressing) * I 2C Slave mode (7-bit addressing) with Start and Stop bit interrupts enabled * I 2C Slave mode (10-bit addressing) with Start and Stop bit interrupts enabled * I 2C Firmware Controlled Master mode, slave is Idle Selection of any I 2C mode, with the SSPEN bit set, forces the SCLx and SDAx pins to be open-drain, provided these pins are programmed to inputs by setting the appropriate TRISC or TRISD bits. To ensure proper operation of the module, pull-up resistors must be provided externally to the SCLx and SDAx pins. 20.4.3 SLAVE MODE In Slave mode, the SCLx and SDAx pins must be configured as inputs (TRISC<4:3> or TRISD<5:4> are set). The MSSP module will override the input state with the output data when required (slave-transmitter). The I 2C Slave mode hardware will always generate an interrupt on an exact address match. In addition, address masking will also allow the hardware to generate an interrupt for more than one address (up to 31 in 7-bit addressing and up to 63 in 10-bit addressing). Through the mode select bits, the user can also choose to interrupt on Start and Stop bits. The SCLx clock input must have a minimum high and low for proper operation. The high and low times of the I2C specification, as well as the requirement of the MSSP module, are shown in timing Parameter 100 and Parameter 101. 20.4.3.1 Once the MSSP module has been enabled, it waits for a Start condition to occur. Following the Start condition, the 8 bits are shifted into the SSPxSR register. All incoming bits are sampled with the rising edge of the clock (SCLx) line. The value of register SSPxSR<7:1> is compared to the value of the SSPxADD register. The address is compared on the falling edge of the eighth clock (SCLx) pulse. If the addresses match and the BF and SSPOV bits are clear, the following events occur: 1. 2. 3. 4. 1. 2. 3. Any combination of the following conditions will cause the MSSP module not to give this ACK pulse: 5. * The Buffer Full bit, BF (SSPxSTAT<0>), was set before the transfer was received. * The MSSP Overflow bit, SSPOV (SSPxCON1<6>), was set before the transfer was received. 6. DS39762F-page 284 The SSPxSR register value is loaded into the SSPxBUF register. The Buffer Full bit, BF, is set. An ACK pulse is generated. The MSSP Interrupt Flag bit, SSPxIF, is set (and the interrupt is generated, if enabled) on the falling edge of the ninth SCLx pulse. In 10-Bit Addressing mode, two address bytes need to be received by the slave. The five Most Significant bits (MSbs) of the first address byte specify if this is a 10-bit address. Bit, R/W (SSPxSTAT<2>), must specify a write so the slave device will receive the second address byte. For a 10-bit address, the first byte would equal `11110 A9 A8 0', where `A9' and `A8' are the two MSbs of the address. The sequence of events for 10-bit addressing is as follows, with Steps 7 through 9 for the slave-transmitter: When an address is matched, or the data transfer after an address match is received, the hardware automatically will generate the Acknowledge (ACK) pulse and load the SSPxBUF register with the received value currently in the SSPxSR register. In this case, the SSPxSR register value is not loaded into the SSPxBUF, but bit, SSPxIF, is set. The BF bit is cleared by reading the SSPxBUF register, while bit, SSPOV, is cleared through software. Addressing 4. 7. 8. 9. Receive first (high) byte of address (bits, SSPxIF, BF and UA, are set). Update the SSPxADD register with second (low) byte of address (clears bit, UA, and releases the SCLx line). Read the SSPxBUF register (clears bit, BF) and clear flag bit, SSPxIF. Receive second (low) byte of address (bits, SSPxIF, BF and UA, are set). Update the SSPxADD register with the first (high) byte of address. If match releases SCLx line, this will clear bit, UA. Read the SSPxBUF register (clears bit, BF) and clear flag bit, SSPxIF. Receive Repeated Start condition. Receive first (high) byte of address (bits, SSPxIF and BF, are set). Read the SSPxBUF register (clears bit, BF) and clear flag bit, SSPxIF. 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 20.4.3.2 Address Masking Masking an address bit causes that bit to become a "don't care". When one address bit is masked, two addresses will be Acknowledged and cause an interrupt. It is possible to mask more than one address bit at a time, which makes it possible to Acknowledge up to 31 addresses in 7-bit mode, and up to 63 addresses in 10-bit mode (see Example 20-2). The I2C Slave behaves the same way whether address masking is used or not. However, when address masking is used, the I2C slave can Acknowledge multiple addresses and cause interrupts. When this occurs, it is necessary to determine which address caused the interrupt by checking SSPxBUF. In 7-Bit Addressing mode, address mask bits, ADMSK<5:1> (SSPxCON2<5:1>), mask the corresponding address bits in the SSPxADD register. For any ADMSK bits that are set (ADMSK<n> = 1), the corresponding address bit is ignored (SSPxADD<n> = x). For the module to issue an address Acknowledge, it is sufficient to match only on addresses that do not have an active address mask. EXAMPLE 20-2: In 10-Bit Addressing mode, bits, ADMSK<5:2>, mask the corresponding address bits in the SSPxADD register. In addition, ADMSK1 simultaneously masks the two LSbs of the address (SSPxADD<1:0>). For any ADMSK bits that are active (ADMSK<n> = 1), the corresponding address bit is ignored (SSPxADD<n> = x). Also note, that although in 10-Bit Addressing mode, the upper address bits re-use part of the SSPxADD register bits. The address mask bits do not interact with those bits; they only affect the lower address bits. Note 1: ADMSK1 masks the two Significant bits of the address. Least 2: The two Most Significant bits of the address are not affected by address masking. ADDRESS MASKING EXAMPLES 7-Bit Addressing: SSPxADD<7:1> = A0h (1010000) (SSPxADD<0> is assumed to be `0') ADMSK<5:1> = 00111 Addresses Acknowledged: A0h, A2h, A4h, A6h, A8h, AAh, ACh, AEh 10-Bit Addressing: SSPxADD<7:0> = A0h (10100000) (the two MSb of the address are ignored in this example since they are not affected by masking) ADMSK<5:1> = 00111 Addresses Acknowledged: A0h, A1h, A2h, A3h, A4h, A5h, A6h, A7h, A8h, A9h, AAh, ABh, ACh, ADh, AEh, AFh 2011 Microchip Technology Inc. DS39762F-page 285 PIC18F97J60 FAMILY 20.4.3.3 Reception When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPxSTAT register is cleared. The received address is loaded into the SSPxBUF register and the SDAx line is held low (ACK). When the address byte overflow condition exists, then the no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit, BF (SSPxSTAT<0>), is set, or bit, SSPOV (SSPxCON1<6>), is set. An MSSP interrupt is generated for each data transfer byte. The interrupt flag bit, SSPxIF, must be cleared in software. The SSPxSTAT register is used to determine the status of the byte. If SEN is enabled (SSPxCON2<0> = 1), SCKx/SCLx (RC3 or RD6) will be held low (clock stretch) following each data transfer. The clock must be released by setting bit, CKP (SSPxCON1<4>). See Section 20.4.4 "Clock Stretching" for more details. 20.4.3.4 Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPxSTAT register is set. The received address is loaded into the SSPxBUF register. The ACK pulse will be sent on the ninth bit and pin RC3 or RD6 is held low, regardless of SEN (see Section 20.4.4 "Clock Stretching" for more details). By stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. The transmit data must be loaded into the SSPxBUF register which also loads the SSPxSR register. Then, pin, RC3 or RD6, should be enabled by setting bit, CKP (SSPxCON1<4>). The eight data bits are shifted out on the falling edge of the SCLx input. This ensures that the SDAx signal is valid during the SCLx high time (Figure 20-10). The ACK pulse from the master-receiver is latched on the rising edge of the ninth SCLx input pulse. If the SDAx line is high (not ACK), then the data transfer is complete. In this case, when the ACK is latched by the slave, the slave logic is reset (resets SSPxSTAT register) and the slave monitors for another occurrence of the Start bit. If the SDAx line was low (ACK), the next transmit data must be loaded into the SSPxBUF register. Again, pin, RC3 or RD6, must be enabled by setting bit, CKP. An MSSP interrupt is generated for each data transfer byte. The SSPxIF bit must be cleared in software and the SSPxSTAT register is used to determine the status of the byte. The SSPxIF bit is set on the falling edge of the ninth clock pulse. DS39762F-page 286 2011 Microchip Technology Inc. 2011 Microchip Technology Inc. 2 CKP 3 4 A4 5 A3 Receiving Address A5 6 A2 (CKP does not reset to `0' when SEN = 0) SSPOV (SSPxCON1<6>) BF (SSPxSTAT<0>) SSPxIF (PIR1<3> or PIR3<7>) 1 SCLx S SDAx A6 7 A1 8 9 ACK R/W = 0 1 D7 3 4 D4 5 D3 Receiving Data D5 Cleared in software SSPxBUF is read 2 D6 6 D2 7 D1 8 D0 9 ACK 1 D7 2 D6 3 4 D4 5 D3 Receiving Data D5 6 D2 7 D1 8 D0 Bus master terminates transfer P SSPOV is set because SSPxBUF is still full. ACK is not sent. 9 ACK FIGURE 20-8: A7 PIC18F97J60 FAMILY I2CTM SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) DS39762F-page 287 DS39762F-page 288 2 A6 Note CKP 3 4 X 5 A3 Receiving Address A5 6 X 1 3 4 D4 5 D3 Receiving Data D5 Cleared in software SSPxBUF is read 2 D6 6 D2 7 D1 8 D0 In this example, an address equal to A7.A6.A5.X.A3.X.X will be Acknowledged and cause an interrupt. 9 D7 x = Don't care (i.e., address bit can be either a `1' or a `0'). 8 ACK R/W = 0 2: 7 X 1: (CKP does not reset to `0' when SEN = 0) SSPOV (SSPxCON1<6>) BF (SSPxSTAT<0>) SSPxIF (PIR1<3> or PIR3<7>) 1 SCLx S A7 9 ACK 1 D7 2 D6 3 4 D4 5 D3 Receiving Data D5 6 D2 7 D1 8 D0 Bus master terminates transfer P SSPOV is set because SSPxBUF is still full. ACK is not sent. 9 ACK FIGURE 20-9: SDAx PIC18F97J60 FAMILY I2CTM SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01011 (RECEPTION, 7-BIT ADDRESS) 2011 Microchip Technology Inc. 2011 Microchip Technology Inc. 2 Data in sampled 1 A6 CKP BF (SSPxSTAT<0>) 3 4 A4 5 A3 6 A2 Receiving Address A5 SSPxIF (PIR1<3> or PIR3<7>) S A7 7 A1 8 R/W = 0 9 ACK 4 5 D3 6 D2 Transmitting Data D4 Cleared in software 3 D5 SSPxBUF is written in software 2 D6 CKP is set in software SCLx held low while CPU responds to SSPxIF 1 D7 7 D1 9 From SSPxIF ISR 8 D0 ACK 1 D7 4 D4 5 D3 Cleared in software 3 D5 6 D2 CKP is set in software SSPxBUF is written in software 2 D6 7 8 D0 9 ACK From SSPxIF ISR D1 Transmitting Data P FIGURE 20-10: SCLx SDAx PIC18F97J60 FAMILY I2CTM SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) DS39762F-page 289 DS39762F-page 290 2 1 3 1 5 0 7 A8 UA is set indicating that the SSPxADD needs to be updated 8 9 (CKP does not reset to `0' when SEN = 0) UA (SSPxSTAT<1>) SSPOV (SSPxCON1<6>) 6 A9 SSPxBUF is written with contents of SSPxSR Cleared in software BF (SSPxSTAT<0>) CKP 1 4 SSPxIF (PIR1<3> or PIR3<7>) 1 SCLx S 1 ACK R/W = 0 A7 2 4 A4 5 A3 6 A2 8 9 A0 ACK UA is set indicating that SSPxADD needs to be updated Cleared by hardware when SSPxADD is updated with low byte of address 7 A1 Cleared in software 3 A5 Dummy read of SSPxBUF to clear BF flag 1 A6 Receive Second Byte of Address 1 D7 4 5 6 7 D1 Cleared in software 3 D3 D2 Cleared by hardware when SSPxADD is updated with high byte of address 2 D6 D5 D4 Receive Data Byte Clock is held low until update of SSPxADD has taken place 8 9 1 2 4 5 D3 6 D2 Cleared in software 3 D0 ACK D7 D6 D5 D4 Receive Data Byte 7 8 D1 D0 9 P Bus master terminates transfer SSPOV is set because SSPxBUF is still full. ACK is not sent. ACK FIGURE 20-11: SDAx Receive First Byte of Address Clock is held low until update of SSPxADD has taken place PIC18F97J60 FAMILY I2CTM SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) 2011 Microchip Technology Inc. 2011 Microchip Technology Inc. 2 1 3 1 Note 5 0 7 A8 8 UA is set indicating that the SSPxADD needs to be updated SSPxBUF is written with contents of SSPxSR 6 A9 9 2 X 4 5 A3 6 A2 Cleared in software 3 A5 7 X 4 5 6 Cleared in software 3 7 8 9 1 2 4 5 6 D3 D2 Cleared in software 3 D5 D4 Receive Data Byte D1 D0 ACK D7 D6 Cleared by hardware when SSPxADD is updated with high byte of address 2 D3 D2 Note that the Most Significant bits of the address are not affected by the bit masking. 1 D6 D5 D4 3: 9 D7 x = Don't care (i.e., address bit can be either a `1' or a `0'). 8 X Receive Data Byte In this example, an address equal to A9.A8.A7.A6.A5.X.A3.A2.X.X will be Acknowledged and cause an interrupt. UA is set indicating that SSPxADD needs to be updated Cleared by hardware when SSPxADD is updated with low byte of address Dummy read of SSPxBUF to clear BF flag 1 A6 ACK 1: A7 Receive Second Byte of Address 2: (CKP does not reset to `0' when SEN = 0) UA (SSPxSTAT<1>) SSPOV (SSPxCON1<6>) BF (SSPxSTAT<0>) CKP 4 1 Cleared in software SSPxIF (PIR1<3> or PIR3<7>) 1 SCLx S 1 ACK R/W = 0 Clock is held low until update of SSPxADD has taken place 7 8 D1 D0 9 P Bus master terminates transfer SSPOV is set because SSPxBUF is still full. ACK is not sent. ACK FIGURE 20-12: SDAx Receive First Byte of Address Clock is held low until update of SSPxADD has taken place PIC18F97J60 FAMILY I2CTM SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01001 (RECEPTION, 10-BIT ADDRESS) DS39762F-page 291 DS39762F-page 292 2 1 3 1 4 1 CKP (SSPxCON1<4>) UA (SSPxSTAT<1>) BF (SSPxSTAT<0>) 5 0 6 7 A9 A8 8 UA is set indicating that the SSPxADD needs to be updated SSPxBUF is written with contents of SSPxSR SSPxIF (PIR1<3> or PIR3<7>) 1 SCLx S 1 9 ACK R/W = 0 1 3 4 5 Cleared in software 2 7 UA is set indicating that SSPxADD needs to be updated Cleared by hardware when SSPxADD is updated with low byte of address 6 8 A6 A5 A4 A3 A2 A1 A0 Receive Second Byte of Address Dummy read of SSPxBUF to clear BF flag A7 9 ACK 2 3 1 4 1 Cleared in software 1 1 5 0 6 8 9 ACK R/W = 1 1 2 4 5 6 Cleared in software 3 CKP is set in software 9 P Completion of data transmission clears BF flag 8 ACK CKP is automatically cleared in hardware, holding SCLx low 7 D7 D6 D5 D4 D3 D2 D1 D0 Transmitting Data Byte Clock is held low until CKP is set to `1' Write of SSPxBUF BF flag is clear initiates transmit at the end of the third address sequence 7 A9 A8 Cleared by hardware when SSPxADD is updated with high byte of address. Dummy read of SSPxBUF to clear BF flag Sr 1 Receive First Byte of Address Clock is held low until update of SSPxADD has taken place FIGURE 20-13: SDAx Receive First Byte of Address Clock is held low until update of SSPxADD has taken place Bus master terminates transfer PIC18F97J60 FAMILY I2CTM SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 20.4.4 CLOCK STRETCHING Both 7-Bit and 10-Bit Slave modes implement automatic clock stretching during a transmit sequence. The SEN bit (SSPxCON2<0>) allows clock stretching to be enabled during receives. Setting SEN will cause the SCLx pin to be held low at the end of each data receive sequence. 20.4.4.1 Clock Stretching for 7-Bit Slave Receive Mode (SEN = 1) In 7-Bit Slave Receive mode, on the falling edge of the ninth clock at the end of the ACK sequence, if the BF bit is set, the CKP bit in the SSPxCON1 register is automatically cleared, forcing the SCLx output to be held low. The CKP being cleared to `0' will assert the SCLx line low. The CKP bit must be set in the user's ISR before reception is allowed to continue. By holding the SCLx line low, the user has time to service the ISR and read the contents of the SSPxBUF before the master device can initiate another receive sequence. This will prevent buffer overruns from occurring (see Figure 20-15). Note 1: If the user reads the contents of the SSPxBUF before the falling edge of the ninth clock, thus clearing the BF bit, the CKP bit will not be cleared and clock stretching will not occur. 2: The CKP bit can be set in software regardless of the state of the BF bit. The user should be careful to clear the BF bit in the ISR before the next receive sequence in order to prevent an overflow condition. 20.4.4.2 Clock Stretching for 10-Bit Slave Receive Mode (SEN = 1) 20.4.4.3 Clock Stretching for 7-Bit Slave Transmit Mode The 7-Bit Slave Transmit mode implements clock stretching by clearing the CKP bit after the falling edge of the ninth clock, if the BF bit is clear. This occurs regardless of the state of the SEN bit. The user's ISR must set the CKP bit before transmission is allowed to continue. By holding the SCLx line low, the user has time to service the ISR and load the contents of the SSPxBUF before the master device can initiate another transmit sequence (see Figure 20-10). Note 1: If the user loads the contents of SSPxBUF, setting the BF bit before the falling edge of the ninth clock, the CKP bit will not be cleared and clock stretching will not occur. 2: The CKP bit can be set in software regardless of the state of the BF bit. 20.4.4.4 Clock Stretching for 10-Bit Slave Transmit Mode In 10-Bit Slave Transmit mode, clock stretching is controlled during the first two address sequences by the state of the UA bit, just as it is in 10-Bit Slave Receive mode. The first two addresses are followed by a third address sequence which contains the high-order bits of the 10-bit address and the R/W bit set to `1'. After the third address sequence is performed, the UA bit is not set, the module is now configured in Transmit mode and clock stretching is controlled by the BF flag as in 7-Bit Slave Transmit mode (see Figure 20-13). In 10-Bit Slave Receive mode during the address sequence, clock stretching automatically takes place but CKP is not cleared. During this time, if the UA bit is set after the ninth clock, clock stretching is initiated. The UA bit is set after receiving the upper byte of the 10-bit address and following the receive of the second byte of the 10-bit address with the R/W bit cleared to `0'. The release of the clock line occurs upon updating SSPxADD. Clock stretching will occur on each data receive sequence as described in 7-bit mode. Note: If the user polls the UA bit and clears it by updating the SSPxADD register before the falling edge of the ninth clock occurs and if the user hasn't cleared the BF bit by reading the SSPxBUF register before that time, then the CKP bit will still NOT be asserted low. Clock stretching on the basis of the state of the BF bit only occurs during a data sequence, not an address sequence. 2011 Microchip Technology Inc. DS39762F-page 293 PIC18F97J60 FAMILY 20.4.4.5 Clock Synchronization and the CKP bit When the CKP bit is cleared, the SCLx output is forced to `0'. However, clearing the CKP bit will not assert the SCLx output low until the SCLx output is already sampled low. Therefore, the CKP bit will not assert the SCLx line until an external I2C master device has FIGURE 20-14: already asserted the SCLx line. The SCLx output will remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCLx. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCLx (see Figure 20-14). CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDAx DX - 1 DX SCLx CKP Master device asserts clock Master device deasserts clock WR SSPxCON1 DS39762F-page 294 2011 Microchip Technology Inc. 2011 Microchip Technology Inc. 2 A6 CKP SSPOV (SSPxCON1<6>) BF (SSPxSTAT<0>) SSPxIF (PIR1<3> or PIR3<7>) 1 SCLx S A7 3 4 A4 5 A3 6 A2 Receiving Address A5 7 A1 8 9 ACK R/W = 0 3 4 D4 5 D3 Receiving Data D5 Cleared in software 2 D6 If BF is cleared prior to the falling edge of the 9th clock, CKP will not be reset to `0' and no clock stretching will occur SSPxBUF is read 1 D7 6 D2 7 D1 9 ACK 1 D7 BF is set after falling edge of the 9th clock, CKP is reset to `0' and clock stretching occurs 8 D0 3 4 D4 5 D3 Receiving Data D5 CKP written to `1' in software 2 D6 Clock is held low until CKP is set to `1' 6 D2 7 D1 8 D0 Bus master terminates transfer P SSPOV is set because SSPxBUF is still full. ACK is not sent. 9 ACK Clock is not held low because ACK = 1 FIGURE 20-15: SDAx Clock is not held low because buffer full bit is clear prior to falling edge of 9th clock PIC18F97J60 FAMILY I2CTM SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) DS39762F-page 295 DS39762F-page 296 2 1 3 1 UA (SSPxSTAT<1>) SSPOV (SSPxCON1<6>) BF (SSPxSTAT<0>) CKP 4 1 5 0 6 7 A9 A8 8 UA is set indicating that the SSPxADD needs to be updated SSPxBUF is written with contents of SSPxSR Cleared in software SSPxIF (PIR1<3> or PIR3<7>) 1 SCLx S 1 9 ACK R/W = 0 A7 2 4 A4 5 A3 6 A2 Cleared in software 3 A5 7 A1 8 A0 Note: An update of the SSPxADD register before the falling edge of the ninth clock will have no effect on UA and UA will remain set. UA is set indicating that SSPxADD needs to be updated Cleared by hardware when SSPxADD is updated with low byte of address after falling edge of ninth clock Dummy read of SSPxBUF to clear BF flag 1 A6 Receive Second Byte of Address 9 ACK 2 4 5 6 Cleared in software 3 D3 D2 7 8 1 4 5 6 D2 Cleared in software 3 CKP written to `1' in software 2 D3 Receive Data Byte D7 D6 D5 D4 Note: An update of the SSPxADD register before the falling edge of the ninth clock will have no effect on UA and UA will remain set. 9 ACK Clock is held low until CKP is set to `1' D1 D0 Cleared by hardware when SSPxADD is updated with high byte of address after falling edge of ninth clock Dummy read of SSPxBUF to clear BF flag 1 D7 D6 D5 D4 Receive Data Byte Clock is held low until update of SSPxADD has taken place 7 8 9 ACK Bus master terminates transfer P SSPOV is set because SSPxBUF is still full. ACK is not sent. D1 D0 Clock is not held low because ACK = 1 FIGURE 20-16: SDAx Receive First Byte of Address Clock is held low until update of SSPxADD has taken place PIC18F97J60 FAMILY I2CTM SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS) 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 20.4.5 GENERAL CALL ADDRESS SUPPORT If the general call address matches, the SSPxSR is transferred to the SSPxBUF, the BF flag bit is set (eighth bit) and on the falling edge of the ninth bit (ACK bit), the SSPxIF interrupt flag bit is set. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master. The exception is the general call address, which can address all devices. When this address is used, all devices should, in theory, respond with an Acknowledge. When the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the SSPxBUF. The value can be used to determine if the address was device-specific or a general call address. In 10-Bit Addressing mode, the SSPxADD is required to be updated for the second half of the address to match, and the UA bit is set (SSPxSTAT<1>). If the general call address is sampled when the GCEN bit is set, while the slave is configured in 10-Bit Addressing mode, then the second half of the address is not necessary, the UA bit will not be set and the slave will begin receiving data after the Acknowledge (Figure 20-17). The general call address is one of eight addresses reserved for specific purposes by the I2C protocol. It consists of all `0's with R/W = 0. The general call address is recognized when the General Call Enable bit, GCEN, is enabled (SSPxCON2<7> set). Following a Start bit detect, 8 bits are shifted into the SSPxSR and the address is compared against the SSPxADD. It is also compared to the general call address and fixed in hardware. FIGURE 20-17: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT ADDRESSING MODE) Address is compared to General Call Address after ACK, set interrupt SCLx S 1 2 3 4 5 Receiving Data R/W = 0 General Call Address SDAx ACK D7 6 7 8 9 1 ACK D6 D5 D4 D3 D2 D1 D0 2 3 4 5 6 7 8 9 SSPxIF BF (SSPxSTAT<0>) Cleared in software SSPxBUF is read SSPOV (SSPxCON1<6>) `0' GCEN (SSPxCON2<7>) `1' 2011 Microchip Technology Inc. DS39762F-page 297 PIC18F97J60 FAMILY MASTER MODE Note: Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPxCON1 and by setting the SSPEN bit. In Master mode, the SCLx and SDAx lines are manipulated by the MSSP hardware. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit is set, or the bus is Idle, with both the S and P bits clear. The following events will cause the MSSP Interrupt Flag bit, SSPxIF, to be set (and MSSP interrupt, if enabled): In Firmware Controlled Master mode, user code conducts all I 2C bus operations based on Start and Stop bit conditions. * * * * * Once Master mode is enabled, the user has six options. 1. 2. 3. 4. 5. 6. Assert a Start condition on SDAx and SCLx. Assert a Repeated Start condition on SDAx and SCLx. Write to the SSPxBUF register, initiating transmission of data/address. Configure the I2C port to receive data. Generate an Acknowledge condition at the end of a received byte of data. Generate a Stop condition on SDAx and SCLx. FIGURE 20-18: The MSSP module, when configured in I2C Master mode, does not allow queueing of events. For instance, the user is not allowed to initiate a Start condition and immediately write the SSPxBUF register to initiate transmission before the Start condition is complete. In this case, the SSPxBUF will not be written to and the WCOL bit will be set, indicating that a write to the SSPxBUF did not occur. Start Condition Stop Condition Data Transfer Byte Transmitted/Received Acknowledge Transmit Repeated Start MSSP BLOCK DIAGRAM (I2CTM MASTER MODE) Internal Data Bus Read SSPM<3:0> SSPxADD<6:0> Write SSPxBUF SDAx Baud Rate Generator Shift Clock SDAx In SCLx In Bus Collision DS39762F-page 298 LSb Start bit, Stop bit, Acknowledge Generate Start bit Detect Stop bit Detect Write Collision Detect Clock Arbitration State Counter for End of XMIT/RCV Clock Cntl SCLx Receive Enable SSPxSR MSb Clock Arbitrate/WCOL Detect (hold off clock source) 20.4.6 Set/Reset S, P, WCOL (SSPxSTAT, SSPxCON1) Set SSPxIF, BCLxIF Reset ACKSTAT, PEN (SSPxCON2) 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 20.4.6.1 I2C Master Mode Operation The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDAx, while SCLx outputs the serial clock. The first byte transmitted contains the slave address of the receiving device (7 bits) and the Read/Write (R/W) bit. In this case, the R/W bit will be logic `0'. Serial data is transmitted 8 bits at a time. After each byte is transmitted, an Acknowledge bit is received. Start and Stop conditions are output to indicate the beginning and the end of a serial transfer. In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device (7 bits) and the R/W bit. In this case, the R/W bit will be logic `1'. Thus, the first byte transmitted is a 7-bit slave address followed by a `1' to indicate the receive bit. Serial data is received via SDAx, while SCLx outputs the serial clock. Serial data is received, 8 bits at a time. After each byte is received, an Acknowledge bit is transmitted. Start and Stop conditions indicate the beginning and end of transmission. The Baud Rate Generator used for the SPI mode operation is used to set the SCLx clock frequency for either 100 kHz, 400 kHz or 1 MHz I2C operation. See Section 20.4.7 "Baud Rate" for more detail. 2011 Microchip Technology Inc. A typical transmit sequence would go as follows: 1. The user generates a Start condition by setting the Start Enable bit, SEN (SSPxCON2<0>). 2. SSPxIF is set. The MSSP module will wait the required start time before any other operation takes place. 3. The user loads the SSPxBUF with the slave address to transmit. 4. Address is shifted out on the SDAx pin until all 8 bits are transmitted. 5. The MSSP module shifts in the ACK bit from the slave device and writes its value into the SSPxCON2 register (SSPxCON2<6>). 6. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPxIF bit. 7. The user loads the SSPxBUF with eight bits of data. 8. Data is shifted out on the SDAx pin until all 8 bits are transmitted. 9. The MSSP module shifts in the ACK bit from the slave device and writes its value into the SSPxCON2 register (SSPxCON2<6>). 10. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPxIF bit. 11. The user generates a Stop condition by setting the Stop Enable bit, PEN (SSPxCON2<2>). 12. Interrupt is generated once the Stop condition is complete. DS39762F-page 299 PIC18F97J60 FAMILY 20.4.7 BAUD RATE 20.4.7.1 2 In I C Master mode, the Baud Rate Generator (BRG) reload value is placed in the lower 7 bits of the SSPxADD register (Figure 20-19). When a write occurs to SSPxBUF, the Baud Rate Generator will automatically begin counting. The BRG counts down to 0 and stops until another reload has taken place. The BRG count is decremented twice per instruction cycle (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the BRG is reloaded automatically. Baud Rate and Module Interdependence Because MSSP1 and MSSP2 are independent, they can operate simultaneously in I2C Master mode at different baud rates. This is done by using different BRG reload values for each module. Because this mode derives its basic clock source from the system clock, any changes to the clock will affect both modules in the same proportion. It may be possible to change one or both baud rates back to a previous value by changing the BRG reload value. Once the given operation is complete (i.e., transmission of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCLx pin will remain in its last state. Table 20-3 demonstrates clock rates based on instruction cycles and the BRG value loaded into SSPxADD. FIGURE 20-19: BAUD RATE GENERATOR BLOCK DIAGRAM SSPM<3:0> SSPM<3:0> SCLx SSPxADD<6:0> Reload Reload Control BRG Down Counter CLKO TABLE 20-3: Note 1: FOSC/4 I2CTM CLOCK RATE w/BRG FOSC BRG Value FSCL (2 Rollovers of BRG) 41.667 MHz 19h 400 kHz(1) 41.667 MHz 67h 100 kHz 31.25 MHz 13h 400 kHz(1) 31.25 MHz 4Dh 100 kHz 20.833 MHz 09h 400 kHz(1) 20.833 MHz 33h 100 kHz The I2CTM interface does not conform to the 400 kHz I2C specification (which applies to rates greater than 100 kHz) in all details, but may be used with care where higher rates are required by the application. DS39762F-page 300 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 20.4.7.2 Clock Arbitration Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, deasserts the SCLx pin (SCLx allowed to float high). When the SCLx pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCLx pin is actually sampled high. When the FIGURE 20-20: SDAx SCLx pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<6:0> and begins counting. This ensures that the SCLx high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure 20-20). BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION DX - 1 DX SCLx deasserted but slave holds SCLx low (clock arbitration) SCLx allowed to transition high SCLx BRG decrements on Q2 and Q4 cycles BRG Value 03h BRG Reload 2011 Microchip Technology Inc. 02h 01h 00h (hold off) 03h 02h SCLx is sampled high, reload takes place and BRG starts its count DS39762F-page 301 PIC18F97J60 FAMILY I2C MASTER MODE START CONDITION TIMING Note: To initiate a Start condition, the user sets the Start Enable bit, SEN (SSPxCON2<0>). If the SDAx and SCLx pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<6:0> and starts its count. If SCLx and SDAx are both sampled high when the Baud Rate Generator times out (TBRG), the SDAx pin is driven low. The action of the SDAx being driven low while SCLx is high is the Start condition and causes the S bit (SSPxSTAT<3>) to be set. Following this, the Baud Rate Generator is reloaded with the contents of SSPxADD<6:0> and resumes its count. When the Baud Rate Generator times out (TBRG), the SEN bit (SSPxCON2<0>) will be automatically cleared by hardware. The Baud Rate Generator is suspended, leaving the SDAx line held low and the Start condition is complete. 20.4.8.1 20.4.8 FIGURE 20-21: If, at the beginning of the Start condition, the SDAx and SCLx pins are already sampled low, or if during the Start condition, the SCLx line is sampled low before the SDAx line is driven low, a bus collision occurs. The Bus Collision Interrupt Flag, BCLxIF, is set, the Start condition is aborted and the I2C module is reset into its Idle state. WCOL Status Flag If the user writes the SSPxBUF when a Start sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn't occur). Note: Because queueing of events is not allowed, writing to the lower 5 bits of SSPxCON2 is disabled until the Start condition is complete. FIRST START BIT TIMING Set S bit (SSPxSTAT<3>) Write to SEN bit occurs here SDAx = 1, SCLx = 1 TBRG At completion of Start bit, hardware clears SEN bit and sets SSPxIF bit TBRG Write to SSPxBUF occurs here 1st bit SDAx 2nd bit TBRG SCLx TBRG S DS39762F-page 302 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 20.4.9 I2C MASTER MODE REPEATED START CONDITION TIMING Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. A Repeated Start condition occurs when the RSEN bit (SSPxCON2<1>) is programmed high and the I2C logic module is in the Idle state. When the RSEN bit is set, the SCLx pin is asserted low. When the SCLx pin is sampled low, the Baud Rate Generator is loaded with the contents of SSPxADD<6:0> and begins counting. The SDAx pin is released (brought high) for one Baud Rate Generator count (TBRG). When the Baud Rate Generator times out, if SDAx is sampled high, the SCLx pin will be deasserted (brought high). When SCLx is sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<6:0> and begins counting. SDAx and SCLx must be sampled high for one TBRG. This action is then followed by assertion of the SDAx pin (SDAx = 0) for one TBRG while SCLx is high. Following this, the RSEN bit (SSPxCON2<1>) will be automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDAx pin held low. As soon as a Start condition is detected on the SDAx and SCLx pins, the S bit (SSPxSTAT<3>) will be set. The SSPxIF bit will not be set until the Baud Rate Generator has timed out. 2: A bus collision during the Repeated Start condition occurs if: * SDAx is sampled low when SCLx goes from low-to-high. * SCLx goes low before SDAx is asserted low. This may indicate that another master is attempting to transmit a data `1'. Immediately following the SSPxIF bit getting set, the user may write the SSPxBUF with the 7-bit address in 7-bit mode or the default first address in 10-bit mode. After the first eight bits are transmitted and an ACK is received, the user may then transmit an additional eight bits of address (10-bit mode) or eight bits of data (7-bit mode). 20.4.9.1 If the user writes the SSPxBUF when a Repeated Start sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn't occur). Note: FIGURE 20-22: WCOL Status Flag Because queueing of events is not allowed, writing of the lower 5 bits of SSPxCON2 is disabled until the Repeated Start condition is complete. REPEATED START CONDITION WAVEFORM S bit set by hardware SDAx = 1, SCLx = 1 Write to SSPxCON2 occurs here: SDAx = 1, SCLx (no change) TBRG TBRG At completion of Start bit, hardware clears RSEN bit and sets SSPxIF TBRG 1st bit SDAx RSEN bit set by hardware on falling edge of ninth clock, end of Xmit Write to SSPxBUF occurs here TBRG SCLx TBRG Sr = Repeated Start 2011 Microchip Technology Inc. DS39762F-page 303 PIC18F97J60 FAMILY 20.4.10 I2C MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPxBUF register. This action will set the Buffer Full flag bit, BF, and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDAx pin after the falling edge of SCLx is asserted (see data hold time specification Parameter 106). SCLx is held low for one Baud Rate Generator rollover count (TBRG). Data should be valid before SCLx is released high (see data setup time specification Parameter 107). When the SCLx pin is released high, it is held that way for TBRG. The data on the SDAx pin must remain stable for that duration and some hold time after the next falling edge of SCLx. After the eighth bit is shifted out (the falling edge of the eighth clock), the BF flag is cleared and the master releases SDAx. This allows the slave device being addressed to respond with an ACK bit during the ninth bit time if an address match occurred, or if data was received properly. The status of ACK is written into the ACKDT bit on the falling edge of the ninth clock. If the master receives an Acknowledge, the Acknowledge Status bit, ACKSTAT, is cleared; if not, the bit is set. After the ninth clock, the SSPxIF bit is set and the master clock (Baud Rate Generator) is suspended until the next data byte is loaded into the SSPxBUF, leaving SCLx low and SDAx unchanged (Figure 20-23). After the write to the SSPxBUF, each bit of the address will be shifted out on the falling edge of SCLx until all seven address bits and the R/W bit are completed. On the falling edge of the eighth clock, the master will deassert the SDAx pin, allowing the slave to respond with an Acknowledge. On the falling edge of the ninth clock, the master will sample the SDAx pin to see if the address was recognized by a slave. The status of the ACK bit is loaded into the ACKSTAT status bit (SSPxCON2<6>). Following the falling edge of the ninth clock transmission of the address, the SSPxIF is set, the BF flag is cleared and the Baud Rate Generator is turned off until another write to the SSPxBUF takes place, holding SCLx low and allowing SDAx to float. 20.4.10.1 BF Status Flag In Transmit mode, the BF bit (SSPxSTAT<0>) is set when the CPU writes to SSPxBUF, and is cleared when all 8 bits are shifted out. 20.4.10.2 WCOL Status Flag The user should verify that the WCOL is clear after each write to SSPxBUF to ensure the transfer is correct. In all cases, WCOL must be cleared in software. 20.4.10.3 ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit (SSPxCON2<6>) is cleared when the slave has sent an Acknowledge (ACK = 0) and is set when the slave does not Acknowledge (ACK = 1). A slave sends an Acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data. 20.4.11 I2C MASTER MODE RECEPTION Master mode reception is enabled by programming the Receive Enable bit, RCEN (SSPxCON2<3>). Note: The MSSP module must be in an Idle state before the RCEN bit is set or the RCEN bit will be disregarded. The Baud Rate Generator begins counting and on each rollover. The state of the SCLx pin changes (high-to-low/low-to-high) and data is shifted into the SSPxSR. After the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the SSPxSR are loaded into the SSPxBUF, the BF flag bit is set, the SSPxIF flag bit is set and the Baud Rate Generator is suspended from counting, holding SCLx low. The MSSP is now in Idle state awaiting the next command. When the buffer is read by the CPU, the BF flag bit is automatically cleared. The user can then send an Acknowledge bit at the end of reception by setting the Acknowledge Sequence Enable bit, ACKEN (SSPxCON2<4>). 20.4.11.1 BF Status Flag In receive operation, the BF bit is set when an address or data byte is loaded into SSPxBUF from SSPxSR. It is cleared when the SSPxBUF register is read. 20.4.11.2 SSPOV Status Flag In receive operation, the SSPOV bit is set when 8 bits are received into the SSPxSR and the BF flag bit is already set from a previous reception. 20.4.11.3 WCOL Status Flag If the user writes the SSPxBUF when a receive is already in progress (i.e., SSPxSR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write doesn't occur). If the user writes to the SSPxBUF when a transmit is already in progress (i.e., SSPxSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write doesn't occur) after 2 TCY after the SSPxBUF write. If SSPxBUF is rewritten within 2 TCY, the WCOL bit is set and SSPxBUF is updated. This may result in a corrupted transfer. DS39762F-page 304 2011 Microchip Technology Inc. 2011 Microchip Technology Inc. S R/W PEN SEN BF (SSPxSTAT<0>) SSPxIF SCLx SDAx A6 A5 A4 A3 A2 A1 3 4 5 Cleared in software 2 6 7 8 9 After Start condition, SEN cleared by hardware SSPxBUF written 1 D7 1 SCLx held low while CPU responds to SSPxIF ACK = 0 R/W = 0 SSPxBUF written with 7-bit address and R/W start transmit A7 Transmit Address to Slave 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 SSPxBUF is written in software Cleared in software service routine from MSSP interrupt 2 D6 Transmitting Data or Second Half of 10-bit Address P ACKSTAT in SSPxCON2 = 1 Cleared in software 9 ACK From slave, clear ACKSTAT bit (SSPxCON2<6>) FIGURE 20-23: SEN = 0 Write SSPxCON2<0> (SEN = 1), Start condition begins PIC18F97J60 FAMILY I 2CTM MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) DS39762F-page 305 DS39762F-page 306 S ACKEN SSPOV BF (SSPxSTAT<0>) SDAx = 0, SCLx = 1 while CPU responds to SSPxIF SSPxIF SCLx SDAx 1 A7 2 4 5 Cleared in software 3 6 A6 A5 A4 A3 A2 Transmit Address to Slave 7 A1 8 9 R/W = 1 ACK 2 3 5 6 7 8 D0 9 ACK 2 3 4 5 6 7 Cleared in software Set SSPxIF interrupt at end of Acknowledge sequence Data shifted in on falling edge of CLK 1 D7 D6 D5 D4 D3 D2 D1 Cleared in software Set SSPxIF at end of receive 9 ACK is not sent ACK P Set SSPxIF interrupt at end of Acknowledge sequence Bus master terminates transfer Set P bit (SSPxSTAT<4>) and SSPxIF PEN bit = 1 written here SSPOV is set because SSPxBUF is still full 8 D0 RCEN cleared automatically Set ACKEN, start Acknowledge sequence SDAx = ACKDT = 1 Receiving Data from Slave RCEN = 1, start next receive ACK from Master, SDAx = ACKDT = 0 Last bit is shifted into SSPxSR and contents are unloaded into SSPxBUF Cleared in software Set SSPxIF interrupt at end of receive 4 Cleared in software 1 D7 D6 D5 D4 D3 D2 D1 Receiving Data from Slave RCEN cleared automatically Master configured as a receiver by programming SSPxCON2<3> (RCEN = 1) FIGURE 20-24: SEN = 0 Write to SSPxBUF occurs here, ACK from Slave start XMIT Write to SSPxCON2<0> (SEN = 1), begin Start condition Write to SSPxCON2<4> to start Acknowledge sequence SDAx = ACKDT (SSPxCON2<5>) = 0 PIC18F97J60 FAMILY I 2CTM MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 20.4.12 ACKNOWLEDGE SEQUENCE TIMING 20.4.13 A Stop bit is asserted on the SDAx pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN (SSPxCON2<2>). At the end of a receive/transmit, the SCLx line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDAx line low. When the SDAx line is sampled low, the Baud Rate Generator is reloaded and counts down to `0'. When the Baud Rate Generator times out, the SCLx pin will be brought high and one TBRG (Baud Rate Generator rollover count) later, the SDAx pin will be deasserted. When the SDAx pin is sampled high while SCLx is high, the P bit (SSPxSTAT<4>) is set. A TBRG later, the PEN bit is cleared and the SSPxIF bit is set (Figure 20-26). An Acknowledge sequence is enabled by setting the Acknowledge Sequence Enable bit, ACKEN (SSPxCON2<4>). When this bit is set, the SCLx pin is pulled low and the contents of the Acknowledge data bit are presented on the SDAx pin. If the user wishes to generate an Acknowledge, then the ACKDT bit should be cleared. If not, the user should set the ACKDT bit before starting an Acknowledge sequence. The Baud Rate Generator then counts for one rollover period (TBRG) and the SCLx pin is deasserted (pulled high). When the SCLx pin is sampled high (clock arbitration), the Baud Rate Generator counts for TBRG. The SCLx pin is then pulled low. Following this, the ACKEN bit is automatically cleared, the Baud Rate Generator is turned off and the MSSP module then goes into Idle mode (Figure 20-25). 20.4.12.1 20.4.13.1 WCOL Status Flag If the user writes the SSPxBUF when a Stop sequence is in progress, then the WCOL bit is set and the contents of the buffer are unchanged (the write doesn't occur). WCOL Status Flag If the user writes the SSPxBUF when an Acknowledge sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write doesn't occur). FIGURE 20-25: STOP CONDITION TIMING ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, write to SSPxCON2 ACKEN = 1, ACKDT = 0 SDAx ACKEN automatically cleared TBRG ACK D0 SCLx TBRG 8 9 SSPxIF Cleared in software SSPxIF set at the end of receive Cleared in software SSPxIF set at the end of Acknowledge sequence Note: TBRG = one Baud Rate Generator period. FIGURE 20-26: STOP CONDITION RECEIVE OR TRANSMIT MODE SCLx = 1 for TBRG, followed by SDAx = 1 for TBRG after SDAx sampled high. P bit (SSPxSTAT<4>) is set. Write to SSPxCON2, set PEN Falling edge of 9th clock SCLx SDAx PEN bit (SSPxCON2<2>) is cleared by hardware and the SSPxIF bit is set TBRG ACK P TBRG TBRG TBRG SCLx brought high after TBRG SDAx asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period. 2011 Microchip Technology Inc. DS39762F-page 307 PIC18F97J60 FAMILY 20.4.14 SLEEP OPERATION 20.4.17 2 While in Sleep mode, the I C module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). 20.4.15 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. 20.4.16 MULTI-MASTER MODE In Multi-Master mode, the interrupt generation on the detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit (SSPxSTAT<4>) is set, or the bus is Idle, with both the S and P bits clear. When the bus is busy, enabling the MSSP interrupt will generate the interrupt when the Stop condition occurs. In multi-master operation, the SDAx line must be monitored for arbitration to see if the signal level is the expected output level. This check is performed in hardware with the result placed in the BCLxIF bit. The states where arbitration can be lost are: * * * * * Address Transfer Data Transfer A Start Condition A Repeated Start Condition An Acknowledge Condition MULTI -MASTER COMMUNICATION, BUS COLLISION AND BUS ARBITRATION Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDAx pin, arbitration takes place when the master outputs a `1' on SDAx, by letting SDAx float high and another master asserts a `0'. When the SCLx pin floats high, data should be stable. If the expected data on SDAx is a `1' and the data sampled on the SDAx pin = 0, then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLxIF and reset the I2C port to its Idle state (Figure 20-27). If a transmit was in progress when the bus collision occurred, the transmission is halted, the BF flag is cleared, the SDAx and SCLx lines are deasserted and the SSPxBUF can be written to. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. If a Start, Repeated Start, Stop or Acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the SDAx and SCLx lines are deasserted and the respective control bits in the SSPxCON2 register are cleared. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. The master will continue to monitor the SDAx and SCLx pins. If a Stop condition occurs, the SSPxIF bit will be set. A write to the SSPxBUF will start the transmission of data at the first data bit regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPxSTAT register, or the bus is Idle and the S and P bits are cleared. FIGURE 20-27: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCLx = 0 SDAx line pulled low by another source SDAx released by master Sample SDAx. While SCLx is high, data doesn't match what is driven by the master. Bus collision has occurred. SDAx SCLx Set bus collision interrupt (BCLxIF) BCLxIF DS39762F-page 308 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 20.4.17.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDAx or SCLx are sampled low at the beginning of the Start condition (Figure 20-28). SCLx is sampled low before SDAx is asserted low (Figure 20-29). During a Start condition, both the SDAx and the SCLx pins are monitored. If the SDAx pin is sampled low during this count, the BRG is reset and the SDAx line is asserted early (Figure 20-30). If, however, a `1' is sampled on the SDAx pin, the SDAx pin is asserted low at the end of the BRG count. The Baud Rate Generator is then reloaded and counts down to 0. If the SCLx pin is sampled as `0' during this time, a bus collision does not occur. At the end of the BRG count, the SCLx pin is asserted low. Note: If the SDAx pin is already low, or the SCLx pin is already low, then all of the following occur: * the Start condition is aborted; * the BCLxIF flag is set; and * the MSSP module is reset to its Idle state (Figure 20-28). The Start condition begins with the SDAx and SCLx pins deasserted. When the SDAx pin is sampled high, the Baud Rate Generator is loaded from SSPxADD<6:0> and counts down to 0. If the SCLx pin is sampled low while SDAx is high, a bus collision occurs, because it is assumed that another master is attempting to drive a data `1' during the Start condition. FIGURE 20-28: The reason that bus collision is not a factor during a Start condition is that no two bus masters can assert a Start condition at the exact same time. Therefore, one master will always assert SDAx before the other. This condition does not cause a bus collision because the two masters must be allowed to arbitrate the first address following the Start condition. If the address is the same, arbitration must be allowed to continue into the data portion, Repeated Start or Stop conditions. BUS COLLISION DURING START CONDITION (SDAx ONLY) SDAx goes low before the SEN bit is set. Set BCLxIF, S bit and SSPxIF set because SDAx = 0, SCLx = 1. SDAx SCLx Set SEN, enable Start condition if SDAx = 1, SCLx = 1 SEN cleared automatically because of bus collision. MSSP module reset into Idle state. SEN BCLxIF SDAx sampled low before Start condition. Set BCLxIF. S bit and SSPxIF set because SDAx = 0, SCLx = 1. SSPxIF and BCLxIF are cleared in software S SSPxIF SSPxIF and BCLxIF are cleared in software 2011 Microchip Technology Inc. DS39762F-page 309 PIC18F97J60 FAMILY FIGURE 20-29: BUS COLLISION DURING START CONDITION (SCLx = 0) SDAx = 0, SCLx = 1 TBRG TBRG SDAx Set SEN, enable Start sequence if SDAx = 1, SCLx = 1 SCLx SCLx = 0 before SDAx = 0, bus collision occurs. Set BCLxIF. SEN SCLx = 0 before BRG time-out, bus collision occurs. Set BCLxIF. BCLxIF Interrupt cleared in software S `0' `0' SSPxIF `0' `0' FIGURE 20-30: BRG RESET DUE TO SDAx ARBITRATION DURING START CONDITION SDAx = 0, SCLx = 1 Set S Less than TBRG SDAx SCLx Set SSPxIF TBRG SDAx pulled low by other master. Reset BRG and assert SDAx. S SCLx pulled low after BRG time-out SEN Set SEN, enable Start sequence if SDAx = 1, SCLx = 1 `0' BCLxIF S SSPxIF SDAx = 0, SCLx = 1, set SSPxIF DS39762F-page 310 Interrupts cleared in software 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 20.4.17.2 Bus Collision During a Repeated Start Condition reloaded and begins counting. If SDAx goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDAx at exactly the same time. During a Repeated Start condition, a bus collision occurs if: a) b) If SCLx goes from high-to-low before the BRG times out and SDAx has not already been asserted, a bus collision occurs. In this case, another master is attempting to transmit a data `1' during the Repeated Start condition (see Figure 20-32). A low level is sampled on SDAx when SCLx goes from low level to high level. SCLx goes low before SDAx is asserted low, indicating that another master is attempting to transmit a data `1'. If, at the end of the BRG time-out, both SCLx and SDAx are still high, the SDAx pin is driven low and the BRG is reloaded and begins counting. At the end of the count, regardless of the status of the SCLx pin, the SCLx pin is driven low and the Repeated Start condition is complete. When the user deasserts SDAx and the pin is allowed to float high, the BRG is loaded with SSPxADD<6:0> and counts down to 0. The SCLx pin is then deasserted and when sampled high, the SDAx pin is sampled. If SDAx is low, a bus collision has occurred (i.e., another master is attempting to transmit a data `0', see Figure 20-31). If SDAx is sampled high, the BRG is FIGURE 20-31: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDAx SCLx Sample SDAx when SCLx goes high. If SDAx = 0, set BCLxIF and release SDAx and SCLx. RSEN BCLxIF Cleared in software S `0' SSPxIF `0' FIGURE 20-32: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDAx SCLx BCLxIF SCLx goes low before SDAx, set BCLxIF. Release SDAx and SCLx. Interrupt cleared in software RSEN S `0' SSPxIF 2011 Microchip Technology Inc. DS39762F-page 311 PIC18F97J60 FAMILY 20.4.17.3 Bus Collision During a Stop Condition The Stop condition begins with SDAx asserted low. When SDAx is sampled low, the SCLx pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPxADD<6:0> and counts down to 0. After the BRG times out, SDAx is sampled. If SDAx is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data `0' (Figure 20-33). If the SCLx pin is sampled low before SDAx is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data `0' (Figure 20-34). Bus collision occurs during a Stop condition if: a) b) After the SDAx pin has been deasserted and allowed to float high, SDAx is sampled low after the BRG has timed out. After the SCLx pin is deasserted, SCLx is sampled low before SDAx goes high. FIGURE 20-33: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG SDAx sampled low after TBRG, set BCLxIF TBRG SDAx SDAx asserted low SCLx PEN BCLxIF P `0' SSPxIF `0' FIGURE 20-34: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDAx Assert SDAx SCLx SCLx goes low before SDAx goes high, set BCLxIF PEN BCLxIF P `0' SSPxIF `0' DS39762F-page 312 2011 Microchip Technology Inc. PIC18F97J60 FAMILY TABLE 20-4: Name REGISTERS ASSOCIATED WITH I2CTM OPERATION Bit 7 INTCON Bit 6 GIE/GIEH PEIE/GIEL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 71 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 71 71 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP PIR2 OSCFIF CMIF ETHIF r BCL1IF -- TMR3IF CCP2IF 71 PIE2 OSCFIE CMIE ETHIE r BCL1IE -- TMR3IE CCP2IE 71 IPR2 OSCFIP CMIP ETHIP r BCL1IP -- TMR3IP CCP2IP 71 PIR3 SSP2IF(1) BCL2IF(1) RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 71 PIE3 SSP2IE(1) BCL2IE (1) RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 71 IPR3 SSP2IP(1) BCL2IP(1) RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 71 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 71 TRISD4 TRISD3 TRISD2 TRISD1 TRISC TRISD7 TRISD5 (1) TRISD0 71 SSP1BUF MSSP1 Receive Buffer/Transmit Register 70 SSP1ADD MSSP1 Address Register (I2CTM Slave mode), MSSP1 Baud Rate Reload Register (I2C Master mode) 73 TRISD TRISD6 (1) SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 70 SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 70 GCEN ACKSTAT ADMSK5(2) ADMSK4(2) ADMSK3(2) ADMSK2(2) ADMSK1(2) SEN 70 SMP CKE D/A P S R/W UA BF 70 SSP1STAT SSP2BUF MSSP2 Receive Buffer/Transmit Register 70 SSP2ADD MSSP2 Address Register (I2C Slave mode), MSSP2 Baud Rate Reload Register (I2C Master mode) 73 SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 73 GCEN ACKSTAT ADMSK5(2) ADMSK4(2) ADMSK3(2) ADMSK2(2) ADMSK1(2) SEN 73 BF 73 SSP2STAT Legend: Note 1: 2: SMP CKE D/A P S R/W UA 73 -- = unimplemented, read as `0', r = reserved. Shaded cells are not used by the MSSP module in I2CTM mode. These bits are only available in 100-pin devices; otherwise, they are unimplemented and read as `0'. Alternate bit definitions in I2CTM Slave mode. 2011 Microchip Technology Inc. DS39762F-page 313 PIC18F97J60 FAMILY NOTES: DS39762F-page 314 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 21.0 ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is one of two serial I/O modules. (Generically, the EUSART is also known as a Serial Communications Interface or SCI.) The EUSART can be configured as a full-duplex asynchronous system that can communicate with peripheral devices, such as CRT terminals and personal computers. It can also be configured as a half-duplex synchronous system that can communicate with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs, etc. The Enhanced USART module implements additional features, including automatic baud rate detection and calibration, automatic wake-up on Sync Break reception and 12-bit Break character transmit. These features make it ideally suited for use in Local Interconnect Network bus (LIN/J2602 bus) systems. The 64-pin devices of the PIC18F97J60 family are equipped with one EUSART module, referred to as EUSART1. The 80-pin and 100-pin devices each have two independent EUSART modules, referred to as EUSART1 and EUSART2. They can be configured in the following modes: * Asynchronous (full-duplex) with: - Auto-Wake-up on Character Reception - Auto-Baud Calibration - 12-Bit Break Character Transmission * Synchronous - Master (half-duplex) with Selectable Clock Polarity * Synchronous - Slave (half-duplex) with Selectable Clock Polarity 2011 Microchip Technology Inc. The pins of EUSART1 and EUSART2 are multiplexed with the functions of PORTC (RC6/TX1/CK1 and RC7/RX1/DT1) and PORTG (RG1/TX2/CK2 and RG2/RX2/DT2), respectively. In order to configure these pins as an EUSART: * For EUSART1: - SPEN bit (RCSTA1<7>) must be set (= 1) - TRISC<7> bit must be set (= 1) - TRISC<6> bit must be cleared (= 0) for Asynchronous and Synchronous Master modes - TRISC<6> bit must be set (= 1) for Synchronous Slave mode * For EUSART2: - SPEN bit (RCSTA2<7>) must be set (= 1) - TRISG<2> bit must be set (= 1) - TRISG<1> bit must be cleared (= 0) for Asynchronous and Synchronous Master modes - TRISG<1> bit must be set (= 1) for Synchronous Slave mode Note: The EUSARTx control will automatically reconfigure the pin from input to output as needed. The operation of each Enhanced USART module is controlled through three registers: * Transmit Status and Control (TXSTAx) * Receive Status and Control (RCSTAx) * Baud Rate Control (BAUDCONx) These are detailed on the following pages in Register 21-1, Register 21-2 and Register 21-3, respectively. Note: Throughout this section, references to register and bit names that may be associated with a specific EUSART module are referred to generically by the use of `x' in place of the specific module number. Thus, "RCSTAx" might refer to the Receive Status register for either EUSART1 or EUSART2. DS39762F-page 315 PIC18F97J60 FAMILY REGISTER 21-1: R/W-0 CSRC TXSTAx: TRANSMIT STATUS AND CONTROL REGISTER x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0 TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don't care. Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-Bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit(1) 1 = Transmit is enabled 0 = Transmit is disabled bit 4 SYNC: EUSARTx Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission is completed Synchronous mode: Don't care. bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode. bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR is empty 0 = TSR is full bit 0 TX9D: 9th bit of Transmit Data Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Sync mode. DS39762F-page 316 2011 Microchip Technology Inc. PIC18F97J60 FAMILY REGISTER 21-2: RCSTAx: RECEIVE STATUS AND CONTROL REGISTER x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port is enabled (configures RXx/DTx and TXx/CKx pins as serial port pins) 0 = Serial port is disabled (held in Reset) bit 6 RX9: 9-Bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don't care. Synchronous mode - Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode - Slave: Don't care. bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit, CREN, is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit 9-Bit Asynchronous mode (RX9 = 1): 1 = Enables address detection, enables interrupt and loads the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit 9-Bit Asynchronous mode (RX9 = 0): Don't care. bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREGx register and receiving next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit, CREN) 0 = No overrun error bit 0 RX9D: 9th bit of Received Data This can be an address/data bit or a parity bit and must be calculated by user firmware. 2011 Microchip Technology Inc. DS39762F-page 317 PIC18F97J60 FAMILY REGISTER 21-3: BAUDCONx: BAUD RATE CONTROL REGISTER x R/W-0 R-1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 ABDOVF RCIDL RXDTP TXCKP BRG16 -- WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit 1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software) 0 = No BRG rollover has occurred bit 6 RCIDL: Receive Operation Idle Status bit 1 = Receive operation is Idle 0 = Receive operation is active bit 5 RXDTP: Received Data Polarity Select bit Asynchronous mode: 1 = Receive data (RXx) is inverted. Idle state is a low level. 0 = No inversion of receive data (RXx). Idle state is a high level. Synchronous modes: 1 = Data (DTx) is inverted; Idle state is a low level 0 = No inversion of data (DTx); Idle state is a high level bit 4 TXCKP: Clock and Data Polarity Select bit Asynchronous mode: 1 = Transmit data (TXx) is inverted; Idle state is a low level 0 = No inversion of transmit data (TXx); Idle state is a high level Synchronous modes: 1 = Idle state for clock (CKx) is a high level 0 = Idle state for clock (CKx) is a low level bit 3 BRG16: 16-Bit Baud Rate Register Enable bit 1 = 16-bit Baud Rate Generator - SPBRGHx and SPBRGx 0 = 8-bit Baud Rate Generator - SPBRGx only, SPBRGHx value ignored (Compatible mode) bit 2 Unimplemented: Read as `0' bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = EUSARTx will continue to sample the RXx pin - interrupt generated on falling edge; bit cleared in hardware on following rising edge 0 = RXx pin not monitored or rising edge detected Synchronous mode: Unused in this mode. bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Enable baud rate measurement on the next character. Requires reception of a Sync field (55h); cleared in hardware upon completion. 0 = Baud rate measurement disabled or completed Synchronous mode: Unused in this mode. DS39762F-page 318 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 21.1 Baud Rate Generator (BRG) The BRG is a dedicated, 8-bit or 16-bit generator that supports both the Asynchronous and Synchronous modes of the EUSARTx. By default, the BRG operates in 8-bit mode; setting the BRG16 bit (BAUDCONx<3>) selects 16-bit mode. The SPBRGHx:SPBRGx register pair controls the period of a free-running timer. In Asynchronous mode, bits BRGH (TXSTAx<2>) and BRG16 (BAUDCONx<3>) also control the baud rate. In Synchronous mode, BRGH is ignored. Table 21-1 shows the formula for computation of the baud rate for different EUSARTx modes which only apply in Master mode (internally generated clock). Given the desired baud rate and FOSC, the nearest integer value for the SPBRGHx:SPBRGx registers can be calculated using the formulas in Table 21-1. From this, the error in baud rate can be determined. An example calculation is shown in Example 21-1. Typical baud rates and error values for the various Asynchronous modes are shown in Table 21-2. It may be advantageous to use TABLE 21-1: the high baud rate (BRGH = 1), or the 16-bit BRG to reduce the baud rate error, or achieve a slow baud rate for a fast oscillator frequency. Writing a new value to the SPBRGHx:SPBRGx registers causes the BRG timer to be reset (or cleared). This ensures that the BRG does not wait for a timer overflow before outputting the new baud rate. 21.1.1 OPERATION IN POWER-MANAGED MODES The device clock is used to generate the desired baud rate. When one of the power-managed modes is entered, the new clock source may be operating at a different frequency. This may require an adjustment to the value in the SPBRGx register pair. 21.1.2 SAMPLING The data on the RXx pin (either RC7/RX1/DT1 or RG2/RX2/DT2) is sampled three times by a majority detect circuit to determine if a high or a low level is present at the RXx pin. BAUD RATE FORMULAS Configuration Bits BRG/EUSARTx Mode Baud Rate Formula 8-bit/Asynchronous FOSC/[64 (n + 1)] SYNC BRG16 BRGH 0 0 0 0 0 1 8-bit/Asynchronous 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous 1 1 x 16-bit/Synchronous FOSC/[16 (n + 1)] FOSC/[4 (n + 1)] Legend: x = Don't care, n = value of SPBRGHx:SPBRGx register pair 2011 Microchip Technology Inc. DS39762F-page 319 PIC18F97J60 FAMILY EQUATION 21-1: CALCULATING BAUD RATE ERROR For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: Desired Baud Rate = FOSC/(64 ([SPBRGHx:SPBRGx] + 1)) Solving for SPBRGHx:SPBRGx: X = ((FOSC/Desired Baud Rate)/64) - 1 = ((16000000/9600)/64) - 1 = [25.042] = 25 Calculated Baud Rate=16000000/(64 (25 + 1)) = 9615 Error = (Calculated Baud Rate - Desired Baud Rate)/Desired Baud Rate = (9615 - 9600)/9600 = 0.16% TABLE 21-2: Name REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: TXSTAx CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 71 RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 71 RCIDL RXDTP TXCKP BRG16 -- WUE ABDEN 72 BAUDCONx ABDOVF SPBRGHx EUSARTx Baud Rate Generator Register High Byte 72 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 72 Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the BRG. DS39762F-page 320 2011 Microchip Technology Inc. PIC18F97J60 FAMILY TABLE 21-3: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRG16 = 0, BRGH = 0 BAUD RATE (K) FOSC = 41.667 MHz Actual Rate (K) % Error FOSC = 31.25 MHz SPBRG Actual Value Rate (K) (decimal) % Error FOSC = 25.000 MHz SPBRG Actual Value Rate (K) (decimal) % Error FOSC = 20.833 MHz SPBRG Actual Value Rate (K) (decimal) % Error SPBRG Value (decimal) 0.3 -- -- -- -- -- -- -- -- -- -- -- -- 1.2 -- -- -- -- -- -- -- -- -- 1.271 5.96 255 135 2.4 2.543 5.96 255 2.405 0.22 202 2.396 -0.15 162 2.393 -0.27 9.6 9.574 -0.27 67 9.574 -0.27 50 9.527 -0.76 40 9.574 -0.27 33 19.2 19.148 -0.27 33 19.531 1.73 24 19.531 1.73 19 19.147 -0.27 16 57.6 59.186 2.75 10 61.035 5.96 7 55.804 -3.12 6 54.253 -5.81 5 115.2 108.508 -5.81 5 122.070 5.96 3 130.208 13.03 2 108.505 -5.81 2 SYNC = 0, BRG16 = 0, BRGH = 0 BAUD RATE (K) FOSC = 13.889 MHz Actual Rate (K) % Error FOSC = 6.250 MHz SPBRG Actual Value Rate (K) (decimal) % Error FOSC = 4.167 MHz SPBRG Actual Value Rate (K) (decimal) % Error SPBRG Value (decimal) 0.3 -- -- -- -- -- -- 0.300 0.01 216 1.2 1.198 -0.08 180 1.206 0.47 80 1.206 0.48 53 2.4 2.411 0.47 89 2.382 -0.76 40 2.411 0.48 26 9.6 9.435 -1.71 22 9.766 1.73 9 9.301 -3.11 6 19.2 19.279 2.75 10 19.531 1.73 4 21.703 13.04 2 57.6 54.254 -5.81 3 48.828 -15.23 1 65.109 13.04 0 115.2 108.508 -5.81 1 97.656 -15.23 0 65.109 -43.48 0 SYNC = 0, BRG16 = 0, BRGH = 1 BAUD RATE (K) 0.3 1.2 FOSC = 41.667 MHz Actual Rate (K) % Error -- -- -- -- FOSC = 31.25 MHz SPBRG Actual Value Rate (K) (decimal) -- -- -- -- % Error -- -- FOSC = 25.000 MHz SPBRG Actual Value Rate (K) (decimal) -- -- -- -- % Error -- -- FOSC = 20.833 MHz SPBRG Actual Value Rate (K) (decimal) -- -- -- -- % Error SPBRG Value (decimal) -- -- -- -- 2.4 -- -- -- -- -- -- -- -- -- -- -- -- 9.6 10.172 5.96 255 9.621 0.22 202 9.586 -0.15 162 9.573 -0.27 135 19.2 19.148 -0.27 135 19.148 -0.27 101 19.290 0.47 80 19.147 -0.27 67 57.6 57.871 0.47 44 57.445 -0.27 33 57.870 0.47 26 56.611 -1.72 22 115.2 113.226 -1.71 22 114.890 -0.27 16 111.607 -3.12 13 118.369 2.75 10 SYNC = 0, BRG16 = 0, BRGH = 1 BAUD RATE (K) 0.3 1.2 FOSC = 13.889 MHz Actual Rate (K) % Error -- -- -- -- FOSC = 6.250 MHz SPBRG Actual Value Rate (K) (decimal) -- -- -- -- % Error FOSC = 4.167 MHz SPBRG Actual Value Rate (K) (decimal) % Error SPBRG Value (decimal) -- -- -- -- -- 1.200 -- 0.01 -- 216 108 2.4 -- -- -- 2.396 -0.15 162 2.389 -0.44 9.6 9.645 0.47 89 9.527 -0.76 40 9.645 0.48 26 19.2 19.290 0.47 44 19.531 1.73 19 18.603 -3.11 13 57.6 57.871 0.47 14 55.804 -3.12 6 52.088 -9.57 4 115.2 108.508 -5.81 7 130.208. 13.03 2 130.219 13.04 1 2011 Microchip Technology Inc. DS39762F-page 321 PIC18F97J60 FAMILY TABLE 21-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRG16 = 1, BRGH = 0 BAUD RATE (K) FOSC = 41.667 MHz FOSC = 31.25 MHz SPBRG Actual Value Rate (K) (decimal) FOSC = 25.000 MHz SPBRG Actual Value Rate (K) (decimal) FOSC = 20.833 MHz SPBRG Actual Value Rate (K) (decimal) % Error SPBRG Value (decimal) 0.300 0.00 4339 1.200 0.00 1084 650 2.398 -0.09 542 -0.15 162 9.574 -0.27 135 0.47 80 19.148 -0.27 67 Actual Rate (K) % Error 0.3 0.300 0.00 8680 0.300 0.00 6509 0.300 0.01 5207 1.2 1.200 0.01 2169 1.200 -0.02 1627 1.200 0.01 1301 2.4 2.400 0.01 1084 2.399 -0.02 813 2.400 0.01 9.6 9.609 0.10 270 9.621 0.22 202 9.586 19.2 19.148 -0.27 135 19.148 -0.27 101 19.290 % Error % Error 57.6 57.871 0.47 44 57.444 -0.27 33 57.870 0.47 26 56.611 -1.72 22 115.2 113.226 -1.71 22 114.890 -0.27 16 111.607 -3.12 13 118.369 2.75 10 SYNC = 0, BRG16 = 1, BRGH = 0 BAUD RATE (K) FOSC = 13.889 MHz FOSC = 6.250 MHz SPBRG Actual Value Rate (K) (decimal) FOSC = 4.167 MHz SPBRG Actual Value Rate (K) (decimal) SPBRG Value (decimal) Actual Rate (K) % Error 0.3 0.300 -0.02 2893 0.300 0.01 1301 0.300 0.01 867 1.2 1.201 0.05 722 1.198 -0.15 325 1.200 0.01 216 2.4 2.398 -0.08 361 2.396 -0.15 162 2.389 -0.44 108 9.6 9.645 0.47 89 9.527 -0.76 40 9.646 0.48 26 19.2 19.290 0.47 44 19.531 1.73 19 18.603 -3.11 13 57.6 57.871 0.47 14 55.804 -3.12 6 52.088 -9.57 4 115.2 108.508 -5.81 7 130.208 13.03 2 130.218 13.04 1 % Error % Error SYNC = 0, BRG16 = 1, BRGH = 1 or SYNC = 1, BRG16 = 1 BAUD RATE (K) FOSC = 41.667 MHz FOSC = 31.25 MHz SPBRG Actual Value Rate (K) (decimal) FOSC = 25.000 MHz SPBRG Actual Value Rate (K) (decimal) FOSC = 20.833 MHz SPBRG Actual Value Rate (K) (decimal) Actual Rate (K) % Error 0.3 0.300 0.00 34722 0.300 0.00 26041 0.300 0.00 20832 1.2 1.200 0.00 8680 1.200 0.01 6509 1.200 0.01 5207 % Error % Error % Error SPBRG Value (decimal) 0.300 0.00 17360 1.200 0.00 4339 2169 2.4 2.400 0.01 4339 2.400 0.01 3254 2.400 0.01 2603 2.400 0.00 9.6 9.601 0.01 1084 9.598 -0.02 813 9.601 0.01 650 9.592 -0.09 542 19.2 19.184 -0.08 542 19.195 -0.02 406 19.172 -0.15 325 19.219 0.10 270 57.6 57.551 -0.08 180 57.445 -0.27 135 57.339 -0.45 108 57.869 0.47 89 115.2 115.742 0.47 89 114.890 -0.27 67 115.741 0.47 53 115.739 0.47 44 SYNC = 0, BRG16 = 1, BRGH = 1 or SYNC = 1, BRG16 = 1 BAUD RATE (K) FOSC = 13.889 MHz Actual Rate (K) % Error FOSC = 6.250 MHz SPBRG Actual Value Rate (K) (decimal) % Error FOSC = 4.167 MHz SPBRG Actual Value Rate (K) (decimal) % Error SPBRG Value (decimal) 0.3 0.300 0.00 11573 0.300 0.01 5207 0.300 -0.01 3472 1.2 1.200 -0.02 2893 1.200 0.01 1301 1.200 0.01 867 2.4 2.400 -0.02 1446 2.400 0.01 650 2.400 0.01 433 9.6 9.592 -0.08 361 9.586 -0.15 162 9.557 -0.44 108 19.2 19.184 -0.08 180 19.290 0.47 80 19.292 0.48 53 57.6 57.870 0.47 59 57.870 0.47 26 57.875 0.48 17 115.2 115.742 0.47 29 111.607 -3.12 13 115.750 0.48 8 DS39762F-page 322 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 21.1.3 AUTO-BAUD RATE DETECT The Enhanced USARTx module supports the automatic detection and calibration of baud rate. This feature is active only in Asynchronous mode and while the WUE bit is clear. The automatic baud rate measurement sequence (Figure 21-1) begins whenever a Start bit is received and the ABDEN bit is set. The calculation is self-averaging. While the ABD sequence takes place, the EUSARTx state machine is held in Idle. The RCxIF interrupt is set once the fifth rising edge on RXx is detected. The value in the RCREGx needs to be read to clear the RCxIF interrupt. The contents of RCREGx should be discarded. Note 1: If the WUE bit is set with the ABDEN bit, Auto-Baud Rate Detection will occur on the byte following the Break character. 2: It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source. Some combinations of oscillator frequency and EUSARTx baud rates are not possible due to bit error rates. Overall system timing and communication baud rates must be taken into consideration when using the Auto-Baud Rate Detection feature. In the Auto-Baud Rate Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RXx signal, the RXx signal is timing the BRG. In ABD mode, the internal Baud Rate Generator is used as a counter to time the bit period of the incoming serial byte stream. Once the ABDEN bit is set, the state machine will clear the BRG and look for a Start bit. The Auto-Baud Rate Detect must receive a byte with the value 55h (ASCII "U", which is also the LIN/J2602 bus Sync character) in order to calculate the proper bit rate. The measurement is taken over both a low and high bit time in order to minimize any effects caused by asymmetry of the incoming signal. After a Start bit, the SPBRGx begins counting up, using the preselected clock source on the first rising edge of RXx. After eight bits on the RXx pin or the fifth rising edge, an accumulated value totalling the proper BRG period is left in the SPBRGHx:SPBRGx register pair. Once the 5th edge is seen (this should correspond to the Stop bit), the ABDEN bit is automatically cleared. If a rollover of the BRG occurs (an overflow from FFFFh to 0000h), the event is trapped by the ABDOVF status bit (BAUDCONx<7>). It is set in hardware by BRG rollovers and can be set or cleared by the user in software. ABD mode remains active after rollover events and the ABDEN bit remains set (Figure 21-2). While calibrating the baud rate period, the BRG registers are clocked at 1/8th the preconfigured clock rate. Note that the BRG clock will be configured by the BRG16 and BRGH bits. Independent of the BRG16 bit setting, both the SPBRGx and SPBRGHx will be used as a 16-bit counter. This allows the user to verify that no carry occurred for 8-bit modes by checking for 00h in the SPBRGHx register. Refer to Table 21-4 for counter clock rates to the BRG. 2011 Microchip Technology Inc. TABLE 21-4: BRG COUNTER CLOCK RATES BRG16 BRGH BRG Counter Clock 0 0 FOSC/512 0 1 FOSC/128 1 0 FOSC/128 1 1 FOSC/32 Note: During the ABD sequence, SPBRGx and SPBRGHx are both used as a 16-bit counter, independent of the BRG16 setting. 21.1.3.1 ABD and EUSARTx Transmission Since the BRG clock is reversed during ABD acquisition, the EUSARTx transmitter cannot be used during ABD. This means that whenever the ABDEN bit is set, TXREGx cannot be written to. Users should also ensure that ABDEN does not become set during a transmit sequence. Failing to do this may result in unpredictable EUSARTx operation. DS39762F-page 323 PIC18F97J60 FAMILY FIGURE 21-1: BRG Value AUTOMATIC BAUD RATE CALCULATION XXXXh 0000h 001Ch Start RXx pin Edge #1 Bit 1 Bit 0 Edge #2 Bit 3 Bit 2 Edge #3 Bit 5 Bit 4 Edge #4 Bit 7 Bit 6 Edge #5 Stop Bit BRG Clock Auto-Cleared Set by User ABDEN bit RCxIF bit (Interrupt) Read RCREGx SPBRGx XXXXh 1Ch SPBRGHx XXXXh 00h Note: The ABD sequence requires the EUSARTx module to be configured in Asynchronous mode and WUE = 0. FIGURE 21-2: BRG OVERFLOW SEQUENCE BRG Clock ABDEN bit RXx pin Start Bit 0 ABDOVF bit FFFFh BRG Value DS39762F-page 324 XXXXh 0000h 0000h 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 21.2 EUSARTx Asynchronous Mode The Asynchronous mode of operation is selected by clearing the SYNC bit (TXSTAx<4>). In this mode, the EUSARTx uses standard Non-Return-to-Zero (NRZ) format (one Start bit, eight or nine data bits and one Stop bit). The most common data format is 8 bits. An on-chip, dedicated 8-bit/16-bit Baud Rate Generator can be used to derive standard baud rate frequencies from the oscillator. The EUSARTx transmits and receives the LSb first. The EUSARTx module's transmitter and receiver are functionally independent but use the same data format and baud rate. The Baud Rate Generator produces a clock, either x16 or x64 of the bit shift rate, depending on the BRGH and BRG16 bits (TXSTAx<2> and BAUDCONx<3>). Parity is not supported by the hardware but can be implemented in software and stored as the 9th data bit. The TXCKP (BAUDCONx<4>) and RXDTP (BAUDCONx<5>) bits allow the TXx and RXx signals to be inverted (polarity reversed). Devices that buffer signals between TTL and RS-232 levels also invert the signal. Setting the TXCKP and RXDTP bits allows for the use of circuits that provide buffering without inverting the signal. When operating in Asynchronous mode, the EUSARTx module consists of the following important elements: * * * * * * * Baud Rate Generator Sampling Circuit Asynchronous Transmitter Asynchronous Receiver Auto-Wake-up on Sync Break Character 12-Bit Break Character Transmit Auto-Baud Rate Detection 21.2.1 EUSARTx ASYNCHRONOUS TRANSMITTER The EUSARTx transmitter block diagram is shown in Figure 21-3. The heart of the transmitter is the Transmit (Serial) Shift Register (TSR). The Shift register obtains its data from the Read/Write Transmit Buffer register, TXREGx. The TXREGx register is loaded with data in software. The TSR register is not loaded until the Stop bit has been transmitted from the previous load. As soon as the Stop bit is transmitted, the TSR is loaded with new data from the TXREGx register (if available). 2011 Microchip Technology Inc. Once the TXREGx register transfers the data to the TSR register (occurs in one TCY), the TXREGx register is empty and the TXxIF flag bit is set. This interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TXxIE. TXxIF will be set regardless of the state of TXxIE; it cannot be cleared in software. TXxIF is also not cleared immediately upon loading TXREGx, but becomes valid in the second instruction cycle following the load instruction. Polling TXxIF, immediately following a load of TXREGx, will return invalid results. While TXxIF indicates the status of the TXREGx register, another bit, TRMT (TXSTAx<1>), shows the status of the TSR register. TRMT is a read-only bit which is set when the TSR register is empty. No interrupt logic is tied to this bit so the user has to poll this bit in order to determine if the TSR register is empty. Note 1: The TSR register is not mapped in data memory, so it is not available to the user. 2: Flag bit, TXxIF, is set when enable bit TXEN is set. To set up an Asynchronous Transmission: 1. 2. 3. 4. 5. 6. 7. 8. 9. Initialize the SPBRGHx:SPBRGx registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. Enable the asynchronous serial port by clearing the SYNC bit and setting bit, SPEN. If the signal from the TXx pin is to be inverted, set the TXCKP bit. If interrupts are desired, set enable bit, TXxIE. If 9-bit transmission is desired, set transmit bit, TX9. Can be used as address/data bit. Enable the transmission by setting the TXEN bit which will also set bit, TXxIF. If 9-bit transmission is selected, the ninth bit should be loaded in bit, TX9D. Load data to the TXREGx register (starts transmission). If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. DS39762F-page 325 PIC18F97J60 FAMILY FIGURE 21-3: EUSARTx TRANSMIT BLOCK DIAGRAM Data Bus TXxIF TXREGx Register TXxIE 8 MSb LSb (8) Pin Buffer and Control 0 TSR Register TXx pin Interrupt TXEN Baud Rate CLK TRMT SPEN TXCKP BRG16 SPBRGHx SPBRGx TX9 Baud Rate Generator FIGURE 21-4: TX9D ASYNCHRONOUS TRANSMISSION, TXCKP = 0 (TXx NOT INVERTED) Write to TXREGx BRG Output (Shift Clock) Word 1 TXx (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXxIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) FIGURE 21-5: 1 TCY Word 1 Transmit Shift Reg ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK), TXCKP = 0 (TXx NOT INVERTED) Write to TXREGx BRG Output (Shift Clock) Word 1 TXx (pin) TXxIF bit (Interrupt Reg. Flag) TRMT bit (Transmit Shift Reg. Empty Flag) Word 2 Start bit bit 0 1 TCY bit 1 bit 7/8 Stop bit Start bit bit 0 Word 2 Word 1 1 TCY Word 1 Transmit Shift Reg. Word 2 Transmit Shift Reg. Note: This timing diagram shows two consecutive transmissions. DS39762F-page 326 2011 Microchip Technology Inc. PIC18F97J60 FAMILY TABLE 21-5: Name INTCON REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Bit 7 Bit 6 Bit 5 GIE/GIEH PEIE/GIEL TMR0IE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: INT0IE RBIE TMR0IF INT0IF RBIF 69 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 71 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 71 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 71 PIR3 SSP2IF BCL2IF RC2IF TX2IF(1) TMR4IF CCP5IF CCP4IF CCP3IF 71 PIE3 SSP2IE BCL2IE RC2IE TX2IE(1) TMR4IE CCP5IE CCP4IE CCP3IE 71 IPR3 SSP2IP BCL2IP RC2IP TX2IP(1) TMR4IP CCP5IP CCP4IP CCP3IP 71 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 71 RCSTAx TXREGx TXSTAx BAUDCONx EUSARTx Transmit Register 71 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 71 ABDOVF RCIDL RXDTP TXCKP BRG16 -- WUE ABDEN 72 SPBRGHx EUSARTx Baud Rate Generator Register High Byte 72 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 72 Legend: -- = unimplemented locations read as `0'. Shaded cells are not used for asynchronous transmission. Note 1: These bits are only available in 80-pin and 100-pin devices; otherwise, they are unimplemented and read as `0'. 2011 Microchip Technology Inc. DS39762F-page 327 PIC18F97J60 FAMILY 21.2.2 EUSARTx ASYNCHRONOUS RECEIVER The receiver block diagram is shown in Figure 21-6. The data is received on the RXx pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would typically be used in RS-232 systems. The RXDTP bit (BAUDCON<5>) allows the RXx signal to be inverted (polarity reversed). Devices that buffer signals from RS-232 to TTL levels also perform an inversion of the signal (when RS-232 = positive, TTL = 0). Inverting the polarity of the RXx pin data by setting the RXDTP bit allows for the use of circuits that provide buffering without inverting the signal. To set up an Asynchronous Reception: 1. Initialize the SPBRGHx:SPBRGx registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Enable the asynchronous serial port by clearing the SYNC bit and setting bit, SPEN. 3. If the signal at the RXx pin is to be inverted, set the RXDTP bit. 4. If interrupts are desired, set enable bit, RCxIE. 5. If 9-bit reception is desired, set bit, RX9. 6. Enable the reception by setting bit, CREN. 7. Flag bit, RCxIF, will be set when reception is complete and an interrupt will be generated if enable bit, RCxIE, was set. 8. Read the RCSTAx register to get the 9th bit (if enabled) and determine if any error occurred during reception. 9. Read the 8-bit received data by reading the RCREGx register. 10. If any error occurred, clear the error by clearing enable bit, CREN. 11. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. DS39762F-page 328 21.2.3 SETTING UP 9-BIT MODE WITH ADDRESS DETECT This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with Address Detect Enable: 1. Initialize the SPBRGHx:SPBRGx registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. 3. If the signal at the RXx pin is to be inverted, set the RXDTP bit. If the signal from the TXx pin is to be inverted, set the TXCKP bit. 4. If interrupts are required, set the RCEN bit and select the desired priority level with the RCxIP bit. 5. Set the RX9 bit to enable 9-bit reception. 6. Set the ADDEN bit to enable address detect. 7. Enable reception by setting the CREN bit. 8. The RCxIF bit will be set when reception is complete. The interrupt will be Acknowledged if the RCxIE and GIE bits are set. 9. Read the RCSTAx register to determine if any error occurred during reception, as well as read Bit 9 of data (if applicable). 10. Read RCREGx to determine if the device is being addressed. 11. If any error occurred, clear the CREN bit. 12. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and interrupt the CPU. 2011 Microchip Technology Inc. PIC18F97J60 FAMILY FIGURE 21-6: EUSARTx RECEIVE BLOCK DIAGRAM CREN FERR OERR x64 Baud Rate CLK BRG16 SPBRGHx 64 or 16 or 4 SPBRGx Baud Rate Generator RSR Register MSb Stop (8) 7 LSb 1 0 Start RX9 Pin Buffer and Control Data Recovery RXx RX9D RCREGx Register FIFO RXDTP SPEN 8 Interrupt FIGURE 21-7: Data Bus RCxIF RCxIE ASYNCHRONOUS RECEPTION, RXDTP = 0 (RXx NOT INVERTED) Start bit RXx (pin) bit 0 bit 1 Start bit bit 7/8 Stop bit Rcv Shift Reg Rcv Buffer Reg bit 0 Word 1 RCREGx Read Rcv Buffer Reg RCREGx bit 7/8 Stop bit Start bit bit 7/8 Stop bit Word 2 RCREGx RCxIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RXx input. The RCREGx (Receive Buffer) is read after the third word, causing the OERR (Overrun Error) bit to be set. TABLE 21-6: Name INTCON REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Bit 7 Bit 6 Bit 5 GIE/GIEH PEIE/GIEL TMR0IE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: INT0IE RBIE TMR0IF INT0IF RBIF 69 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 71 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 71 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 71 PIR3 SSP2IF BCL2IF RC2IF(1) TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 71 PIE3 SSP2IE BCL2IE RC2IE(1) TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 71 IPR3 SSP2IP BCL2IP RC2IP(1) TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 71 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 71 RCSTAx RCREGx TXSTAx EUSARTx Receive Register CSRC BAUDCONx ABDOVF 71 TX9 TXEN SYNC SENDB BRGH TRMT TX9D 71 RCIDL RXDTP TXCKP BRG16 -- WUE ABDEN 72 SPBRGHx EUSARTx Baud Rate Generator Register High Byte 72 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 72 Legend: -- = unimplemented locations read as `0'. Shaded cells are not used for asynchronous reception. Note 1: These bits are only available in 80-pin and 100-pin devices; otherwise, they are unimplemented and read as `0'. 2011 Microchip Technology Inc. DS39762F-page 329 PIC18F97J60 FAMILY 21.2.4 AUTO-WAKE-UP ON SYNC BREAK CHARACTER During Sleep mode, all clocks to the EUSARTx are suspended. Because of this, the Baud Rate Generator is inactive and a proper byte reception cannot be performed. The auto-wake-up feature allows the controller to wake-up due to activity on the RXx/DTx line while the EUSARTx is operating in Asynchronous mode. The auto-wake-up feature is enabled by setting the WUE bit (BAUDCONx<1>). Once set, the typical receive sequence on RXx/DTx is disabled and the EUSARTx remains in an Idle state, monitoring for a wake-up event independent of the CPU mode. A wake-up event consists of a high-to-low transition on the RXx/DTx line. (This coincides with the start of a Sync Break or a Wake-up Signal character for the LIN/J2602 protocol.) Following a wake-up event, the module generates an RCxIF interrupt. The interrupt is generated synchronously to the Q clocks in normal operating modes (Figure 21-8) and asynchronously if the device is in Sleep mode (Figure 21-9). The interrupt condition is cleared by reading the RCREGx register. The WUE bit is automatically cleared once a low-to-high transition is observed on the RXx line following the wake-up event. At this point, the EUSARTx module is in Idle mode and returns to normal operation. This signals to the user that the Sync Break event is over. 21.2.4.1 Oscillator start-up time must also be considered, especially in applications using oscillators with longer start-up intervals (i.e., HS or HSPLL mode). The Sync Break (or Wake-up Signal) character must be of sufficient length and be followed by a sufficient interval to allow enough time for the selected oscillator to start and provide proper initialization of the EUSARTx. 21.2.4.2 Special Considerations Using the WUE Bit The timing of WUE and RCxIF events may cause some confusion when it comes to determining the validity of received data. As noted, setting the WUE bit places the EUSARTx in an Idle mode. The wake-up event causes a receive interrupt by setting the RCxIF bit. The WUE bit is cleared after this when a rising edge is seen on RXx/DTx. The interrupt condition is then cleared by reading the RCREGx register. Ordinarily, the data in RCREGx will be dummy data and should be discarded. The fact that the WUE bit has been cleared (or is still set), and the RCxIF flag is set, should not be used as an indicator of the integrity of the data in RCREGx. Users should consider implementing a parallel method in firmware to verify received data integrity. To assure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process. If a receive operation is not occurring, the WUE bit may then be set just prior to entering the Sleep mode. Special Considerations Using Auto-Wake-up Since auto-wake-up functions by sensing rising edge transitions on RXx/DTx, information with any state changes before the Stop bit may signal a false End-of-Character (EOC) and cause data or framing errors. To work properly, therefore, the initial character in the transmission must be all `0's. This can be 00h (8 bytes) for standard RS-232 devices or 000h (12 bits) for LIN/J2602 bus. DS39762F-page 330 2011 Microchip Technology Inc. PIC18F97J60 FAMILY FIGURE 21-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Bit set by user Auto-Cleared WUE bit(1) RXx/DTx Line RCxIF Cleared due to user read of RCREGx Note 1: The EUSARTx remains in Idle while the WUE bit is set. FIGURE 21-9: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 WUE bit(2) Bit set by user Auto-Cleared RXx/DTx Line Note 1 RCxIF SLEEP Command Executed Note 1: 2: Sleep Ends Cleared due to user read of RCREGx If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur before the oscillator is ready. This sequence should not depend on the presence of Q clocks. The EUSARTx remains in Idle while the WUE bit is set. 2011 Microchip Technology Inc. DS39762F-page 331 PIC18F97J60 FAMILY 21.2.5 BREAK CHARACTER SEQUENCE The EUSARTx module has the capability of sending the special Break character sequences that are required by the LIN/J2602 bus standard. The Break character transmit consists of a Start bit, followed by twelve `0' bits and a Stop bit. The Frame Break character is sent whenever the SENDB and TXEN bits (TXSTAx<3> and TXSTAx<5>) are set while the Transmit Shift Register (TSR) is loaded with data. Note that the value of data written to TXREGx will be ignored and all `0's will be transmitted. The SENDB bit is automatically reset by hardware after the corresponding Stop bit is sent. This allows the user to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync character in the LIN/J2602 support specification). Note that the data value written to the TXREGx for the Break character is ignored. The write simply serves the purpose of initiating the proper sequence. The TRMT bit indicates when the transmit operation is active or Idle, just as it does during normal transmission. See Figure 21-10 for the timing of the Break character sequence. 21.2.5.1 Break and Sync Transmit Sequence The following sequence will send a message frame header made up of a Break, followed by an Auto-Baud Sync byte. This sequence is typical of a LIN/J2602 bus master. FIGURE 21-10: 1. 2. 3. 4. 5. Configure the EUSARTx for the desired mode. Set the TXEN and SENDB bits to set up the Break character. Load the TXREGx with a dummy character to initiate transmission (the value is ignored). Write `55h' to TXREGx to load the Sync character into the transmit FIFO buffer. After the Break has been sent, the SENDB bit is reset by hardware. The Sync character now transmits in the preconfigured mode. When the TXREGx becomes empty, as indicated by the TXxIF, the next data byte can be written to TXREGx. 21.2.6 RECEIVING A BREAK CHARACTER The Enhanced USARTx module can receive a Break character in two ways. The first method forces configuration of the baud rate at a frequency of 9/13 the typical speed. This allows for the Stop bit transition to be at the correct sampling location (13 bits for Break versus Start bit, and 8 data bits for typical data). The second method uses the auto-wake-up feature described in Section 21.2.4 "Auto-Wake-up on Sync Break Character". By enabling this feature, the EUSARTx will sample the next two transitions on RXx/DTx, cause an RCxIF interrupt and receive the next data byte followed by another interrupt. Note that following a Break character, the user will typically want to enable the Auto-Baud Rate Detect feature. For both methods, the user can set the ABDEN bit once the TXxIF interrupt is observed. SEND BREAK CHARACTER SEQUENCE Write to TXREGx Dummy Write BRG Output (Shift Clock) TXx (pin) Start bit bit 0 bit 1 bit 11 Stop bit Break TXxIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) SENDB Sampled Here Auto-Cleared SENDB bit (Transmit Shift Reg. Empty Flag) DS39762F-page 332 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 21.3 Once the TXREGx register transfers the data to the TSR register (occurs in one TCY), the TXREGx is empty and the TXxIF flag bit is set. The interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TXxIE. TXxIF is set regardless of the state of enable bit, TXxIE; it cannot be cleared in software. It will reset only when new data is loaded into the TXREGx register. EUSARTx Synchronous Master Mode The Synchronous Master mode is entered by setting the CSRC bit (TXSTAx<7>). In this mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit, SYNC (TXSTAx<4>). In addition, enable bit, SPEN (RCSTAx<7>), is set in order to configure the TXx and RXx pins to CKx (clock) and DTx (data) lines, respectively. While flag bit, TXxIF, indicates the status of the TXREGx register, another bit, TRMT (TXSTAx<1>), shows the status of the TSR register. TRMT is a read-only bit which is set when the TSR is empty. No interrupt logic is tied to this bit, so the user must poll this bit in order to determine if the TSR register is empty. The TSR is not mapped in data memory so it is not available to the user. Clock polarity (CKx) is selected with the TXCKP bit (BAUDCON<4>). Setting TXCKP sets the Idle state on CKx as high, while clearing the bit sets the Idle state as low. Data polarity (DTx) is selected with the RXDTP bit (BAUDCONx<5>). Setting RXDTP sets the Idle state on DTx as high, while clearing the bit sets the Idle state as low. DTx is sampled when CKx returns to its Idle state. This option is provided to support Microwire devices with this module. 21.3.1 To set up a Synchronous Master Transmission: 1. 2. 3. 4. 5. 6. EUSARTx SYNCHRONOUS MASTER TRANSMISSION The EUSARTx transmitter block diagram is shown in Figure 21-3. The heart of the transmitter is the Transmit (Serial) Shift Register (TSR). The Transmit Shift register obtains its data from the Read/Write Transmit Buffer register, TXREGx. The TXREGx register is loaded with data in software. The TSR register is not loaded until the last bit has been transmitted from the previous load. As soon as the last bit is transmitted, the TSR is loaded with new data from the TXREGx (if available). FIGURE 21-11: 7. 8. Initialize the SPBRGHx:SPBRGx registers for the appropriate baud rate. Set or clear the BRG16 bit, as required, to achieve the desired baud rate. Enable the synchronous master serial port by setting bits, SYNC, SPEN and CSRC. If interrupts are desired, set enable bit, TXxIE. If 9-bit transmission is desired, set bit, TX9. Enable the transmission by setting bit, TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit, TX9D. Start transmission by loading data to the TXREGx register. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. SYNCHRONOUS TRANSMISSION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 RC7/RX1/DT1 bit 0 bit 1 Word 1 RC6/TX1/CK1 pin (TXCKP = 0) bit 2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 bit 7 bit 0 bit 1 bit 7 Word 2 RC6/TX1/CK1 pin (TXCKP = 1) Write to TXREG1 Reg Write Word 1 Write Word 2 TX1IF bit (Interrupt Flag) TRMT bit TXEN bit Note: `1' `1' Sync Master mode, SPBRG1 = 0; continuous transmission of two 8-bit words. This example is equally applicable to EUSART2 (RG1/TX2/CK2 and RG2/RX2/DT2). 2011 Microchip Technology Inc. DS39762F-page 333 PIC18F97J60 FAMILY FIGURE 21-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX1/DT1 pin bit 0 bit 1 bit 2 bit 6 bit 7 RC6/TX1/CK1 pin Write to TXREG1 reg TX1IF bit TRMT bit TXEN bit Note: This example is equally applicable to EUSART2 (RG1/TX2/CK2 and RG2/RX2/DT2). TABLE 21-7: Name INTCON REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Bit 7 Bit 6 Bit 5 GIE/GIEH PEIE/GIEL TMR0IE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: INT0IE RBIE TMR0IF INT0IF RBIF 69 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 71 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 71 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 71 PIR3 SSP2IF BCL2IF RC2IF TX2IF(1) TMR4IF CCP5IF CCP4IF CCP3IF 71 PIE3 SSP2IE BCL2IE RC2IE TX2IE(1) TMR4IE CCP5IE CCP4IE CCP3IE 71 IPR3 SSP2IP BCL2IP RC2IP TX2IP(1) TMR4IP CCP5IP CCP4IP CCP3IP 71 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 71 RCSTAx TXREGx TXSTAx EUSARTx Transmit Register CSRC BAUDCONx ABDOVF 71 TX9 TXEN SYNC SENDB BRGH TRMT TX9D 71 RCIDL RXDTP TXCKP BRG16 -- WUE ABDEN 72 SPBRGHx EUSARTx Baud Rate Generator Register High Byte 72 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 72 Legend: -- = unimplemented, read as `0'. Shaded cells are not used for synchronous master transmission. Note 1: These bits are only available in 80-pin and 100-pin devices; otherwise, they are unimplemented and read as `0'. DS39762F-page 334 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 21.3.2 EUSARTx SYNCHRONOUS MASTER RECEPTION 4. Once Synchronous mode is selected, reception is enabled by setting either the Single Receive Enable bit, SREN (RCSTAx<5>), or the Continuous Receive Enable bit, CREN (RCSTAx<4>). Data is sampled on the RXx pin on the falling edge of the clock. If enable bit, SREN, is set, only a single word is received. If enable bit, CREN, is set, the reception is continuous until CREN is cleared. If both bits are set, then CREN takes precedence. To set up a Synchronous Master Reception: 1. 2. 3. Initialize the SPBRGHx:SPBRGx registers for the appropriate baud rate. Set or clear the BRG16 bit, as required, to achieve the desired baud rate. Enable the synchronous master serial port by setting bits, SYNC, SPEN and CSRC. Ensure bits, CREN and SREN, are clear. FIGURE 21-13: If the signal from the CKx pin is to be inverted, set the TXCKP bit. If the signal from the DTx pin is to be inverted, set the RXDTP bit. 5. If interrupts are desired, set enable bit, RCxIE. 6. If 9-bit reception is desired, set bit, RX9. 7. If a single reception is required, set bit, SREN. For continuous reception, set bit, CREN. 8. Interrupt flag bit, RCxIF, will be set when reception is complete and an interrupt will be generated if the enable bit, RCxIE, was set. 9. Read the RCSTAx register to get the 9th bit (if enabled) and determine if any error occurred during reception. 10. Read the 8-bit received data by reading the RCREGx register. 11. If any error occurred, clear the error by clearing bit, CREN. 12. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 RC7/RX1/DT1 pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 RC6/TX1/CK1 pin (TXCKP = 0) RC6/TX1/CK1 pin (TXCKP = 1) Write to SREN bit SREN bit CREN bit `0' `0' RC1IF bit (Interrupt) Read RCREG1 Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. This example is equally applicable to EUSART2 (RG1/TX2/CK2 and RG2/RX2/DT2). 2011 Microchip Technology Inc. DS39762F-page 335 PIC18F97J60 FAMILY TABLE 21-8: Name INTCON REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Bit 7 Bit 6 GIE/GIEH PEIE/GIEL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 71 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 71 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 71 PIR3 SSP2IF BCL2IF RC2IF(1) TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 71 (1) TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 71 TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 71 CREN ADDEN FERR OERR RX9D 71 PIE3 SSP2IE BCL2IE RC2IE IPR3 SSP2IP BCL2IP RC2IP(1) RCSTAx RCREGx TXSTAx SPEN RX9 SREN EUSARTx Receive Register CSRC BAUDCONx ABDOVF 71 TX9 TXEN SYNC SENDB BRGH TRMT TX9D 71 RCIDL RXDTP TXCKP BRG16 -- WUE ABDEN 72 SPBRGHx EUSARTx Baud Rate Generator Register High Byte 72 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 72 Legend: -- = unimplemented, read as `0'. Shaded cells are not used for synchronous master reception. Note 1: These bits are only available in 80-pin and 100-pin devices; otherwise, they are unimplemented and read as `0'. DS39762F-page 336 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 21.4 To set up a Synchronous Slave Transmission: EUSARTx Synchronous Slave Mode 1. Synchronous Slave mode is entered by clearing bit, CSRC (TXSTAx<7>). This mode differs from the Synchronous Master mode in that the shift clock is supplied externally at the CKx pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in any low-power mode. 2. 3. 21.4.1 EUSARTx SYNCHRONOUS SLAVE TRANSMISSION 4. 5. 6. The operation of the Synchronous Master and Slave modes is identical, except in the case of Sleep mode. 7. If two words are written to the TXREGx and then the SLEEP instruction is executed, the following will occur: 8. a) b) c) d) e) The first word will immediately transfer to the TSR register and transmit. The second word will remain in the TXREGx register. Flag bit, TXxIF, will not be set. When the first word has been shifted out of TSR, the TXREGx register will transfer the second word to the TSR and flag bit, TXxIF, will now be set. If enable bit, TXxIE, is set, the interrupt will wake the chip from Sleep. If the global interrupt is enabled, the program will branch to the interrupt vector. TABLE 21-9: Name INTCON 9. Enable the synchronous slave serial port by setting bits, SYNC and SPEN, and clearing bit, CSRC. Clear bits, CREN and SREN. If the signal from the CKx pin is to be inverted, set the TXCKP bit. If the signal from the DTx pin is to be inverted, set the RXDTP bit. If interrupts are desired, set enable bit, TXxIE. If 9-bit transmission is desired, set bit, TX9. Enable the transmission by setting enable bit, TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit, TX9D. Start transmission by loading data to the TXREGx register. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Bit 7 Bit 6 Bit 5 GIE/GIEH PEIE/GIEL TMR0IE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: INT0IE RBIE TMR0IF INT0IF RBIF 69 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 71 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 71 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 71 PIR3 SSP2IF BCL2IF RC2IF TX2IF(1) TMR4IF CCP5IF CCP4IF CCP3IF 71 PIE3 SSP2IE BCL2IE RC2IE TX2IE(1) TMR4IE CCP5IE CCP4IE CCP3IE 71 (1) IPR3 RCSTAx TXREGx TXSTAx SSP2IP BCL2IP RC2IP SPEN RX9 SREN TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 71 CREN ADDEN FERR OERR RX9D 71 EUSARTx Transmit Register CSRC BAUDCONx ABDOVF 71 TX9 TXEN SYNC SENDB BRGH TRMT TX9D 71 RCIDL RXDTP TXCKP BRG16 -- WUE ABDEN 72 SPBRGHx EUSARTx Baud Rate Generator Register High Byte 72 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 72 Legend: -- = unimplemented, read as `0'. Shaded cells are not used for synchronous slave transmission. Note 1: These bits are only available in 80-pin and 100-pin devices; otherwise, they are unimplemented and read as `0'. 2011 Microchip Technology Inc. DS39762F-page 337 PIC18F97J60 FAMILY 21.4.2 EUSARTx SYNCHRONOUS SLAVE RECEPTION To set up a Synchronous Slave Reception: 1. The operation of the Synchronous Master and Slave modes is identical, except in the case of Sleep or any Idle mode, and bit, SREN, which is a "don't care" in Slave mode. If receive is enabled by setting the CREN bit prior to entering Sleep or any Idle mode, then a word may be received while in this low-power mode. Once the word is received, the RSR register will transfer the data to the RCREGx register. If the RCxIE enable bit is set, the interrupt generated will wake the chip from the low-power mode. If the global interrupt is enabled, the program will branch to the interrupt vector. Enable the synchronous master serial port by setting bits, SYNC and SPEN, and clearing bit, CSRC. 2. If interrupts are desired, set enable bit, RCxIE. 3. If the signal from the CKx pin is to be inverted, set the TXCKP bit. If the signal from the DTx pin is to be inverted, set the RXDTP bit. 4. If 9-bit reception is desired, set bit, RX9. 5. To enable reception, set enable bit, CREN. 6. Flag bit, RCxIF, will be set when reception is complete. An interrupt will be generated if enable bit, RCxIE, was set. 7. Read the RCSTAx register to get the 9th bit (if enabled) and determine if any error occurred during reception. 8. Read the 8-bit received data by reading the RCREGx register. 9. If any error occurred, clear the error by clearing bit, CREN. 10. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. TABLE 21-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Name Bit 7 Bit 6 Bit 5 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: INT0IE RBIE TMR0IF INT0IF RBIF 69 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 71 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 71 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 71 TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 71 TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 71 INTCON GIE/GIEH PEIE/GIEL TMR0IE Bit 4 PIR3 SSP2IF BCL2IF RC2IF(1) PIE3 SSP2IE BCL2IE RC2IE(1) SSP2IP BCL2IP RC2IP(1) TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 71 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 71 IPR3 RCSTAx RCREGx TXSTAx EUSARTx Receive Register CSRC BAUDCONx ABDOVF 71 TX9 TXEN SYNC SENDB BRGH TRMT TX9D 71 RCIDL RXDTP TXCKP BRG16 -- WUE ABDEN 72 SPBRGHx EUSARTx Baud Rate Generator Register High Byte 72 SPBRGx EUSARTx Baud Rate Generator Register Low Byte 72 Legend: -- = unimplemented, read as `0'. Shaded cells are not used for synchronous slave reception. Note 1: These bits are only available in 80-pin and 100-pin devices; otherwise, they are unimplemented and read as `0'. DS39762F-page 338 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 22.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The Analog-to-Digital (A/D) Converter module has 11 inputs for the 64-pin devices, 15 inputs for the 80-pin devices and 16 inputs for the 100-pin devices. This module allows conversion of an analog input signal to a corresponding 10-bit digital number. REGISTER 22-1: The module has five registers: * * * * * A/D Result Register High Byte (ADRESH) A/D Result Register Low Byte (ADRESL) A/D Control Register 0 (ADCON0) A/D Control Register 1 (ADCON1) A/D Control Register 2 (ADCON2) The ADCON0 register, shown in Register 22-1, controls the operation of the A/D module. The ADCON1 register, shown in Register 22-2, configures the functions of the port pins. The ADCON2 register, shown in Register 22-3, configures the A/D clock source, programmed acquisition time and justification. ADCON0: A/D CONTROL REGISTER 0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCAL -- CHS3 CHS2 CHS1 CHS0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 ADCAL: A/D Calibration bit 1 = Calibration is performed on next A/D conversion 0 = Normal A/D Converter operation (no calibration is performed) bit 6 Unimplemented: Read as `0' bit 5-2 CHS<3:0>: Analog Channel Select bits 0000 = Channel 0 (AN0) 0001 = Channel 1 (AN1) 0010 = Channel 2 (AN2) 0011 = Channel 3 (AN3) 0100 = Channel 4 (AN4) 0101 = Channel 5 (AN5)(1,3) 0110 = Channel 6 (AN6) 0111 = Channel 7 (AN7) 1000 = Channel 8 (AN8) 1001 = Channel 9 (AN9) 1010 = Channel 10 (AN10) 1011 = Channel 11 (AN11) 1100 = Channel 12 (AN12)(2,3) 1101 = Channel 13 (AN13)(2,3) 1110 = Channel 14 (AN14)(2,3) 1111 = Channel 15 (AN15)(2,3) bit 1 GO/DONE: A/D Conversion Status bit When ADON = 1: 1 = A/D conversion is in progress 0 = A/D is Idle bit 0 ADON: A/D On bit 1 = A/D Converter module is enabled 0 = A/D Converter module is disabled Note 1: 2: 3: x = Bit is unknown This channel is implemented on 100-pin devices only. These channels are implemented on 80-pin and 100-pin devices only. Performing a conversion on unimplemented channels will return random values. 2011 Microchip Technology Inc. DS39762F-page 339 PIC18F97J60 FAMILY REGISTER 22-2: ADCON1: A/D CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared PCFG<3:0> AN8 AN7 AN6 AN5(2) AN4 AN3 AN2 AN1(3) AN0(3) PCFG<3:0>: A/D Port Configuration Control bits: AN9 bit 3-0 AN10 VCFG0: Voltage Reference Configuration bit (VREF+ source) 1 = VREF+ (AN3) 0 = AVDD AN11 bit 4 AN12(1) VCFG1: Voltage Reference Configuration bit (VREF- source) 1 = VREF- (AN2) 0 = AVSS AN13(1) bit 5 AN14(1) Unimplemented: Read as `0' AN15(1) bit 7-6 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 A D D D D D D D D D D D D D D D A D D D D D D D D D D D D D D D A A D D D D D D D D D D D D D D A A A D D D D D D D D D D D D D A A A A D D D D D D D D D D D D A A A A A D D D D D D D D D D D A A A A A A D D D D D D D D D D A A A A A A A D D D D D D D D D A A A A A A A A D D D D D D D D A A A A A A A A A D D D D D D D A A A A A A A A A A D D D D D D A A A A A A A A A A A D D D D D A A A A A A A A A A A A D D D D A A A A A A A A A A A A A D D D A A A A A A A A A A A A A A D D A A A A A A A A A A A A A A A D A = Analog input Note 1: 2: 3: x = Bit is unknown D = Digital I/O AN12 through AN15 are available in 80-pin and 100-pin devices only. AN5 is available in 100-pin devices only. AN0 and AN1 can also operate as Ethernet LED outputs in either Analog or Digital I/O modes. DS39762F-page 340 2011 Microchip Technology Inc. PIC18F97J60 FAMILY REGISTER 22-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM -- ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as `0' bit 5-3 ACQT<2:0>: A/D Acquisition Time Select bits 111 = 20 TAD 110 = 16 TAD 101 = 12 TAD 100 = 8 TAD 011 = 6 TAD 010 = 4 TAD 001 = 2 TAD 000 = 0 TAD(1) bit 2-0 ADCS<2:0>: A/D Conversion Clock Select bits 111 = FRC (clock derived from A/D RC oscillator)(1) 110 = FOSC/64 101 = FOSC/16 100 = FOSC/4 011 = FRC (clock derived from A/D RC oscillator)(1) 010 = FOSC/32 001 = FOSC/8 000 = FOSC/2 Note 1: x = Bit is unknown If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D clock starts. This allows the SLEEP instruction to be executed before starting a conversion. 2011 Microchip Technology Inc. DS39762F-page 341 PIC18F97J60 FAMILY The analog reference voltage is software selectable to either the device's positive and negative supply voltage (AVDD and AVSS), or the voltage level on the RA3/AN3/VREF+ and RA2/AN2/VREF- pins. the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRESH:ADRESL register pair, the GO/DONE bit (ADCON0<1>) is cleared and the A/D Interrupt Flag bit, ADIF, is set. The A/D Converter has a unique feature of being able to operate while the device is in Sleep mode. To operate in Sleep, the A/D conversion clock must be derived from the A/D Converter's internal RC oscillator. A device Reset forces all registers to their Reset state. This forces the A/D module to be turned off and any conversion in progress is aborted. The value in the ADRESH:ADRESL register pair is not modified for a Power-on Reset. These registers will contain unknown data after a Power-on Reset. The output of the sample and hold is the input into the converter, which generates the result via successive approximation. The block diagram of the A/D module is shown in Figure 22-1. Each port pin associated with the A/D Converter can be configured as an analog input or as a digital I/O. The ADRESH and ADRESL registers contain the result of FIGURE 22-1: A/D BLOCK DIAGRAM CHS<3:0> 1111 1110 AN14(1) 1101 AN13(1) 1100 AN12(1) 1011 AN11 1010 1001 1000 0111 0110 0101 0100 VAIN 0011 (Input Voltage) 10-Bit A/D Converter 0010 0001 VCFG<1:0> 0000 VDD Reference Voltage AN15(1) AN10 AN9 AN8 AN7 AN6 AN5(2) AN4 AN3 AN2 AN1 AN0 VREF+ VREFVSS Note 1: 2: DS39762F-page 342 Channels AN15 through AN12 are not available in 64-pin devices. Channel AN5 is implemented in 100-pin devices only. 2011 Microchip Technology Inc. PIC18F97J60 FAMILY After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as inputs. To determine acquisition time, see Section 22.1 "A/D Acquisition Requirements". After this acquisition time has elapsed, the A/D conversion can be started. An acquisition time can be programmed to occur between setting the GO/DONE bit and the actual start of the conversion. 2. 3. 4. 5. The following steps should be followed to do an A/D conversion: 1. Configure the A/D module: * Configure analog pins, voltage reference and digital I/O (ADCON1) * Select A/D input channel (ADCON0) * Select A/D acquisition time (ADCON2) * Select A/D conversion clock (ADCON2) * Turn on A/D module (ADCON0) FIGURE 22-2: Configure A/D interrupt (if desired): * Clear ADIF bit * Set ADIE bit * Set GIE bit Wait the required acquisition time (if required). Start conversion: * Set GO/DONE bit (ADCON0<1>) Wait for A/D conversion to complete, by either: * Polling for the GO/DONE bit to be cleared OR 6. 7. * Waiting for the A/D interrupt Read A/D Result registers (ADRESH:ADRESL); clear bit, ADIF, if required. For the next conversion, go to Step 1 or Step 2, as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2 TAD is required before next acquisition starts. ANALOG INPUT MODEL VDD RS VAIN Sampling Switch VT = 0.6V ANx RIC 1k CPIN 5 pF VT = 0.6V SS RSS ILEAKAGE 100 nA CHOLD = 25 pF VSS Legend: CPIN = Input Capacitance = Threshold Voltage VT ILEAKAGE = Leakage Current at the pin due to various junctions = Interconnect Resistance RIC = Sampling Switch SS = Sample/Hold Capacitance (from DAC) CHOLD RSS = Sampling Switch Resistance 2011 Microchip Technology Inc. VDD 1 2 3 4 Sampling Switch (k DS39762F-page 343 PIC18F97J60 FAMILY 22.1 A/D Acquisition Requirements For the A/D Converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 22-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor, CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD). The source impedance affects the offset voltage at the analog input (due to pin leakage current). The maximum recommended impedance for analog sources is 2.5 k. After the analog input channel is selected (changed), the channel must be sampled for at least the minimum acquisition time before starting a conversion. EQUATION 22-1: CHOLD Rs Conversion Error VDD Temperature = = = = 25 pF 2.5 k 1/2 LSb 3V Rss = 2 k 85C (system max.) ACQUISITION TIME = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF EQUATION 22-2: VHOLD or TC Equation 22-3 shows the calculation of the minimum required acquisition time, TACQ. This calculation is based on the following application system assumptions: When the conversion is started, the holding capacitor is disconnected from the input pin. Note: TACQ To calculate the minimum acquisition time, Equation 22-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified resolution. A/D MINIMUM CHARGING TIME = (VREF - (VREF/2048)) * (1 - e(-TC/CHOLD(RIC + RSS + RS))) = -(CHOLD)(RIC + RSS + RS) ln(1/2048) EQUATION 22-3: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME TACQ = TAMP + TC + TCOFF TAMP = 0.2 s TCOFF = (Temp - 25C)(0.02 s/C) (85C - 25C)(0.02 s/C) 1.2 s Temperature coefficient is only required for temperatures > 25C. Below 25C, TCOFF = 0 ms. TC = -(CHOLD)(RIC + RSS + RS) ln(1/2048) s -(25 pF) (1 k + 2 k + 2.5 k) ln(0.0004883) s 1.05 s TACQ = 0.2 s + 1 s + 1.2 s 2.4 s DS39762F-page 344 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 22.2 Selecting and Configuring Automatic Acquisition Time The ADCON2 register allows the user to select an acquisition time that occurs each time the GO/DONE bit is set. When the GO/DONE bit is set, sampling is stopped and a conversion begins. The user is responsible for ensuring the required acquisition time has passed between selecting the desired input channel and setting the GO/DONE bit. This occurs when the ACQT<2:0> bits (ADCON2<5:3>) remain in their Reset state (`000') and is compatible with devices that do not offer programmable acquisition times. If desired, the ACQT bits can be set to select a programmable acquisition time for the A/D module. When the GO/DONE bit is set, the A/D module continues to sample the input for the selected acquisition time, then automatically begins a conversion. Since the acquisition time is programmed, there may be no need to wait for an acquisition time between selecting a channel and setting the GO/DONE bit. In either case, when the conversion is completed, the GO/DONE bit is cleared, the ADIF flag is set and the A/D begins sampling the currently selected channel again. If an acquisition time is programmed, there is nothing to indicate if the acquisition time has ended or if the conversion has begun. 22.3 Selecting the A/D Conversion Clock The A/D conversion time per bit is defined as TAD. The A/D conversion requires 11 TAD per 10-bit conversion. The source of the A/D conversion clock is software selectable. There are seven possible options for TAD: * * * * * * * 2 TOSC 4 TOSC 8 TOSC 16 TOSC 32 TOSC 64 TOSC Internal RC Oscillator Table 22-1 shows the resultant TAD times derived from the device operating frequencies and the A/D clock source selected. TABLE 22-1: TAD vs. DEVICE OPERATING FREQUENCIES AD Clock Source (TAD) Operation ADCS<2:0> Maximum Device Frequency 2 TOSC 000 2.86 MHz 4 TOSC 100 5.71 MHz 8 TOSC 001 11.43 MHz 16 TOSC 101 22.86 MHz 32 TOSC 010 41.67 MHz 64 TOSC 110 41.67 MHz RC(2) x11 1.00 MHz(1) Note 1: 2: 22.4 The RC source has a typical TAD time of 4 ms. See Parameter 130 in Table 28-27 for A/D RC clock specifications. Configuring Analog Port Pins The ADCON1, TRISA, TRISF and TRISH registers control the operation of the A/D port pins. The port pins needed as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The A/D operation is independent of the state of the CHS<3:0> bits and the TRIS bits. Note 1: When reading the PORT register, all pins configured as analog input channels will read as cleared (a low level). Pins configured as digital inputs will convert an analog input. Analog levels on a digitally configured input will be accurately converted. 2: Analog levels on any pin defined as a digital input may cause the digital input buffer to consume current out of the device's specification limits. For correct A/D conversions, the A/D conversion clock (TAD) must be as short as possible but greater than the minimum TAD. See Section 28.0 "Electrical Characteristics", A/D Parameter 130 in Table 28-27 for more information. 2011 Microchip Technology Inc. DS39762F-page 345 PIC18F97J60 FAMILY 22.5 A/D Conversions 22.6 Figure 22-3 shows the operation of the A/D Converter after the GO/DONE bit has been set and the ACQT<2:0> bits are cleared. A conversion is started after the following instruction to allow entry into Sleep mode before the conversion begins. An A/D conversion can be started by the "Special Event Trigger" of the ECCP2 module. This requires that the CCP2M<3:0> bits (CCP2CON<3:0>) be programmed as `1011' and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the GO/DONE bit will be set, starting the A/D acquisition and conversion and the Timer1 (or Timer3) counter will be reset to zero. Timer1 (or Timer3) is reset to automatically repeat the A/D acquisition period with minimal software overhead (moving ADRESH/ADRESL to the desired location). The appropriate analog input channel must be selected and the minimum acquisition period is either timed by the user, or an appropriate TACQ time is selected before the Special Event Trigger sets the GO/DONE bit (starts a conversion). Figure 22-4 shows the operation of the A/D Converter after the GO/DONE bit has been set, the ACQT<2:0> bits are set to `010' and a 4 TAD acquisition time has been selected before the conversion starts. Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D Result register pair will NOT be updated with the partially completed A/D conversion sample. This means the ADRESH:ADRESL registers will continue to contain the value of the last completed conversion (or the last value written to the ADRESH:ADRESL registers). If the A/D module is not enabled (ADON is cleared), the Special Event Trigger will be ignored by the A/D module but will still reset the Timer1 (or Timer3) counter. After the A/D conversion is completed or aborted, a 2 TAD wait is required before the next acquisition can be started. After this wait, acquisition on the selected channel is automatically started. Note: Use of the ECCP2 Trigger The GO/DONE bit should NOT be set in the same instruction that turns on the A/D. FIGURE 22-3: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0) TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b4 b1 b0 b6 b7 b2 b9 b8 b3 b5 Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO/DONE bit Next Q4: ADRESH/ADRESL is loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD) FIGURE 22-4: TACQT Cycles 1 2 3 Automatic Acquisition Time TAD Cycles 4 1 3 4 5 6 7 8 9 10 11 b8 b7 b6 b5 b4 b3 b2 b1 b0 Conversion starts (Holding capacitor is disconnected) Set GO/DONE bit (Holding capacitor continues acquiring input) DS39762F-page 346 2 b9 Next Q4: ADRESH:ADRESL is loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is reconnected to analog input. 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 22.7 A/D Converter Calibration The A/D Converter in the PIC18F97J60 family of devices includes a self-calibration feature which compensates for any offset generated within the module. The calibration process is automated and is initiated by setting the ADCAL bit (ADCON0<7>). The next time the GO/DONE bit is set, the module will perform a "dummy" conversion (that is, with reading none of the input channels) and store the resulting value internally to compensate for offset. Thus, subsequent offsets will be compensated. The calibration process assumes that the device is in a relatively steady-state operating condition. If A/D calibration is used, it should be performed after each device Reset, or if there are other major changes in operating conditions. 22.8 Operation in Power-Managed Modes The selection of the automatic acquisition time and A/D conversion clock is determined in part by the clock source and frequency while in a power-managed mode. TABLE 22-2: Name If the A/D is expected to operate while the device is in a power-managed mode, the ACQT<2:0> and ADCS<2:0> bits in ADCON2 should be updated in accordance with the power-managed mode clock that will be used. After the power-managed mode is entered (either of the power-managed Run modes), an A/D acquisition or conversion may be started. Once an acquisition or conversion is started, the device should continue to be clocked by the same power-managed mode clock source until the conversion has been completed. If desired, the device may be placed into the corresponding power-managed Idle mode during the conversion. If the power-managed mode clock frequency is less than 1 MHz, the A/D RC clock source should be selected. Operation in Sleep mode requires the A/D RC clock to be selected. If bits, ACQT<2:0>, are set to `000' and a conversion is started, the conversion will be delayed one instruction cycle to allow execution of the SLEEP instruction and entry to Sleep mode. The IDLEN and SCS bits in the OSCCON register must have already been cleared prior to starting the conversion. SUMMARY OF A/D REGISTERS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 71 PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 71 IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 71 INTCON GIE/GIEH PEIE/GIEL PIR2 OSCFIF CMIF ETHIF r BCL1IF -- TMR3IF CCP2IF 71 PIE2 OSCFIE CMIE ETHIE r BCL1IE -- TMR3IE CCP2IE 71 IPR2 OSCFIP CMIP ETHIP r BCL1IP -- TMR3IP CCP2IP 71 ADRESH A/D Result Register High Byte 70 ADRESL A/D Result Register Low Byte 70 ADCON0 ADCAL -- CHS3 CHS3 CHS1 CHS0 GO/DONE ADON 70 ADCON1 -- -- VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 70 ADCON2 ADFM -- ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 70 CCP2CON P2M1 P2M0 DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 70 PORTA RJPU -- RA5 RA4 RA3 RA2 RA1 RA0 72 TRISA -- -- TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 71 PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 RF0 (1) 72 TRISF0(1) 71 PORTH(2) RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0 72 TRISH(2) TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 71 Legend: -- = unimplemented, read as `0', r = reserved. Shaded cells are not used for A/D conversion. Note 1: Implemented in 100-pin devices only. 2: This register is not implemented in 64-pin devices. 2011 Microchip Technology Inc. DS39762F-page 347 PIC18F97J60 FAMILY NOTES: DS39762F-page 348 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 23.0 COMPARATOR MODULE The analog comparator module contains two comparators that can be configured in a variety of ways. The inputs can be selected from the analog inputs, multiplexed with pins, RF1 through RF6, as well as the on-chip voltage reference (see Section 24.0 "Comparator Voltage Reference Module"). The digital outputs (normal or inverted) are available at the pin level and can also be read through the control register. REGISTER 23-1: The CMCON register (Register 23-1) selects the comparator input and output configuration. Block diagrams of the various comparator configurations are shown in Figure 23-1. CMCON: COMPARATOR CONTROL REGISTER R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 C2OUT: Comparator 2 Output bit When C2INV = 0: 1 = C2 VIN+ > C2 VIN0 = C2 VIN+ < C2 VINWhen C2INV = 1: 1 = C2 VIN+ < C2 VIN0 = C2 VIN+ > C2 VIN- bit 6 C1OUT: Comparator 1 Output bit When C1INV = 0: 1 = C1 VIN+ > C1 VIN0 = C1 VIN+ < C1 VINWhen C1INV = 1: 1 = C1 VIN+ < C1 VIN0 = C1 VIN+ > C1 VIN- bit 5 C2INV: Comparator 2 Output Inversion bit 1 = C2 output is inverted 0 = C2 output is not inverted bit 4 C1INV: Comparator 1 Output Inversion bit 1 = C1 output is inverted 0 = C1 output is not inverted bit 3 CIS: Comparator Input Switch bit When CM<2:0> = 110: 1 = C1 VIN- connects to RF5/AN10/CVREF C2 VIN- connects to RF3/AN8 0 = C1 VIN- connects to RF6/AN11 C2 VIN- connects to RA4/AN9 bit 2-0 CM<2:0>: Comparator Mode bits Figure 23-1 shows the Comparator modes and the CM<2:0> bit settings. 2011 Microchip Technology Inc. x = Bit is unknown DS39762F-page 349 PIC18F97J60 FAMILY 23.1 Comparator Configuration There are eight modes of operation for the comparators, shown in Figure 23-1. Bits CM<2:0> of the CMCON register are used to select these modes. The TRISF register controls the data direction of the comparator pins for each mode. If the Comparator FIGURE 23-1: A RF5/AN10/ A CVREF RF4/AN9 RF3/AN8 Comparators Off (POR Default Value) CM<2:0> = 111 VINVIN+ A VIN- A VIN+ C1 Off (Read as `0') C2 Off (Read as `0') Two Independent Comparators CM<2:0> = 010 RF6/AN11 A VIN+ A VIN- A VIN+ RF3/AN8 RF6/AN11 D VIN- RF5/AN10/ CVREF D VIN+ RF4/AN9 D VIN- D VIN+ RF3/AN8 C1 Off (Read as `0') C2 Off (Read as `0') Two Independent Comparators with Outputs CM<2:0> = 011 VIN- RF5/AN10/ A CVREF RF4/AN9 Comparator interrupts should be disabled during a Comparator mode change; otherwise, a false interrupt may occur. Note: COMPARATOR I/O OPERATING MODES Comparator Outputs Disabled CM<2:0> = 000 RF6/AN11 mode is changed, the comparator output level may not be valid for the specified mode change delay shown in Section 28.0 "Electrical Characteristics". RF6/AN11 A VIN- C1 C1OUT VIN+ RF5/AN10/ A CVREF RF2/AN7/C1OUT* C2 C2OUT RF4/AN9 A VIN- RF3/AN8 A VIN+ C1 C1OUT C2 C2OUT RF1/AN6/C2OUT* Two Common Reference Comparators CM<2:0> = 100 RF6/AN11 A VIN- RF5/AN10/ A CVREF VIN+ A VIN- D VIN+ RF4/AN9 RF3/AN8 Two Common Reference Comparators with Outputs CM<2:0> = 101 RF6/AN11 C1 C1OUT C2 C2OUT A A RF5/AN10/ CVREF RF2/AN7/C1OUT* RF4/AN9 RF3/AN8 VINVIN+ A VIN- D VIN+ C1 C1OUT C2 C2OUT RF1/AN6/C2OUT* One Independent Comparator with Output CM<2:0> = 001 A VIN- RF5/AN10/ A CVREF VIN+ RF6/AN11 C1 C1OUT RF2/AN7/C1OUT* RF4/AN9 D VIN- RF3/AN8 D VIN+ C2 Off (Read as `0') Four Inputs Multiplexed to Two Comparators CM<2:0> = 110 RF6/AN11 A RF5/AN10/ CVREF A RF4/AN9 A RF3/AN8 A CIS = 0 CIS = 1 VIN- CIS = 0 CIS = 1 VIN- VIN+ VIN+ C1 C1OUT C2 C2OUT CVREF From VREF module A = Analog Input, port reads zeros always D = Digital Input CIS (CMCON<3>) is the Comparator Input Switch * Setting the TRISF<2:1> bits will disable the comparator outputs by configuring the pins as inputs. DS39762F-page 350 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 23.2 23.3.2 Comparator Operation A single comparator is shown in Figure 23-2, along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input VIN-, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input, VIN-, the output of the comparator is a digital high level. The shaded areas of the output of the comparator in Figure 23-2 represent the uncertainty due to input offsets and response time. 23.3 Comparator Reference Depending on the comparator operating mode, either an external or internal voltage reference may be used. The analog signal present at VIN- is compared to the signal at VIN+ and the digital output of the comparator is adjusted accordingly (Figure 23-2). FIGURE 23-2: SINGLE COMPARATOR VIN+ + VIN- - Output VINVIN+ Output 23.3.1 INTERNAL REFERENCE SIGNAL The comparator module also allows the selection of an internally generated voltage reference from the comparator voltage reference module. This module is described in more detail in Section 24.0 "Comparator Voltage Reference Module". The internal reference is only available in the mode where four inputs are multiplexed to two comparators (CM<2:0> = 110). In this mode, the internal voltage reference is applied to the VIN+ pin of both comparators. 23.4 Comparator Response Time Response time is the minimum time, after selecting a new reference voltage or input source, before the comparator output has a valid level. If the internal reference is changed, the maximum delay of the internal voltage reference must be considered when using the comparator outputs. Otherwise, the maximum delay of the comparators should be used (see Section 28.0 "Electrical Characteristics"). 23.5 Comparator Outputs The comparator outputs are read through the CMCON register. These bits are read-only. The comparator outputs may also be directly output to the RF1 and RF2 I/O pins. When enabled, multiplexors in the output path of the RF1 and RF2 pins will switch and the output of each pin will be the unsynchronized output of the comparator. The uncertainty of each of the comparators is related to the input offset voltage and the response time given in the specifications. Figure 23-3 shows the comparator output block diagram. The TRISF bits will still function as an output enable/disable for the RF1 and RF2 pins while in this mode. EXTERNAL REFERENCE SIGNAL When external voltage references are used, the comparator module can be configured to have the comparators operate from the same or different reference sources. However, threshold detector applications may require the same reference. The reference signal must be between VSS and VDD and can be applied to either pin of the comparator(s). 2011 Microchip Technology Inc. The polarity of the comparator outputs can be changed using the C2INV and C1INV bits (CMCON<5:4>). Note 1: When reading the PORT register, all pins configured as analog inputs will read as `0'. Pins configured as digital inputs will convert an analog input according to the Schmitt Trigger input specification. 2: Analog levels on any pin defined as a digital input may cause the input buffer to consume more current than is specified. DS39762F-page 351 PIC18F97J60 FAMILY + To CxOUT pin - Port Pins COMPARATOR OUTPUT BLOCK DIAGRAM MULTIPLEX FIGURE 23-3: D Bus Data Q CxINV Read CMCON EN D Q EN CL From Other Comparator Reset 23.6 Comparator Interrupts The comparator interrupt flag is set whenever there is a change in the output value of either comparator. Software will need to maintain information about the status of the output bits, as read from CMCON<7:6>, to determine the actual change that occurred. The CMIF bit (PIR2<6>) is the Comparator Interrupt Flag. The CMIF bit must be reset by clearing it. Since it is also possible to write a `1' to this register, a simulated interrupt may be initiated. Both the CMIE bit (PIE2<6>) and the PEIE bit (INTCON<6>) must be set to enable the interrupt. In addition, the GIE bit (INTCON<7>) must also be set. If any of these bits are clear, the interrupt is not enabled, though the CMIF bit will still be set if an interrupt condition occurs. Note: If a change in the CMCON register (C1OUT or C2OUT) should occur when a read operation is being executed (start of the Q2 cycle), then the CMIF (PIR2 register) interrupt flag may not get set. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) b) Set CMIF bit 23.7 Comparator Operation During Sleep When a comparator is active and the device is placed in Sleep mode, the comparator remains active and the interrupt is functional, if enabled. This interrupt will wake-up the device from Sleep mode, when enabled. Each operational comparator will consume additional current, as shown in the comparator specifications. To minimize power consumption while in Sleep mode, turn off the comparators (CM<2:0> = 111) before entering Sleep. If the device wakes up from Sleep, the contents of the CMCON register are not affected. 23.8 Effects of a Reset A device Reset forces the CMCON register to its Reset state, causing the comparator modules to be turned off (CM<2:0> = 111). However, the input pins (RF3 through RF6) are configured as analog inputs by default on device Reset. The I/O configuration for these pins is determined by the setting of the PCFG<3:0> bits (ADCON1<3:0>). Therefore, device current is minimized when analog inputs are present at Reset time. Any read or write of CMCON will end the mismatch condition. Clear flag bit, CMIF. A mismatch condition will continue to set flag bit, CMIF. Reading CMCON will end the mismatch condition and allow flag bit, CMIF, to be cleared. DS39762F-page 352 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 23.9 range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up condition may occur. A maximum source impedance of 10 k is recommended for the analog sources. Any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current. Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 23-4. Since the analog pins are connected to a digital output, they have reverse biased diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this FIGURE 23-4: COMPARATOR ANALOG INPUT MODEL VDD VT = 0.6V RS < 10k AIN CPIN 5 pF VA VT = 0.6V RIC Comparator Input ILEAKAGE 500 nA VSS Legend: TABLE 23-1: Name INTCON CPIN VT ILEAKAGE RIC RS VA = = = = = = Input Capacitance Threshold Voltage Leakage Current at the pin due to various junctions Interconnect Resistance Source Impedance Analog Voltage REGISTERS ASSOCIATED WITH COMPARATOR MODULE Bit 7 Bit 6 GIE/GIEH PEIE/GIEL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 69 PIR2 OSCFIF CMIF ETHIF r BCL1IF -- TMR3IF CCP2IF 71 PIE2 OSCFIE CMIE ETHIE r BCL1IE -- TMR3IE CCP2IE 71 IPR2 OSCFIP CMIP ETHIP r BCL1IP -- TMR3IP CCP2IP 71 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 70 CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 70 PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 72 TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 71 Legend: -- = unimplemented, read as `0', r = reserved. Shaded cells are not used by the comparator module. 2011 Microchip Technology Inc. DS39762F-page 353 PIC18F97J60 FAMILY NOTES: DS39762F-page 354 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 24.0 COMPARATOR VOLTAGE REFERENCE MODULE The comparator voltage reference is a 16-tap resistor ladder network that provides a selectable reference voltage. Although its primary purpose is to provide a reference for the analog comparators, it may also be used independently of them. A block diagram of the module is shown in Figure 24-1. The resistor ladder is segmented to provide two ranges of CVREF values and has a power-down function to conserve power when the reference is not being used. The module's supply reference can be provided from either device VDD/VSS or an external voltage reference. 24.1 Configuring the Comparator Voltage Reference The voltage reference module is controlled through the CVRCON register (Register 24-1). The comparator voltage reference provides two ranges of output voltage, each with 16 distinct levels. The range to be used REGISTER 24-1: is selected by the CVRR bit (CVRCON<5>). The primary difference between the ranges is the size of the steps selected by the CVREF selection bits (CVR<3:0>), with one range offering finer resolution. The equations used to calculate the output of the comparator voltage reference are as follows: If CVRR = 1: CVREF = ((CVR<3:0>)/24) x (CVRSRC) If CVRR = 0: CVREF = (CVRSRC/4) + ((CVR<3:0>)/32) x (CVRSRC) The comparator reference supply voltage can come from either VDD and VSS, or the external VREF+ and VREF- that are multiplexed with RA2 and RA3. The voltage source is selected by the CVRSS bit (CVRCON<4>). The settling time of the comparator voltage reference must be considered when changing the CVREF output (see Table 28-3 in Section 28.0 "Electrical Characteristics"). CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE(1) CVRR CVRSS CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down bit 6 CVROE: Comparator VREF Output Enable bit(1) 1 = CVREF voltage level is also output on the RF5/AN10/CVREF pin 0 = CVREF voltage is disconnected from the RF5/AN10/CVREF pin bit 5 CVRR: Comparator VREF Range Selection bit 1 = 0 to 0.667 CVRSRC, with CVRSRC/24 step size (low range) 0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size (high range) bit 4 CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source, CVRSRC = (VREF+) - (VREF-) 0 = Comparator reference source, CVRSRC = VDD - VSS bit 3-0 CVR<3:0>: Comparator VREF Value Selection bits (0 (CVR<3:0>) 15) When CVRR = 1: CVREF = ((CVR<3:0>)/24) (CVRSRC) When CVRR = 0: CVREF = (CVRSRC/4) + ((CVR<3:0>)/32) (CVRSRC) Note 1: CVROE overrides the TRISF<5> bit setting. 2011 Microchip Technology Inc. DS39762F-page 355 PIC18F97J60 FAMILY FIGURE 24-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM VREF+ VDD CVRSS = 1 8R CVRSS = 0 CVR<3:0> R CVREN R R 16-to-1 MUX R 16 Steps R CVREF R R CVRR VREF- 8R CVRSS = 1 CVRSS = 0 24.2 Comparator Voltage Reference Accuracy/Error The full range of voltage reference cannot be realized due to the construction of the module. The transistors on the top and bottom of the resistor ladder network (Figure 24-1) keep CVREF from approaching the reference source rails. The voltage reference is derived from the reference source; therefore, the CVREF output changes with fluctuations in that source. The tested absolute accuracy of the voltage reference can be found in Section 28.0 "Electrical Characteristics". 24.3 Operation During Sleep When the device wakes up from Sleep through an interrupt, or a Watchdog Timer time-out, the contents of the CVRCON register are not affected. To minimize current consumption in Sleep mode, the voltage reference should be disabled. 24.4 Effects of a Reset A device Reset disables the voltage reference by clearing bit, CVREN (CVRCON<7>). This Reset also disconnects the reference from the RA2 pin by clearing bit, CVROE (CVRCON<6>), and selects the high-voltage range by clearing bit, CVRR (CVRCON<5>). The CVR value select bits are also cleared. 24.5 Connection Considerations The voltage reference module operates independently of the comparator module. The output of the reference generator may be connected to the RF5 pin if the CVROE bit is set. Enabling the voltage reference output onto RA2, when it is configured as a digital input, will increase current consumption. Connecting RF5 as a digital output with CVRSS enabled will also increase current consumption. The RF5 pin can be used as a simple D/A output with limited drive capability. Due to the limited current drive capability, a buffer must be used on the voltage reference output for external connections to VREF. Figure 24-2 shows an example buffering technique. DS39762F-page 356 2011 Microchip Technology Inc. PIC18F97J60 FAMILY FIGURE 24-2: COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC18FXXJ6X CVREF Module Note 1: TABLE 24-1: Name CVRCON R(1) Voltage Reference Output Impedance + - RF5 CVREF Output R is dependent upon the comparator voltage reference configuration bits, CVRCON<5> and CVRCON<3:0>. REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 70 CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 70 TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 71 Legend: -- = unimplemented, read as `0'. Shaded cells are not used with the comparator voltage reference module. 2011 Microchip Technology Inc. DS39762F-page 357 PIC18F97J60 FAMILY NOTES: DS39762F-page 358 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 25.0 SPECIAL FEATURES OF THE CPU PIC18F97J60 family devices include several features intended to maximize reliability and minimize cost through elimination of external components. These are: * Oscillator Selection * Resets: - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) * Interrupts * Watchdog Timer (WDT) * Fail-Safe Clock Monitor * Two-Speed Start-up * Code Protection * In-Circuit Serial Programming The oscillator can be configured for the application depending on frequency, power, accuracy and cost. All of the options are discussed in detail in Section 3.0 "Oscillator Configurations". A complete discussion of device Resets and interrupts is available in previous sections of this data sheet. In addition to their Power-up and Oscillator Start-up Timers provided for Resets, the PIC18F97J60 family of devices has a configurable Watchdog Timer which is controlled in software. The inclusion of an internal RC oscillator also provides the additional benefits of a Fail-Safe Clock Monitor (FSCM) and Two-Speed Start-up. FSCM provides for background monitoring of the peripheral clock and automatic switchover in the event of its failure. Two-Speed Start-up enables code to be executed almost immediately on start-up while the primary clock source completes its start-up delays. All of these features are enabled and configured by setting the appropriate Configuration register bits. 25.1 Configuration Bits 25.1.1 CONSIDERATIONS FOR CONFIGURING THE PIC18F97J60 FAMILY DEVICES Devices of the PIC18F97J60 family do not use persistent memory registers to store configuration information. The configuration bytes are implemented as volatile memory which means that configuration data must be programmed each time the device is powered up. Configuration data is stored in the four words at the top of the on-chip program memory space, known as the Flash Configuration Words, which are located in the program memory space, as shown in Table 6-1. The Configuration Words are stored in the same order shown in Table 25-1, with CONFIG1L at the lowest address and CONFIG3H at the highest. The data is automatically loaded in the proper Configuration registers during device power-up. When creating applications for these devices, users should always specifically allocate the location of the Flash Configuration Word for configuration data. This is to make certain that program code is not stored in this address when the code is compiled. The volatile memory cells used for the Configuration bits always reset to `1' on Power-on Resets. For all other types of Reset events, the previously programmed values are maintained and used without reloading from program memory. The four Most Significant bits of CONFIG1H, CONFIG2H and CONFIG3H, in program memory, should also be `1111'. This makes these Configuration Words appear to be NOP instructions in the remote event that their locations are ever executed by accident. Since Configuration bits are not implemented in the corresponding locations, writing `1's to these locations has no effect on device operation. To prevent inadvertent configuration changes during code execution, all programmable Configuration bits are write-once. After a bit is initially programmed during a power cycle, it cannot be written to again. Changing a device configuration requires that power to the device be cycled. The Configuration bits can be programmed (read as `0') or left unprogrammed (read as `1') to select various device configurations. These bits are mapped starting at program memory location, 300000h. A complete list is shown in Table 25-1. A detailed explanation of the various bit functions is provided in Register 25-1 through Register 25-8. 2011 Microchip Technology Inc. DS39762F-page 359 PIC18F97J60 FAMILY TABLE 25-1: CONFIGURATION BITS AND DEVICE IDs File Name 300000h CONFIG1L Default/ Unprogrammed Value(1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DEBUG XINST STVREN -- -- -- -- WDTEN 110- ---1 (2) (2) (2) (2) (3) 300001h CONFIG1H -- CP0 -- -- ---- 01-- 300002h CONFIG2L IESO FCMEN -- -- -- FOSC2 FOSC1 FOSC0 11-- -111 300003h CONFIG2H --(2) --(2) --(2) --(2) WDTPS3 WDTPS2 WDTPS1 WDTPS0 ---- 1111 300004h CONFIG3L WAIT(4) BW(4) EMB1(4) -- -- -- 1111 1--- 300005h CONFIG3H --(2) --(2) --(2) --(2) -- 3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 xxxx xxxx(6) 3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 xxxx xxxx(6) Legend: Note 1: 2: 3: 4: 5: 6: -- -- -- -- EMB0(4) EASHFT(4) ETHLED ECCPMX(5) CCP2MX(5) ---- -111 x = unknown, u = unchanged, - = unimplemented. Shaded cells are unimplemented, read as `0'. Values reflect the unprogrammed state as received from the factory and following Power-on Resets. In all other Reset states, the configuration bytes maintain their previously programmed states. The value of these bits in program memory should always be `1'. This ensures that the location is executed as a NOP if it is accidentally executed. This bit should always be maintained as `0'. Implemented in 100-pin devices only. Implemented in 80-pin and 100-pin devices only. See Register 25-7 and Register 25-8 for DEVID values. These registers are read-only and cannot be programmed by the user. DS39762F-page 360 2011 Microchip Technology Inc. PIC18F97J60 FAMILY REGISTER 25-1: CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h) R/WO-1 R/WO-1 R/WO-0 U-0 U-0 U-0 U-0 R/WO-1 DEBUG XINST STVREN -- -- -- -- WDTEN bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit -n = Value when device is unprogrammed U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared bit 7 DEBUG: Background Debugger Enable bit 1 = Background debugger is disabled; RB6 and RB7 are configured as general purpose I/O pins 0 = Background debugger is enabled; RB6 and RB7 are dedicated to In-Circuit Debug bit 6 XINST: Extended Instruction Set Enable bit 1 = Instruction set extension and Indexed Addressing mode are enabled 0 = Instruction set extension and Indexed Addressing mode are disabled (Legacy mode) bit 5 STVREN: Stack Overflow/Underflow Reset Enable bit 1 = Reset on stack overflow/underflow is enabled 0 = Reset on stack overflow/underflow is disabled bit 4-1 Unimplemented: Read as `0' bit 0 WDTEN: Watchdog Timer Enable bit 1 = WDT is enabled 0 = WDT is disabled (control is placed on SWDTEN bit) REGISTER 25-2: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h) U-0 U-0 U-0 U-0 U-0(1) R/WO-1 U-0 U-0 --(2) --(2) --(2) --(2) -- CP0 -- -- bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit -n = Value when device is unprogrammed bit 7-3 Unimplemented: Read as `0' bit 2 CP0: Code Protection bit 1 = Program memory is not code-protected 0 = Program memory is code-protected bit 1-0 Unimplemented: Read as `0' Note 1: 2: U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared This bit should always be maintained as `0'. The value of these bits in program memory should always be `1'. This ensures that the location is executed as a NOP if it is accidentally executed. 2011 Microchip Technology Inc. DS39762F-page 361 PIC18F97J60 FAMILY REGISTER 25-3: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h) R/WO-1 R/WO-1 U-0 U-0 U-0 R/WO-1 R/WO-1 R/WO-1 IESO FCMEN -- -- -- FOSC2 FOSC1 FOSC0 bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit -n = Value when device is unprogrammed U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared bit 7 IESO: Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit 1 = Two-Speed Start-up is enabled 0 = Two-Speed Start-up is disabled bit 6 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor is enabled 0 = Fail-Safe Clock Monitor is disabled bit 5-3 Unimplemented: Read as `0' bit 2 FOSC2: Default/Reset System Clock Select bit 1 = Clock selected by FOSC<1:0> as system clock is enabled when OSCCON<1:0> = 00 0 = INTRC enabled as system clock when OSCCON<1:0> = 00 bit 1-0 FOSC<1:0>: Oscillator Selection bits 11 = EC oscillator, PLL is enabled and under software control, CLKO function on OSC2 10 = EC oscillator, CLKO function on OSC2 01 = HS oscillator, PLL is enabled and under software control 00 = HS oscillator DS39762F-page 362 2011 Microchip Technology Inc. PIC18F97J60 FAMILY REGISTER 25-4: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h) U-0 U-0 U-0 U-0 R/WO-1 R/WO-1 R/WO-1 R/WO-1 --(1) --(1) --(1) --(1) WDTPS3 WDTPS2 WDTPS1 WDTPS0 bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit -n = Value when device is unprogrammed U = Unimplemented bit, read as `0' `1' = Bit is set bit 7-4 Unimplemented: Read as `0' bit 3-0 WDTPS<3:0>: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 Note 1: `0' = Bit is cleared The value of these bits in program memory should always be `1'. This ensures that the location is executed as a NOP if it is accidentally executed. 2011 Microchip Technology Inc. DS39762F-page 363 PIC18F97J60 FAMILY REGISTER 25-5: R/WO-1 CONFIG3L: CONFIGURATION REGISTER 3 LOW (BYTE ADDRESS 300004h) R/WO-1 (1) BW WAIT (1) R/WO-1 R/WO-1 (1) (1) EMB1 EMB0 R/WO-1 EASHFT (1) U-0 U-0 U-0 -- -- -- bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit -n = Value when device is unprogrammed U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared bit 7 WAIT: External Bus Wait Enable bit(1) 1 = Wait states for operations on external memory bus is disabled 0 = Wait states for operations on external memory bus is enabled and selected by MEMCON<5:4> bit 6 BW: Data Bus Width Select bit(1) 1 = 16-Bit Data Width mode 0 = 8-Bit Data Width mode bit 5-4 EMB<1:0>: External Memory Bus Configuration bits(1) 11 = Microcontroller mode, external bus disabled 10 = Extended Microcontroller mode,12-Bit Addressing mode 01 = Extended Microcontroller mode,16-Bit Addressing mode 00 = Extended Microcontroller mode, 20-Bit Addressing mode bit 3 EASHFT: External Address Bus Shift Enable bit(1) 1 = Address shifting is enabled; address on external bus is offset to start at 000000h 0 = Address shifting is disabled; address on external bus reflects the PC value bit 2-0 Unimplemented: Read as `0' Note 1: Implemented on 100-pin devices only. DS39762F-page 364 2011 Microchip Technology Inc. PIC18F97J60 FAMILY REGISTER 25-6: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h) U-0 U-0 U-0 U-0 (1) (1) (1) (1) -- -- -- -- U-0 -- R/WO-1 ETHLED R/WO-1 ECCPMX (2) R/WO-1 CCP2MX(2) bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit -n = Value when device is unprogrammed U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared bit 7-3 Unimplemented: Read as `0' bit 2 ETHLED: Ethernet LED Enable bit 1 = RA0/RA1 are multiplexed with LEDA/LEDB when the Ethernet module is enabled and function as I/O when the Ethernet is disabled 0 = RA0/RA1 function as I/O regardless of Ethernet module status bit 1 ECCPMX: ECCP MUX bit(2) 1 = ECCP1 outputs (P1B/P1C) are multiplexed with RE6 and RE5; ECCP3 outputs (P3B/P3C) are multiplexed with RE4 and RE3 0 = ECCP1 outputs (P1B/P1C) are multiplexed with RH7 and RH6; ECCP3 outputs (P3B/P3C) are multiplexed with RH5 and RH4 bit 0 CCP2MX: ECCP2 MUX bit(2) 1 = ECCP2/P2A is multiplexed with RC1 0 = ECCP2/P2A is multiplexed with RE7 in Microcontroller mode (80-pin and 100-pin devices) or with RB3 in Extended Microcontroller mode (100-pin devices only) Note 1: 2: The value of these bits in program memory should always be `1'. This ensures that the location is executed as a NOP if it is accidentally executed. Implemented in 80-pin and 100-pin devices only. 2011 Microchip Technology Inc. DS39762F-page 365 PIC18F97J60 FAMILY REGISTER 25-7: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F97J60 FAMILY DEVICES R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Read-only bit P = Programmable bit U = Unimplemented bit, read as `0' -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7-5 DEV<2:0>: Device ID bits See Register 25-8 for a complete listing. bit 4-0 REV<4:0>: Revision ID bits These bits are used to indicate the device revision. REGISTER 25-8: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F97J60 FAMILY DEVICES R R R R R R R R DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 bit 7 bit 0 Legend: R = Read-only bit P = Programmable bit -n = Value when device is unprogrammed bit 7-0 U = Unimplemented bit, read as `0' u = Unchanged from programmed state DEV<10:3>: Device ID bits: DS39762F-page 366 DEV<10:3> (DEVID2<7:0>) DEV<2:0> (DEVID1<7:5>) Device 0001 1000 000 PIC18F66J60 0001 1111 000 PIC18F66J65 0001 1111 001 PIC18F67J60 0001 1000 001 PIC18F86J60 0001 1111 010 PIC18F86J65 0001 1111 011 PIC18F87J60 0001 1000 010 PIC18F96J60 0001 1111 100 PIC18F96J65 0001 1111 101 PIC18F97J60 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 25.2 Watchdog Timer (WDT) For PIC18F97J60 family devices, the WDT is driven by the INTRC oscillator. When the WDT is enabled, the clock source is also enabled. The nominal WDT period is 4 ms and has the same stability as the INTRC oscillator. The 4 ms period of the WDT is multiplied by a 16-bit postscaler. Any output of the WDT postscaler is selected by a multiplexor, controlled by the WDTPS bits in Configuration Register 2H. Available periods range from 4 ms to 131.072 seconds (2.18 minutes). The WDT and postscaler are cleared whenever a SLEEP or CLRWDT instruction is executed, or a clock failure (primary or Timer1 oscillator) has occurred. FIGURE 25-1: SWDTEN Note 1: The CLRWDT and SLEEP instructions clear the WDT and postscaler counts when executed. 2: When a CLRWDT instruction is executed, the postscaler count will be cleared. 25.2.1 CONTROL REGISTER The WDTCON register (Register 25-9) is a readable and writable register. The SWDTEN bit enables or disables WDT operation. This allows software to override the WDTEN Configuration bit and enable the WDT only if it has been disabled by the Configuration bit. WDT BLOCK DIAGRAM Enable WDT INTRC Control WDT Counter INTRC Oscillator Wake-up from Power-Managed Modes 128 Programmable Postscaler 1:1 to 1:32,768 CLRWDT All Device Resets Reset WDT Reset WDT WDTPS<3:0> 4 Sleep 2011 Microchip Technology Inc. DS39762F-page 367 PIC18F97J60 FAMILY REGISTER 25-9: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 -- -- -- -- -- -- -- SWDTEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-1 Unimplemented: Read as `0' bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit(1) 1 = Watchdog Timer is on 0 = Watchdog Timer is off Note 1: This bit has no effect if the Configuration bit, WDTEN, is enabled. TABLE 25-2: Name RCON WDTCON x = Bit is unknown SUMMARY OF WATCHDOG TIMER REGISTERS Bit 0 Reset Values on Page: POR BOR 70 -- SWDTEN 70 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 IPEN -- CM RI TO PD -- -- -- -- -- -- Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the Watchdog Timer. DS39762F-page 368 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 25.3 On-Chip Voltage Regulator All of the PIC18F97J60 family devices power their core digital logic at a nominal 2.5V. This may create an issue for designs that are required to operate at a higher typical voltage, such as 3.3V. To simplify system design, all devices in the PIC18F97J60 family incorporate an on-chip regulator that allows the device to run its core logic from VDD. The regulator is controlled by the ENVREG pin. Tying VDD to the pin enables the regulator, which in turn, provides power to the core from the other VDD pins. When the regulator is enabled, a low-ESR filter capacitor must be connected to the VDDCORE/VCAP pin (Figure 25-2). This helps to maintain the stability of the regulator. The recommended value for the filter capacitor is provided in Section 28.3 "DC Characteristics: PIC18F97J60 Family (Industrial)". If ENVREG is tied to VSS, the regulator is disabled. In this case, separate power for the core logic, at a nominal 2.5V, must be supplied to the device on the VDDCORE/VCAP pin to run the I/O pins at higher voltage levels, typically 3.3V. Alternatively, the VDDCORE/VCAP and VDD pins can be tied together to operate at a lower nominal voltage. Refer to Figure 25-2 for possible configurations. 25.3.1 FIGURE 25-2: Regulator Enabled (ENVREG tied to VDD): 3.3V PIC18FXXJ6X VDD ENVREG VDDCORE/VCAP CF (VDD > VDDCORE) 2.5V(1) 3.3V(1) PIC18FXXJ6X VDD ENVREG VDDCORE/VCAP VSS (VDD = VDDCORE) 2.5V(1) PIC18FXXJ6X VDD The operation of the BOR is described in more detail in Section 5.4 "Brown-out Reset (BOR)" and Section 5.4.1 "Detecting BOR". The Brown-out Reset voltage levels are specific in Section 28.1 "DC Characteristics: Supply Voltage, PIC18F97J60 Family (Industrial)" 25.3.2 POWER-UP REQUIREMENTS The on-chip regulator is designed to meet the power-up requirements for the device. If the application does not use the regulator, then strict power-up conditions must be adhered to. While powering up, VDDCORE must never exceed VDD by 0.3 volts. 2011 Microchip Technology Inc. VSS Regulator Disabled (ENVREG tied to ground): ON-CHIP REGULATOR AND BOR When the on-chip regulator is enabled, PIC18F97J60 family devices also have a simple brown-out capability. If the voltage supplied to the regulator is inadequate to maintain a regulated level, the regulator Reset circuitry will generate a Brown-out Reset. This event is captured by the BOR flag bit (RCON<0>). CONNECTIONS FOR THE ON-CHIP REGULATOR ENVREG VDDCORE/VCAP VSS Note 1: These are typical operating voltages. Refer to Section 28.1 "DC Characteristics: Supply Voltage" for the full operating ranges of VDD and VDDCORE. DS39762F-page 369 PIC18F97J60 FAMILY 25.4 In all other power-managed modes, Two-Speed Start-up is not used. The device will be clocked by the currently selected clock source until the primary clock source becomes available. The setting of the IESO bit is ignored. Two-Speed Start-up The Two-Speed Start-up feature helps to minimize the latency period, from oscillator start-up to code execution, by allowing the microcontroller to use the INTRC oscillator as a clock source until the primary clock source is available. It is enabled by setting the IESO Configuration bit. 25.4.1 Two-Speed Start-up should be enabled only if the primary oscillator mode is HS or HSPLL (Crystal-Based) modes. Since the EC and ECPLL modes do not require an Oscillator Start-up Timer delay, Two-Speed Start-up should be disabled. While using the INTRC oscillator in Two-Speed Start-up, the device still obeys the normal command sequences for entering power-managed modes, including serial SLEEP instructions (refer to Section 4.1.4 "Multiple Sleep Commands"). In practice, this means that user code can change the SCS<1:0> bit settings, or issue SLEEP instructions, before the OST times out. This would allow an application to briefly wake-up, perform routine "housekeeping" tasks and return to Sleep before the device starts to operate from the primary oscillator. When enabled, Resets and wake-ups from Sleep mode cause the device to configure itself to run from the internal oscillator block as the clock source, following the time-out of the Power-up Timer after a Power-on Reset is enabled. This allows almost immediate code execution while the primary oscillator starts and the OST is running. Once the OST times out, the device automatically switches to PRI_RUN mode. FIGURE 25-3: SPECIAL CONSIDERATIONS FOR USING TWO-SPEED START-UP User code can also check if the primary clock source is currently providing the device clocking by checking the status of the OSTS bit (OSCCON<3>). If the bit is set, the primary oscillator is providing the clock. Otherwise, the internal oscillator block is providing the clock during wake-up from Reset or Sleep mode. TIMING TRANSITION FOR TWO-SPEED START-UP (INTRC TO HSPLL) Q1 Q2 Q3 Q4 Q2 Q3 Q4 Q1 Q2 Q3 Q1 INTRC OSC1 TOST(1) TPLL(1) 1 PLL Clock Output 2 n-1 n Clock Transition CPU Clock Peripheral Clock Program Counter PC Wake from Interrupt Event Note 1: DS39762F-page 370 PC + 2 PC + 4 PC + 6 OSTS bit Set TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 25.5 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the microcontroller to continue operation in the event of an external oscillator failure by automatically switching the device clock to the internal oscillator block. The FSCM function is enabled by setting the FCMEN Configuration bit. When FSCM is enabled, the INTRC oscillator runs at all times to monitor clocks to peripherals and provide a backup clock in the event of a clock failure. Clock monitoring (shown in Figure 25-4) is accomplished by creating a sample clock signal which is the INTRC output, divided by 64. This allows ample time between FSCM sample clocks for a peripheral clock edge to occur. The peripheral device clock and the sample clock are presented as inputs to the Clock Monitor (CM) latch. The CM is set on the falling edge of the device clock source but cleared on the rising edge of the sample clock. FIGURE 25-4: FSCM BLOCK DIAGRAM Clock Monitor Latch (CM) (edge-triggered) Peripheral Clock INTRC Source / 64 (32 s) 488 Hz (2.048 ms) S Q C Q The FSCM will detect failures of the primary or secondary clock sources only. If the internal oscillator block fails, no failure would be detected, nor would any action be possible. 25.5.1 Clock failure is tested for on the falling edge of the sample clock. If a sample clock falling edge occurs while CM is still set, a clock failure has been detected (Figure 25-5). This causes the following: * The FSCM generates an oscillator fail interrupt by setting bit, OSCFIF (PIR2<7>) * The device clock source is switched to the internal oscillator block (OSCCON is not updated to show the current clock source - this is the fail-safe condition) * The WDT is reset FSCM AND THE WATCHDOG TIMER Both the FSCM and the WDT are clocked by the INTRC oscillator. Since the WDT operates with a separate divider and counter, disabling the WDT has no effect on the operation of the INTRC oscillator when the FSCM is enabled. As already noted, the clock source is switched to the INTRC clock when a clock failure is detected. This may mean a substantial change in the speed of code execution. If the WDT is enabled with a small prescale value, a decrease in clock speed allows a WDT time-out to occur and a subsequent device Reset. For this reason, Fail-Safe Clock events also reset the WDT and postscaler, allowing it to start timing from when execution speed was changed, and decreasing the likelihood of an erroneous time-out. 25.5.2 Clock Failure Detected 2011 Microchip Technology Inc. During switchover, the postscaler frequency from the internal oscillator block may not be sufficiently stable for timing-sensitive applications. In these cases, it may be desirable to select another clock configuration and enter an alternate power-managed mode. This can be done to attempt a partial recovery or execute a controlled shutdown. See Section 4.1.4 "Multiple Sleep Commands" and Section 25.4.1 "Special Considerations for Using Two-Speed Start-up" for more details. EXITING FAIL-SAFE OPERATION The fail-safe condition is terminated by either a device Reset or by entering a power-managed mode. On Reset, the controller starts the primary clock source specified in Configuration Register 2H (with any required start-up delays that are required for the oscillator mode, such as OST or PLL timer). The INTRC oscillator provides the device clock until the primary clock source becomes ready (similar to a Two-Speed Start-up). The clock source is then switched to the primary clock (indicated by the OSTS bit in the OSCCON register becoming set). The Fail-Safe Clock Monitor then resumes monitoring the peripheral clock. The primary clock source may never become ready during start-up. In this case, operation is clocked by the INTRC oscillator. The OSCCON register will remain in its Reset state until a power-managed mode is entered. DS39762F-page 371 PIC18F97J60 FAMILY FIGURE 25-5: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure Device Clock Output CM Output (Q) Failure Detected OSCFIF CM Test Note: 25.5.3 CM Test The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. FSCM INTERRUPTS IN POWER-MANAGED MODES By entering a power-managed mode, the clock multiplexor selects the clock source selected by the OSCCON register. Fail-Safe Monitoring of the power-managed clock source resumes in the power-managed mode. If an oscillator failure occurs during power-managed operation, the subsequent events depend on whether or not the oscillator failure interrupt is enabled. If enabled (OSCFIF = 1), code execution will be clocked by the INTRC multiplexor. An automatic transition back to the failed clock source will not occur. If the interrupt is disabled, subsequent interrupts while in Idle mode will cause the CPU to begin executing instructions while being clocked by the INTRC source. 25.5.4 CM Test POR OR WAKE-UP FROM SLEEP The FSCM is designed to detect oscillator failure at any point after the device has exited Power-on Reset (POR) or low-power Sleep mode. When the primary device clock is either EC or INTRC, monitoring can begin immediately following these events. DS39762F-page 372 For HS or HSPLL modes, the situation is somewhat different. Since the oscillator may require a start-up time considerably longer than the FSCM sample clock time, a false clock failure may be detected. To prevent this, the internal oscillator block is automatically configured as the device clock and functions until the primary clock is stable (the OST and PLL timers have timed out). This is identical to Two-Speed Start-up mode. Once the primary clock is stable, the INTRC returns to its role as the FSCM source. Note: The same logic that prevents false oscillator failure interrupts on POR, or wake from Sleep, will also prevent the detection of the oscillator's failure to start at all following these events. This can be avoided by monitoring the OSTS bit and using a timing routine to determine if the oscillator is taking too long to start. Even so, no oscillator failure interrupt will be flagged. As noted in Section 25.4.1 "Special Considerations for Using Two-Speed Start-up", it is also possible to select another clock configuration and enter an alternate power-managed mode while waiting for the primary clock to become stable. When the new power-managed mode is selected, the primary clock is disabled. 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 25.6 Program Verification and Code Protection For all devices in the PIC18F97J60 family, the on-chip program memory space is treated as a single block. Code protection for this block is controlled by one Configuration bit, CP0. This bit inhibits external reads and writes to the program memory space. It has no direct effect in normal execution mode. 25.6.1 CONFIGURATION REGISTER PROTECTION The Configuration registers are protected against untoward changes or reads in two ways. The primary protection is the write-once feature of the Configuration bits which prevents reconfiguration once the bit has been programmed during a power cycle. To safeguard against unpredictable events, Configuration bit changes resulting from individual cell level disruptions (such as ESD events) will cause a parity error and trigger a device Reset. The data for the Configuration registers is derived from the Flash Configuration Words in program memory. When the CP0 bit is programmed (cleared), the source data for device configuration is also protected as a consequence. 2011 Microchip Technology Inc. 25.7 In-Circuit Serial Programming PIC18F97J60 family microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. 25.8 In-Circuit Debugger When the DEBUG Configuration bit is programmed to a `0', the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB(R) IDE. When the microcontroller has this feature enabled, some resources are not available for general use. Table 25-3 shows which resources are required by the background debugger. TABLE 25-3: DEBUGGER RESOURCES I/O pins: RB6, RB7 Stack: 2 levels Program Memory: 512 bytes Data Memory: 10 bytes DS39762F-page 373 PIC18F97J60 FAMILY NOTES: DS39762F-page 374 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 26.0 INSTRUCTION SET SUMMARY The PIC18F97J60 family of devices incorporates the standard set of 75 PIC18 core instructions, as well as an extended set of 8 new instructions for the optimization of code that is recursive or that utilizes a software stack. The extended set is discussed later in this section. 26.1 Standard Instruction Set The standard PIC18 instruction set adds many enhancements to the previous PIC(R) MCU instruction sets, while maintaining an easy migration from these PIC MCU instruction sets. Most instructions are a single program memory word (16 bits), but there are four instructions that require two program memory locations. Each single-word instruction is a 16-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into four basic categories: * * * * Byte-oriented operations Bit-oriented operations Literal operations Control operations The PIC18 instruction set summary in Table 26-2 lists byte-oriented, bit-oriented, literal and control operations. Table 26-1 shows the opcode field descriptions. Most byte-oriented instructions have three operands: 1. 2. 3. The file register (specified by `f') The destination of the result (specified by `d') The accessed memory (specified by `a') The file register designator `f' specifies which file register is to be used by the instruction. The destination designator `d' specifies where the result of the operation is to be placed. If `d' is zero, the result is placed in the WREG register. If `d' is one, the result is placed in the file register specified in the instruction. All bit-oriented instructions have three operands: 1. 2. 3. The file register (specified by `f') The bit in the file register (specified by `b') The accessed memory (specified by `a') The literal instructions may use some of the following operands: * A literal value to be loaded into a file register (specified by `k') * The desired FSR register to load the literal value into (specified by `f') * No operand required (specified by `--') The control instructions may use some of the following operands: * A program memory address (specified by `n') * The mode of the CALL or RETURN instructions (specified by `s') * The mode of the table read and table write instructions (specified by `m') * No operand required (specified by `--') All instructions are a single word, except for four double-word instructions. These instructions were made double-word to contain the required information in 32 bits. In the second word, the 4 MSbs are `1's. If this second word is executed as an instruction (by itself), it will execute as a NOP. All single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a NOP. The double-word instructions execute in two instruction cycles. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true, or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. Two-word branch instructions (if true) would take 3 s. Figure 26-1 shows the general formats that the instructions can have. All examples use the convention `nnh' to represent a hexadecimal number. The Instruction Set Summary, shown in Table 26-2, lists the standard instructions recognized by the Microchip MPASMTM Assembler. Section 26.1.1 "Standard Instruction Set" provides a description of each instruction. The bit field designator `b' selects the number of the bit affected by the operation, while the file register designator `f' represents the number of the file in which the bit is located. 2011 Microchip Technology Inc. DS39762F-page 375 PIC18F97J60 FAMILY TABLE 26-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit: a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative. d Destination select bit: d = 0: store result in WREG d = 1: store result in file register f dest Destination: either the WREG register or the specified register file location. f 8-bit Register file address (00h to FFh), or 2-bit FSR designator (0h to 3h). fs 12-bit Register file address (000h to FFFh). This is the source address. fd 12-bit Register file address (000h to FFFh). This is the destination address. GIE Global Interrupt Enable bit. k Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value). label Label name. mm The mode of the TBLPTR register for the table read and table write instructions. Only used with table read and table write instructions: * No Change to register (such as TBLPTR with table reads and writes) *+ Post-Increment register (such as TBLPTR with table reads and writes) *- Post-Decrement register (such as TBLPTR with table reads and writes) Pre-Increment register (such as TBLPTR with table reads and writes) +* n The relative address (2's complement number) for relative branch instructions or the direct address for Call/Branch and Return instructions. PC Program Counter. PCL Program Counter Low Byte. PCH Program Counter High Byte. PCLATH Program Counter High Byte Latch. PCLATU Program Counter Upper Byte Latch. PD Power-Down bit. PRODH Product of Multiply High Byte. PRODL Product of Multiply Low Byte. s Fast Call/Return mode select bit: s = 0: do not update into/from shadow registers s = 1: certain registers loaded into/from shadow registers (Fast mode) TBLPTR 21-bit Table Pointer (points to a program memory location). TABLAT 8-bit Table Latch. TO Time-out bit. TOS Top-of-Stack. u Unused or Unchanged. WDT Watchdog Timer. WREG Working register (accumulator). x Don't care (`0' or `1'). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. zs 7-bit offset value for indirect addressing of register files (source). 7-bit offset value for indirect addressing of register files (destination). zd { } Optional argument. [text] Indicates an indexed address. (text) The contents of text. [expr]<n> Specifies bit n of the register indicated by the pointer expr. Assigned to. < > Register bit field. In the set of. italics User-defined term (font is Courier New). DS39762F-page 376 2011 Microchip Technology Inc. PIC18F97J60 FAMILY FIGURE 26-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 15 10 9 OPCODE Example Instruction 8 7 d 0 a f (FILE #) ADDWF MYREG, W, B d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 0 OPCODE 15 f (Source FILE #) 12 11 MOVFF MYREG1, MYREG2 0 f (Destination FILE #) 1111 f = 12-bit file register address Bit-oriented file register operations 15 12 11 9 8 7 0 OPCODE b (BIT #) a f (FILE #) BSF MYREG, bit, B b = 3-bit position of bit in file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Literal operations 15 8 7 0 OPCODE k (literal) MOVLW 7Fh k = 8-bit immediate value Control operations CALL, GOTO and Branch operations 15 8 7 0 OPCODE 15 n<7:0> (literal) 12 11 GOTO Label 0 n<19:8> (literal) 1111 n = 20-bit immediate value 15 8 7 S OPCODE 15 0 n<7:0> (literal) 12 11 CALL MYFUNC 0 n<19:8> (literal) 1111 S = Fast bit 15 11 10 OPCODE 15 0 n<10:0> (literal) 8 7 OPCODE 2011 Microchip Technology Inc. BRA MYFUNC 0 n<7:0> (literal) BC MYFUNC DS39762F-page 377 PIC18F97J60 FAMILY TABLE 26-2: PIC18F97J60 FAMILY INSTRUCTION SET Mnemonic, Operands 16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED OPERATIONS ADDWF ADDWFC ANDWF CLRF COMF CPFSEQ CPFSGT CPFSLT DECF DECFSZ DCFSNZ INCF INCFSZ INFSNZ IORWF MOVF MOVFF f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a fs, fd MOVWF MULWF NEGF RLCF RLNCF RRCF RRNCF SETF SUBFWB f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a f, d, a SUBWF SUBWFB f, d, a Add WREG and f Add WREG and Carry bit to f AND WREG with f Clear f Complement f Compare f with WREG, Skip = Compare f with WREG, Skip > Compare f with WREG, Skip < Decrement f Decrement f, Skip if 0 Decrement f, Skip if Not 0 Increment f Increment f, Skip if 0 Increment f, Skip if Not 0 Inclusive OR WREG with f Move f Move fs (source) to 1st word fd (destination) 2nd word Move WREG to f Multiply WREG with f Negate f Rotate Left f through Carry Rotate Left f (No Carry) Rotate Right f through Carry Rotate Right f (No Carry) Set f Subtract f from WREG with Borrow Subtract WREG from f Subtract WREG from f with Borrow Swap Nibbles in f Test f, Skip if 0 Exclusive OR WREG with f 1 1 1 1 1 1 (2 or 3) 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 2 C, DC, Z, OV, N C, DC, Z, OV, N Z, N Z Z, N None None None C, DC, Z, OV, N None None C, DC, Z, OV, N None None Z, N Z, N None 1, 2 1, 2 1,2 2 1, 2 4 4 1, 2 1, 2, 3, 4 1, 2, 3, 4 1, 2 1, 2, 3, 4 4 1, 2 1, 2 1 1 1 1 1 1 1 1 1 1 0010 0010 0001 0110 0001 0110 0110 0110 0000 0010 0100 0010 0011 0100 0001 0101 1100 1111 0110 0000 0110 0011 0100 0011 0100 0110 0101 01da 00da 01da 101a 11da 001a 010a 000a 01da 11da 11da 10da 11da 10da 00da 00da ffff ffff 111a 001a 110a 01da 01da 00da 00da 100a 01da ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff 1 1 0101 0101 11da 10da ffff ffff ffff C, DC, Z, OV, N 1, 2 ffff C, DC, Z, OV, N 1 1 (2 or 3) 1 0011 0110 0001 10da 011a 10da ffff ffff ffff ffff None ffff None ffff Z, N None None 1, 2 C, DC, Z, OV, N C, Z, N 1, 2 Z, N C, Z, N Z, N None 1, 2 C, DC, Z, OV, N 4 1, 2 SWAPF TSTFSZ XORWF f, d, a f, a f, d, a Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as an input and is driven low by an external device, the data will be written back with a `0'. If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. 2: 3: 4: DS39762F-page 378 2011 Microchip Technology Inc. PIC18F97J60 FAMILY TABLE 26-2: PIC18F97J60 FAMILY INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes BIT-ORIENTED OPERATIONS BCF BSF BTFSC BTFSS BTG f, b, a f, b, a f, b, a f, b, a f, b, a Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Bit Toggle f 1 1 1 (2 or 3) 1 (2 or 3) 1 1001 1000 1011 1010 0111 bbba bbba bbba bbba bbba ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff None None None None None 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 2 0010 0110 0011 0111 0101 0001 0100 0nnn 0000 110s kkkk 0000 0000 1111 kkkk 0000 xxxx 0000 0000 1nnn 0000 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0000 0000 kkkk kkkk 0000 xxxx 0000 0000 nnnn 1111 0001 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0100 0111 kkkk kkkk 0000 xxxx 0110 0101 nnnn 1111 000s None None None None None None None None None None 1 1 1 1 2 1 2 1110 1110 1110 1110 1110 1110 1110 1101 1110 1110 1111 0000 0000 1110 1111 0000 1111 0000 0000 1101 0000 0000 2 2 1 0000 0000 0000 1100 0000 0000 kkkk 0001 0000 1, 2 1, 2 3, 4 3, 4 1, 2 CONTROL OPERATIONS BC BN BNC BNN BNOV BNZ BOV BRA BZ CALL n n n n n n n n n n, s NOP NOP POP PUSH RCALL RESET RETFIE -- -- -- -- n s Branch if Carry Branch if Negative Branch if Not Carry Branch if Not Negative Branch if Not Overflow Branch if Not Zero Branch if Overflow Branch Unconditionally Branch if Zero Call Subroutine 1st word 2nd word Clear Watchdog Timer Decimal Adjust WREG Go to Address 1st word 2nd word No Operation No Operation Pop Top of Return Stack (TOS) Push Top of Return Stack (TOS) Relative Call Software Device Reset Return from Interrupt Enable RETLW RETURN SLEEP k s -- Return with Literal in WREG Return from Subroutine Go into Standby mode Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as an input and is driven low by an external device, the data will be written back with a `0'. If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. CLRWDT -- DAW -- GOTO n 2: 3: 4: 2011 Microchip Technology Inc. 1 1 2 TO, PD C None None None None None None All GIE/GIEH, PEIE/GIEL kkkk None 001s None 0011 TO, PD 4 DS39762F-page 379 PIC18F97J60 FAMILY TABLE 26-2: PIC18F97J60 FAMILY INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes LITERAL OPERATIONS ADDLW ANDLW IORLW LFSR k k k f, k MOVLB MOVLW MULLW RETLW SUBLW XORLW k k k k k k Add Literal and WREG AND Literal with WREG Inclusive OR Literal with WREG Move Literal (12-bit) 2nd word to FSR(f) 1st word Move Literal to BSR<3:0> Move Literal to WREG Multiply Literal with WREG Return with Literal in WREG Subtract WREG from Literal Exclusive OR Literal with WREG 1 1 1 2 1 1 1 2 1 1 0000 0000 0000 1110 1111 0000 0000 0000 0000 0000 0000 1111 1011 1001 1110 0000 0001 1110 1101 1100 1000 1010 kkkk kkkk kkkk 00ff kkkk 0000 kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk C, DC, Z, OV, N Z, N Z, N None 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 1001 1010 1011 1100 1101 1110 1111 None None None None None None None None None None None None C, DC, Z, OV, N Z, N DATA MEMORY PROGRAM MEMORY OPERATIONS TBLRD* TBLRD*+ TBLRD*TBLRD+* TBLWT* TBLWT*+ TBLWT*TBLWT+* Note 1: 2: 3: 4: Table Read 2 Table Read with Post-Increment Table Read with Post-Decrement Table Read with Pre-Increment Table Write 2 Table Write with Post-Increment Table Write with Post-Decrement Table Write with Pre-Increment When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as an input and is driven low by an external device, the data will be written back with a `0'. If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. DS39762F-page 380 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 26.1.1 STANDARD INSTRUCTION SET ADDLW ADD Literal to W ADDWF ADD W to f Syntax: ADDLW Syntax: ADDWF Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) + (f) dest Status Affected: N, OV, C, DC, Z k Operands: 0 k 255 Operation: (W) + k W Status Affected: N, OV, C, DC, Z Encoding: 0000 1111 kkkk kkkk Description: The contents of W are added to the 8-bit literal `k' and the result is placed in W. Words: 1 Cycles: 1 Encoding: 0010 Description: Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k' Process Data Write to W Example: ADDLW 01da ffff ffff Add W to register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 15h Before Instruction W = 10h After Instruction W = 25h f {,d {,a}} Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example: ADDWF Before Instruction W = REG = After Instruction W = REG = Note: REG, 0, 0 17h 0C2h 0D9h 0C2h All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s). 2011 Microchip Technology Inc. DS39762F-page 381 PIC18F97J60 FAMILY ADDWFC ADD W and Carry bit to f ANDLW AND Literal with W Syntax: ADDWFC Syntax: ANDLW Operands: 0 f 255 d [0,1] a [0,1] f {,d {,a}} Operation: (W) + (f) + (C) dest Status Affected: N,OV, C, DC, Z Encoding: 0010 Description: 00da ffff Add W, the Carry flag and data memory location `f'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed in data memory location `f'. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Cycles: 1 Operands: 0 k 255 Operation: (W) .AND. k W Status Affected: N, Z Encoding: ffff k 0000 1011 kkkk kkkk Description: The contents of W are ANDed with the 8-bit literal `k'. The result is placed in W. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k' Process Data Write to W Example: ANDLW Before Instruction W = After Instruction W = 05Fh A3h 03h Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example: ADDWFC Before Instruction Carry bit = REG = W = After Instruction Carry bit = REG = W = DS39762F-page 382 REG, 0, 1 1 02h 4Dh 0 02h 50h 2011 Microchip Technology Inc. PIC18F97J60 FAMILY ANDWF AND W with f BC Branch if Carry Syntax: ANDWF Syntax: BC Operands: 0 f 255 d [0,1] a [0,1] f {,d {,a}} Operation: (W) .AND. (f) dest Status Affected: N, Z Encoding: 0001 Description: Operands: -128 n 127 Operation: if Carry bit is `1', (PC) + 2 + 2n PC Status Affected: None Encoding: 01da ffff ffff 1110 Description: The contents of W are ANDed with register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example: ANDWF Before Instruction W = REG = After Instruction W = REG = REG, 0, 0 17h C2h 02h C2h 2011 Microchip Technology Inc. 0010 nnnn nnnn If the Carry bit is '1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. n Words: 1 Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data Write to PC No operation No operation No operation No operation If No Jump: Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data No operation Example: HERE Before Instruction PC After Instruction If Carry PC If Carry PC BC 5 = address (HERE) = = = = 1; address (HERE + 12) 0; address (HERE + 2) DS39762F-page 383 PIC18F97J60 FAMILY BCF Bit Clear f BN Branch if Negative Syntax: BCF Syntax: BN Operands: 0 f 255 0b7 a [0,1] f, b {,a} Operation: 0 f<b> Status Affected: None Encoding: 1001 Description: Operands: -128 n 127 Operation: if Negative bit is `1', (PC) + 2 + 2n PC Status Affected: None Encoding: bbba ffff ffff 1110 Description: Bit `b' in register `f' is cleared. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Cycles: 1 Q1 Q2 Q3 Q4 Read register `f' Process Data Write register `f' Example: BCF Before Instruction FLAG_REG = C7h After Instruction FLAG_REG = 47h DS39762F-page 384 FLAG_REG, 7, 0 0110 nnnn nnnn If the Negative bit is `1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words: 1 Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data Write to PC No operation No operation No operation No operation Q Cycle Activity: Decode n If No Jump: Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data No operation Example: HERE Before Instruction PC After Instruction If Negative PC If Negative PC BN Jump = address (HERE) = = = = 1; address (Jump) 0; address (HERE + 2) 2011 Microchip Technology Inc. PIC18F97J60 FAMILY BNC Branch if Not Carry BNN Branch if Not Negative Syntax: BNC Syntax: BNN n n Operands: -128 n 127 Operands: -128 n 127 Operation: if Carry bit is `0', (PC) + 2 + 2n PC Operation: if Negative bit is `0', (PC) + 2 + 2n PC Status Affected: None Status Affected: None Encoding: 1110 Description: 0011 nnnn nnnn If the Carry bit is `0', then the program will branch. Encoding: 1110 Description: The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. nnnn nnnn The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: If Jump: 0111 If the Negative bit is `0', then the program will branch. Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data Write to PC Decode Read literal `n' Process Data Write to PC No operation No operation No operation No operation No operation No operation No operation No operation Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data No operation Decode Read literal `n' Process Data No operation If No Jump: Example: If No Jump: HERE Before Instruction PC After Instruction If Carry PC If Carry PC BNC Jump = address (HERE) = = = = 0; address (Jump) 1; address (HERE + 2) 2011 Microchip Technology Inc. Example: HERE Before Instruction PC After Instruction If Negative PC If Negative PC BNN Jump = address (HERE) = = = = 0; address (Jump) 1; address (HERE + 2) DS39762F-page 385 PIC18F97J60 FAMILY BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: BNOV Syntax: BNZ n n Operands: -128 n 127 Operands: -128 n 127 Operation: if Overflow bit is `0', (PC) + 2 + 2n PC Operation: if Zero bit is `0', (PC) + 2 + 2n PC Status Affected: None Status Affected: None Encoding: 1110 Description: 0101 nnnn nnnn If the Overflow bit is `0', then the program will branch. Encoding: 1110 Description: The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. nnnn nnnn The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: If Jump: 0001 If the Zero bit is `0', then the program will branch. Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data Write to PC Decode Read literal `n' Process Data Write to PC No operation No operation No operation No operation No operation No operation No operation No operation Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data No operation Decode Read literal `n' Process Data No operation If No Jump: If No Jump: Example: HERE Before Instruction PC After Instruction If Overflow PC If Overflow PC DS39762F-page 386 BNOV Jump = address (HERE) = = = = 0; address (Jump) 1; address (HERE + 2) Example: HERE Before Instruction PC After Instruction If Zero PC If Zero PC BNZ Jump = address (HERE) = = = = 0; address (Jump) 1; address (HERE + 2) 2011 Microchip Technology Inc. PIC18F97J60 FAMILY BRA Unconditional Branch BSF Bit Set f Syntax: BRA Syntax: BSF Operands: -1024 n 1023 Operands: Operation: (PC) + 2 + 2n PC Status Affected: None 0 f 255 0b7 a [0,1] Operation: 1 f<b> Status Affected: None Encoding: n 1101 Description: 0nnn nnnn nnnn Add the 2's complement number `2n' to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction. Words: 1 Cycles: 2 Encoding: 1000 Description: Q1 Q2 Q3 Q4 Read literal `n' Process Data Write to PC No operation No operation No operation No operation Example: bbba ffff ffff Bit `b' in register `f' is set. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Q Cycle Activity: Decode f, b {,a} Words: 1 Cycles: 1 Q Cycle Activity: HERE Before Instruction PC After Instruction PC BRA Jump = address (HERE) = address (Jump) Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write register `f' Example: BSF Before Instruction FLAG_REG After Instruction FLAG_REG 2011 Microchip Technology Inc. FLAG_REG, 7, 1 = 0Ah = 8Ah DS39762F-page 387 PIC18F97J60 FAMILY BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set Syntax: BTFSC f, b {,a} Syntax: BTFSS f, b {,a} Operands: 0 f 255 0b7 a [0,1] Operands: 0 f 255 0b<7 a [0,1] Operation: skip if (f<b>) = 0 Operation: skip if (f<b>) = 1 Status Affected: None Status Affected: None Encoding: 1011 Description: bbba ffff ffff If bit `b' in register `f' is `0', then the next instruction is skipped. If bit `b' is `0', then the next instruction fetched during the current instruction execution is discarded and a NOP is executed instead, making this a two-cycle instruction. Encoding: 1010 Description: bbba ffff ffff If bit `b' in register `f' is `1', then the next instruction is skipped. If bit `b' is `1', then the next instruction fetched during the current instruction execution is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Words: 1 Cycles: 1(2) Note: Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read register `f' Process Data No operation Decode Read register `f' Process Data No operation Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation If skip: If skip: If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE FALSE TRUE Before Instruction PC After Instruction If FLAG<1> PC If FLAG<1> PC DS39762F-page 388 BTFSC : : FLAG, 1, 0 = address (HERE) = = = = 0; address (TRUE) 1; address (FALSE) Example: HERE FALSE TRUE Before Instruction PC After Instruction If FLAG<1> PC If FLAG<1> PC BTFSS : : FLAG, 1, 0 = address (HERE) = = = = 0; address (FALSE) 1; address (TRUE) 2011 Microchip Technology Inc. PIC18F97J60 FAMILY BTG Bit Toggle f BOV Branch if Overflow Syntax: BTG f, b {,a} Syntax: BOV Operands: 0 f 255 0b<7 a [0,1] Operands: -128 n 127 Operation: if Overflow bit is `1', (PC) + 2 + 2n PC Status Affected: None Operation: (f<b>) f<b> Status Affected: None Encoding: 0111 Description: Encoding: bbba ffff ffff 1110 Description: Bit `b' in data memory location `f' is inverted. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write register `f' Example: BTG PORTC, 2011 Microchip Technology Inc. Words: 1 Cycles: nnnn nnnn 1(2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data Write to PC No operation No operation No operation No operation If No Jump: Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data No operation 4, 0 Before Instruction: PORTC = 0111 0101 [75h] After Instruction: PORTC = 0110 0101 [65h] 0100 If the Overflow bit is `1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. n Example: HERE Before Instruction PC After Instruction If Overflow PC If Overflow PC BOV Jump = address (HERE) = = = = 1; address (Jump) 0; address (HERE + 2) DS39762F-page 389 PIC18F97J60 FAMILY BZ Branch if Zero CALL Subroutine Call Syntax: BZ Syntax: CALL k {,s} n Operands: -128 n 127 Operands: Operation: if Zero bit is `1', (PC) + 2 + 2n PC 0 k 1048575 s [0,1] Operation: Status Affected: None (PC) + 4 TOS, k PC<20:1>; if s = 1, (W) WS, (STATUS) STATUSS, (BSR) BSRS Status Affected: None Encoding: 1110 Description: 0000 nnnn nnnn If the Zero bit is `1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. Words: 1 Cycles: 1(2) Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) Q1 Q2 Q3 Q4 Read literal `n' Process Data Write to PC No operation No operation No operation No operation Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data No operation If No Jump: Example: HERE Before Instruction PC After Instruction If Zero PC If Zero PC DS39762F-page 390 BZ Jump = address (HERE) = = = = 1; address (Jump) 0; address (HERE + 2) k7kkk kkkk 110s k19kkk kkkk0 kkkk8 Description: Subroutine call of entire 2-Mbyte memory range. First, return address (PC+ 4) is pushed onto the return stack. If `s' = 1, the W, STATUS and BSR registers are also pushed into their respective shadow registers, WS, STATUSS and BSRS. If `s' = 0, no update occurs (default). Then, the 20-bit value `k' is loaded into PC<20:1>. CALL is a two-cycle instruction. Words: 2 Cycles: 2 Q Cycle Activity: If Jump: Decode 1110 1111 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k'<7:0>, Push PC to stack Read literal 'k'<19:8>, Write to PC No operation No operation No operation No operation Example: HERE Before Instruction PC = After Instruction PC = TOS = WS = BSRS = STATUSS = CALL THERE,1 address (HERE) address (THERE) address (HERE + 4) W BSR STATUS 2011 Microchip Technology Inc. PIC18F97J60 FAMILY CLRF Clear f Syntax: CLRF Operands: 0 f 255 a [0,1] f {,a} Operation: 000h f, 1Z Status Affected: Z Encoding: 0110 Description: 101a ffff ffff Clears the contents of the specified register. CLRWDT Clear Watchdog Timer Syntax: CLRWDT Operands: None Operation: 000h WDT, 000h WDT postscaler, 1 TO, 1 PD Status Affected: TO, PD Encoding: 0000 Words: 1 Cycles: 1 Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write register `f' Example: CLRF Before Instruction FLAG_REG After Instruction FLAG_REG FLAG_REG,1 = 5Ah = 00h 2011 Microchip Technology Inc. 0100 Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation Process Data No operation Example: Q Cycle Activity: 0000 CLRWDT instruction resets the Watchdog Timer. It also resets the postscaler of the WDT. Status bits, TO and PD, are set. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 0000 Description: CLRWDT Before Instruction WDT Counter After Instruction WDT Counter WDT Postscaler TO PD = ? = = = = 00h 0 1 1 DS39762F-page 391 PIC18F97J60 FAMILY COMF Complement f CPFSEQ Compare f with W, Skip if f = W Syntax: COMF Syntax: CPFSEQ Operands: 0 f 255 a [0,1] Operation: (f) - (W), skip if (f) = (W) (unsigned comparison) Status Affected: None f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) dest Status Affected: N, Z Encoding: 0001 Description: 11da ffff ffff The contents of register `f' are complemented. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). Encoding: Description: If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 Cycles: 1 Q Cycle Activity: Q1 Decode Q2 Read register `f' Example: COMF Before Instruction REG = After Instruction REG = W = 13h 13h ECh Q3 Process Data REG, 0, 0 ffff ffff If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Q4 Words: 1 Write to destination Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Decode Q2 Read register `f' Q3 Process Data Q4 No operation If skip: Q1 Q2 Q3 No No No operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No No No operation operation operation No No No operation operation operation Example: HERE NEQUAL EQUAL Before Instruction PC Address W REG After Instruction If REG PC If REG PC DS39762F-page 392 001a Compares the contents of data memory location `f' to the contents of W by performing an unsigned subtraction. If `f' = W, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). Words: 0110 f {,a} Q4 No operation Q4 No operation No operation CPFSEQ REG, 0 : : = = = HERE ? ? = = = W; Address (EQUAL) W; Address (NEQUAL) 2011 Microchip Technology Inc. PIC18F97J60 FAMILY CPFSGT Compare f with W, Skip if f > W CPFSLT Compare f with W, Skip if f < W Syntax: CPFSGT Syntax: CPFSLT Operands: 0 f 255 a [0,1] Operands: 0 f 255 a [0,1] Operation: (f) -W), skip if (f) > (W) (unsigned comparison) Operation: (f) -W), skip if (f) < (W) (unsigned comparison) Status Affected: None Status Affected: None Encoding: Description: 0110 f {,a} 010a ffff ffff Compares the contents of data memory location `f' to the contents of the W by performing an unsigned subtraction. Encoding: 0110 Description: If the contents of `f' are greater than the contents of WREG, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. Words: 1 Cycles: 1(2) Note: Q Cycle Activity: Q1 Decode 3 cycles if skip and followed by a 2-word instruction. Q2 Read register `f' Q3 Process Data Q4 No operation Example: HERE NGREATER GREATER Before Instruction PC W After Instruction If REG PC If REG PC Q4 No operation Q4 No operation No operation CPFSGT REG, 0 : : = = Address (HERE) ? = = W; Address (GREATER) W; Address (NGREATER) 2011 Microchip Technology Inc. ffff ffff Compares the contents of data memory location `f' to the contents of W by performing an unsigned subtraction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data No operation If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation If skip: Q1 Q2 Q3 No No No operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No No No operation operation operation No No No operation operation operation 000a If the contents of `f' are less than the contents of W, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. f {,a} Example: HERE NLESS LESS Before Instruction PC W After Instruction If REG PC If REG PC CPFSLT REG, 1 : : = = Address (HERE) ? < = = W; Address (LESS) W; Address (NLESS) DS39762F-page 393 PIC18F97J60 FAMILY DAW Decimal Adjust W Register DECF Decrement f Syntax: DAW Syntax: DECF f {,d {,a}} Operands: None Operands: Operation: If [W<3:0> > 9] or [DC = 1], then (W<3:0>) + 6 W<3:0>; else (W<3:0>) W<3:0> 0 f 255 d [0,1] a [0,1] Operation: (f) - 1 dest Status Affected: C, DC, N, OV, Z Encoding: If [W<7:4> > 9] or [C = 1], then (W<7:4>) + 6 W<7:4>, C =1; else (W<7:4>) W<7:4> Status Affected: 0000 Description: C Encoding: 0000 0000 0000 DAW adjusts the eight-bit value in W, resulting from the earlier addition of two variables (each in packed BCD format) and produces a correct packed BCD result. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register W Process Data Write W Example 1: DAW Before Instruction W = C = DC = After Instruction W = C = DC = A5h 0 0 05h 1 0 Example 2: Before Instruction W = C = DC = After Instruction W = C = DC = DS39762F-page 394 ffff ffff Decrement register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). 0111 Description: 01da If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example: DECF Before Instruction CNT = Z = After Instruction CNT = Z = CNT, 1, 0 01h 0 00h 1 CEh 0 0 34h 1 0 2011 Microchip Technology Inc. PIC18F97J60 FAMILY DECFSZ Decrement f, Skip if 0 DCFSNZ Decrement f, Skip if Not 0 Syntax: DECFSZ f {,d {,a}} Syntax: DCFSNZ Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) - 1 dest, skip if result = 0 Operation: (f) - 1 dest, skip if result 0 Status Affected: None Status Affected: None Encoding: 0010 Description: 11da ffff ffff The contents of register `f' are decremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). Encoding: 0100 Description: If the result is `0', the next instruction which is already fetched is discarded and a NOP is executed instead, making it a two-cycle instruction. Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q1 Q2 Q3 Q4 Read register `f' Process Data Write to destination Q1 Q2 Q3 Q4 No operation No operation No operation No operation Words: 1 Cycles: 1(2) Note: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation DECFSZ GOTO CNT, 1, 1 LOOP Example: HERE CONTINUE Before Instruction PC = After Instruction CNT = If CNT = PC = If CNT PC = Address (HERE) CNT - 1 0; Address (CONTINUE) 0; Address (HERE + 2) 2011 Microchip Technology Inc. 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination If skip: If skip and followed by 2-word instruction: ffff If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Q Cycle Activity: Decode ffff If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 11da The contents of register `f' are decremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If the result is not `0', the next instruction which is already fetched is discarded and a NOP is executed instead, making it a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). Words: f {,d {,a}} If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE ZERO NZERO Before Instruction TEMP After Instruction TEMP If TEMP PC If TEMP PC DCFSNZ : : TEMP, 1, 0 = ? = = = = TEMP - 1, 0; Address (ZERO) 0; Address (NZERO) DS39762F-page 395 PIC18F97J60 FAMILY GOTO Unconditional Branch INCF Increment f Syntax: GOTO k Syntax: INCF Operands: 0 k 1048575 Operands: Operation: k PC<20:1> Status Affected: None 0 f 255 d [0,1] a [0,1] Operation: (f) + 1 dest Status Affected: C, DC, N, OV, Z Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 Description: GOTO allows an unconditional branch anywhere within entire 2-Mbyte memory range. The 20-bit value `k' is loaded into PC<20:1>. GOTO is always a two-cycle instruction. Words: 2 Cycles: 2 Encoding: 0010 Description: Q1 Q2 Q3 Q4 Read literal `k'<7:0>, No operation Read literal `k'<19:8>, Write to PC No operation No operation No operation No operation Example: GOTO THERE After Instruction PC = Address (THERE) ffff ffff The contents of register `f' are incremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example: INCF Before Instruction CNT = Z = C = DC = After Instruction CNT = Z = C = DC = DS39762F-page 396 10da If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). Q Cycle Activity: Decode f {,d {,a}} CNT, 1, 0 FFh 0 ? ? 00h 1 1 1 2011 Microchip Technology Inc. PIC18F97J60 FAMILY INCFSZ Increment f, Skip if 0 INFSNZ Syntax: INCFSZ Syntax: INFSNZ 0 f 255 d [0,1] a [0,1] f {,d {,a}} Increment f, Skip if Not 0 f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operands: Operation: (f) + 1 dest, skip if result = 0 Operation: (f) + 1 dest, skip if result 0 Status Affected: None Status Affected: None Encoding: 0011 Description: 11da ffff ffff The contents of register `f' are incremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f'. (default) Encoding: 0100 Description: 10da ffff ffff The contents of register `f' are incremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If the result is `0', the next instruction which is already fetched is discarded and a NOP is executed instead, making it a two-cycle instruction. If the result is not `0', the next instruction which is already fetched is discarded and a NOP is executed instead, making it a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Words: 1 Cycles: 1(2) Note: Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Decode Read register `f' Process Data Write to destination Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation If skip: If skip: If skip and followed by 2-word instruction: If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE NZERO ZERO Before Instruction PC = After Instruction CNT = If CNT = PC = If CNT PC = INCFSZ : : Address (HERE) CNT + 1 0; Address (ZERO) 0; Address (NZERO) 2011 Microchip Technology Inc. CNT, 1, 0 Example: HERE ZERO NZERO Before Instruction PC = After Instruction REG = If REG PC = If REG = PC = INFSNZ REG, 1, 0 Address (HERE) REG + 1 0; Address (NZERO) 0; Address (ZERO) DS39762F-page 397 PIC18F97J60 FAMILY IORLW Inclusive OR Literal with W IORWF Inclusive OR W with f Syntax: IORLW k Syntax: IORWF Operands: 0 k 255 Operands: Operation: (W) .OR. k W Status Affected: N, Z 0 f 255 d [0,1] a [0,1] Operation: (W) .OR. (f) dest Status Affected: N, Z Encoding: 0000 1001 kkkk kkkk Description: The contents of W are ORed with the eight-bit literal `k'. The result is placed in W. Words: 1 Cycles: 1 Encoding: 0001 Description: Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k' Process Data Write to W Example: IORLW Before Instruction W = After Instruction W = 00da ffff ffff Inclusive OR W with register `f'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 35h 9Ah BFh f {,d {,a}} Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example: IORWF Before Instruction RESULT = W = After Instruction RESULT = W = DS39762F-page 398 RESULT, 0, 1 13h 91h 13h 93h 2011 Microchip Technology Inc. PIC18F97J60 FAMILY LFSR Load FSR MOVF Move f Syntax: LFSR f, k Syntax: MOVF Operands: 0f2 0 k 4095 Operands: Operation: k FSRf 0 f 255 d [0,1] a [0,1] Status Affected: None Operation: f dest Status Affected: N, Z Encoding: 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk Description: The 12-bit literal `k' is loaded into the File Select Register pointed to by `f'. Words: 2 Cycles: 2 Encoding: 0101 Description: Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k' MSB Process Data Write literal `k' MSB to FSRfH Decode Read literal `k' LSB Process Data Write literal `k' to FSRfL Example: After Instruction FSR2H FSR2L 03h ABh 00da ffff ffff The contents of register `f' are moved to a destination dependent upon the status of `d'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). Location `f' can be anywhere in the 256-byte bank. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. LFSR 2, 3ABh = = f {,d {,a}} Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write W Example: MOVF Before Instruction REG W After Instruction REG W 2011 Microchip Technology Inc. REG, 0, 0 = = 22h FFh = = 22h 22h DS39762F-page 399 PIC18F97J60 FAMILY MOVFF Move f to f MOVLB Move Literal to Low Nibble in BSR Syntax: MOVFF fs,fd Syntax: MOVLW k Operands: 0 fs 4095 0 fd 4095 Operands: 0 k 255 Operation: k BSR Status Affected: None Operation: (fs) fd Status Affected: None Encoding: 1st word (source) 2nd word (destin.) Encoding: 1100 1111 Description: ffff ffff ffff ffff ffffs ffffd The contents of source register `fs' are moved to destination register `fd'. Location of source `fs' can be anywhere in the 4096-byte data space (000h to FFFh) and location of destination `fd' can also be anywhere from 000h to FFFh. Either source or destination can be W (a useful special situation). MOVFF is particularly useful for transferring a data memory location to a peripheral register (such as the transmit buffer or an I/O port). The MOVFF instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register Words: 2 Cycles: 2 0000 0001 kkkk kkkk Description: The eight-bit literal `k' is loaded into the Bank Select Register (BSR). The value of BSR<7:4> always remains `0' regardless of the value of k7:k4. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k' Process Data Write literal `k' to BSR MOVLB 5 Example: Before Instruction BSR Register = After Instruction BSR Register = 02h 05h Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' (src) Process Data No operation Decode No operation No operation Write register `f' (dest) No dummy read Example: MOVFF Before Instruction REG1 REG2 After Instruction REG1 REG2 DS39762F-page 400 REG1, REG2 = = 33h 11h = = 33h 33h 2011 Microchip Technology Inc. PIC18F97J60 FAMILY MOVLW Move Literal to W MOVWF Move W to f Syntax: MOVLW k Syntax: MOVWF Operands: 0 k 255 Operands: Operation: kW 0 f 255 a [0,1] Status Affected: None Encoding: 0000 Description: 1110 kkkk kkkk The eight-bit literal `k' is loaded into W. Words: 1 Cycles: 1 Operation: (W) f Status Affected: None Encoding: 0110 Description: Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k' Process Data Write to W Example: After Instruction W = MOVLW f {,a} 111a ffff ffff Move data from W to register `f'. Location `f' can be anywhere in the 256-byte bank. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 5Ah 5Ah Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write register `f' Example: MOVWF Before Instruction W = REG = After Instruction W = REG = 2011 Microchip Technology Inc. REG, 0 4Fh FFh 4Fh 4Fh DS39762F-page 401 PIC18F97J60 FAMILY MULLW Multiply Literal with W MULWF Syntax: MULLW Syntax: MULWF Operands: 0 k 255 Operands: Operation: (W) x k PRODH:PRODL 0 f 255 a [0,1] Status Affected: None Operation: (W) x (f) PRODH:PRODL Status Affected: None Encoding: 0000 Description: k 1101 kkkk kkkk An unsigned multiplication is carried out between the contents of W and the 8-bit literal `k'. The 16-bit result is placed in PRODH:PRODL register pair. PRODH contains the high byte. Multiply W with f Encoding: 0000 Description: W is unchanged. None of the Status flags are affected. 1 Cycles: 1 Q1 Q2 Q3 Q4 Read literal `k' Process Data Write registers PRODH: PRODL MULLW 0C4h = = = E2h ? ? = = = E2h ADh 08h If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write registers PRODH: PRODL Example: Before Instruction W REG PRODH PRODL After Instruction W REG PRODH PRODL DS39762F-page 402 ffff If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). Decode Before Instruction W PRODH PRODL After Instruction W PRODH PRODL ffff Note that neither Overflow nor Carry is possible in this operation. A Zero result is possible but not detected. Q Cycle Activity: Example: 001a An unsigned multiplication is carried out between the contents of W and the register file location `f'. The 16-bit result is stored in the PRODH:PRODL register pair. PRODH contains the high byte. Both W and `f' are unchanged. None of the Status flags are affected. Note that neither Overflow nor Carry is possible in this operation. A Zero result is possible but not detected. Words: f {,a} MULWF REG, 1 = = = = C4h B5h ? ? = = = = C4h B5h 8Ah 94h 2011 Microchip Technology Inc. PIC18F97J60 FAMILY NEGF Negate f Syntax: NEGF Operands: 0 f 255 a [0,1] f {,a} Operation: (f) + 1 f Status Affected: N, OV, C, DC, Z Encoding: 0110 Description: 110a ffff If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 Syntax: NOP Operands: None Operation: No operation Status Affected: None 0000 1111 ffff If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). Cycles: No Operation Encoding: Location `f' is negated using two's complement. The result is placed in the data memory location `f'. Words: NOP 0000 xxxx Description: No operation. Words: 1 Cycles: 1 0000 xxxx 0000 xxxx Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation No operation No operation Example: None. Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write register `f' Example: NEGF Before Instruction REG = After Instruction REG = REG, 1 0011 1010 [3Ah] 1100 0110 [C6h] 2011 Microchip Technology Inc. DS39762F-page 403 PIC18F97J60 FAMILY POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: POP Syntax: PUSH Operands: None Operands: None Operation: (TOS) bit bucket Operation: (PC + 2) TOS Status Affected: None Status Affected: None Encoding: 0000 0000 0000 0110 Encoding: 0000 0000 0000 0101 Description: The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack. This instruction is provided to enable the user to properly manage the return stack to incorporate a software stack. Description: The PC + 2 is pushed onto the top of the return stack. The previous TOS value is pushed down on the stack. This instruction allows implementing a software stack by modifying TOS and then pushing it onto the return stack. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation POP TOS value No operation POP GOTO NEW Example: Q2 Q3 Q4 PUSH PC + 2 onto return stack No operation No operation Example: Before Instruction TOS Stack (1 level down) = = 0031A2h 014332h After Instruction TOS PC = = 014332h NEW DS39762F-page 404 Q1 Decode PUSH Before Instruction TOS PC = = 345Ah 0124h After Instruction PC TOS Stack (1 level down) = = = 0126h 0126h 345Ah 2011 Microchip Technology Inc. PIC18F97J60 FAMILY RCALL Relative Call RESET Reset Syntax: RCALL Syntax: RESET n Operands: -1024 n 1023 Operands: None Operation: (PC) + 2 TOS, (PC) + 2 + 2n PC Operation: Reset all registers and flags that are affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: 1101 Description: 1nnn nnnn nnnn Subroutine call with a jump up to 1K from the current location. First, return address (PC + 2) is pushed onto the stack. Then, add the 2's complement number `2n' to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction. Words: 1 Cycles: 2 Encoding: 0000 Q1 Q2 Q3 Q4 Decode Read literal `n' Process Data Write to PC No operation No operation 1111 1111 This instruction provides a way to execute a MCLR Reset in software. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Start reset No operation No operation Example: Q Cycle Activity: 0000 Description: After Instruction Registers = Flags* = RESET Reset Value Reset Value PUSH PC to stack No operation Example: No operation HERE RCALL Jump Before Instruction PC = Address (HERE) After Instruction PC = Address (Jump) TOS = Address (HERE + 2) 2011 Microchip Technology Inc. DS39762F-page 405 PIC18F97J60 FAMILY RETFIE Return from Interrupt RETLW Return Literal to W Syntax: RETFIE {s} Syntax: RETLW k Operands: s [0,1] Operands: 0 k 255 Operation: (TOS) PC, 1 GIE/GIEH or PEIE/GIEL; if s = 1, (WS) W, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged Operation: k W, (TOS) PC, PCLATU, PCLATH are unchanged Status Affected: None Status Affected: 0000 0000 0001 1 Cycles: 2 Q Cycle Activity: Q2 Q3 Q4 Decode No operation No operation POP PC from stack Set GIEH or GIEL No operation RETFIE After Interrupt PC W BSR STATUS GIE/GIEH, PEIE/GIEL DS39762F-page 406 kkkk kkkk W is loaded with the eight-bit literal `k'. The program counter is loaded from the top of the stack (the return address). The high address latch (PCLATH) remains unchanged. Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k' Process Data POP PC from stack, write to W No operation No operation No operation No operation Example: Q1 Example: 1100 Description: 000s Return from interrupt. Stack is popped and Top-of-Stack (TOS) is loaded into the PC. Interrupts are enabled by setting either the high or low-priority Global Interrupt Enable bit. If `s' = 1, the contents of the shadow registers WS, STATUSS and BSRS are loaded into their corresponding registers W, STATUS and BSR. If `s' = 0, no update of these registers occurs (default). Words: No operation 0000 GIE/GIEH, PEIE/GIEL. Encoding: Description: Encoding: No operation No operation 1 = = = = = TOS WS BSRS STATUSS 1 CALL TABLE ; ; ; ; : TABLE ADDWF PCL ; RETLW k0 ; RETLW k1 ; : : RETLW kn ; Before Instruction W = After Instruction W = W contains table offset value W now has table value W = offset Begin table End of table 07h value of kn 2011 Microchip Technology Inc. PIC18F97J60 FAMILY RETURN Return from Subroutine RLCF Rotate Left f through Carry Syntax: RETURN {s} Syntax: RLCF Operands: s [0,1] Operands: Operation: (TOS) PC; if s = 1, (WS) W, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged 0 f 255 d [0,1] a [0,1] Operation: (f<n>) dest<n + 1>, (f<7>) C, (C) dest<0> Status Affected: C, N, Z Status Affected: None Encoding: 0000 Description: Encoding: 0000 0001 001s 0011 Description: Return from subroutine. The stack is popped and the top of the stack (TOS) is loaded into the program counter. If `s'= 1, the contents of the shadow registers WS, STATUSS and BSRS are loaded into their corresponding registers W, STATUS and BSR. If `s' = 0, no update of these registers occurs (default). Words: 1 Cycles: 2 Q1 Q2 Q3 Q4 No operation Process Data POP PC from stack No operation No operation No operation No operation 01da ffff ffff The contents of register `f' are rotated one bit to the left through the Carry flag. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Q Cycle Activity: Decode f {,d {,a}} register f C Words: 1 Cycles: 1 Q Cycle Activity: Example: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination RETURN After Instruction: PC = TOS Example: Before Instruction REG = C = After Instruction REG = W = C = 2011 Microchip Technology Inc. RLCF REG, 0, 0 1110 0110 0 1110 0110 1100 1100 1 DS39762F-page 407 PIC18F97J60 FAMILY RLNCF Rotate Left f (no carry) RRCF Rotate Right f through Carry Syntax: RLNCF Syntax: RRCF Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f<n>) dest<n + 1>, (f<7>) dest<0> Operation: Status Affected: N, Z (f<n>) dest<n - 1>, (f<0>) C, (C) dest<7> Status Affected: C, N, Z Encoding: 0100 Description: f {,d {,a}} 01da ffff ffff The contents of register `f' are rotated one bit to the left. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register `f' (default). Encoding: 0011 Description: If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). 1 1 Q1 Decode Q2 Read register `f' Example: Before Instruction REG = After Instruction REG = DS39762F-page 408 RLNCF Q3 Process Data Q4 Write to destination Words: 1 Cycles: register f 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination REG, 1, 0 1010 1011 0101 0111 ffff The contents of register `f' are rotated one bit to the right through the Carry flag. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). C Q Cycle Activity: ffff If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. register f Cycles: 00da If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: f {,d {,a}} Example: RRCF Before Instruction REG = C = After Instruction REG = W = C = REG, 0, 0 1110 0110 0 1110 0110 0111 0011 0 2011 Microchip Technology Inc. PIC18F97J60 FAMILY RRNCF Rotate Right f (no carry) SETF Set f Syntax: RRNCF Syntax: SETF Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 a [0,1] Operation: (f<n>) dest<n - 1>, (f<0>) dest<7> Status Affected: N, Z Encoding: 0100 Description: f {,d {,a}} 00da Operation: FFh f Status Affected: None Encoding: ffff ffff 0110 Description: The contents of register `f' are rotated one bit to the right. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). register f Words: 1 Cycles: 1 Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example 1: RRNCF Before Instruction REG = After Instruction REG = Example 2: ffff Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write register `f' SETF Before Instruction REG After Instruction REG REG,1 = 5Ah = FFh REG, 1, 0 1101 0111 1110 1011 RRNCF Before Instruction W = REG = After Instruction W = REG = ffff If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Example: Q Cycle Activity: 100a The contents of the specified register are set to FFh. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. f {,a} REG, 0, 0 ? 1101 0111 1110 1011 1101 0111 2011 Microchip Technology Inc. DS39762F-page 409 PIC18F97J60 FAMILY SLEEP Enter Sleep Mode SUBFWB Subtract f from W with Borrow Syntax: SLEEP Syntax: SUBFWB Operands: None Operands: Operation: 00h WDT, 0 WDT postscaler, 1 TO, 0 PD 0 f 255 d [0,1] a [0,1] Operation: (W) - (f) - (C) dest Status Affected: N, OV, C, DC, Z Status Affected: TO, PD Encoding: 0000 Description: Encoding: 0000 0000 0011 0101 Description: The Power-Down status bit (PD) is cleared. The Time-out status bit (TO) is set. The Watchdog Timer and its postscaler are cleared. The processor is put into Sleep mode with the oscillator stopped. Words: 1 Cycles: 1 Q1 Q2 Q3 Q4 No operation Process Data Go to Sleep Example: SLEEP Before Instruction TO = ? ? PD = After Instruction 1 TO = PD = 0 If WDT causes wake-up, this bit is cleared. DS39762F-page 410 01da ffff ffff Subtract register `f' and Carry flag (borrow) from W (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Q Cycle Activity: Decode f {,d {,a}} Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination SUBFWB REG, 1, 0 Example 1: Before Instruction REG = 3 W = 2 C = 1 After Instruction REG = FF W = 2 C = 0 Z = 0 N = 1 ; result is negative SUBFWB REG, 0, 0 Example 2: Before Instruction REG = 2 W = 5 C = 1 After Instruction REG = 2 W = 3 C = 1 Z = 0 N = 0 ; result is positive SUBFWB REG, 1, 0 Example 3: Before Instruction REG = 1 W = 2 C = 0 After Instruction REG = 0 W = 2 C = 1 Z = 1 ; result is zero N = 0 2011 Microchip Technology Inc. PIC18F97J60 FAMILY SUBLW Subtract W from Literal SUBWF Subtract W from f Syntax: SUBLW k Syntax: SUBWF Operands: 0 k 255 Operands: Operation: k - (W) W Status Affected: N, OV, C, DC, Z 0 f 255 d [0,1] a [0,1] Operation: (f) - (W) dest Status Affected: N, OV, C, DC, Z Encoding: 0000 1000 kkkk kkkk Description: W is subtracted from the eight-bit literal `k'. The result is placed in W. Words: 1 Cycles: 1 Encoding: 0101 Description: Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k' Process Data Write to W Example 1: Before Instruction W = C = After Instruction W = C = Z = N = Example 2: Before Instruction W = C = After Instruction W = C = Z = N = Example 3: Before Instruction W = C = After Instruction W = C = Z = N = SUBLW SUBLW ; result is positive 02h ? 00h 1 1 0 SUBLW ; result is zero 02h 03h ? FFh 0 0 1 ; (2's complement) ; result is negative ffff Subtract W from register `f' (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination SUBWF REG, 1, 0 Example 1: Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = Example 2: Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = Example 3: Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = 2011 Microchip Technology Inc. ffff If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 02h 02h 11da If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). 01h ? 01h 1 0 0 f {,d {,a}} 3 2 ? 1 2 1 0 0 ; result is positive SUBWF REG, 0, 0 2 2 ? 2 0 1 1 0 SUBWF ; result is zero REG, 1, 0 1 2 ? FFh ;(2's complement) 2 0 ; result is negative 0 1 DS39762F-page 411 PIC18F97J60 FAMILY SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: SUBWFB Syntax: SWAPF f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) - (W) - (C) dest Operation: Status Affected: N, OV, C, DC, Z (f<3:0>) dest<7:4>, (f<7:4>) dest<3:0> Status Affected: None Encoding: 0101 Description: f {,d {,a}} 10da ffff ffff Subtract W and the Carry flag (borrow) from register `f' (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). Encoding: 0011 Description: If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). 1 Cycles: 1 Q Cycle Activity: Q1 Decode Q2 Read register `f' Example 1: SUBWFB Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = Example 2: Q4 Write to destination If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination REG, 1, 0 19h 0Dh 1 (0001 1001) (0000 1101) 0Ch 0Dh 1 0 0 (0000 1011) (0000 1101) ffff Example: SWAPF Before Instruction REG = After Instruction REG = REG, 1, 0 53h 35h ; result is positive SUBWFB REG, 0, 0 Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = Example 3: 1Bh 1Ah 0 (0001 1011) (0001 1010) 1Bh 00h 1 1 0 (0001 1011) SUBWFB Before Instruction REG = W = C = After Instruction REG = W C Z N Q3 Process Data ffff If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: 10da The upper and lower nibbles of register `f' are exchanged. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed in register `f' (default). = = = = DS39762F-page 412 ; result is zero REG, 1, 0 03h 0Eh 1 (0000 0011) (0000 1101) F5h (1111 0100) ; [2's comp] (0000 1101) 0Eh 0 0 1 ; result is negative 2011 Microchip Technology Inc. PIC18F97J60 FAMILY TBLRD Table Read TBLRD Table Read (Continued) Syntax: TBLRD ( *; *+; *-; +*) Example 1: TBLRD Operands: None Operation: if TBLRD*, (Prog Mem (TBLPTR)) TABLAT; TBLPTR - No Change if TBLRD*+, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) + 1 TBLPTR if TBLRD*-, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) - 1 TBLPTR if TBLRD +*, (TBLPTR) + 1 TBLPTR; (Prog Mem (TBLPTR)) TABLAT Before Instruction TABLAT TBLPTR MEMORY(00A356h) After Instruction TABLAT TBLPTR Example 2: Status Affected: None Encoding: Description: 0000 0000 0000 TBLRD Before Instruction TABLAT TBLPTR MEMORY(01A357h) MEMORY(01A358h) After Instruction TABLAT TBLPTR *+ ; = = = 55h 00A356h 34h = = 34h 00A357h +* ; = = = = AAh 01A357h 12h 34h = = 34h 01A358h 10nn nn=0 * =1 *+ =2 *=3 +* This instruction is used to read the contents of Program Memory (P.M.). To address the program memory, a pointer called Table Pointer (TBLPTR) is used. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows: * no change * post-increment * post-decrement * pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation No operation No operation No operation No operation (Read Program Memory) No operation No operation (Write TABLAT) 2011 Microchip Technology Inc. DS39762F-page 413 PIC18F97J60 FAMILY TBLWT Table Write TBLWT Table Write (Continued) Syntax: TBLWT ( *; *+; *-; +*) Example 1: TBLWT*+; Operands: None Operation: if TBLWT*, (TABLAT) Holding Register; TBLPTR - No Change if TBLWT*+, (TABLAT) Holding Register; (TBLPTR) + 1 TBLPTR if TBLWT*-, (TABLAT) Holding Register; (TBLPTR) - 1 TBLPTR if TBLWT+*, (TBLPTR) + 1 TBLPTR; (TABLAT) Holding Register Status Affected: Example 2: None Encoding: Description: Before Instruction TABLAT = 55h TBLPTR = 00A356h HOLDING REGISTER (00A356h) = FFh After Instructions (table write completion) TABLAT = 55h TBLPTR = 00A357h HOLDING REGISTER (00A356h) = 55h 0000 0000 0000 11nn nn=0 * =1 *+ =2 *=3 +* This instruction uses the 3 LSBs of TBLPTR to determine which of the 8 holding registers the TABLAT is written to. The holding registers are used to program the contents of Program Memory (P.M.). (Refer to Section 6.0 "Memory Organization" for additional details on programming Flash memory.) TBLWT +*; Before Instruction TABLAT = 34h TBLPTR = 01389Ah HOLDING REGISTER (01389Ah) = FFh HOLDING REGISTER (01389Bh) = FFh After Instruction (table write completion) TABLAT = 34h TBLPTR = 01389Bh HOLDING REGISTER (01389Ah) = FFh HOLDING REGISTER (01389Bh) = 34h The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. The LSb of the TBLPTR selects which byte of the program memory location to access. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows: * * * * no change post-increment post-decrement pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Decode Q2 Q3 Q4 No No No operation operation operation No No No No operation operation operation operation (Read (Write to TABLAT) Holding Register) DS39762F-page 414 2011 Microchip Technology Inc. PIC18F97J60 FAMILY TSTFSZ Test f, Skip if 0 XORLW Exclusive OR Literal with W Syntax: TSTFSZ f {,a} Syntax: XORLW k Operands: 0 f 255 a [0,1] Operands: 0 k 255 Operation: (W) .XOR. k W Status Affected: N, Z Operation: skip if f = 0 Status Affected: None Encoding: Encoding: 0110 Description: 011a ffff ffff If `f' = 0, the next instruction fetched during the current instruction execution is discarded and a NOP is executed, making this a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. 0000 1010 kkkk kkkk Description: The contents of W are XORed with the 8-bit literal `k'. The result is placed in W. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k' Process Data Write to W Example: Before Instruction W = After Instruction W = XORLW 0AFh B5h 1Ah Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data No operation If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE NZERO ZERO Before Instruction PC After Instruction If CNT PC If CNT PC TSTFSZ : : CNT, 1 = Address (HERE) = = = 00h, Address (ZERO) 00h, Address (NZERO) 2011 Microchip Technology Inc. DS39762F-page 415 PIC18F97J60 FAMILY XORWF Exclusive OR W with f Syntax: XORWF Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) .XOR. (f) dest Status Affected: N, Z Encoding: 0001 Description: f {,d {,a}} 10da ffff ffff Exclusive OR the contents of W with register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in the register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank (default). If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 26.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example: XORWF Before Instruction REG = W = After Instruction REG = W = DS39762F-page 416 REG, 1, 0 AFh B5h 1Ah B5h 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 26.2 A summary of the instructions in the extended instruction set is provided in Table 26-3. Detailed descriptions are provided in Section 26.2.2 "Extended Instruction Set". The opcode field descriptions in Table 26-1 (page 376) apply to both the standard and extended PIC18 instruction sets. Extended Instruction Set In addition to the standard 75 instructions of the PIC18 instruction set, the PIC18F97J60 family of devices also provide an optional extension to the core CPU functionality. The added features include eight additional instructions that augment Indirect and Indexed Addressing operations and the implementation of Indexed Literal Offset Addressing for many of the standard PIC18 instructions. Note: The additional features of the extended instruction set are enabled by default on unprogrammed devices. Users must properly set or clear the XINST Configuration bit during programming to enable or disable these features. The instructions in the extended set can all be classified as literal operations, which either manipulate the File Select Registers, or use them for Indexed Addressing. Two of the instructions, ADDFSR and SUBFSR, each have an additional special instantiation for using FSR2. These versions (ADDULNK and SUBULNK) allow for automatic return after execution. 26.2.1 EXTENDED INSTRUCTION SYNTAX Most of the extended instructions use indexed arguments, using one of the File Select Registers and some offset to specify a source or destination register. When an argument for an instruction serves as part of Indexed Addressing, it is enclosed in square brackets ("[ ]"). This is done to indicate that the argument is used as an index or offset. The MPASMTM Assembler will flag an error if it determines that an index or offset value is not bracketed. The extended instructions are specifically implemented to optimize reentrant program code (that is, code that is recursive or that uses a software stack) written in high-level languages, particularly C. Among other things, they allow users working in high-level languages to perform certain operations on data structures more efficiently. These include: When the extended instruction set is enabled, brackets are also used to indicate index arguments in byte-oriented and bit-oriented instructions. This is in addition to other changes in their syntax. For more details, see Section 26.2.3.1 "Extended Instruction Syntax with Standard PIC18 Commands". * Dynamic allocation and deallocation of software stack space when entering and leaving subroutines * Function Pointer invocation * Software Stack Pointer manipulation * Manipulation of variables located in a software stack TABLE 26-3: The instruction set extension and the Indexed Literal Offset Addressing mode were designed for optimizing applications written in C; the user may likely never use these instructions directly in assembler. The syntax for these commands is provided as a reference for users who may be reviewing code that has been generated by a compiler. Note: In the past, square brackets have been used to denote optional arguments in the PIC18 and earlier instruction sets. In this text and going forward, optional arguments are denoted by braces ("{ }"). EXTENSIONS TO THE PIC18 INSTRUCTION SET 16-Bit Instruction Word Mnemonic, Operands ADDFSR ADDULNK CALLW MOVSF f, k k MOVSS zs, zd PUSHL k SUBFSR SUBULNK f, k k zs, fd Description Cycles MSb Add Literal to FSR Add Literal to FSR2 and Return Call Subroutine using WREG Move zs (source) to 1st word fd (destination) 2nd word Move zs (source) to 1st word zd (destination) 2nd word Store Literal at FSR2, Decrement FSR2 Subtract Literal from FSR Subtract Literal from FSR2 and Return 2011 Microchip Technology Inc. 1 2 2 2 LSb Status Affected 1000 1000 0000 1011 ffff 1011 xxxx 1010 ffkk 11kk 0001 0zzz ffff 1zzz xzzz kkkk kkkk kkkk 0100 zzzz ffff zzzz zzzz kkkk None None None None 1 1110 1110 0000 1110 1111 1110 1111 1110 1 2 1110 1110 1001 1001 ffkk 11kk kkkk kkkk None None 2 None None DS39762F-page 417 PIC18F97J60 FAMILY 26.2.2 EXTENDED INSTRUCTION SET ADDFSR Add Literal to FSR ADDULNK Syntax: ADDFSR f, k Syntax: ADDULNK k Operands: 0 k 63 f [ 0, 1, 2 ] Operands: 0 k 63 Operation: FSR(f) + k FSR(f) Status Affected: None Encoding: 1110 Add Literal to FSR2 and Return FSR2 + k FSR2, Operation: (TOS) PC Status Affected: 1000 ffkk kkkk Description: The 6-bit literal `k' is added to the contents of the FSR specified by `f'. Words: 1 Cycles: 1 None Encoding: 1110 Description: Q2 Q3 Q4 Decode Read literal `k' Process Data Write to FSR Example: After Instruction FSR2 = 03FFh Words: 1 Cycles: 2 Q Cycle Activity: 0422h Q1 Q2 Q3 Q4 Decode Read literal `k' Process Data Write to FSR No Operation No Operation No Operation No Operation Example: Note: kkkk This may be thought of as a special case of the ADDFSR instruction, where f = 3 (binary `11'); it operates only on FSR2. ADDFSR 2, 23h Before Instruction FSR2 = 11kk The instruction takes two cycles to execute; a NOP is performed during the second cycle. Q Cycle Activity: Q1 1000 The 6-bit literal `k' is added to the contents of FSR2. A RETURN is then executed by loading the PC with the TOS. ADDULNK 23h Before Instruction FSR2 = PC = 03FFh 0100h After Instruction FSR2 = PC = 0422h (TOS) All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s). DS39762F-page 418 2011 Microchip Technology Inc. PIC18F97J60 FAMILY CALLW Subroutine Call using WREG MOVSF Move Indexed to f Syntax: CALLW Syntax: MOVSF [zs], fd Operands: None Operands: Operation: (PC + 2) TOS, (W) PCL, (PCLATH) PCH, (PCLATU) PCU 0 zs 127 0 fd 4095 Operation: ((FSR2) + zs) fd Status Affected: None Status Affected: None Encoding: 0000 Description 0000 0001 0100 First, the return address (PC + 2) is pushed onto the return stack. Next, the contents of W are written to PCL; the existing value is discarded. Then, the contents of PCLATH and PCLATU are latched into PCH and PCU, respectively. The second cycle is executed as a NOP instruction while the new next instruction is fetched. Encoding: 1st word (source) 2nd word (destin.) Description: Unlike CALL, there is no option to update W, STATUS or BSR. Words: 1 Cycles: 2 Q1 Q2 Q3 Q4 Read WREG Push PC to stack No operation No operation No operation No operation No operation Before Instruction PC = PCLATH = PCLATU = W = After Instruction PC = TOS = PCLATH = PCLATU = W = Words: 2 Cycles: 2 Q Cycle Activity: CALLW Decode address (HERE) 10h 00h 06h 001006h address (HERE + 2) 10h 00h 06h 2011 Microchip Technology Inc. zzzzs ffffd If the resultant source address points to an indirect addressing register, the value returned will be 00h. Decode HERE 0zzz ffff The contents of the source register are moved to destination register `fd'. The actual address of the source register is determined by adding the 7-bit literal offset `zs', in the first word, to the value of FSR2. The address of the destination register is specified by the 12-bit literal `fd' in the second word. Both addresses can be anywhere in the 4096-byte data space (000h to FFFh). Q1 Example: 1011 ffff The MOVSF instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. Q Cycle Activity: Decode 1110 1111 Q2 Q3 Determine Determine source addr source addr No operation No operation No dummy read Example: MOVSF Before Instruction FSR2 Contents of 85h REG2 After Instruction FSR2 Contents of 85h REG2 Q4 Read source reg Write register `f' (dest) [05h], REG2 = 80h = = 33h 11h = 80h = = 33h 33h DS39762F-page 419 PIC18F97J60 FAMILY MOVSS Move Indexed to Indexed PUSHL Store Literal at FSR2, Decrement FSR2 Syntax: MOVSS [zs], [zd] Syntax: PUSHL k Operands: 0 zs 127 0 zd 127 Operands: 0k 255 Operation: k (FSR2), FSR2 - 1 FSR2 Status Affected: None Operation: ((FSR2) + zs) ((FSR2) + zd) Status Affected: None Encoding: 1st word (source) 2nd word (dest.) 1110 1111 Description 1011 xxxx 1zzz xzzz zzzzs zzzzd The contents of the source register are moved to the destination register. The addresses of the source and destination registers are determined by adding the 7-bit literal offsets `zs' or `zd', respectively, to the value of FSR2. Both registers can be located anywhere in the 4096-byte data memory space (000h to FFFh). The MOVSS instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. If the resultant source address points to an indirect addressing register, the value returned will be 00h. If the resultant destination address points to an indirect addressing register, the instruction will execute as a NOP. Words: 2 Cycles: 2 Q Cycle Activity: Q1 Decode Decode Q2 Q3 Determine Determine source addr source addr Determine dest addr Example: 1110 Description: 1010 kkkk kkkk The 8-bit literal `k' is written to the data memory address specified by FSR2. FSR2 is decremented by 1 after the operation. This instruction allows users to push values onto a software stack. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read `k' Process data Write to destination Example: PUSHL 08h Before Instruction FSR2H:FSR2L Memory (01ECh) = = 01ECh 00h After Instruction FSR2H:FSR2L Memory (01ECh) = = 01EBh 08h Q4 Read source reg Write to dest reg MOVSS [05h], [06h] Before Instruction FSR2 Contents of 85h Contents of 86h After Instruction FSR2 Contents of 85h Contents of 86h DS39762F-page 420 Determine dest addr Encoding: = 80h = 33h = 11h = 80h = 33h = 33h 2011 Microchip Technology Inc. PIC18F97J60 FAMILY SUBFSR Subtract Literal from FSR SUBULNK Syntax: SUBFSR f, k Syntax: SUBULNK k Operands: 0 k 63 Operands: 0 k 63 f [ 0, 1, 2 ] Operation: Operation: FSRf - k FSRf FSR2 - k FSR2, (TOS) PC Status Affected: None Status Affected: None Encoding: 1110 1001 ffkk kkkk Description: The 6-bit literal `k' is subtracted from the contents of the FSR specified by `f'. Words: 1 Cycles: 1 Encoding: 1110 Description: Q1 Q2 Q3 Q4 Read register `f' Process Data Write to destination Example: Before Instruction FSR2 = After Instruction FSR2 = SUBFSR 2, 23h 1001 11kk kkkk The 6-bit literal `k' is subtracted from the contents of the FSR2. A RETURN is then executed by loading the PC with the TOS. The instruction takes two cycles to execute; a NOP is performed during the second cycle. Q Cycle Activity: Decode Subtract Literal from FSR2 and Return This may be thought of as a special case of the SUBFSR instruction, where f = 3 (binary `11'); it operates only on FSR2. Words: 1 Cycles: 2 Q Cycle Activity: 03FFh 03DCh Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination No Operation No Operation No Operation No Operation Example: 2011 Microchip Technology Inc. SUBULNK 23h Before Instruction FSR2 = PC = 03FFh 0100h After Instruction FSR2 = PC = 03DCh (TOS) DS39762F-page 421 PIC18F97J60 FAMILY 26.2.3 Note: BYTE-ORIENTED AND BIT-ORIENTED INSTRUCTIONS IN INDEXED LITERAL OFFSET MODE Enabling the PIC18 instruction set extension may cause legacy applications to behave erratically or fail entirely. In addition to eight new commands in the extended set, enabling the extended instruction set also enables Indexed Literal Offset Addressing (Section 6.6.1 "Indexed Addressing with Literal Offset"). This has a significant impact on the way that many commands of the standard PIC18 instruction set are interpreted. When the extended set is disabled, addresses embedded in opcodes are treated as literal memory locations: either as a location in the Access Bank (a = 0) or in a GPR bank designated by the BSR (a = 1). When the extended instruction set is enabled and a = 0, however, a file register argument of 5Fh or less is interpreted as an offset from the pointer value in FSR2 and not as a literal address. For practical purposes, this means that all instructions that use the Access RAM bit as an argument - that is, all byte-oriented and bit-oriented instructions, or almost half of the core PIC18 instructions - may behave differently when the extended instruction set is enabled. When the content of FSR2 is 00h, the boundaries of the Access RAM are essentially remapped to their original values. This may be useful in creating backward-compatible code. If this technique is used, it may be necessary to save the value of FSR2 and restore it when moving back and forth between C and assembly routines in order to preserve the Stack Pointer. Users must also keep in mind the syntax requirements of the extended instruction set (see Section 26.2.3.1 "Extended Instruction Syntax with Standard PIC18 Commands"). Although the Indexed Literal Offset mode can be very useful for dynamic stack and pointer manipulation, it can also be very annoying if a simple arithmetic operation is carried out on the wrong register. Users who are accustomed to the PIC18 programming must keep in mind that, when the extended instruction set is enabled, register addresses of 5Fh or less are used for Indexed Literal Offset Addressing. Representative examples of typical byte-oriented and bit-oriented instructions in the Indexed Literal Offset mode are provided on the following page to show how execution is affected. The operand conditions shown in the examples are applicable to all instructions of these types. DS39762F-page 422 26.2.3.1 Extended Instruction Syntax with Standard PIC18 Commands When the extended instruction set is enabled, the file register argument `f' in the standard byte-oriented and bit-oriented commands is replaced with the literal offset value `k'. As already noted, this occurs only when `f' is less than or equal to 5Fh. When an offset value is used, it must be indicated by square brackets ("[ ]"). As with the extended instructions, the use of brackets indicates to the compiler that the value is to be interpreted as an index or an offset. Omitting the brackets, or using a value greater than 5Fh within the brackets, will generate an error in the MPASM Assembler. If the index argument is properly bracketed for Indexed Literal Offset Addressing, the Access RAM argument is never specified; it will automatically be assumed to be `0'. This is in contrast to standard operation (extended instruction set disabled), when `a' is set on the basis of the target address. Declaring the Access RAM bit in this mode will also generate an error in the MPASM Assembler. The destination argument `d' functions as before. In the latest versions of the MPASM Assembler, language support for the extended instruction set must be explicitly invoked. This is done with either the command line option, /y, or the PE directive in the source listing. 26.2.4 CONSIDERATIONS WHEN ENABLING THE EXTENDED INSTRUCTION SET It is important to note that the extensions to the instruction set may not be beneficial to all users. In particular, users who are not writing code that uses a software stack may not benefit from using the extensions to the instruction set. Additionally, the Indexed Literal Offset Addressing mode may create issues with legacy applications written to the PIC18 assembler. This is because instructions in the legacy code may attempt to address registers in the Access Bank below 5Fh. Since these addresses are interpreted as literal offsets to FSR2 when the instruction set extension is enabled, the application may read or write to the wrong data addresses. When porting an application to the PIC18F97J60 family, it is very important to consider the type of code. A large, reentrant application that is written in C and would benefit from efficient compilation will do well when using the instruction set extensions. Legacy applications that heavily use the Access Bank will most likely not benefit from using the extended instruction set. 2011 Microchip Technology Inc. PIC18F97J60 FAMILY ADD W to Indexed (Indexed Literal Offset mode) BSF Bit Set Indexed (Indexed Literal Offset mode) Syntax: ADDWF Syntax: BSF [k], b Operands: 0 k 95 d [0,1] Operands: 0 f 95 0b7 Operation: (W) + ((FSR2) + k) dest Operation: 1 ((FSR2) + k)<b> Status Affected: N, OV, C, DC, Z Status Affected: None ADDWF Encoding: [k] {,d} 0010 Description: 01d0 kkkk kkkk The contents of W are added to the contents of the register indicated by FSR2, offset by the value `k'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). Words: 1 Cycles: 1 Encoding: 1000 bbb0 kkkk kkkk Description: Bit `b' of the register indicated by FSR2, offset by the value `k', is set. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read `k' Process Data Write to destination Example: ADDWF Before Instruction W OFST FSR2 Contents of 0A2Ch After Instruction W Contents of 0A2Ch [OFST] ,0 Example: BSF Before Instruction FLAG_OFST FSR2 Contents of 0A0Ah After Instruction Contents of 0A0Ah [FLAG_OFST], 7 = = 0Ah 0A00h = 55h = D5h = = = 17h 2Ch 0A00h = 20h = 37h SETF Set Indexed (Indexed Literal Offset mode) = 20h Syntax: SETF [k] Operands: 0 k 95 Operation: FFh ((FSR2) + k) Status Affected: None Encoding: 0110 1000 kkkk kkkk Description: The contents of the register indicated by FSR2, offset by `k', are set to FFh. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read `k' Process Data Write register Example: SETF Before Instruction OFST FSR2 Contents of 0A2Ch After Instruction Contents of 0A2Ch 2011 Microchip Technology Inc. [OFST] = = 2Ch 0A00h = 00h = FFh DS39762F-page 423 PIC18F97J60 FAMILY 26.2.5 SPECIAL CONSIDERATIONS WITH MICROCHIP MPLAB(R) IDE TOOLS The latest versions of Microchip's software tools have been designed to fully support the extended instruction set for the PIC18F97J60 family. This includes the MPLAB C18 C Compiler, MPASM assembly language and MPLAB Integrated Development Environment (IDE). When selecting a target device for software development, MPLAB IDE will automatically set default Configuration bits for that device. The default setting for the XINST Configuration bit is `0', disabling the extended instruction set and Indexed Literal Offset Addressing. For proper execution of applications developed to take advantage of the extended instruction set, XINST must be set during programming. DS39762F-page 424 To develop software for the extended instruction set, the user must enable support for the instructions and the Indexed Addressing mode in their language tool(s). Depending on the environment being used, this may be done in several ways: * A menu option or dialog box within the environment that allows the user to configure the language tool and its settings for the project * A command line option * A directive in the source code These options vary between different compilers, assemblers and development environments. Users are encouraged to review the documentation accompanying their development systems for the appropriate information. 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 27.0 DEVELOPMENT SUPPORT The PIC(R) microcontrollers and dsPIC(R) digital signal controllers are supported with a full range of software and hardware development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Compilers/Assemblers/Linkers - MPLAB C Compiler for Various Device Families - HI-TECH C for Various Device Families - MPASMTM Assembler - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB Assembler/Linker/Librarian for Various Device Families * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB REAL ICETM In-Circuit Emulator * In-Circuit Debuggers - MPLAB ICD 3 - PICkitTM 3 Debug Express * Device Programmers - PICkitTM 2 Programmer - MPLAB PM3 Device Programmer * Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits 27.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. The MPLAB IDE is a Windows(R) operating system-based application that contains: * A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - In-Circuit Emulator (sold separately) - In-Circuit Debugger (sold separately) * A full-featured editor with color-coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Mouse over variable inspection * Drag and drop variables from source to watch windows * Extensive on-line help * Integration of select third party tools, such as IAR C Compilers The MPLAB IDE allows you to: * Edit your source files (either C or assembly) * One-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) * Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. 2011 Microchip Technology Inc. DS39762F-page 425 PIC18F97J60 FAMILY 27.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip's PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 27.3 HI-TECH C for Various Device Families The HI-TECH C Compiler code development systems are complete ANSI C compilers for Microchip's PIC family of microcontrollers and the dsPIC family of digital signal controllers. These compilers provide powerful integration capabilities, omniscient code generation and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The compilers include a macro assembler, linker, preprocessor, and one-step driver, and can run on multiple platforms. 27.4 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: 27.5 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction 27.6 MPLAB Assembler, Linker and Librarian for Various Device Families MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire device instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility * Integration into MPLAB IDE projects * User-defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process DS39762F-page 426 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 27.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC(R) DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. 27.8 MPLAB REAL ICE In-Circuit Emulator System MPLAB REAL ICE In-Circuit Emulator System is Microchip's next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs PIC(R) Flash MCUs and dsPIC(R) Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The emulator is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with incircuit debugger systems (RJ11) or with the new highspeed, noise tolerant, Low-Voltage Differential Signal (LVDS) interconnection (CAT5). The emulator is field upgradable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. 2011 Microchip Technology Inc. 27.9 MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost effective high-speed hardware debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU) devices. It debugs and programs PIC(R) Flash microcontrollers and dsPIC(R) DSCs with the powerful, yet easyto-use graphical user interface of MPLAB Integrated Development Environment (IDE). The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers. 27.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express The MPLAB PICkit 3 allows debugging and programming of PIC(R) and dsPIC(R) Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB Integrated Development Environment (IDE). The MPLAB PICkit 3 is connected to the design engineer's PC using a full speed USB interface and can be connected to the target via an Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the reset line to implement in-circuit debugging and In-Circuit Serial ProgrammingTM. The PICkit 3 Debug Express include the PICkit 3, demo board and microcontroller, hookup cables and CDROM with user's guide, lessons, tutorial, compiler and MPLAB IDE software. DS39762F-page 427 PIC18F97J60 FAMILY 27.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 27.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkitTM 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip's Flash families of microcontrollers. The full featured Windows(R) programming interface supports baseline (PIC10F, PIC12F5xx, PIC16F5xx), midrange (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many Microchip Serial EEPROM products. With Microchip's powerful MPLAB Integrated Development Environment (IDE) the PICkitTM 2 enables in-circuit debugging on most PIC(R) microcontrollers. In-Circuit-Debugging runs, halts and single steps the program while the PIC microcontroller is embedded in the application. When halted at a breakpoint, the file registers can be examined and modified. A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The PICkit 2 Debug Express include the PICkit 2, demo board and microcontroller, hookup cables and CDROM with user's guide, lessons, tutorial, compiler and MPLAB IDE software. 27.12 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSPTM cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. DS39762F-page 428 The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ(R) security ICs, CAN, IrDA(R), PowerSmart battery management, SEEVAL(R) evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 28.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings() Ambient temperature under bias.............................................................................................................-40C to +100C Storage temperature .............................................................................................................................. -65C to +150C Voltage on any digital only input pin or MCLR with respect to VSS (except VDD) ........................................ -0.3V to 6.0V Voltage on any combined digital and analog pin with respect to VSS ............................................. -0.3V to (VDD + 0.3V) Voltage on VDDCORE with respect to VSS ................................................................................................... -0.3V to 2.75V Voltage on VDD with respect to VSS ........................................................................................................... -0.3V to 4.0V Total power dissipation (Note 1) ...............................................................................................................................1.0W Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin ..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD) (Note 2) 0 mA Output clamp current, IOK (VO < 0 or VO > VDD) (Note 2) 0 mA Maximum output current sunk by any PORTB and PORTC I/O pins......................................................................25 mA Maximum output current sunk by any PORTD, PORTE and PORTJ I/O pins ..........................................................8 mA Maximum output current sunk by any PORTA, PORTF, PORTG and PORTH I/O pins (Note 3) .............................2 mA Maximum output current sourced by any PORTB and PORTC I/O pins.................................................................25 mA Maximum output current sourced by any PORTD, PORTE and PORTJ I/O pins .....................................................8 mA Maximum output current sourced by any PORTA, PORTF, PORTG and PORTH I/O pins (Note 3) ........................2 mA Maximum current sunk byall ports combined.......................................................................................................200 mA Maximum current sourced by all ports combined..................................................................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOL x IOL) + (VTPOUT x ITPOUT) 2: No clamping diodes are present. 3: Exceptions are RA<1> and RA<0>, which are capable of directly driving LEDs up to 25 mA. NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2011 Microchip Technology Inc. DS39762F-page 429 PIC18F97J60 FAMILY FIGURE 28-1: PIC18F97J60 FAMILY VOLTAGE-FREQUENCY GRAPH, REGULATOR ENABLED (ENVREG TIED TO VDD) 4.0V 3.6V 3.5V Voltage (VDD)(1) PIC18F6XJ6X/8XJ6X/9XJ6X 3.0V 2.7V 2.5V 2.0V 0 Frequency 41.6667 MHz When the on-chip regulator is enabled, its BOR circuit will automatically trigger a device Reset before VDD reaches a level at which full-speed operation is not possible. Note 1: FIGURE 28-2: PIC18F97J60 FAMILY VOLTAGE-FREQUENCY GRAPH, REGULATOR DISABLED (ENVREG TIED TO VSS) 3.00V Voltage (VDDCORE)(1) 2.75V 2.7V 2.50V PIC18F6XJ6X/8XJ6X/9XJ6X 2.35V 2.25V 2.00V 41.6667 MHz 4 MHz Frequency For frequencies between 4 MHz and 41.6667 MHz, FMAX = (107.619 MHz/V) * (VDDCORE - 2V) + 4 MHz. Note 1: When the on-chip voltage regulator is disabled, VDD and VDDCORE must be maintained so that VDDCOREVDD3.6V. DS39762F-page 430 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 28.1 DC Characteristics: Supply Voltage, PIC18F97J60 Family (Industrial) PIC18F97J60 Family (Industrial) Param No. Symbol Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Characteristic D001 VDD D001B VDDCORE External Supply for Microcontroller Core Supply Voltage Min Typ Max Units VDDCORE 2.7 3.1 -- -- -- 3.6 3.6 3.6 V V V 2.0 -- 2.7 V D001C AVDD Analog Supply Voltage VDD - 0.3 -- VDD + 0.3 V D002 VDR RAM Data Retention Voltage(1) 1.5 -- -- V D003 VPOR VDD Power-on Reset Voltage -- -- 0.7 V D004 SVDD VDD Rise Rate to Ensure Internal Power-on Reset 0.05 -- -- D005 BOR Brown-out Reset 2.35 2.4 2.7 Note 1: Conditions ENVREG tied to VSS ENVREG tied to VDD Ethernet module enabled (ECON2<5> = 1) See Section 5.3 "Power-on Reset (POR)" for details V/ms See Section 5.3 "Power-on Reset (POR)" for details V This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data. 2011 Microchip Technology Inc. DS39762F-page 431 PIC18F97J60 FAMILY 28.2 DC Characteristics: PIC18F97J60 Family (Industrial) Param No. Power-Down and Supply Current PIC18F97J60 Family (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Device Typ Max Units Conditions 19.0 69.0 A -40C 21.0 69.0 A +25C 45.0 149.0 A +85C 26.0 104.0 A -40C 29.0 104.0 A +25C 60.0 184.0 A +85C 40.0 203.0 A -40C 44.0 203.0 A +25C 105.0 209.0 A +85C Power-Down Current (IPD)(1) All devices All devices All devices Note 1: 2: 3: 4: 5: 6: VDD = 2.0V, VDDCORE = 2.0V(4) (Sleep mode) VDD = 2.5V, VDDCORE = 2.5V(4) (Sleep mode) VDD = 3.3V(5) (Sleep mode) The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 oscillator, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. Standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. Voltage regulator disabled (ENVREG = 0, tied to VSS). Voltage regulator enabled (ENVREG = 1, tied to VDD). For IETH, the specified current includes current sunk through TPOUT+ and TPOUT-. LEDA and LEDB are disabled for all testing. DS39762F-page 432 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 28.2 DC Characteristics: PIC18F97J60 Family (Industrial) Param No. Power-Down and Supply Current PIC18F97J60 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Device Typ Max Units Conditions 12.0 34.0 A -40C 12.0 34.0 A +25C 74.0 108.0 A +85C 20.0 45.0 A -40C 20.0 45.0 A +25C +85C Supply Current (IDD)(2,3) All devices All devices 82.0 126.0 A All devices 105.0 168.0 A -40C 105.0 168.0 A +25C 182.0 246.0 A +85C All devices All devices All devices Note 1: 2: 3: 4: 5: 6: 8.0 32.0 A -40C 8.0 32.0 A +25C 62.0 98.0 A +85C 12.0 35.0 A -40C 12.0 35.0 A +25C 70.0 95.0 A +85C 90.0 152.0 A -40C 90.0 152.0 A +25C 170.0 225.0 A +85C VDD = 2.0V, VDDCORE = 2.0V(4) VDD = 2.5V, VDDCORE = 2.5V(4) FOSC = 31 kHz (RC_RUN mode, Internal Oscillator Source) VDD = 3.3V(5) VDD = 2.0V, VDDCORE = 2.0V(4) VDD = 2.5V, VDDCORE = 2.5V(4) FOSC = 31 kHz (RC_IDLE mode, Internal Oscillator Source) VDD = 3.3V(5) The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 oscillator, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. Standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. Voltage regulator disabled (ENVREG = 0, tied to VSS). Voltage regulator enabled (ENVREG = 1, tied to VDD). For IETH, the specified current includes current sunk through TPOUT+ and TPOUT-. LEDA and LEDB are disabled for all testing. 2011 Microchip Technology Inc. DS39762F-page 433 PIC18F97J60 FAMILY 28.2 DC Characteristics: PIC18F97J60 Family (Industrial) Param No. Power-Down and Supply Current PIC18F97J60 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Device Typ Max Units Conditions 0.8 1.5 mA -40C 0.8 1.5 mA +25C 0.9 1.7 mA +85C 1.1 1.8 mA -40C 1.1 1.8 mA +25C 1.2 2.0 mA +85C 2.1 3.4 mA -40C 2.0 3.4 mA +25C 2.1 3.4 mA +85C Supply Current (IDD)(2) All devices All devices All devices All devices All devices All devices All devices Note 1: 2: 3: 4: 5: 6: 9.2 14.5 mA -40C 9.0 14.5 mA +25C 9.2 14.5 mA +85C 13.0 18.4 mA -40C 12.4 18.4 mA +25C 13.0 18.4 mA +85C 13.4 19.8 mA -40C 13.0 19.8 mA +25C 13.4 19.8 mA +85C 14.5 21.6 mA -40C 14.4 21.6 mA +25C 14.5 21.6 mA +85C VDD = 2.0V, VDDCORE = 2.0V(4) VDD = 2.5V, VDDCORE = 2.5V(4) FOSC = 1 MHZ (PRI_RUN mode, EC oscillator) VDD = 3.3V(5) VDD = 2.5V, VDDCORE = 2.5V(4) VDD = 3.3V(5) VDD = 2.5V, VDDCORE = 2.5V(4) FOSC = 25 MHz (PRI_RUN mode, EC oscillator) FOSC = 41.6667 MHZ (PRI_RUN mode, EC oscillator) VDD = 3.3V(5) The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 oscillator, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. Standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. Voltage regulator disabled (ENVREG = 0, tied to VSS). Voltage regulator enabled (ENVREG = 1, tied to VDD). For IETH, the specified current includes current sunk through TPOUT+ and TPOUT-. LEDA and LEDB are disabled for all testing. DS39762F-page 434 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 28.2 DC Characteristics: PIC18F97J60 Family (Industrial) Param No. Power-Down and Supply Current PIC18F97J60 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Device Typ Max Units Conditions 2.8 5.2 mA -40C 2.5 5.2 mA +25C 2.8 5.2 mA +85C Supply Current (IDD)(2) All devices All devices All devices All devices All devices All devices All devices All devices Note 1: 2: 3: 4: 5: 6: 3.6 6.4 mA -40C 3.3 6.4 mA +25C 3.6 6.4 mA +85C 6.4 11.0 mA -40C 6.0 11.0 mA +25C 6.4 11.0 mA +85C 7.8 12.5 mA -40C 7.4 12.5 mA +25C 7.8 12.5 mA +85C 9.2 14.5 mA -40C 9.0 14.5 mA +25C 9.2 14.5 mA +85C 13.0 18.4 mA -40C 12.4 18.4 mA +25C 13.0 18.4 mA +85C 13.4 19.8 mA -40C 13.0 19.8 mA +25C 13.4 19.8 mA +85C 14.5 21.6 mA -40C 14.4 21.6 mA +25C 14.5 21.6 mA +85C VDD = 2.5V, VDDCORE = 2.5V(4) FOSC = 25 MHZ, 2.7778 MHz internal (PRI_RUN HS mode) VDD = 3.3V(5) VDD = 2.5V, VDDCORE = 2.5V(4) FOSC = 25 MHZ, 13.8889 MHz internal (PRI_RUN HSPLL mode) VDD = 3.3V(5) VDD = 2.5V, VDDCORE = 2.5V(4) FOSC = 25 MHZ, 25 MHz internal (PRI_RUN HS mode) VDD = 3.3V(5) VDD = 2.5V, VDDCORE = 2.5V(4) FOSC = 25 MHZ, 41.6667 MHz internal (PRI_RUN HSPLL mode) VDD = 3.3V(5) The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 oscillator, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. Standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. Voltage regulator disabled (ENVREG = 0, tied to VSS). Voltage regulator enabled (ENVREG = 1, tied to VDD). For IETH, the specified current includes current sunk through TPOUT+ and TPOUT-. LEDA and LEDB are disabled for all testing. 2011 Microchip Technology Inc. DS39762F-page 435 PIC18F97J60 FAMILY 28.2 DC Characteristics: PIC18F97J60 Family (Industrial) Param No. Power-Down and Supply Current PIC18F97J60 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Device Typ Max Units Conditions 0.5 1.1 mA -40C 0.5 1.1 mA +25C 0.6 1.2 mA +85C 0.9 1.4 mA -40C 0.9 1.4 mA +25C 1.0 1.5 mA +85C 1.9 2.6 mA -40C 1.8 2.6 mA +25C 1.9 2.6 mA +85C Supply Current (IDD)(2) All devices All devices All devices All devices All devices All devices All devices Note 1: 2: 3: 4: 5: 6: 5.9 9.5 mA -40C 5.6 9.5 mA +25C 5.9 9.5 mA +85C 7.5 13.2 mA -40C 7.2 13.2 mA +25C 7.5 13.2 mA +85C 8.6 14.0 mA -40C 8.0 14.0 mA +25C 8.6 14.0 mA +85C 9.8 16.0 mA -40C 9.4 16.0 mA +25C 9.8 16.0 mA +85C VDD = 2.0V, VDDCORE = 2.0V(4) VDD = 2.5V, VDDCORE = 2.5V(4) FOSC = 1 MHz (PRI_IDLE mode, EC oscillator) VDD = 3.3V(5) VDD = 2.5V, VDDCORE = 2.5V(4) FOSC = 25 MHZ (PRI_IDLE mode, EC oscillator) VDD = 3.3V(5) VDD = 2.5V, VDDCORE = 2.5V(4) FOSC = 41.6667 MHz (PRI_IDLE mode, EC oscillator) VDD = 3.3V(5) The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 oscillator, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. Standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. Voltage regulator disabled (ENVREG = 0, tied to VSS). Voltage regulator enabled (ENVREG = 1, tied to VDD). For IETH, the specified current includes current sunk through TPOUT+ and TPOUT-. LEDA and LEDB are disabled for all testing. DS39762F-page 436 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 28.2 DC Characteristics: PIC18F97J60 Family (Industrial) Param No. Power-Down and Supply Current PIC18F97J60 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Device Typ Max Units Conditions 22.0 45.0 A -10C 22.0 45.0 A +25C 78.0 114.0 A +70C 27.0 52.0 A -10C 27.0 52.0 A +25C +70C Supply Current (IDD)(2) All devices All devices 92.0 135.0 A All devices 106.0 168.0 A -10C 106.0 168.0 A +25C 188.0 246.0 A +70C All devices All devices All devices Note 1: 2: 3: 4: 5: 6: 18.0 37.0 A -10C 18.0 37.0 A +25C 75.0 105.0 A +70C 21.0 40.0 A -10C 21.0 40.0 A +25C 84.0 98.0 A +70C 94.0 152.0 A -10C 94.0 152.0 A +25C 182.0 225.0 A +70C VDD = 2.0V, VDDCORE = 2.0V(4) VDD = 2.5V, VDDCORE = 2.5V(4) FOSC = 32 kHz(3) (SEC_RUN mode, Timer1 as clock) VDD = 3.3V(5) VDD = 2.0V, VDDCORE = 2.0V(4) VDD = 2.5V, VDDCORE = 2.5V(4) FOSC = 32 kHz(3) (SEC_IDLE mode, Timer1 as clock) VDD = 3.3V(5) The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 oscillator, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. Standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. Voltage regulator disabled (ENVREG = 0, tied to VSS). Voltage regulator enabled (ENVREG = 1, tied to VDD). For IETH, the specified current includes current sunk through TPOUT+ and TPOUT-. LEDA and LEDB are disabled for all testing. 2011 Microchip Technology Inc. DS39762F-page 437 PIC18F97J60 FAMILY 28.2 DC Characteristics: PIC18F97J60 Family (Industrial) Param No. D022 (IWDT) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Device D027 IETH(6) 4: 5: 6: Units Conditions VDD = 2.0V, VDDCORE = 2.0V(4) 7.0 19.0 8.0 A A A +25C +85C -40C 3.0 14.0 5.0 5.0 19.0 12.0 8.0 22.0 12.0 12.0 30.0 20.0 A A A A A A +25C +85C -40C +25C +85C -40C 12.0 24.0 13.0 20.0 36.0 21.0 A A A +25C +85C -40C 13.0 26.0 14.0 14.0 29.0 21.0 38.0 25.0 25.0 40.0 A A A A A +25C +85C -40C +25C +85C 1.2 10.0 A -40C to +85C VDD = 2.0V, VDDCORE = 2.0V(4) 1.2 10.0 A -40C to +85C VDD = 2.5V, VDDCORE = 2.5V(4) 1.2 Ethernet Module 130.0 11.0 156.0 A mA -40C to +85C -40C to +85C 180.0 214.0 mA -40C to +85C A/D Converter 3: Max 2.4 12.0 3.0 Timer1 Oscillator D026 (IAD) 2: Typ Module Differential Currents (IWDT, IOSCB, IAD, IETH) Watchdog Timer 2.4 7.0 A -40C D025 (IOSCB) Note 1: Power-Down and Supply Current PIC18F97J60 Family (Industrial) (Continued) VDD = 2.5V, VDDCORE = 2.5V(4) VDD = 3.3V(5) VDD = 2.0V, VDDCORE = 2.0V(4) 32 kHz on Timer1(3) VDD = 2.5V, VDDCORE = 2.5V(4) 32 kHz on Timer1(3) VDD = 3.3V(5) 32 kHz on Timer1(3) A/D on, not converting VDD = 3.3V(5) VDD = 3.3V(5) No transmit activity Transmission in progress The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 oscillator, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. Standard, low-cost 32 kHz crystals have an operating temperature range of -10C to +70C. Extended temperature crystals are available at a much higher cost. Voltage regulator disabled (ENVREG = 0, tied to VSS). Voltage regulator enabled (ENVREG = 1, tied to VDD). For IETH, the specified current includes current sunk through TPOUT+ and TPOUT-. LEDA and LEDB are disabled for all testing. DS39762F-page 438 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 28.3 DC Characteristics: PIC18F97J60 Family (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial DC CHARACTERISTICS Param Symbol No. VIL Characteristic Min Max Units Conditions Input Low Voltage All I/O Ports: D030 with TTL Buffer D031 with Schmitt Trigger Buffer VSS 0.15VDD V VDD <2.7V VSS 0.8 V 2.7V VDD 3.6V VSS 0.2 VDD V D032 MCLR VSS 0.2 VDD V D033 OSC1 VSS 0.3 VDD V HS, HSPLL modes D033A OSC1 VSS 0.2 VDD V EC mode D034 T13CKI VSS 0.3 V 0.25 VDD + 0.8V VDD V 0.8 VDD VDD V 0.25 VDD + 0.8V 5.5 V VIH Input High Voltage I/O Ports, with Analog Functions: D040 with TTL Buffer D041 with Schmitt Trigger Buffer I/O Ports, Digital Only: with TTL Buffer 0.8 VDD 5.5 V D042 MCLR 0.8 VDD VDD V D043 OSC1 0.7 VDD VDD V HS, HSPLL modes D043A OSC1 0.8 VDD VDD V EC mode 1.6 VDD V with Schmitt Trigger Buffer D044 T13CKI IIL Input Leakage Current(1) D060 I/O Ports -- 1 A VSS VPIN VDD, Pin at high-impedance D061 MCLR -- 1 A Vss VPIN VDD OSC1 -- 1 A Vss VPIN VDD 80 400 A VDD = 3.3V, VPIN = VSS D063 D070 Note 1: IPU Weak Pull-up Current IPURB PORTB, PORTD, PORTE, PORTJ Negative current is defined as current sourced by the pin. 2011 Microchip Technology Inc. DS39762F-page 439 PIC18F97J60 FAMILY 28.3 DC Characteristics: PIC18F97J60 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial DC CHARACTERISTICS Param Symbol No. VOL D080 Characteristic Min Max Units Conditions PORTD, PORTE, PORTJ -- 0.4 V IOL = 4 mA, VDD = 3.3V, -40C to +85C PORTA<5:2>, PORTF, PORTG, PORTH -- 0.4 V IOL = 2 mA, VDD = 3.3V, -40C to +85C PORTA<1:0>, PORTB, PORTC -- 0.4 V IOL = 8 mA, VDD = 3.3V, -40C to +85C -- 0.4 V IOL = 2 mA, VDD = 3.3V, -40C to +85C PORTD, PORTE, PORTJ 2.4 -- V IOH = -4 mA, VDD = 3.3V, -40C to +85C PORTA<5:2>, PORTF, PORTG, PORTH 2.4 -- V IOH = -2 mA, VDD = 3.3V, -40C to +85C PORTA<1:0>, PORTB, PORTC 2.4 -- V IOH = -8 mA, VDD = 3.3V, -40C to +85C 2.4 -- V IOH = -1.0 mA, VDD = 3.3V, -40C to +85C -- 15 pF In HS mode when external clock is used to drive OSC1 Output Low Voltage I/O Ports: D083 OSC2/CLKO (EC, ECPLL modes) VOH D090 Output High Voltage(1) I/O Ports: D092 OSC2/CLKO (EC, ECPLL modes) V Capacitive Loading Specs on Output Pins D100 COSC2 OSC2 pin D101 CIO All I/O pins and OSC2 (in Internal RC mode, EC, ECPLL) -- 50 pF To meet the AC timing specifications D102 CB SCLx, SDAx -- 400 pF I2CTM specification Note 1: Negative current is defined as current sourced by the pin. DS39762F-page 440 2011 Microchip Technology Inc. PIC18F97J60 FAMILY TABLE 28-1: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial DC CHARACTERISTICS Param No. Sym Characteristic Min Typ Max Units Conditions Program Flash Memory D130 EP Cell Endurance 100 1K -- D131 VPR VDD for Read VMIN -- 3.6 V VMIN = Minimum operating voltage Voltage for Self-Timed Erase or Write VDD VDDCORE 2.70 2.35 -- -- 3.6 2.7 V V ENVREG tied to VDD ENVREG tied to VSS -- 2.8 -- ms 20 -- -- Year Provided no other specifications are violated -- 10 -- mA D132B VPEW D133A TIW Self-Timed Write Cycle Time D134 TRETD Characteristic Retention D135 IDDP Supply Current during Programming E/W -40C to +85C Ethernet module disabled Data in "Typ" column is at 3.3V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2011 Microchip Technology Inc. DS39762F-page 441 PIC18F97J60 FAMILY TABLE 28-2: COMPARATOR SPECIFICATIONS Operating Conditions: 3.0V VDD 3.6V, -40C TA +85C (unless otherwise stated) Param No. Sym Characteristics Min Typ Max Units D300 VIOFF Input Offset Voltage* -- 5.0 25 mV D301 VICM Input Common-Mode Voltage* 0 -- AVDD - 1.5 V D302 CMRR Common-Mode Rejection Ratio* 55 -- -- dB 300 TRESP Response Time(1)* -- 150 400 ns 301 TMC2OV Comparator Mode Change to Output Valid* -- -- 10 s * Note 1: Comments These parameters are characterized but not tested. Response time measured with one comparator input at (AVDD - 1.5)/2, while the other input transitions from VSS to AVDD. TABLE 28-3: VOLTAGE REFERENCE SPECIFICATIONS Operating Conditions: 3.0V VDD 3.6V, -40C TA +85C (unless otherwise stated) Param No. Sym Characteristics Min Typ Max Units VDD/24 -- VDD/32 LSb VRES Resolution D311 VRAA Absolute Accuracy -- -- 1/2 LSb D312 VRUR Unit Resistor Value (R) -- 2k -- TSET Time(1) -- -- 10 s D310 310 Note 1: Settling Comments Settling time measured while CVRR = 1 and CVR<3:0> transitions from `0000' to `1111'. TABLE 28-4: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Operating Conditions: -40C TA +85C (unless otherwise stated) Param No. Sym Characteristics Min Typ Max Units VRGOUT Regulator Output Voltage -- 2.5 -- V CF External Filter Capacitor Value 1 10 -- F DS39762F-page 442 Comments Capacitor must be low series resistance 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 28.4 28.4.1 AC (Timing) Characteristics TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc ECCP1 ck CLKO cs CS di SDIx do SDOx dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (High-Impedance) L Low I2C only AA Output access BUF Bus free TCC:ST (I2C specifications only) CC HD Hold ST DAT DATA input hold STA Start condition 2011 Microchip Technology Inc. 3. TCC:ST 4. Ts (I2C specifications only) (I2C specifications only) T Time osc rd rw sc ss t0 t1 wr OSC1 RD RD or WR SCKx SSx T0CKI T13CKI WR P R V Z Period Rise Valid High-Impedance High Low High Low SU Setup STO Stop condition DS39762F-page 443 PIC18F97J60 FAMILY 28.4.2 TIMING CONDITIONS The temperature and voltages specified in Table 28-5 apply to all timing specifications unless otherwise noted. Figure 28-3 specifies the load conditions for the timing specifications. TABLE 28-5: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC AC CHARACTERISTICS FIGURE 28-3: Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Operating voltage VDD range as described in DC spec Section 28.1 "DC Characteristics: Supply Voltage, PIC18F97J60 Family (Industrial)" and Section 28.3 "DC Characteristics: PIC18F97J60 Family (Industrial)". LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 2 Load Condition 1 VDD/2 RL CL Pin CL Pin VSS VSS RL = 464 DS39762F-page 444 CL = 50 pF for all pins except OSC2/CLKO and including D and E outputs as ports CL = 15 pF for OSC2/CLKO 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 28.4.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 28-4: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 4 3 4 2 CLKO TABLE 28-6: Param. No. 1A EXTERNAL CLOCK TIMING REQUIREMENTS Symbol FOSC Characteristic Min Max Units External CLKI Frequency(1) DC 41.6667 MHz TOSC EC Oscillator mode 6 25 MHz HS Oscillator mode External CLKI Period(1) 24 -- ns EC Oscillator mode Oscillator Period(1) Oscillator Frequency 1 (1) Conditions 40 167 ns HS Oscillator mode 2 TCY Instruction Cycle Time(1) 96 -- ns TCY = 4/FOSC, Industrial 3 TOSL, TOSH External Clock in (OSC1) High or Low Time 10 -- ns EC Oscillator mode 4 TOSR, TOSF External Clock in (OSC1) Rise or Fall Time -- 7.5 ns EC Oscillator mode Clock Frequency Tolerance -- 50 ppm 5 Note 1: Ethernet module enabled Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations except PLL. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the "max." cycle time limit is "DC" (no clock) for all devices. 2011 Microchip Technology Inc. DS39762F-page 445 PIC18F97J60 FAMILY TABLE 28-7: Param No. PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.6V TO 3.6V) Sym Characteristic Min Typ Max Units Conditions F10 FOSC Oscillator Frequency Range 8 8 -- -- 25 37.5 MHz HSPLL mode MHz ECPLL mode F11 FSYS On-Chip VCO System Frequency 20 -- 62.5 MHz F12 trc PLL Start-up Time (Lock Time) -- -- 2 ms F13 CLK CLKO Stability (Jitter) -2 -- +2 % Data in "Typ" column is at 3.3V, 25C, unless otherwise stated. These parameters are for design guidance only and are not tested. TABLE 28-8: AC CHARACTERISTICS: INTERNAL RC ACCURACY PIC18F97J60 FAMILY (INDUSTRIAL) Param No. Note 1: Characteristic Min Typ Max Units INTRC Accuracy @ Freq = 31 kHz(1) 21.7 -- 40.3 kHz Conditions INTRC frequency changes as VDDCORE changes. DS39762F-page 446 2011 Microchip Technology Inc. PIC18F97J60 FAMILY FIGURE 28-5: CLKO AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKO 13 12 14 18 19 16 I/O pin (Input) 15 17 I/O pin (Output) New Value Old Value 20, 21 Refer to Figure 28-3 for load conditions. Note: TABLE 28-9: Param No. CLKO AND I/O TIMING REQUIREMENTS Symbol Characteristic Min Typ Max Units Conditions 10 TOSH2CKL OSC1 to CLKO -- 75 200 ns 11 TOSH2CKH OSC1 to CLKO -- 75 200 ns 12 TCKR CLKO Rise Time -- 15 30 ns 13 TCKF CLKO Fall Time -- 15 30 ns -- -- 0.5 TCY + 20 ns 0.25 TCY + 25 -- -- ns 14 TCKL2IOV CLKO to Port Out Valid 15 TIOV2CKH Port In Valid before CLKO 16 TCKH2IOI 17 TOSH2IOV OSC1 (Q1 cycle) to Port Out Valid 18 TOSH2IOI 19 Port In Hold after CLKO 0 -- -- ns -- 50 150 ns 100 -- -- ns TIOV2OSH Port Input Valid to OSC1 (I/O in setup time) 0 -- -- ns OSC1 (Q2 cycle) to Port Input Invalid (I/O in hold time) 20 TIOR Port Output Rise Time -- -- 6 ns 21 TIOF Port Output Fall Time -- -- 5 ns 22 TINP INTx pin High or Low Time TCY -- -- ns 23 TRBP RB<7:4> Change INTx High or Low Time TCY -- -- ns These parameters are asynchronous events not related to any internal clock edges. 2011 Microchip Technology Inc. DS39762F-page 447 PIC18F97J60 FAMILY FIGURE 28-6: PROGRAM MEMORY READ TIMING DIAGRAM Q1 Q2 Q3 Q4 Q1 Q2 OSC1 A<19:16> BA0 AD<15:0> Address Address Address Data from External 150 151 Address 163 160 162 161 155 166 167 ALE 168 164 169 171 CE 171A OE 165 Operating Conditions: 2.0V < VCC < 3.6V, -40C < TA < +125C, unless otherwise stated. TABLE 28-10: CLKO AND I/O TIMING REQUIREMENTS Param. No Symbol Characteristics Min Typ Max Units 150 TadV2alL Address Out Valid to ALE (address setup time) 0.25 TCY - 10 -- -- ns 151 TalL2adl ALE to Address Out Invalid (address hold time) 5 -- -- ns 155 TalL2oeL ALE to OE 10 0.125 TCY -- ns 160 TadZ2oeL AD high-Z to OE (bus release to OE) 0 -- -- ns 161 ToeH2adD OE to AD Driven 0.125 TCY - 5 -- -- ns 162 TadV2oeH Least Significant Data Valid before OE (data setup time) 20 -- -- ns 163 ToeH2adl OE to Data In Invalid (data hold time) 0 -- -- ns 164 TalH2alL ALE Pulse Width 165 ToeL2oeH OE Pulse Width -- TCY -- ns 0.5 TCY - 5 0.5 TCY -- ns 166 TalH2alH ALE to ALE (cycle time) -- 0.25 TCY -- ns 167 Tacc Address Valid to Data Valid 0.75 TCY - 25 -- -- ns 168 Toe OE to Data Valid -- 0.5 TCY - 25 ns 169 TalL2oeH ALE to OE 0.625 TCY - 10 -- 0.625 TCY + 10 ns 171 TalH2csL Chip Enable Active to ALE 0.25 TCY - 20 -- -- ns 171A TubL2oeH AD Valid to Chip Enable Active -- -- 10 ns DS39762F-page 448 2011 Microchip Technology Inc. PIC18F97J60 FAMILY FIGURE 28-7: PROGRAM MEMORY WRITE TIMING DIAGRAM Q1 Q2 Q3 Q4 Q1 Q2 OSC1 A<19:16> BA0 Address Address 166 AD<15:0> Data Address Address 153 150 156 151 ALE 171 CE 171A 154 WRH or WRL 157A 157 UB or LB Operating Conditions: 2.0V < VCC < 3.6V, -40C < TA < +125C, unless otherwise stated. TABLE 28-11: PROGRAM MEMORY WRITE TIMING REQUIREMENTS Param. No Symbol Characteristics Min Typ Max Units 150 TadV2alL Address Out Valid to ALE (address setup time) 0.25 TCY - 10 -- -- ns 151 TalL2adl ALE to Address Out Invalid (address hold time) 5 -- -- ns 153 TwrH2adl WRn to Data Out Invalid (data hold time) 154 TwrL WRn Pulse Width 156 TadV2wrH Data Valid before WRn (data setup time) 157 TbsV2wrL Byte Select Valid before WRn (byte select setup time) 157A TwrH2bsI WRn to Byte Select Invalid (byte select hold time) 166 TalH2alH 171 TalH2csL 171A TubL2oeH AD Valid to Chip Enable Active 5 -- -- ns 0.5 TCY - 5 0.5 TCY -- ns 0.5 TCY - 10 -- -- ns 0.25 TCY -- -- ns 0.125 TCY - 5 -- -- ns ALE to ALE (cycle time) -- 0.25 TCY -- ns Chip Enable Active to ALE 0.25 TCY - 20 -- -- ns -- -- 10 ns 2011 Microchip Technology Inc. DS39762F-page 449 PIC18F97J60 FAMILY FIGURE 28-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 Oscillator Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O pins Note: Refer to Figure 28-3 for load conditions. TABLE 28-12: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. Symbol No. Characteristic Min Typ Max Units Conditions 30 TMCL MCLR Pulse Width (low) 2 -- -- s 31 TWDT Watchdog Timer Time-out Period (no postscaler) 2.8 4.1 5.4 ms 32 TOST Oscillation Start-up Timer Period 1024 TOSC -- 1024 TOSC -- 33 TPWRT Power-up Timer Period 46.2 66 85.8 ms 34 TIOZ I/O High-Impedance from MCLR Low or Watchdog Timer Reset -- -- 3TCY + 2 s System clock available -- -- 415 s System clock unavailable (Sleep mode or primary oscillator off) CPU Start-up Time -- 200 -- s 38 TCSD DS39762F-page 450 TOSC = OSC1 period 2011 Microchip Technology Inc. PIC18F97J60 FAMILY FIGURE 28-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 41 40 42 T1OSO/T13CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 28-3 for load conditions. TABLE 28-13: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No. Symbol Characteristic 40 TT0H T0CKI High Pulse Width 41 TT0L T0CKI Low Pulse Width 42 TT0P T0CKI Period No prescaler With prescaler No prescaler With prescaler No prescaler With prescaler 45 46 47 TT1H TT1L T13CKI High Synchronous, no prescaler Time Synchronous, with prescaler Max Units 0.5 TCY + 20 -- ns 10 -- ns 0.5 TCY + 20 -- ns 10 -- ns TCY + 10 -- ns Greater of: 20 ns or (TCY + 40)/N -- ns 0.5 TCY + 20 -- ns 10 -- ns Asynchronous 30 -- ns T13CKI Low Synchronous, no prescaler Time Synchronous, with prescaler 0.5 TCY + 5 -- ns 10 -- ns Asynchronous 30 -- ns Greater of: 20 ns or (TCY + 40)/N -- ns TT1P T13CKI Input Synchronous Period FT 1 T13CKI Oscillator Input Frequency Range Asynchronous 48 Min TCKE2TMRI Delay from External T13CKI Clock Edge to Timer Increment 2011 Microchip Technology Inc. 60 -- ns DC 50 kHz 2 TOSC 7 TOSC -- Conditions N = prescale value (1, 2, 4,..., 256) N = prescale value (1, 2, 4, 8) DS39762F-page 451 PIC18F97J60 FAMILY FIGURE 28-10: CAPTURE/COMPARE/PWM TIMINGS (INCLUDING ECCPx MODULES) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 53 Note: 54 Refer to Figure 28-3 for load conditions. TABLE 28-14: CAPTURE/COMPARE/PWM REQUIREMENTS (INCLUDING ECCPx MODULES) Param Symbol No. 50 51 TCCL TCCH Characteristic Min Max Units CCPx Input Low No prescaler Time With prescaler 0.5 TCY + 20 -- ns 10 -- ns CCPx Input High Time 0.5 TCY + 20 -- ns 10 -- ns 3 TCY + 40 N -- ns No prescaler With prescaler TCCP CCPx Input Period 53 TCCR CCPx Output Fall Time -- 25 ns 54 TCCF CCPx Output Fall Time -- 25 ns 52 Conditions N = prescale value (1, 4 or 16) TABLE 28-15: PARALLEL SLAVE PORT REQUIREMENTS Param. No. Symbol Characteristic Min Max Units 62 TdtV2wrH Data In Valid before WR or CS (setup time) 20 -- ns 63 TwrH2dtI WR or CS to Data-In Invalid (hold time) 20 -- ns 64 TrdL2dtV RD and CS to Data-Out Valid -- 80 ns 65 TrdH2dtI RD or CS to Data-Out Invalid 10 30 ns 66 TibfINH Inhibit of the IBF Flag bit being Cleared from WR or CS -- 3 TCY DS39762F-page 452 Conditions 2011 Microchip Technology Inc. PIC18F97J60 FAMILY FIGURE 28-11: EXAMPLE SPI MASTER MODE TIMING (CKE = 0) SCKx (CKP = 0) 78 79 79 78 SCKx (CKP = 1) 80 bit 6 - - - - - - 1 MSb SDOx LSb 75, 76 SDIx MSb In bit 6 - - - - 1 LSb In 74 73 Note: Refer to Figure 28-3 for load conditions. TABLE 28-16: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0) Param No. Symbol Characteristic Min Max Units 73 TDIV2SCH, TDIV2SCL Setup Time of SDIx Data Input to SCKx Edge 100 -- ns 74 TSCH2DIL, TSCL2DIL Hold Time of SDIx Data Input to SCKx Edge 100 -- ns 75 TDOR SDOx Data Output Rise Time -- 25 ns 76 TDOF SDOx Data Output Fall Time -- 25 ns 78 TSCR SCKx Output Rise Time -- 25 ns 79 TSCF SCKx Output Fall Time -- 25 ns 80 TSCH2DOV, SDOx Data Output Valid after SCKx Edge TSCL2DOV -- 50 ns 2011 Microchip Technology Inc. Conditions DS39762F-page 453 PIC18F97J60 FAMILY FIGURE 28-12: EXAMPLE SPI MASTER MODE TIMING (CKE = 1) 81 SCKx (CKP = 0) 79 73 SCKx (CKP = 1) 80 78 MSb SDOx bit 6 - - - - - - 1 LSb bit 6 - - - - 1 LSb In 75, 76 SDIx MSb In 74 Note: Refer to Figure 28-3 for load conditions. TABLE 28-17: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1) Param. No. Symbol Characteristic Min Max Units 73 TDIV2SCH, TDIV2SCL Setup Time of SDIx Data Input to SCKx Edge 100 -- ns 74 TSCH2DIL, TSCL2DIL Hold Time of SDIx Data Input to SCKx Edge 100 -- ns 75 TDOR SDOx Data Output Rise Time -- 25 ns 76 TDOF SDOx Data Output Fall Time -- 25 ns 78 TSCR SCKx Output Rise Time -- 25 ns 79 TSCF SCKx Output Fall Time 80 TSCH2DOV, SDOx Data Output Valid after SCKx Edge TSCL2DOV 81 TDOV2SCH, SDOx Data Output Setup to SCKx Edge TDOV2SCL DS39762F-page 454 -- 25 ns -- 50 ns TCY -- ns Conditions 2011 Microchip Technology Inc. PIC18F97J60 FAMILY FIGURE 28-13: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0) SSx 70 SCKx (CKP = 0) 83 71 72 SCKx (CKP = 1) 80 MSb SDOx bit 6 - - - - - - 1 LSb 75, 76 MSb In SDIx SDI 77 bit 6 - - - - 1 LSb In 74 73 Refer to Figure 28-3 for load conditions. Note: TABLE 28-18: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0) Param No. Symbol Characteristic 70 TSSL2SCH, SSx to SCKx or SCKx Input TSSL2SCL 71 TSCH SCKx Input High Time 71A 72 TSCL SCKx Input Low Time 72A Min TCY Max Units Conditions -- ns Continuous 1.25 TCY + 30 -- ns Single Byte 40 -- ns Continuous 1.25 TCY + 30 -- ns 40 -- ns 100 -- ns -- ns 100 -- ns Single Byte 73 TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge TDIV2SCL 73A TB2B 74 TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge TSCL2DIL 75 TDOR SDOx Data Output Rise Time -- 25 ns 76 TDOF SDOx Data Output Fall Time -- 25 ns 77 TSSH2DOZ SSx to SDOx Output High-impedance 10 50 ns 80 TSCH2DOV, SDOx Data Output Valid after SCKx Edge TSCL2DOV -- 50 ns 83 TSCH2SSH, SSx after SCKx Edge TSCL2SSH 1.5 TCY + 40 -- ns Note 1: 2: Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 (Note 1) (Note 1) (Note 2) Requires the use of Parameter #73A. Only if Parameter #71A and #72A are used. 2011 Microchip Technology Inc. DS39762F-page 455 PIC18F97J60 FAMILY FIGURE 28-14: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1) 82 SSx SCKx (CKP = 0) 70 83 71 72 SCKx (CKP = 1) 80 MSb SDOx bit 6 - - - - - - 1 LSb 75, 76 SDI SDIx MSb In 77 bit 6 - - - - 1 LSb In 74 Note: Refer to Figure 28-3 for load conditions. TABLE 28-19: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1) Param No. Symbol Characteristic 70 TSSL2SCH, SSx to SCKx or SCKx Input TSSL2SCL 71 TSCH SCKx Input High Time 71A 72 TSCL SCKx Input Low Time 72A Min Max Units Conditions TCY -- ns Continuous 1.25 TCY + 30 -- ns Single Byte 40 -- ns Continuous 1.25 TCY + 30 -- ns Single Byte 40 -- ns (Note 1) -- ns (Note 2) -- ns 73A TB2B 74 TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge TSCL2DIL Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 100 75 TDOR SDOx Data Output Rise Time -- 25 ns 76 TDOF SDOx Data Output Fall Time -- 25 ns 77 TSSH2DOZ SSx to SDOx Output High-Impedance 10 50 ns 80 TSCH2DOV, SDOx Data Output Valid after SCKx Edge TSCL2DOV -- 50 ns 82 TSSL2DOV SDOx Data Output Valid after SSx Edge -- 50 ns 83 TSCH2SSH, SSx after SCKx Edge TSCL2SSH 1.5 TCY + 40 -- ns Note 1: 2: (Note 1) Requires the use of Parameter #73A. Only if Parameter #71A and #72A are used. DS39762F-page 456 2011 Microchip Technology Inc. PIC18F97J60 FAMILY FIGURE 28-15: I2CTM BUS START/STOP BITS TIMING SCLx 91 93 90 92 SDAx Stop Condition Start Condition Note: Refer to Figure 28-3 for load conditions. TABLE 28-20: I2CTM BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol No. Characteristic 90 TSU:STA Start Condition 91 THD:STA 92 TSU:STO 93 THD:STO Stop Condition Max Units Conditions 4700 -- ns Only relevant for Repeated Start condition ns After this period, the first clock pulse is generated Setup Time 400 kHz mode 600 -- Start Condition 100 kHz mode 4000 -- Hold Time 400 kHz mode 600 -- Stop Condition 100 kHz mode 4700 -- Setup Time Hold Time FIGURE 28-16: 100 kHz mode Min 400 kHz mode 600 -- 100 kHz mode 4000 -- 400 kHz mode 600 -- ns ns I2CTM BUS DATA TIMING 103 102 100 101 SCLx 90 106 107 91 92 SDAx In 110 109 109 SDAx Out Note: Refer to Figure 28-3 for load conditions. 2011 Microchip Technology Inc. DS39762F-page 457 PIC18F97J60 FAMILY TABLE 28-21: I2CTM BUS DATA REQUIREMENTS (SLAVE MODE) Param. Symbol No. 100 THIGH 101 TLOW 102 TR 103 TF 90 91 106 Characteristic Clock High Time Clock Low Time 110 2: -- s PIC18F97J60 family must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 -- s PIC18F97J60 family must operate at a minimum of 10 MHz MSSP module 1.5 TCY -- 100 kHz mode 4.7 -- s PIC18F97J60 family must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 -- s PIC18F97J60 family must operate at a minimum of 10 MHz 1.5 TCY -- -- 1000 ns 400 kHz mode 20 + 0.1 CB 300 ns SDAx and SCLx Fall Time 100 kHz mode 300 ns 300 ns CB is specified to be from 10 to 400 pF Only relevant for Repeated Start condition -- 400 kHz mode 20 + 0.1 CB 4.7 -- s 400 kHz mode 0.6 -- s THD:STA Start Condition Hold Time 100 kHz mode 4.0 -- s 400 kHz mode 0.6 -- s 100 kHz mode 0 -- ns 400 kHz mode 0 0.9 s CB Note 1: 4.0 100 kHz mode TBUF D102 100 kHz mode TSU:STA Start Condition Setup Time TAA Conditions MSSP module 100 kHz mode 250 -- ns 400 kHz mode 100 -- ns 100 kHz mode 4.7 -- s 400 kHz mode 0.6 -- s Output Valid from Clock 100 kHz mode -- 3500 ns 400 kHz mode -- -- ns TSU:STO Stop Condition Setup Time 109 Units 100 kHz mode TSU:DAT Data Input Setup Time 92 Max SDAx and SCLx Rise Time THD:DAT Data Input Hold Time 107 Min Bus Free Time Bus Capacitive Loading 100 kHz mode 4.7 -- s 400 kHz mode 1.3 -- s -- 400 pF CB is specified to be from 10 to 400 pF After this period, the first clock pulse is generated (Note 2) (Note 1) Time the bus must be free before a new transmission can start As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCLx to avoid unintended generation of Start or Stop conditions. A Fast mode I2CTM bus device can be used in a Standard mode I2C bus system, but the requirement, TSU:DAT 250 ns, must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLx signal. If such a device does stretch the LOW period of the SCLx signal, it must output the next data bit to the SDAx line, TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCLx line is released. DS39762F-page 458 2011 Microchip Technology Inc. PIC18F97J60 FAMILY FIGURE 28-17: MASTER SSP I2CTM BUS START/STOP BITS TIMING WAVEFORMS SCLx 93 91 90 92 SDAx Stop Condition Start Condition Note: Refer to Figure 28-3 for load conditions. TABLE 28-22: MASTER SSP I2CTM BUS START/STOP BITS REQUIREMENTS Param. Symbol No. 90 TSU:STA Characteristic Start Condition 100 kHz mode Setup Time 91 THD:STA Start Condition Hold Time 92 TSU:STO Stop Condition Setup Time 93 THD:STO Stop Condition Hold Time Note 1: Min Max Units 2(TOSC)(BRG + 1) -- ns Only relevant for Repeated Start condition ns After this period, the first clock pulse is generated 400 kHz mode 2(TOSC)(BRG + 1) -- 1 MHz mode(1) 2(TOSC)(BRG + 1) -- 100 kHz mode 2(TOSC)(BRG + 1) -- 400 kHz mode 2(TOSC)(BRG + 1) -- 1 MHz mode(1) 2(TOSC)(BRG + 1) -- 100 kHz mode 2(TOSC)(BRG + 1) -- 400 kHz mode 2(TOSC)(BRG + 1) -- 1 MHz mode(1) 2(TOSC)(BRG + 1) -- 100 kHz mode 2(TOSC)(BRG + 1) -- 400 kHz mode 2(TOSC)(BRG + 1) -- 1 MHz mode(1) 2(TOSC)(BRG + 1) -- Conditions ns ns Maximum pin capacitance = 10 pF for all I2CTM pins. FIGURE 28-18: MASTER SSP I2CTM BUS DATA TIMING 103 102 100 101 SCLx 90 106 91 107 92 SDAx In 109 109 110 SDAx Out Note: Refer to Figure 28-3 for load conditions. 2011 Microchip Technology Inc. DS39762F-page 459 PIC18F97J60 FAMILY TABLE 28-23: MASTER SSP I2CTM BUS DATA REQUIREMENTS Param. Symbol No. 100 101 THIGH TLOW Characteristic Min Max Units Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) -- ms 400 kHz mode 2(TOSC)(BRG + 1) -- ms 1 MHz mode(1) 2(TOSC)(BRG + 1) -- ms Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) -- ms 400 kHz mode 2(TOSC)(BRG + 1) -- ms (1) 2(TOSC)(BRG + 1) -- ms -- 1000 ns 20 + 0.1 CB 300 ns -- 300 ns 1 MHz mode 102 TR SDAx and SCLx 100 kHz mode Rise Time 400 kHz mode 1 MHz mode(1) 103 90 91 106 107 92 109 110 D102 TF TSU:STA SDAx and SCLx 100 kHz mode Fall Time 400 kHz mode Start Condition Setup Time THD:STA Start Condition Hold Time THD:DAT Data Input Hold Time TSU:DAT Data Input Setup Time TSU:STO Stop Condition Setup Time TAA TBUF CB Output Valid from Clock Bus Free Time -- 300 ns 20 + 0.1 CB 300 ns 1 MHz mode(1) -- 100 ns 100 kHz mode 2(TOSC)(BRG + 1) -- ms 400 kHz mode 2(TOSC)(BRG + 1) -- ms 1 MHz mode(1) 2(TOSC)(BRG + 1) -- ms 100 kHz mode 2(TOSC)(BRG + 1) -- ms 400 kHz mode 2(TOSC)(BRG + 1) -- ms 1 MHz mode(1) 2(TOSC)(BRG + 1) -- ms 100 kHz mode 0 -- ns 400 kHz mode 0 0.9 ms 1 MHz mode(1) TBD -- ns 100 kHz mode 250 -- ns 400 kHz mode 100 -- ns 1 MHz mode(1) TBD -- ns 100 kHz mode 2(TOSC)(BRG + 1) -- ms 400 kHz mode 2(TOSC)(BRG + 1) -- ms 1 MHz mode(1) 2(TOSC)(BRG + 1) -- ms 100 kHz mode -- 3500 ns 400 kHz mode -- 1000 ns (1) 1 MHz mode -- -- ns 100 kHz mode 4.7 -- ms 400 kHz mode 1.3 -- ms 1 MHz mode(1) TBD -- ms -- 400 pF Bus Capacitive Loading Conditions CB is specified to be from 10 to 400 pF CB is specified to be from 10 to 400 pF Only relevant for Repeated Start condition After this period, the first clock pulse is generated (Note 2) Time the bus must be free before a new transmission can start Legend: TBD = To Be Determined Note 1: Maximum pin capacitance = 10 pF for all I2CTM pins. 2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but Parameter #107 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLx signal. If such a device does stretch the LOW period of the SCLx signal, it must output the next data bit to the SDAx line, Parameter #102 + Parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode), before the SCLx line is released. DS39762F-page 460 2011 Microchip Technology Inc. PIC18F97J60 FAMILY FIGURE 28-19: EUSARTx SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING TXx/CKx pin 121 121 RXx/DTx pin 120 Note: 122 Refer to Figure 28-3 for load conditions. TABLE 28-24: EUSARTx SYNCHRONOUS TRANSMISSION REQUIREMENTS Param No. Symbol Characteristic Min Max Units 120 TCKH2DTV SYNC XMIT (MASTER and SLAVE) Clock High to Data Out Valid -- 40 ns 121 TCKRF Clock Out Rise Time and Fall Time (Master mode) -- 20 ns 122 TDTRF Data Out Rise Time and Fall Time -- 20 ns FIGURE 28-20: Conditions EUSARTx SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING TXx/CKx pin 125 RXx/DTx pin 126 Note: Refer to Figure 28-3 for load conditions. TABLE 28-25: EUSARTx SYNCHRONOUS RECEIVE REQUIREMENTS Param. No. Symbol Characteristic 125 TDTV2CKL SYNC RCV (MASTER and SLAVE) Data Hold before CKx (DTx hold time) 126 TCKL2DTL Data Hold after CKx (DTx hold time) 2011 Microchip Technology Inc. Min Max Units 10 -- ns 15 -- ns Conditions DS39762F-page 461 PIC18F97J60 FAMILY TABLE 28-26: A/D CONVERTER CHARACTERISTICS: PIC18F97J60 FAMILY (INDUSTRIAL) Param Symbol No. Characteristic Min Typ Max Units -- -- 10 bit Conditions VREF 2.0V A01 NR Resolution A03 EIL Integral Linearity Error -- -- <1 LSb VREF 2.0V A04 EDL Differential Linearity Error -- -- <1 LSb VREF 2.0V A06 EOFF Offset Error -- -- <3 LSb VREF 2.0V A07 EGN Gain Error -- -- <3 LSb VREF 2.0V A10 -- Monotonicity A20 VREF Reference Voltage Range (VREFH - VREFL) -- VSS VAIN VREF 1.8 3 -- -- -- -- V V VDD 3.0V VDD 3.0V -- -- AVDD + 0.5 V Guaranteed(1) VREFSUM Reference Voltage Sum (VREFH + VREFL) A21 VREFH Reference Voltage High VREFL -- AVDD V A22 VREFL Reference Voltage Low AVSS -- VREFH V A25 VAIN Analog Input Voltage VREFL -- VREFH V A30 ZAIN Recommended Impedance of Analog Voltage Source -- -- 2.5 k A50 IREF VREF Input Current(2) -- -- -- -- 5 1000 A A Note 1: 2: During VAIN acquisition. During A/D conversion cycle. The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. VREFH current is from RA3/AN3/VREF+ pin or AVDD, whichever is selected as the VREFH source. VREFL current is from RA2/AN2/VREF- pin or AVSS, whichever is selected as the VREFL source. FIGURE 28-21: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) 131 Q4 A/D CLK(1) 130 132 9 A/D DATA 8 7 ... ... 2 OLD_DATA ADRES 1 0 NEW_DATA TCY ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. DS39762F-page 462 2011 Microchip Technology Inc. PIC18F97J60 FAMILY TABLE 28-27: A/D CONVERSION REQUIREMENTS Param Symbol No. Characteristic Min Max Units 0.7 25.0(1) s TOSC based, VREF 2.0V A/D RC mode 130 TAD A/D Clock Period TBD 1 s 131 TCNV Conversion Time (not including acquisition time) (Note 2) 11 12 TAD s 132 TACQ Acquisition Time (Note 3) 1.4 -- 135 TSWC Switching Time from Convert Sample -- (Note 4) TBD TDIS Discharge Time 0.2 -- Legend: Note 1: 2: 3: 4: 28.5 Conditions -40C to +85C s TBD = To Be Determined The time of the A/D clock period is dependent on the device frequency and the TAD clock divider. ADRES registers may be read on the following TCY cycle. The time for the holding capacitor to acquire the "New" input voltage when the voltage changes full scale after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50. On the following cycle of the device clock. Ethernet Specifications and Requirements TABLE 28-28: REQUIREMENTS FOR ETHERNET TRANSCEIVER EXTERNAL MAGNETICS Parameter Min Norm Max Units -- 1:1 -- -- TX Turns Ratio -- 1:1 -- -- Insertion Loss -- -- -1.1 dB RX Turns Ratio H Primary Inductance 350 -- -- Transformer Isolation 1.5 -- -- Differential to Common-Mode Rejection 40 -- -- dB Return Loss -16 -- -- dB 2011 Microchip Technology Inc. Conditions Transformer Center Tap = 3.3V 8 mA bias kVrms Required to meet IEEE 802.3TM requirements 0.1 to 10 MHz DS39762F-page 463 PIC18F97J60 FAMILY NOTES: DS39762F-page 464 2011 Microchip Technology Inc. PIC18F97J60 FAMILY 29.0 PACKAGING INFORMATION 29.1 Package Marking Information Example 64-Lead TQFP XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 18F67J60I/PT e3 1110017 Example 80-Lead TQFP XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN 100-Lead TQFP (12x12x1 mm) XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN 100-Lead TQFP (14x14x1 mm) XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Legend: XX...X Y YY WW NNN e3 * Note: PIC18F87J60I/PT e3 1110017 Example PIC18F97J60I/PT e3 1110017 Example PIC18F97J60I/PF e3 1110017 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2011 Microchip Technology Inc. DS39762F-page 465 PIC18F97J60 FAMILY 29.2 Package Details The following sections give the technical details of the packages. ' ( !" #$ % & 3& '!&" & 4 && 255***' '5 # * !( 4 ! ! & 4 % & & # & D D1 E e E1 N b 123 NOTE 1 NOTE 2 A c A2 A1 L L1 6&! ' !7'&! 8"') %7 7 #& 9 < & #! 8 89 : ; /1+ = = / / / = / 3&7 & 7 / ; / 3& & 7 # # 4 4 !! & #%% ' 77.. 8 .3 3& 9 ?#& . > 1+ /> 9 7 & 1+ # # 4 ?#& . 1+ # # 4 7 & 1+ > 7 #4 !! = 7 #?#& ) # %& > > > # %& 1&&' > > > ( !" # $% &" ' ()"&'"!&) & #*&& & # + '% ! & ! & ,!- ' ' !! #.#&"# '#% ! &"!!#% ! &"!!! & $ #/'' !# ' ! #& .0/ 1+2 1 !' ! & $ & " !**&"&& ! .32 % ' !("!" *&"&& (%%' & " ! ! * + @/1 DS39762F-page 466 2011 Microchip Technology Inc. PIC18F97J60 FAMILY ' ( !" #$ % & 3& '!&" & 4 && 255***' '5 2011 Microchip Technology Inc. # * !( 4 ! ! & 4 % & & # & DS39762F-page 467 PIC18F97J60 FAMILY ) ' ( ## !" #$ % & 3& '!&" & 4 && 255***' '5 # * !( 4 ! ! & 4 % & & # & D D1 E e E1 N b NOTE 1 12 3 NOTE 2 c L A A2 A1 L1 6&! ' !7'&! 8"') %7 7 #& 9 < & #! 8 89 : @ /1+ = = / / / = / 3&7 & 7 / ; / 3& & 7 # # 4 4 !! & #%% ' 77.. 8 .3 3& 9 ?#& . > 1+ /> 9 7 & 1+ # # 4 ?#& . 1+ # # 4 7 & 1+ > 7 #4 !! = 7 #?#& ) # %& > > > # %& 1&&' > > > ( !" # $% &" ' ()"&'"!&) & #*&& & # + '% ! & ! & ,!- ' ' !! #.#&"# '#% ! &"!!#% ! &"!!! & $ ' ! #& .0/ 1+2 1 !' ! & $ & " !**&"&& ! .32 % ' !("!" *&"&& (%%' & " ! ! #/'' !# * + 1 DS39762F-page 468 2011 Microchip Technology Inc. PIC18F97J60 FAMILY ) ' ( ## !" #$ % & 3& '!&" & 4 && 255***' '5 2011 Microchip Technology Inc. # * !( 4 ! ! & 4 % & & # & DS39762F-page 469 PIC18F97J60 FAMILY ' ( ## !" #$ % & 3& '!&" & 4 && 255***' '5 # * !( 4 ! ! & 4 % & & # & D D1 e E E1 N b NOTE 1 1 23 NOTE 2 c A L A1 6&! ' !7'&! 8"') %7 7 #& 9 < & #! 77.. 8 8 89 : 1+ = = / / / = / 3&7 & 7 / ; / 3& & 7 # # 4 4 !! & #%% ' A2 L1 .3 3& I 9 ?#& . > 1+ /> 9 7 & 1+ # # 4 ?#& . 1+ # # 4 7 & 1+ > 7 #4 !! = 7 #?#& ) @ # %& D > > > # %& 1&&' E > > > ( !" # $% &" ' ()"&'"!&) & #*&& & # + '% ! & ! & ,!- ' ' !! #.#&"# '#% ! &"!!#% ! &"!!! & $ ' ! #& .0/ 1+2 1 !' ! & $ & " !**&"&& ! .32 % ' !("!" *&"&& (%%' & " ! ! #/'' !# * + 1 DS39762F-page 470 2011 Microchip Technology Inc. PIC18F97J60 FAMILY ' ( ## !" #$ % & 3& '!&" & 4 && 255***' '5 2011 Microchip Technology Inc. # * !( 4 ! ! & 4 % & & # & DS39762F-page 471 PIC18F97J60 FAMILY ' ( !" #$ % & 3& '!&" & 4 && 255***' '5 # * !( 4 ! ! & 4 % & & # & D D1 e E1 E b N NOTE 1 1 23 A NOTE 2 c A2 A1 L L1 6&! ' !7'&! 8"') %7 7 #& 9 < & #! 8 89 : /1+ = = / / / = / 3&7 & 7 / ; / 3& & 7 # # 4 4 !! & #%% ' 77.. 8 .3 3& I 9 ?#& . > ;1+ /> 9 7 & ;1+ # # 4 ?#& . 1+ # # 4 7 & 1+ > 7 #4 !! = 7 #?#& ) # %& D > > > # %& 1&&' E > > > ( !" # $% &" ' ()"&'"!&) & #*&& & # + '% ! & ! & ,!- ' ' !! #.#&"# '#% ! &"!!#% ! &"!!! & $ ' ! #& .0/ 1+2 1 !' ! & $ & " !**&"&& ! .32 % ' !("!" *&"&& (%%' & " ! ! #/'' !# * + 1 DS39762F-page 472 2011 Microchip Technology Inc. PIC18F97J60 FAMILY ' ( !" #$ % & 3& '!&" & 4 && 255***' '5 2011 Microchip Technology Inc. # * !( 4 ! ! & 4 % & & # & DS39762F-page 473 PIC18F97J60 FAMILY NOTES: DS39762F-page 474 2011 Microchip Technology Inc. PIC18F97J60 FAMILY APPENDIX A: REVISION HISTORY Revision A (March 2006) Original data sheet for the PIC18F97J60 family of devices. Revision B (October 2006) First revision. Includes preliminary electrical specifications; revised and updated material on the Ethernet module; updated material on Reset integration; and updates to the device memory map. Revision C (June 2007) Corrected Table 10.2: Input Voltage Levels; added content on Ethernet module's reading and writing to the buffer; added new, 100-lead PT 12x12x1 mm TQFP package to "Package Marking Information" and "Package Details" sections; updated other package details drawings; changed Product Identification System examples. Revision D (January 2008) Added one line to "Ethernet Features" description. Added land pattern schematics for each package. Revision E (October 2009) Updated to remove Preliminary status. Revision F (April 2011) Added Brown-out Reset (BOR) specs, added Ethernet RX Auto-Polarity circuit section, added EMI filter section, added Section 2.0 "Guidelines for Getting Started with PIC18FJ Microcontrollers", changed the opcode encoding of the PUSHL instruction to 1110 1010 kkk kkkk and changed the 2 TOSC Maximum Device Frequency in Table 22-1 from 2.68 MHz to the correct value of 2.86 MHz. Updated comparator input offset voltage maximum to the correct value of 25 mV. 2011 Microchip Technology Inc. DS39762F-page 475 PIC18F97J60 FAMILY APPENDIX B: DEVICE DIFFERENCES The differences between the devices listed in this data sheet are shown in Table B-1. Interrupt Sources I/O Ports (Pins) Enhanced USART Modules PIC18F86J65 PIC18F87J60 PIC18F96J60 PIC18F96J65 PIC18F97J60 Program Memory (Instructions) PIC18F86J60 Program Memory (Bytes) PIC18F67J60 Features PIC18F66J65 DEVICE DIFFERENCES BETWEEN PIC18F97J60 FAMILY MEMBERS PIC18F66J60 TABLE B-1: 64K 96K 128K 64K 96K 128K 64K 96K 128K 32764 49148 65532 32764 49148 65532 32764 49148 65532 26 Ports A, B, C, D, E, F, G (39) 1 MSSP Modules Parallel Slave Port Communications (PSP) External Memory Bus 10-Bit Analog-to-Digital Module Packages DS39762F-page 476 27 29 Ports A, B, C, D, E, F, G, H, J Ports A, B, C, D, E, F, G, H, J (55) (70) 2 1 2 No Yes No Yes 11 input channels 15 input channels 16 input channels 64-pin TQFP 80-pin TQFP 100-pin TQFP 2011 Microchip Technology Inc. PIC18F97J60 FAMILY INDEX A A/D ................................................................................... 339 Acquisition Requirements ........................................ 344 ADCAL Bit ................................................................ 347 ADCON0 Register .................................................... 339 ADCON1 Register .................................................... 339 ADCON2 Register .................................................... 339 ADRESH Register ............................................ 339, 342 ADRESL Register .................................................... 339 Analog Port Pins, Configuring .................................. 345 Associated Registers ............................................... 347 Automatic Acquisition Time, Selecting and Configuring ...................................................... 345 Configuring the Module ............................................ 343 Conversion Clock (TAD) ........................................... 345 Conversion Requirements ....................................... 463 Conversion Status (GO/DONE Bit) .......................... 342 Conversions ............................................................. 346 Converter Calibration ............................................... 347 Converter Characteristics ........................................ 462 Converter Interrupt, Configuring .............................. 343 Operation in Power-Managed Modes ...................... 347 Special Event Trigger (ECCP) ......................... 202, 346 Use of the ECCP2 Trigger ....................................... 346 Absolute Maximum Ratings ............................................. 429 AC (Timing) Characteristics ............................................. 443 Load Conditions for Device Timing Specifications ................................................... 444 Parameter Symbology ............................................. 443 Temperature and Voltage Specifications ................. 444 Timing Conditions .................................................... 444 ACKSTAT ........................................................................ 304 ACKSTAT Status Flag ..................................................... 304 ADCAL Bit ........................................................................ 347 ADCON0 Register ............................................................ 339 GO/DONE Bit ........................................................... 342 ADCON1 Register ............................................................ 339 ADCON2 Register ............................................................ 339 ADDFSR .......................................................................... 418 ADDLW ............................................................................ 381 ADDULNK ........................................................................ 418 ADDWF ............................................................................ 381 ADDWFC ......................................................................... 382 ADRESH Register ............................................................ 339 ADRESL Register .................................................... 339, 342 Analog-to-Digital Converter. See A/D. ANDLW ............................................................................ 382 ANDWF ............................................................................ 383 Assembler MPASM Assembler .................................................. 426 B Baud Rate Generator ....................................................... 300 BC .................................................................................... 383 BCF .................................................................................. 384 BF .................................................................................... 304 BF Status Flag ................................................................. 304 Block Diagrams 16-Bit Byte Select Mode .......................................... 121 16-Bit Byte Write Mode ............................................ 119 16-Bit Word Write Mode ........................................... 120 8-Bit Multiplexed Mode ............................................ 123 A/D ........................................................................... 342 2011 Microchip Technology Inc. Analog Input Model .................................................. 343 Baud Rate Generator .............................................. 300 Capture Mode Operation ......................................... 191 Comparator Analog Input Model .............................. 353 Comparator I/O Operating Modes ........................... 350 Comparator Output .................................................. 352 Comparator Voltage Reference ............................... 356 Comparator Voltage Reference Output Buffer Example ................................................ 357 Compare Mode Operation ....................................... 192 Connections for On-Chip Voltage Regulator ........... 369 Crystal Oscillator Operation (HS, HSPLL) ................. 50 Device Clock .............................................................. 49 Enhanced PWM ....................................................... 203 Ethernet Interrupt Logic ........................................... 239 Ethernet Module ...................................................... 217 EUSARTx Receive .................................................. 329 EUSARTx Transmit ................................................. 326 External Clock Input Operation (EC) ......................... 50 External Clock Input Operation (HS) ......................... 50 External Power-on Reset Circuit (Slow VDD Power-up) .................................................. 65 Fail-Safe Clock Monitor ........................................... 371 Full-Bridge Application Example .............................. 209 Generic I/O Port Operation ...................................... 145 Half-Bridge Output Mode Applications .................... 207 Interrupt Logic .......................................................... 130 MSSP (I2C Master Mode) ........................................ 298 MSSP (I2C Mode) .................................................... 279 MSSP (SPI Mode) ................................................... 269 On-Chip Reset Circuit ................................................ 63 PIC18F66J60/66J65/67J60 ....................................... 15 PIC18F86J60/86J65/87J60 ....................................... 16 PIC18F96J60/96J65/97J60 ....................................... 17 PORTD and PORTE (Parallel Slave Port) ............... 168 PWM Operation (Simplified) .................................... 194 Reads from Flash Program Memory ....................... 109 Required External Components for Ethernet ........... 219 RX Polarity Correction Circuit (TX not Shown) ........ 221 Single Comparator ................................................... 351 Table Read Operation ............................................. 105 Table Write Operation ............................................. 106 Table Writes to Flash Program Memory .................. 111 Timer0 in 16-Bit Mode ............................................. 172 Timer0 in 8-Bit Mode ............................................... 172 Timer1 ..................................................................... 176 Timer1 (16-Bit Read/Write Mode) ............................ 176 Timer2 ..................................................................... 181 Timer3 ..................................................................... 184 Timer3 (16-Bit Read/Write Mode) ............................ 184 Timer4 ..................................................................... 188 Watchdog Timer ...................................................... 367 BN .................................................................................... 384 BNC ................................................................................. 385 BNN ................................................................................. 385 BNOV .............................................................................. 386 BNZ ................................................................................. 386 BOR. See Brown-out Reset. BOV ................................................................................. 389 BRA ................................................................................. 387 BRG. See Baud Rate Generator. Brown-out Reset (BOR) ..................................................... 65 and On-Chip Voltage Regulator .............................. 369 Detecting ................................................................... 65 DS39762F-page 477 PIC18F97J60 FAMILY BSF .................................................................................. 387 BTFSC ............................................................................. 388 BTFSS .............................................................................. 388 BTG .................................................................................. 389 BZ ..................................................................................... 390 C C Compilers MPLAB C18 ............................................................. 426 CALL ................................................................................ 390 CALLW ............................................................................. 419 Capture (CCP Module) ..................................................... 191 Associated Registers ............................................... 193 CCPRxH:CCPRxL Registers ................................... 191 CCPx Pin Configuration ........................................... 191 Prescaler .................................................................. 191 Software Interrupt .................................................... 191 Timer1/Timer3 Mode Selection ................................ 191 Capture (ECCP Module) .................................................. 202 Capture/Compare/PWM (CCP) ........................................ 189 Capture Mode. See Capture. CCPRxH Register .................................................... 190 CCPRxL Register ..................................................... 190 CCPx/ECCPx Interconnect Configurations .............. 190 CCPx/ECCPx Mode and Timer Resources ............. 190 Compare Mode. See Compare. Module Configuration ............................................... 190 Clock Sources Default System Clock on Reset ................................. 54 Effects of Power-Managed Modes ............................. 54 Oscillator Switching .................................................... 52 CLRF ................................................................................ 391 CLRWDT .......................................................................... 391 Code Examples 16 x 16 Signed Multiply Routine .............................. 128 16 x 16 Unsigned Multiply Routine .......................... 128 8 x 8 Signed Multiply Routine .................................. 127 8 x 8 Unsigned Multiply Routine .............................. 127 Changing Between Capture Prescalers ................... 191 Computed GOTO Using an Offset Value ................... 83 Erasing a Flash Program Memory Row ................... 110 Fast Register Stack .................................................... 83 How to Clear RAM (Bank 1) Using Indirect Addressing ......................................................... 98 Implementing a Real-Time Clock Using a Timer1 Interrupt Service .................................. 179 Initializing PORTA .................................................... 146 Initializing PORTB .................................................... 148 Initializing PORTC .................................................... 151 Initializing PORTD .................................................... 154 Initializing PORTE .................................................... 157 Initializing PORTF .................................................... 160 Initializing PORTG ................................................... 162 Initializing PORTH .................................................... 164 Initializing PORTJ .................................................... 166 Loading the SSP1BUF (SSP1SR) Register ............. 272 Reading a Flash Program Memory Word ................ 109 Saving STATUS, WREG and BSR Registers in RAM ............................................. 144 Writing to Flash Program Memory ........................... 112 Code Protection ............................................................... 359 COMF ............................................................................... 392 DS39762F-page 478 Comparator ...................................................................... 349 Analog Input Connection Considerations ................ 353 Associated Registers ............................................... 353 Configuration ........................................................... 350 Effects of a Reset .................................................... 352 Interrupts ................................................................. 352 Operation ................................................................. 351 Operation During Sleep ........................................... 352 Outputs .................................................................... 351 Reference ................................................................ 351 External Signal ................................................ 351 Internal Signal .................................................. 351 Response Time ........................................................ 351 Comparator Specifications ............................................... 442 Comparator Voltage Reference ....................................... 355 Accuracy and Error .................................................. 356 Associated Registers ............................................... 357 Configuring .............................................................. 355 Connection Considerations ...................................... 356 Effects of a Reset .................................................... 356 Operation During Sleep ........................................... 356 Compare (CCP Module) .................................................. 192 Associated Registers ............................................... 193 CCPRx Register ...................................................... 192 CCPx Pin Configuration ........................................... 192 Software Interrupt Mode .......................................... 192 Timer1/Timer3 Mode Selection ................................ 192 Compare (ECCP Module) ................................................ 202 Special Event Trigger ...................................... 202, 346 Computed GOTO ............................................................... 83 Configuration Bits ............................................................ 359 Configuration Mismatch (CM) Reset .................................. 65 Configuration Register Protection .................................... 373 Core Features Easy Migration ........................................................... 11 Expanded Memory ..................................................... 11 Extended Instruction Set ........................................... 11 External Memory Bus ................................................ 11 Oscillator Options ...................................................... 11 CPFSEQ .......................................................................... 392 CPFSGT .......................................................................... 393 CPFSLT ........................................................................... 393 Crystal Oscillator/Ceramic Resonators (HS Modes) .......... 50 Customer Change Notification Service ............................ 488 Customer Notification Service ......................................... 488 Customer Support ............................................................ 488 D Data Addressing Modes .................................................... 98 Comparing Addressing Modes with the Extended Instruction Set Enabled ................... 102 Direct ......................................................................... 98 Indexed Literal Offset .............................................. 101 Affected Instructions ........................................ 101 BSR ................................................................. 103 Mapping Access Bank ..................................... 103 Indirect ....................................................................... 98 Inherent and Literal .................................................... 98 Data Memory ..................................................................... 86 Access Bank .............................................................. 88 Bank Select Register (BSR) ...................................... 86 Ethernet SFRs ........................................................... 90 Extended Instruction Set ......................................... 100 General Purpose Register File .................................. 88 2011 Microchip Technology Inc. PIC18F97J60 FAMILY Memory Maps Ethernet Special Function Registers ................. 90 PIC18F97J60 Family ......................................... 87 Special Function Registers ................................ 89 Special Function Registers ........................................ 89 DAW ................................................................................. 394 DC Characteristics ........................................................... 439 Power-Down and Supply Current ............................ 432 Supply Voltage ......................................................... 431 DCFSNZ .......................................................................... 395 DECF ............................................................................... 394 DECFSZ ........................................................................... 395 Default System Clock ......................................................... 54 Development Support ...................................................... 425 Device Differences ........................................................... 476 Device Overview ................................................................ 11 Details on Individual Family Members ....................... 12 Features (100-Pin Devices) ....................................... 14 Features (64-Pin Devices) ......................................... 13 Features (80-Pin Devices) ......................................... 13 Direct Addressing ............................................................... 99 E ECCP2 Pin Assignment ........................................................ 190 Effect on Standard PIC Instructions ................................. 422 Electrical Characteristics .................................................. 429 Requirements for Ethernet Transceiver External Magnetics .......................................... 463 Enhanced Capture/Compare/PWM (ECCP) .................... 197 Capture and Compare Modes .................................. 202 Capture Mode. See Capture (ECCP Module). ECCP1/ECCP3 Outputs and Program Memory Mode .................................................. 199 ECCP2 Outputs and Program Memory Modes ........ 199 Enhanced PWM Mode ............................................. 203 Outputs and Configuration ....................................... 199 Pin Configurations for ECCP1 ................................. 200 Pin Configurations for ECCP2 ................................. 200 Pin Configurations for ECCP3 ................................. 201 PWM Mode. See PWM (ECCP Module). Standard PWM Mode ............................................... 202 Timer Resources ...................................................... 199 Use of CCP4/CCP5 with ECCP1/ECCP3 ................ 199 Enhanced Capture/Compare/PWM (ECCPx) Associated Registers ............................................... 215 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART). See EUSART. ENVREG pin .................................................................... 369 Equations 16 x 16 Signed Multiplication Algorithm ................... 128 16 x 16 Unsigned Multiplication Algorithm ............... 128 A/D Acquisition Time ................................................ 344 A/D Minimum Charging Time ................................... 344 Calculating Baud Rate Error .................................... 320 Calculating the A/D Minimum Required Acquisition Time .............................................. 344 Random Access Address Calculation ...................... 253 Receive Buffer Free Space Calculation ................... 254 Errata ................................................................................... 9 2011 Microchip Technology Inc. Ethernet Module .............................................................. 217 Associated Registers, Direct Memory Access Controller ......................................................... 266 Associated Registers, Flow Control ......................... 258 Associated Registers, Reception ............................. 255 Associated Registers, Transmission ....................... 255 Automatic RX Polarity Detection, Correction ........... 220 Buffer and Buffer Pointers ....................................... 223 Buffer Arbiter ................................................... 226 DMA Access .................................................... 226 Receive Buffer ................................................. 225 Transmit Buffer ................................................ 226 Buffer and Register Spaces ..................................... 222 Buffer Organization .................................................. 224 CRC ......................................................................... 248 Direct Memory Access (DMA) Controller ................. 265 Direct Memory Access Controller Checksum Calculations ................................... 266 Copying Memory ............................................. 265 Disabling .................................................................. 246 Duplex Mode Configuration and Negotiation ........... 256 EMI Emissions Considerations ................................ 220 Ethernet and Microcontroller Memory Relationship ..................................................... 222 Ethernet Control Registers ...................................... 227 Flow Control ............................................................ 257 Initializing ................................................................. 245 Interrupts ................................................................. 239 Interrupts and Wake-on-LAN ................................... 244 LED Configuration ................................................... 218 MAC and MII Registers ........................................... 229 MAC Initialization Settings ....................................... 245 Magnetics, Termination and Other External Components .................................................... 219 Memory Maps .......................................................... 234 Oscillator Requirements .......................................... 218 Packet Format ......................................................... 247 Per-Packet Control Bytes ........................................ 249 PHSTAT Registers .................................................. 232 PHY Initialization Settings ....................................... 246 PHY Registers ......................................................... 232 PHY Start-up Timer ................................................. 218 Reading from a PHY Register ................................. 233 Receive Filters ......................................................... 259 Broadcast ........................................................ 259 Hash Table ...................................................... 259 Magic Packet ................................................... 259 Multicast .......................................................... 259 Pattern Match .................................................. 259 Unicast ............................................................ 259 Resets ..................................................................... 267 Microcontroller Reset ....................................... 267 Receive Only ................................................... 267 Transmit Only .................................................. 267 Signal and Power Interfaces .................................... 218 Special Function Registers (SFRs) ......................... 227 DS39762F-page 479 PIC18F97J60 FAMILY Transmitting and Receiving Data ............................. 247 Packet Field Definitions ........................... 247-248 Reading Received Packets .............................. 253 Receive Buffer Space ...................................... 254 Receive Packet Layout .................................... 252 Receive Status Vectors .................................... 253 Receiving Packets ........................................... 252 Transmit Packet Layout ................................... 250 Transmit Status Vectors ................................... 251 Transmitting Packets ....................................... 249 Ethernet Operation, Microcontroller Clock ......................... 51 EUSARTx Asynchronous Mode ................................................ 325 Associated Registers, Receive ........................ 329 Associated Registers, Transmit ....................... 327 Auto-Wake-up on Sync Break Character ......... 330 Break Character Sequence .............................. 332 Receiving ................................................. 332 Receiver ........................................................... 328 Setting Up 9-Bit Mode with Address Detect ..... 328 Transmitter ....................................................... 325 Baud Rate Generator Operation in Power-Managed Modes .............. 319 Baud Rate Generator (BRG) .................................... 319 Associated Registers ....................................... 320 Auto-Baud Rate Detect .................................... 323 Baud Rates, Asynchronous Modes .................. 321 High Baud Rate Select (BRGH Bit) .................. 319 Sampling .......................................................... 319 Synchronous Master Mode ...................................... 333 Associated Registers, Receive ........................ 336 Associated Registers, Transmit ....................... 334 Reception ......................................................... 335 Transmission .................................................... 333 Synchronous Slave Mode ........................................ 337 Associated Registers, Receive ........................ 338 Associated Registers, Transmit ....................... 337 Reception ......................................................... 338 Transmission .................................................... 337 Extended Instruction Set ADDFSR .................................................................. 418 ADDULNK ................................................................ 418 CALLW ..................................................................... 419 MOVSF .................................................................... 419 MOVSS .................................................................... 420 PUSHL ..................................................................... 420 SUBFSR .................................................................. 421 SUBULNK ................................................................ 421 External Clock Input (EC Modes) ....................................... 50 External Memory Bus ....................................................... 115 16-Bit Byte Select Mode .......................................... 121 16-Bit Byte Write Mode ............................................ 119 16-Bit Data Width Modes ......................................... 118 16-Bit Mode Timing .................................................. 122 16-Bit Word Write Mode ........................................... 120 21-Bit Addressing ..................................................... 117 8-Bit Data Width Mode ............................................. 123 8-Bit Mode Timing .................................................... 124 Address and Data Line Usage (table) ...................... 117 Address and Data Width .......................................... 117 Address Shifting ....................................................... 117 Control ..................................................................... 116 I/O Port Functions .................................................... 115 Operation in Power-Managed Modes ...................... 125 Program Memory Modes ......................................... 118 DS39762F-page 480 Extended Microcontroller ................................. 118 Microcontroller ................................................. 118 Wait States .............................................................. 118 Weak Pull-ups on Port Pins ..................................... 118 F Fail-Safe Clock Monitor ........................................... 359, 371 and the Watchdog Timer ......................................... 371 Exiting Operation ..................................................... 371 Interrupts in Power-Managed Modes ....................... 372 POR or Wake-up From Sleep .................................. 372 Fast Register Stack ........................................................... 83 Firmware Instructions ...................................................... 375 Flash Configuration Words ........................................ 78, 359 Flash Program Memory ................................................... 105 Associated Registers ............................................... 113 Control Registers ..................................................... 106 EECON1 and EECON2 ................................... 106 TABLAT (Table Latch) ..................................... 108 TBLPTR (Table Pointer) .................................. 108 Erase Sequence ...................................................... 110 Erasing .................................................................... 110 Operation During Code-Protect ............................... 113 Reading ................................................................... 109 Table Pointer Boundaries Based on Operation ..................... 108 Table Pointer Boundaries ........................................ 108 Table Reads and Table Writes ................................ 105 Write Sequence ....................................................... 111 Writing ..................................................................... 111 Protection Against Spurious Writes ................. 113 Unexpected Termination ................................. 113 Write Verify ...................................................... 113 FSCM. See Fail-Safe Clock Monitor. G GOTO .............................................................................. 396 H Hardware Multiplier .......................................................... 127 Introduction .............................................................. 127 Operation ................................................................. 127 Performance Comparison ........................................ 127 I I/O Ports ........................................................................... 145 Pin Capabilities ........................................................ 145 I2C Mode (MSSP) ............................................................ 279 Acknowledge Sequence Timing .............................. 307 Associated Registers ............................................... 313 Baud Rate Generator .............................................. 300 Bus Collision During a Repeated Start Condition .................. 311 During a Start Condition .................................. 309 During a Stop Condition .................................. 312 Clock Arbitration ...................................................... 301 Clock Rate w/BRG ................................................... 300 Clock Stretching ....................................................... 293 10-Bit Slave Receive Mode (SEN = 1) ............ 293 10-Bit Slave Transmit Mode ............................ 293 7-Bit Slave Receive Mode (SEN = 1) .............. 293 7-Bit Slave Transmit Mode .............................. 293 Clock Synchronization and the CKP Bit ................... 294 Effects of a Reset .................................................... 308 General Call Address Support ................................. 297 2011 Microchip Technology Inc. PIC18F97J60 FAMILY Master Mode ............................................................ 298 Baud Rate Generator ....................................... 300 Operation ......................................................... 299 Reception ......................................................... 304 Repeated Start Condition Timing ..................... 303 Start Condition Timing ..................................... 302 Transmission ................................................... 304 Multi-Master Communication, Bus Collision and Arbitration ................................................. 308 Multi-Master Mode ................................................... 308 Operation ................................................................. 284 Read/Write Bit Information (R/W Bit) ............... 284, 286 Registers .................................................................. 279 Serial Clock (SCKx/SCLx) ....................................... 286 Slave Mode .............................................................. 284 Address Masking ............................................. 285 Addressing ....................................................... 284 Reception ......................................................... 286 Transmission ................................................... 286 Sleep Operation ....................................................... 308 Stop Condition Timing .............................................. 307 INCF ................................................................................. 396 INCFSZ ............................................................................ 397 In-Circuit Debugger .......................................................... 373 In-Circuit Serial Programming (ICSP) ...................... 359, 373 Indexed Literal Offset Addressing and Standard PIC18 Instructions ............................. 422 Indexed Literal Offset Mode ............................................. 422 Indirect Addressing ............................................................ 99 INFSNZ ............................................................................ 397 Initialization Conditions for All Registers ...................... 69-75 Instruction Cycle ................................................................ 84 Clocking Scheme ....................................................... 84 Flow/Pipelining ........................................................... 84 Instruction Set .................................................................. 375 ADDLW .................................................................... 381 ADDWF .................................................................... 381 ADDWF (Indexed Literal Offset Mode) .................... 423 ADDWFC ................................................................. 382 ANDLW .................................................................... 382 ANDWF .................................................................... 383 BC ............................................................................ 383 BCF .......................................................................... 384 BN ............................................................................ 384 BNC ......................................................................... 385 BNN ......................................................................... 385 BNOV ....................................................................... 386 BNZ .......................................................................... 386 BOV ......................................................................... 389 BRA .......................................................................... 387 BSF .......................................................................... 387 BSF (Indexed Literal Offset Mode) .......................... 423 BTFSC ..................................................................... 388 BTFSS ..................................................................... 388 BTG .......................................................................... 389 BZ ............................................................................ 390 CALL ........................................................................ 390 CLRF ........................................................................ 391 CLRWDT .................................................................. 391 COMF ...................................................................... 392 CPFSEQ .................................................................. 392 CPFSGT .................................................................. 393 CPFSLT ................................................................... 393 DAW ......................................................................... 394 DCFSNZ .................................................................. 395 2011 Microchip Technology Inc. DECF ....................................................................... 394 DECFSZ .................................................................. 395 Extended Instructions .............................................. 417 Considerations when Enabling ........................ 422 Syntax ............................................................. 417 Use with MPLAB IDE Tools ............................. 424 General Format ....................................................... 377 GOTO ...................................................................... 396 INCF ........................................................................ 396 INCFSZ .................................................................... 397 INFSNZ .................................................................... 397 IORLW ..................................................................... 398 IORWF ..................................................................... 398 LFSR ....................................................................... 399 MOVF ...................................................................... 399 MOVFF .................................................................... 400 MOVLB .................................................................... 400 MOVLW ................................................................... 401 MOVWF ................................................................... 401 MULLW .................................................................... 402 MULWF ................................................................... 402 NEGF ....................................................................... 403 NOP ......................................................................... 403 POP ......................................................................... 404 PUSH ....................................................................... 404 RCALL ..................................................................... 405 RESET ..................................................................... 405 RETFIE .................................................................... 406 RETLW .................................................................... 406 RETURN .................................................................. 407 RLCF ....................................................................... 407 RLNCF ..................................................................... 408 RRCF ....................................................................... 408 RRNCF .................................................................... 409 SETF ....................................................................... 409 SETF (Indexed Literal Offset Mode) ........................ 423 SLEEP ..................................................................... 410 Standard Instructions ............................................... 375 SUBFWB ................................................................. 410 SUBLW .................................................................... 411 SUBWF .................................................................... 411 SUBWFB ................................................................. 412 SWAPF .................................................................... 412 TBLRD ..................................................................... 413 TBLWT .................................................................... 414 TSTFSZ ................................................................... 415 XORLW ................................................................... 415 XORWF ................................................................... 416 INTCON Register RBIF Bit ................................................................... 148 INTCON Registers ........................................................... 131 Inter-Integrated Circuit. See I2C Mode. Internal Oscillator Block ..................................................... 51 Internal RC Oscillator Use with WDT .......................................................... 367 Internal Voltage Regulator Specifications ........................ 442 Internet Address .............................................................. 488 DS39762F-page 481 PIC18F97J60 FAMILY Interrupt Sources .............................................................. 359 Interrupt-on-Change (RB7:RB4) .............................. 148 INTx Pin ................................................................... 144 PORTB, Interrupt-on-Change .................................. 144 TMR0 ....................................................................... 144 TMR0 Overflow ........................................................ 173 TMR1 Overflow ........................................................ 175 TMR2 to PR2 Match (PWM) .................................... 203 TMR3 Overflow ................................................ 183, 185 TMR4 to PR4 Match ................................................ 188 TMR4 to PR4 Match (PWM) .................................... 187 Interrupts .......................................................................... 129 Context Saving ......................................................... 144 Interrupts, Flag Bits Interrupt-on-Change (RB7:RB4) Flag (RBIF Bit) ......................................................... 148 INTRC. See Internal Oscillator Block. IORLW ............................................................................. 398 IORWF ............................................................................. 398 IPR Registers ................................................................... 140 L LFSR ................................................................................ 399 M Master Clear (MCLR) ......................................................... 65 Master Synchronous Serial Port (MSSP). See MSSP. Memory Organization ......................................................... 77 Data Memory ............................................................. 86 Program Memory ....................................................... 77 Memory Programming Requirements .............................. 441 Microchip Internet Web Site ............................................. 488 MOVF ............................................................................... 399 MOVFF ............................................................................. 400 MOVLB ............................................................................. 400 MOVLW ............................................................................ 401 MOVSF ............................................................................ 419 MOVSS ............................................................................ 420 MOVWF ........................................................................... 401 MPLAB ASM30 Assembler, Linker, Librarian .................. 426 MPLAB Integrated Development Environment Software ................................................................... 425 MPLAB PM3 Device Programmer .................................... 428 MPLAB REAL ICE In-Circuit Emulator System ................ 427 MPLINK Object Linker/MPLIB Object Librarian ............... 426 MSSP ACK Pulse ........................................................ 284, 286 Control Registers (general) ...................................... 269 Module Overview ..................................................... 269 SPI Master/Slave Connection .................................. 273 SSPxBUF Register .................................................. 274 SSPxSR Register ..................................................... 274 MULLW ............................................................................ 402 MULWF ............................................................................ 402 N NEGF ............................................................................... 403 NOP ................................................................................. 403 O Opcode Field Descriptions ............................................... 376 Organizationally Unique Identifier (OUI) .......................... 248 DS39762F-page 482 Oscillator Configuration ..................................................... 49 EC .............................................................................. 49 ECPLL ....................................................................... 49 HS .............................................................................. 49 HSPLL ....................................................................... 49 Internal Oscillator Block ............................................. 51 INTRC ........................................................................ 49 Oscillator Selection .......................................................... 359 Oscillator Start-up Timer (OST) ......................................... 54 Oscillator Transitions ......................................................... 54 Oscillator, Timer1 ..................................................... 175, 185 Oscillator, Timer3 ............................................................. 183 OUI. See Organizationally Unique Identifier. P Packaging ........................................................................ 465 Details ...................................................................... 466 Marking .................................................................... 465 Parallel Slave Port (PSP) ................................................. 168 Associated Registers ............................................... 170 PORTD .................................................................... 168 Select (PSPMODE Bit) ............................................ 168 PIE Registers ................................................................... 137 Pin Functions AVDD .............................................................. 32, 42, 24 AVSS .............................................................. 42, 32, 24 ENVREG ....................................................... 24, 32, 42 MCLR ............................................................ 25, 33, 18 OSC1/CLKI .................................................... 18, 25, 33 OSC2/CLKO .................................................. 18, 25, 33 RA0/LEDA/AN0 ............................................. 18, 25, 33 RA1/LEDB/AN1 ............................................. 18, 25, 33 RA2/AN2/VREF- ............................................. 18, 25, 33 RA3/AN3/VREF+ ............................................ 18, 25, 33 RA4/T0CKI .................................................... 18, 25, 33 RA5/AN4 ........................................................ 18, 25, 33 RB0/INT0/FLT0 .............................................. 19, 26, 34 RB1/INT1 ....................................................... 19, 26, 34 RB2/INT2 ....................................................... 19, 26, 34 RB3/INT3 ............................................................. 19, 26 RB3/INT3/ECCP2/P2A .............................................. 34 RB4/KBI0 ....................................................... 19, 26, 34 RB5/KBI1 ....................................................... 19, 26, 34 RB6/KBI2/PGC .............................................. 19, 26, 34 RB7/KBI3/PGD .............................................. 19, 26, 34 RBIAS ............................................................ 24, 32, 42 RC0/T1OSO/T13CKI ..................................... 20, 27, 35 RC1/T1OSI/ECCP2/P2A ............................... 20, 27, 35 RC2/ECCP1/P1A ........................................... 20, 27, 35 RC3/SCK1/SCL1 ........................................... 20, 27, 35 RC4/SDI1/SDA1 ............................................ 20, 27, 35 RC5/SDO1 ..................................................... 20, 27, 35 RC6/TX1/CK1 ................................................ 20, 27, 35 RC7/RX1/DT1 ................................................ 20, 27, 35 RD0 ........................................................................... 28 RD0/AD0/PSP0 ......................................................... 36 RD0/P1B .................................................................... 21 RD1 ........................................................................... 28 RD1/AD1/PSP1 ......................................................... 36 RD1/ECCP3/P3A ....................................................... 21 RD2 ........................................................................... 28 RD2/AD2/PSP2 ......................................................... 36 2011 Microchip Technology Inc. PIC18F97J60 FAMILY RD2/CCP4/P3D ......................................................... 21 RD3/AD3/PSP3 .......................................................... 36 RD4/AD4/PSP4/SDO2 ............................................... 36 RD5/AD5/PSP5/SDI2/SDA2 ...................................... 36 RD6/AD6/PSP6/SCK2/SCL2 ..................................... 36 RD7/AD7/PSP7/SS2 .................................................. 36 RE0/AD8/RD/P2D ...................................................... 37 RE0/P2D .............................................................. 22, 28 RE1/AD9/WR/P2C ..................................................... 37 RE1/P2C .............................................................. 22, 28 RE2/AD10/CS/P2B .................................................... 37 RE2/P2B .............................................................. 22, 28 RE3/AD11/P3C .......................................................... 37 RE3/P3C .............................................................. 22, 28 RE4/AD12/P3B .......................................................... 37 RE4/P3B .............................................................. 22, 28 RE5/AD13/P1C .......................................................... 37 RE5/P1C .............................................................. 22, 28 RE6/AD14/P1B .......................................................... 37 RE6/P1B .................................................................... 28 RE7/AD15/ECCP2/P2A ............................................. 37 RE7/ECCP2/P2A ....................................................... 28 RF0/AN5 .................................................................... 38 RF1/AN6/C2OUT ........................................... 23, 29, 38 RF2/AN7/C1OUT ........................................... 23, 29, 38 RF3/AN8 ........................................................ 23, 29, 38 RF4/AN9 ........................................................ 23, 29, 38 RF5/AN10/CVREF .......................................... 23, 38, 29 RF6/AN11 ...................................................... 23, 29, 38 RF7/SS1 ........................................................ 23, 38, 29 RG0/ECCP3/P3A ................................................. 30, 39 RG1/TX2/CK2 ...................................................... 30, 39 RG2/RX2/DT2 ...................................................... 30, 39 RG3/CCP4/P3D ................................................... 30, 39 RG4/CCP5/P1D ............................................. 24, 30, 39 RG5 ............................................................................ 39 RG6 ............................................................................ 39 RG7 ............................................................................ 39 RH0 ............................................................................ 31 RH0/A16 .................................................................... 40 RH1 ............................................................................ 31 RH1/A17 .................................................................... 40 RH2 ............................................................................ 31 RH2/A18 .................................................................... 40 RH3 ............................................................................ 31 RH3/A19 .................................................................... 40 RH4/AN12/P3C .................................................... 31, 40 RH5/AN13/P3B .................................................... 31, 40 RH6/AN14/P1C .................................................... 31, 40 RH7/AN15/P1B .................................................... 31, 40 RJ0/ALE ..................................................................... 41 RJ1/OE ...................................................................... 41 RJ2/WRL .................................................................... 41 RJ3/WRH ................................................................... 41 RJ4 ............................................................................. 32 RJ4/BA0 ..................................................................... 41 RJ5 ............................................................................. 32 RJ5/CE ....................................................................... 41 RJ6/LB ....................................................................... 41 RJ7/UB ....................................................................... 41 TPIN- .............................................................. 24, 32, 42 TPIN+ ............................................................. 24, 32, 42 TPOUT- .......................................................... 24, 32, 42 TPOUT+ ......................................................... 24, 32, 42 2011 Microchip Technology Inc. VDD ................................................................ 24, 42, 32 VDDCORE/VCAP .............................................. 42, 24, 32 VDDPLL ........................................................... 32, 42, 24 VDDRX ............................................................ 32, 42, 24 VDDTX ............................................................ 24, 32, 42 VSS ................................................................ 42, 32, 24 VSSPLL ........................................................... 24, 42, 32 VSSRX ............................................................ 32, 24, 42 VSSTX ............................................................. 32, 42, 24 Pinout I/O Descriptions PIC18F66J60/66J65/67J60 ....................................... 18 PIC18F86J60/86J65/87J60 ....................................... 25 PIC18F96J60/96J65/97J60 ....................................... 33 PIR Registers ................................................................... 134 PLL Block .......................................................................... 51 Clock Speeds for Various Configurations .................. 52 POP ................................................................................. 404 POR. See Power-on Reset. PORTA Associated Registers ............................................... 147 LATA Register ......................................................... 146 PORTA Register ...................................................... 146 TRISA Register ........................................................ 146 PORTB Associated Registers ............................................... 150 LATB Register ......................................................... 148 PORTB Register ...................................................... 148 RB7:RB4 Interrupt-on-Change Flag (RBIF Bit) ....... 148 TRISB Register ........................................................ 148 PORTC Associated Registers ............................................... 153 LATC Register ......................................................... 151 PORTC Register ...................................................... 151 RC3/SCK1/SCL1 Pin ............................................... 286 TRISC Register ....................................................... 151 PORTD Associated Registers ............................................... 156 LATD Register ......................................................... 154 PORTD Register ...................................................... 154 TRISD Register ....................................................... 154 PORTE Associated Registers ............................................... 159 LATE Register ......................................................... 157 PORTE Register ...................................................... 157 PSP Mode Select (PSPMODE Bit) .......................... 168 RE0/AD8/RD/P2D Pin ............................................. 168 RE1/AD9/WR/P2C Pin ............................................ 168 RE2/AD10/CS/P2B Pin ............................................ 168 TRISE Register ........................................................ 157 PORTF Associated Registers ............................................... 161 LATF Register ......................................................... 160 PORTF Register ...................................................... 160 TRISF Register ........................................................ 160 PORTG Associated Registers ............................................... 163 LATG Register ......................................................... 162 PORTG Register ..................................................... 162 TRISG Register ....................................................... 162 PORTH Associated Registers ............................................... 165 LATH Register ......................................................... 164 PORTH Register ...................................................... 164 TRISH Register ....................................................... 164 DS39762F-page 483 PIC18F97J60 FAMILY PORTJ Associated Registers ............................................... 167 LATJ Register .......................................................... 166 PORTJ Register ....................................................... 166 TRISJ Register ......................................................... 166 Power-Managed Modes ..................................................... 55 and SPI Operation ................................................... 277 Clock Sources ............................................................ 55 Clock Transitions and Status Indicators ..................... 56 Entering ...................................................................... 55 Exiting Idle and Sleep Modes .................................... 61 By Interrupt ........................................................ 61 By Reset ............................................................ 61 By WDT Time-out .............................................. 61 Without an Oscillator Start-up Timer Delay ........ 61 Idle Modes ................................................................. 59 PRI_IDLE ........................................................... 60 RC_IDLE ............................................................ 61 SEC_IDLE .......................................................... 60 Multiple Sleep Commands ......................................... 56 Run Modes ................................................................. 56 PRI_RUN ........................................................... 56 RC_RUN ............................................................ 58 SEC_RUN .......................................................... 56 Selection .................................................................... 55 Sleep Mode ................................................................ 59 Summary (table) ........................................................ 55 Power-on Reset (POR) ...................................................... 65 Power-up Timer (PWRT) ........................................... 66 Time-out Sequence .................................................... 66 Power-up Delays ................................................................ 54 Power-up Timer (PWRT) .............................................. 54, 66 Prescaler Timer2 ...................................................................... 204 Prescaler, Timer0 ............................................................. 173 Prescaler, Timer2 ............................................................. 195 PRI_IDLE Mode ................................................................. 60 PRI_RUN Mode ................................................................. 56 Program Counter ................................................................ 81 PCL, PCH and PCU Registers ................................... 81 PCLATH and PCLATU Registers .............................. 81 Program Memory Extended Instruction Set .......................................... 100 Instructions ................................................................. 85 Two-Word .......................................................... 85 Interrupt Vector .......................................................... 78 Look-up Tables .......................................................... 83 Memory Maps ............................................................ 77 Hard Vectors and Configuration Words ............. 78 Memory Maps, Modes ............................................... 80 Modes Memory Access (table) ...................................... 80 Reset Vector .............................................................. 78 Program Memory Modes .................................................... 79 Address Shifting (Extended Microcontroller) .............. 80 Extended Microcontroller ........................................... 79 Microcontroller ........................................................... 79 Program Verification and Code Protection ....................... 373 Programming, Device Instructions ................................... 375 PSP. See Parallel Slave Port. Pulse-Width Modulation. See PWM (CCP Module) and PWM (ECCP Module). PUSH ............................................................................... 404 PUSH and POP Instructions .............................................. 82 PUSHL ............................................................................. 420 DS39762F-page 484 PWM (CCP Module) Associated Registers ............................................... 196 Duty Cycle ............................................................... 194 Example Frequencies/Resolutions .......................... 195 Operation Setup ...................................................... 195 Period ...................................................................... 194 TMR2 to PR2 Match ................................................ 203 TMR4 to PR4 Match ................................................ 187 PWM (ECCP Module) ...................................................... 203 CCPR1H:CCPR1L Registers ................................... 203 Direction Change in Full-Bridge Output Mode ......... 209 Duty Cycle ............................................................... 204 Effects of a Reset .................................................... 214 Enhanced PWM Auto-Shutdown ............................. 211 Example Frequencies/Resolutions .......................... 204 Full-Bridge Mode ..................................................... 208 Half-Bridge Mode ..................................................... 207 Output Configurations .............................................. 204 Output Relationships (Active-High) .......................... 205 Output Relationships (Active-Low) .......................... 206 Period ...................................................................... 203 Programmable Dead-Band Delay ............................ 211 Setup for PWM Operation ........................................ 214 Start-up Considerations ........................................... 213 Q Q Clock .................................................................... 195, 204 R RAM. See Data Memory. RC_IDLE Mode .................................................................. 61 RC_RUN Mode .................................................................. 58 RCALL ............................................................................. 405 RCON Register Bit Status During Initialization .................................... 68 Reader Response ............................................................ 489 Receive Filters AND Logic Flow ....................................................... 262 Magic Packet Format ............................................... 264 OR Logic Flow ......................................................... 261 Pattern Match Filter Format ..................................... 263 Register File Summary ................................................ 91-96 Registers ADCON0 (A/D Control 0) ......................................... 339 ADCON1 (A/D Control 1) ......................................... 340 ADCON2 (A/D Control 2) ......................................... 341 BAUDCONx (Baud Rate Control x) ......................... 318 CCPxCON (Capture/Compare/PWM Control, CCP4 and CCP5) ............................................ 189 CCPxCON (Enhanced CCPx Control, ECCP1/ECCP2/ECCP3) ................................. 198 CMCON (Comparator Control) ................................ 349 CONFIG1H (Configuration 1 High) .......................... 361 CONFIG1L (Configuration 1 Low) ........................... 361 CONFIG2H (Configuration 2 High) .......................... 363 CONFIG2L (Configuration 2 Low) ........................... 362 CONFIG3H (Configuration 3 High) .......................... 365 CONFIG3L (Configuration 3 Low) ..................... 79, 364 CVRCON (Comparator Voltage Reference Control) .......................................... 355 DEVID1 (Device ID 1) .............................................. 366 DEVID2 (Device ID 2) .............................................. 366 ECCP1AS (ECCP1 Auto-Shutdown Configuration) .................................................. 212 ECCP1DEL (ECCP1 Dead-Band Delay) ................. 211 2011 Microchip Technology Inc. PIC18F97J60 FAMILY ECON1 (Ethernet Control 1) .................................... 227 ECON2 (Ethernet Control 2) .................................... 228 EECON1 (EEPROM Control 1) ................................ 107 EFLOCON (Ethernet Flow Control) ......................... 258 EIE (Ethernet Interrupt Enable) ................................ 240 EIR (Ethernet Interrupt Request, Flag) .................... 241 ERXFCON (Ethernet Receive Filter Control) ........... 260 ESTAT (Ethernet Status) ......................................... 228 INTCON (Interrupt Control) ...................................... 131 INTCON2 (Interrupt Control 2) ................................. 132 INTCON3 (Interrupt Control 3) ................................. 133 IPR1 (Peripheral Interrupt Priority 1) ........................ 140 IPR2 (Peripheral Interrupt Priority 2) ........................ 141 IPR3 (Peripheral Interrupt Priority 3) ........................ 142 MABBIPG (MAC Back-to-Back Inter-Packet Gap) ............................................ 246 MACON1 (MAC Control 1) ....................................... 229 MACON3 (MAC Control 3) ....................................... 230 MACON4 (MAC Control 4) ....................................... 231 MEMCON (External Memory Bus Control) .............. 116 MICMD (MII Command) ........................................... 231 MISTAT (MII Status) ................................................ 232 OSCCON (Oscillator Control) .................................... 53 OSCTUNE (PLL Block Control) ................................. 51 PHCON1 (PHY Control 1) ........................................ 235 PHCON2 (PHY Control 2) ........................................ 236 PHIE (PHY Interrupt Enable) ................................... 242 PHIR (PHY Interrupt Request, Flag) ........................ 242 PHLCON (PHY Module LED Control) ...................... 238 PHSTAT1 (Physical Layer Status 1) ........................ 235 PHSTAT2 (Physical Layer Status 2) ........................ 237 PIE1 (Peripheral Interrupt Enable 1) ........................ 137 PIE2 (Peripheral Interrupt Enable 2) ........................ 138 PIE3 (Peripheral Interrupt Enable 3) ........................ 139 PIR1 (Peripheral Interrupt Request (Flag) 1) ........... 134 PIR2 (Peripheral Interrupt Request (Flag) 2) ........... 135 PIR3 (Peripheral Interrupt Request (Flag) 3) ........... 136 PSPCON (Parallel Slave Port Control) .................... 169 RCON (Reset Control) ....................................... 64, 143 RCSTAx (Receive Status and Control x) ................. 317 SSPxCON1 (MSSPx Control 1, I2C Mode) .............. 281 SSPxCON1 (MSSPx Control 1, SPI Mode) ............. 271 SSPxCON2 (MSSPx Control 2, I2C Master Mode) ............................................ 282 SSPxCON2 (MSSPx Control 2, I2C Slave Mode) .............................................. 283 SSPxSTAT (MSSPx Status, I2C Mode) ................... 280 SSPxSTAT (MSSPx Status, SPI Mode) .................. 270 STATUS ..................................................................... 97 STKPTR (Stack Pointer) ............................................ 82 T0CON (Timer0 Control) .......................................... 171 T1CON (Timer1 Control) .......................................... 175 T2CON (Timer2 Control) .......................................... 180 T3CON (Timer3 Control) .......................................... 183 T4CON (Timer4 Control) .......................................... 187 TXSTAx (Transmit Status and Control x) ................. 316 WDTCON (Watchdog Timer Control) ...................... 368 RESET ............................................................................. 405 2011 Microchip Technology Inc. Reset ................................................................................. 63 Brown-out Reset (BOR) ............................................. 63 Configuration Mismatch (CM) .................................... 63 MCLR Reset, During Power-Managed Modes .......... 63 MCLR Reset, Normal Operation ................................ 63 Power-on Reset (POR) .............................................. 63 RESET Instruction ..................................................... 63 Stack Full Reset ........................................................ 63 Stack Underflow Reset .............................................. 63 State of Registers ...................................................... 68 Watchdog Timer (WDT) Reset During Execution ............................................... 63 Resets ............................................................................. 359 Brown-out Reset (BOR) ........................................... 359 Oscillator Start-up Timer (OST) ............................... 359 Power-on Reset (POR) ............................................ 359 Power-up Timer (PWRT) ......................................... 359 Stack Full/Underflow .................................................. 83 RETFIE ............................................................................ 406 RETLW ............................................................................ 406 RETURN .......................................................................... 407 Return Address Stack ........................................................ 81 Return Stack Pointer (STKPTR) ........................................ 82 Revision History ............................................................... 475 RLCF ............................................................................... 407 RLNCF ............................................................................. 408 RRCF ............................................................................... 408 RRNCF ............................................................................ 409 S SCKx ............................................................................... 269 SDIx ................................................................................. 269 SDOx ............................................................................... 269 SEC_IDLE Mode ............................................................... 60 SEC_RUN Mode ................................................................ 56 Serial Clock, SCKx .......................................................... 269 Serial Data In (SDIx) ........................................................ 269 Serial Data Out (SDOx) ................................................... 269 Serial Peripheral Interface. See SPI Mode. SETF ............................................................................... 409 Slave Select (SSx) ........................................................... 269 SLEEP ............................................................................. 410 Sleep OSC1 and OSC2 Pin States ...................................... 54 Software Simulator (MPLAB SIM) ................................... 427 Special Event Trigger. See Compare (ECCP Module). Special Features of the CPU ........................................... 359 Special Function Registers Ethernet SFRs ........................................................... 90 SPI Mode (MSSP) Associated Registers ............................................... 278 Bus Mode Compatibility ........................................... 277 Clock Speed and Module Interactions ..................... 277 Effects of a Reset .................................................... 277 Enabling SPI I/O ...................................................... 273 Master Mode ............................................................ 274 Master/Slave Connection ........................................ 273 Operation ................................................................. 272 Operation in Power-Managed Modes ...................... 277 DS39762F-page 485 PIC18F97J60 FAMILY Serial Clock .............................................................. 269 Serial Data In ........................................................... 269 Serial Data Out ........................................................ 269 Slave Mode .............................................................. 275 Slave Select ............................................................. 269 Slave Select Synchronization .................................. 275 SPI Clock ................................................................. 274 Typical Connection .................................................. 273 SSPOV ............................................................................. 304 SSPOV Status Flag .......................................................... 304 SSPSTAT Register R/W Bit ..................................................................... 286 SSPxSTAT Register R/W Bit ..................................................................... 284 ......................................................................................... 269 SUBFSR ........................................................................... 421 SUBFWB .......................................................................... 410 SUBLW ............................................................................ 411 SUBULNK ........................................................................ 421 SUBWF ............................................................................ 411 SUBWFB .......................................................................... 412 SWAPF ............................................................................ 412 T Table Pointer Operations (table) ...................................... 108 Table Reads/Table Writes .................................................. 83 TBLRD ............................................................................. 413 TBLWT ............................................................................. 414 Timer0 .............................................................................. 171 Associated Registers ............................................... 173 Clock Source Select (T0CS Bit) ............................... 172 Operation ................................................................. 172 Overflow Interrupt .................................................... 173 Prescaler .................................................................. 173 Prescaler Assignment (PSA Bit) .............................. 173 Prescaler Select (T0PS2:T0PS0 Bits) ..................... 173 Prescaler, Switching Assignment ............................. 173 Prescaler. See Prescaler, Timer0. Reads and Writes in 16-Bit Mode ............................ 172 Source Edge Select (T0SE Bit) ................................ 172 Timer1 .............................................................................. 175 16-Bit Read/Write Mode ........................................... 177 Associated Registers ............................................... 179 Considerations in Asynchronous Counter Mode ...... 178 Interrupt .................................................................... 178 Operation ................................................................. 176 Oscillator .......................................................... 175, 177 Layout Considerations ..................................... 177 Overflow Interrupt .................................................... 175 Resetting, Using the ECCPx Special Event Trigger ................................................... 178 Special Event Trigger (ECCP) ................................. 202 TMR1H Register ...................................................... 175 TMR1L Register ....................................................... 175 Use as a Clock Source ............................................ 177 Use as a Real-Time Clock ....................................... 178 Timer2 .............................................................................. 180 Associated Registers ............................................... 181 Interrupt .................................................................... 181 Operation ................................................................. 180 Output ...................................................................... 181 PR2 Register .................................................... 194, 203 TMR2 to PR2 Match Interrupt .................................. 203 DS39762F-page 486 Timer3 .............................................................................. 183 16-Bit Read/Write Mode .......................................... 185 Associated Registers ............................................... 185 Operation ................................................................. 184 Oscillator .......................................................... 183, 185 Overflow Interrupt ............................................ 183, 185 Resetting Using the ECCPx Special Event Trigger ................................................... 185 TMR3H Register ...................................................... 183 TMR3L Register ....................................................... 183 Timer4 .............................................................................. 187 Associated Registers ............................................... 188 Operation ................................................................. 187 Output, PWM Time Base ......................................... 188 Postscaler. See Postscaler, Timer4. PR4 Register ................................................... 187, 194 Prescaler. See Prescaler, Timer4. TMR4 Register ......................................................... 187 TMR4 to PR4 Match Interrupt .......................... 187, 188 Timing Diagrams A/D Conversion ........................................................ 462 Asynchronous Reception, RXDTP = 0 (RXx Not Inverted) ........................................... 329 Asynchronous Transmission (Back-to-Back), TXCKP = 0 (TXx Not Inverted) ........................ 326 Asynchronous Transmission, TXCKP = 0 (TXx Not Inverted) ........................................... 326 Automatic Baud Rate Calculation ............................ 324 Auto-Wake-up Bit (WUE) During Normal Operation ......................................................... 331 Auto-Wake-up Bit (WUE) During Sleep ................... 331 Baud Rate Generator with Clock Arbitration ............ 301 BRG Overflow Sequence ......................................... 324 BRG Reset Due to SDAx Arbitration During Start Condition ................................................. 310 Capture/Compare/PWM (Including ECCPx Modules) ............................................. 452 CLKO and I/O .......................................................... 447 Clock Synchronization ............................................. 294 Clock/Instruction Cycle .............................................. 84 EUSARTx Synchronous Receive (Master/Slave) ................................................. 461 EUSARTx Synchronous Transmission (Master/Slave) ................................................. 461 Example SPI Master Mode (CKE = 0) ..................... 453 Example SPI Master Mode (CKE = 1) ..................... 454 Example SPI Slave Mode (CKE = 0) ....................... 455 Example SPI Slave Mode (CKE = 1) ....................... 456 External Clock (All Modes Except PLL) ................... 445 External Memory Bus for Sleep (Extended Microcontroller Mode) .............................. 122, 124 External Memory Bus for TBLRD (Extended Microcontroller Mode) .............................. 122, 124 Fail-Safe Clock Monitor ........................................... 372 First Start Bit ............................................................ 302 Full-Bridge PWM Output .......................................... 208 Half-Bridge PWM Output ......................................... 207 I2C Acknowledge Sequence .................................... 307 I2C Bus Collision During a Repeated Start Condition (Case 1) .................................. 311 I2C Bus Collision During a Repeated Start Condition (Case 2) .................................. 311 I2C Bus Collision During a Stop Condition (Case 1) 312 2011 Microchip Technology Inc. PIC18F97J60 FAMILY I2C Bus Collision During a Stop Condition (Case 2) ........................................... 312 I2C Bus Collision During Start Condition (SCLx = 0) ....................................... 310 I2C Bus Collision During Start Condition (SDAx Only) ..................................... 309 I2C Bus Collision for Transmit and Acknowledge .... 308 I2C Bus Data ............................................................ 457 I2C Bus Start/Stop Bits ............................................. 457 I2C Master Mode (7 or 10-Bit Transmission) ........... 305 I2C Master Mode (7-Bit Reception) .......................... 306 I2C Slave Mode (10-Bit Reception, SEN = 0, ADMSK = 01001) ............................................. 291 I2C Slave Mode (10-Bit Reception, SEN = 0) .......... 290 I2C Slave Mode (10-Bit Reception, SEN = 1) .......... 296 I2C Slave Mode (10-Bit Transmission) ..................... 292 I2C Slave Mode (7-Bit Reception, SEN = 0, ADMSK = 01011) ............................................. 288 I2C Slave Mode (7-Bit Reception, SEN = 0) ............ 287 I2C Slave Mode (7-Bit Reception, SEN = 1) ............ 295 I2C Slave Mode (7-Bit Transmission) ....................... 289 I2C Slave Mode General Call Address Sequence (7 or 10-Bit Addressing Mode) ........ 297 I2C Stop Condition Receive or Transmit Mode ........ 307 Master SSP I2C Bus Data ........................................ 459 Master SSP I2C Bus Start/Stop Bits ........................ 459 Parallel Slave Port (PSP) Read ............................... 170 Parallel Slave Port (PSP) Write ............................... 169 Program Memory Read ............................................ 448 Program Memory Write ............................................ 449 PWM Auto-Shutdown (P1RSEN = 0, Auto-Restart Disabled) .................................... 213 PWM Auto-Shutdown (P1RSEN = 1, Auto-Restart Enabled) ..................................... 213 PWM Direction Change ........................................... 210 PWM Direction Change at Near 100% Duty Cycle ............................................. 210 PWM Output ............................................................ 194 Repeated Start Condition ......................................... 303 Reset, Watchdog Timer (WDT), Oscillator Start-up Timer (OST) and Power-up Timer (PWRT) ..... 450 Send Break Character Sequence ............................ 332 Slave Synchronization ............................................. 275 Slow Rise Time (MCLR Tied to VDD, VDD Rise > TPWRT) ............................................ 67 SPI Mode (Master Mode) ......................................... 274 SPI Mode (Slave Mode, CKE = 0) ........................... 276 SPI Mode (Slave Mode, CKE = 1) ........................... 276 Synchronous Reception (Master Mode, SREN) ...... 335 Synchronous Transmission ...................................... 333 Synchronous Transmission (Through TXEN) .......... 334 Time-out Sequence on Power-up (MCLR Not Tied to VDD), Case 1 ................................... 66 Time-out Sequence on Power-up (MCLR Not Tied to VDD), Case 2 ................................... 67 Time-out Sequence on Power-up (MCLR Tied to VDD, VDD Rise < TPWRT) ................................ 66 Timer0 and Timer1 External Clock .......................... 451 Transition for Entry to Idle Mode ................................ 60 Transition for Entry to SEC_RUN Mode .................... 57 Transition for Entry to Sleep Mode ............................ 59 Transition for Two-Speed Start-up (INTRC to HSPLL) ........................................... 370 Transition for Wake From Idle to Run Mode .............. 60 Transition for Wake From Sleep Mode (HSPLL) ....... 59 2011 Microchip Technology Inc. Transition From RC_RUN Mode to PRI_RUN Mode ................................................. 58 Transition From SEC_RUN Mode to PRI_RUN Mode (HSPLL) .................................. 57 Transition to RC_RUN Mode ..................................... 58 Timing Diagrams and Specifications AC Characteristics Internal RC Accuracy ....................................... 446 Capture/Compare/PWM Requirements (Including ECCPx Modules) ............................ 452 CLKO and I/O Requirements ........................... 447, 448 EUSARTx Synchronous Receive Requirements ..... 461 EUSARTx Synchronous Transmission Requirements .................................................. 461 Example SPI Mode Requirements (Master Mode, CKE = 0) .................................. 453 Example SPI Mode Requirements (Master Mode, CKE = 1) .................................. 454 Example SPI Mode Requirements (Slave Mode, CKE = 0) .................................... 455 Example SPI Slave Mode Requirements (CKE = 1) 456 External Clock Requirements .................................. 445 I2C Bus Data Requirements (Slave Mode) .............. 458 I2C Bus Start/Stop Bits Requirements (Slave Mode) ................................................... 457 Master SSP I2C Bus Data Requirements ................ 460 Master SSP I2C Bus Start/Stop Bits Requirements .................................................. 459 Parallel Slave Port Requirements ............................ 452 PLL Clock ................................................................ 446 Program Memory Write Requirements .................... 449 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements ........................................ 450 Timer0 and Timer1 External Clock Requirements .................................................. 451 Top-of-Stack Access .......................................................... 81 TRISE Register PSPMODE Bit ......................................................... 168 TSTFSZ ........................................................................... 415 Two-Speed Start-up ................................................. 359, 370 Two-Word Instructions Example Cases ......................................................... 85 TXSTAx Register BRGH Bit ................................................................. 319 V VDDCORE/VCAP Pin .......................................... 369, 442, 369 W Watchdog Timer (WDT) ........................................... 359, 367 Associated Registers ............................................... 368 Control Register ....................................................... 367 Programming Considerations .................................. 367 WCOL ...................................................... 302, 303, 304, 307 WCOL Status Flag ................................... 302, 303, 304, 307 WWW Address ................................................................ 488 WWW, On-Line Support ...................................................... 9 X XORLW ........................................................................... 415 XORWF ........................................................................... 416 DS39762F-page 487 PIC18F97J60 FAMILY NOTES: DS39762F-page 488 2011 Microchip Technology Inc. PIC18F97J60 FAMILY THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: Users of Microchip products can receive assistance through several channels: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives * * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://microchip.com/support CUSTOMER CHANGE NOTIFICATION SERVICE Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under "Support", click on "Customer Change Notification" and follow the registration instructions. 2011 Microchip Technology Inc. DS39762F-page 489 PIC18F97J60 FAMILY READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: Technical Publications Manager RE: Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC18F97J60 Family Literature Number: DS39762F Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS39762F-page 490 2011 Microchip Technology Inc. PIC18F97J60 FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Device PIC18F66J60/66J65/67J60, PIC18F86J60/86J65/87J60, PIC18F96J60/96J65/97J60, PIC18F66J60/66J65/67J60T(1), PIC18F86J60/86J65/87J60T(1), PIC18F96J60/96J65/97J60T(1) Temperature Range I Package PT = = PF = Pattern Examples: a) b) PIC18F67J60-I/PT 301 = Industrial temp., TQFP package, QTP pattern #301. PIC18F67J60T-I/PT = Tape and reel, Industrial temp., TQFP package. -40C to +85C (Industrial) 64, 80 and 100-Lead, 12x12x1 mm TQFP (Thin Quad Flatpack) 100-Lead, 14x14x1 mm TQFP Note 1: T = in tape and reel QTP, SQTP, Code or Special Requirements (blank otherwise) 2011 Microchip Technology Inc. DS39762F-page 491 Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.com Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 China - Chongqing Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 Taiwan - Kaohsiung Tel: 886-7-213-7830 Fax: 886-7-330-9305 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 02/18/11 DS39762F-page 492 2011 Microchip Technology Inc.