at Integrated Device Technobgy, he. CMOS ASYNCHRONOUS FIFO 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9 IDT7203 IDT7204 IDT7205 IDT7206 IDT7207 IDT7208 FEATURES: * First-In/First-Out Dual-Port memory * 2,048 x 9 organization (IDT7203) * 4,096 x 9 organization (IDT7204) * 8,192 x 9 organization (IDT7205) * 16,384 x 9 organization (IDT7206) * 32,768 x 9 organization (IDT7207) * 65,636 x 9 organization (IDT7208) * High-speed: 12ns access time * Low power consumption Active: 660mW (max.) Power-down: 44mW (max.) * Asynchronous and simultaneous read and write * Fully expandable in both word depth and width * Pin and functionally compatible with IDT720X family * Status Flags: Empty, Half-Full, Full Retransmit capability * High-performance CMOS technology * Military product compliant to MIL-STD-883, Class B * Standard Military Drawing for #5962-88669 (IDT7203), 5962-89567 (IDT7203), and 5962-89568 (IDT7204) are listed on this function * Industrial temperature range (40C to +85C) is available (for plastic packages only) DESCRIPTION: The IDT7203/7204/7205/7206/7207/7208 are dual-port memory buffers with internal pointers that load and empty data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow and expansion logic to allow for unlimited expansion capability in both word size and depth. Data is toggled in and out of the device through the use of the Write (W) and Read (R) pins. The device's 9-bit width provides a bit for a control or parity at the users option. It also features a Retransmit (RT) capa- bility that allows the read pointer to be reset to its initial position when RT is pulsed LOW. A Half-Full Flag is available in the single device and width expansion modes. These FIFOs are fabricated using IDTs high-speed CMOS technology. They are designed for applications requiring asynchronous and simultaneous read/writes in multiprocess- ing, rate buffering and other applications. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B. FUNCTIONAL BLOCK DIAGRAM DATA INPUTS (Do Ds) _ WRITE W"| CONTROL LLOMI LIrer e __i : WRITE Sy Pode eo READ POINTER 4,096 x 9 POINTER 8,192x9 L 16,384 x 9 LA 32,768 x9 65,536 x9 e > > LUD TTT TT THREE- WY . \~ STATE BUFFERS VY RS DATA OUTPUTS y READ 0 5 RESET CONTROL =| LOGIC 6 i r YY i FLAG =| oo LOGIC EF FLIRT > FF | EXPANSION /** _ x] - LOGIC hhh SOFXXO/HF 2661 drw 01 The IDT logo is a registered trademark of Integrated Device Techology, Inc. MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES SEPTEMBER 1997 1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391. DSC-2661/9 1IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9 MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES PIN CONFIGURATIONS WC os bs Voc Ds U2 271 Da D303 26 Ds D2 (| 4 2] De DiQ{5 2411 D7 Do 6 23 |) FL/RT Xl 7 2217 RS FF Os 21{0 EF Qo 9 20 [1 XO/HF Qi 4 10 1911 Q7 Q2 i 1isF Qe Q3 4 12 177 Qs Qs CU 13 16[1Q4 GND [I 14 ist] R Co 2D 2661 drw 02a Oo 2661 drw 02b TOP VIEW TOP VIEW Reference | Order Device Package Reference Order Device Package Type Identifier | Code Availability Type Identifier Code Availability PLASTIC DIP P28-1 P All devices PLCC J32-1 J All devices PLASTIC THIN DIP| P28-2 TP | Allexcept 7207/7208 Lec L32-1 L All except 7208 CERDIP D28-1 D | All except 7208 THIN CERDIP D28-3 TD | Only for 7203/7204/7205 SsOoIc S$028-3 SO | only for 7204 NOTES: 1. This package is only available in the military temperature range. 2. Consult factory for CERPACK pinout. RECOMMENDED DC OPERATING ABSOLUTE MAXIMUM RATINGS CONDITIONS Symbol Rating Com'l & Ind'l Military Unit Symbol Parameter Min. Typ. |Max. | Unit VTERM | Terminal -0.5t0+7.0 | -0.5to +7.0 Vv VCCM | Military Supply 4.5 5.0) 55] V Voltage with Voltage Respect to Vccc | Commercial Supply 45 5.0] 55] V GND Voltage TSTG Storage -55 to+125 | -6510+155 | C GND | Supply Voltage 0 0 0 V Temperature 1 : VIH) Input High Voltage 2.0 _ |vV IOUT DC Output 50 to +50 50 to +50 mA Commercial Current () NOTE: 3661 tot VIH Input High Voltage 2.2 _ |vV 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT- Military INGS may cause permanent damage to the device. This is astress rating vil Input Low Voltage _ _ 03] V only and functional operation of the device at these or any other conditions Cc ial and above those indicated in the operational sections of this specification is not om mercia! an implied. Exposure to absolute maximum rating conditions for extended Military periods may affect reliability. TA Operating Temperature | 0 to +70 | /] C Commercial TA Operating Temperature | -40 to +85 | |c Industrial TA Operating Temperature |-55 to +125) |c Military NOTE: 2661 tbl 02 1. 1.5V undershoots are allowed for 10ns once per cycle.IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9 MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS (Commercial: Vcc = 5V +10%, TA = 0C to +70C; Industrial: Voc = 5V + 10%, TA = -40C to +85C; Military: Vcc = 5V +10%, TA=-55C to +125C) IDT7203 IDT7203 IDT7204 IDT7204 Commercial and Industrial Military? ta = 12, 15, 20, 25, 35, 50 ns ta = 20, 30, 40, 50, 65, 80, 120 ns Symbol Parameter Min. Typ. Max. Min. Typ. Max. Unit 4) Input Leakage Current (Any Input) -1 _ 1 -1 _ 1 HA ILol) Output Leakage Current -10 _ 10 -10 _ 10 LA VOH Output Logic 1 Voltage IOH =2mA 2.4 _ _ 2.4 _ _ Vv VOL Output Logic O Voltage lol =8mA _ _ 0.4 _ _ 0.4 Vv Icc1'78) | Active Power Supply Current _ _ 120 _ _ 150 mA Icc2'89) | Standby Current (R=W=RS=FL/RT=Vin) 12 25 mA Iccs'89) | Power Down Current _ _ 2 _ _ 4 mA IDT7205 IDT7205 IDT7206 IDT7206 IDT7207 IDT7207 IDT7208""*) Commercial and Industrial Military ta = 15, 20, 25, 35, 50 ns ta = 20, 30, 50 ns Symbol Parameter Min. Typ. Max. Min. Typ. Max. Unit 4) Input Leakage Current (Any Input) -1 _ 1 -1 _ 1 HA ILol) Output Leakage Current -10 _ 10 -10 _ 10 LA VOH Output Logic 1 Voltage IOH =2mA 2.4 _ _ 2.4 _ _ Vv VOL Output Logic O Voltage loL =8mA _ _ 0.4 _ _ 0.4 Vv Icc1'78) | Active Power Supply Current _ _ 120 _ _ 150 mA Icc2"689) | Standby Current (R-W=RS=FL/RT=VIH) = = 12 = = 25 mA Icc3'&89) | Power Down Current _ _ 8 _ _ 12 mA NOTES: 2661 tbl 03 1. Industrial temperature range product for the 25 ns speed grade is available as a standard device (excluding the 7208). Allother speed grades are available by special order. 2. Speed grades of 65, 80, and 120 ns are only available in the ceramic DIP. 3. Only commercial speed grades of 20, 25 and 35 ns are available for the 7208. 4. Measurements with 0.4 < VIN < Vcc. 5. RVI, 0.4 < VouTs Vcc. 6. Tested with outputs open (louT = 0). 7. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz. 8. Icc measurements are made with outputs open. 9. All Inputs = Vcc - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20MHz. AC TEST CONDITIONS Input Pulse Levels GND to 3.0V Input Rise/Fall Times 5ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load See Figure 1 2661 tbl 07 CAPACITANCE) (Ta = +25C, f = 1.0 MHz) Symbol Parameter Condition Max. | Unit Cin'?) Input Capacitance VIN = OV 10 pF Cout"?) | Output Capacitance | Vout = 0V 10 pF NOTES: 2661 tbl 08 1. This parameter is sampled and not 100% tested. 2. With output deselected.IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9 MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS (Commercial: Vcc = 5V + 10%, TA = 0C to +70C; Industrial: Voc = 5V +10%, TA = 40C to +85C; Military: Vcc = 5V +10%, TA =-55C to +125C) Commercial Com'l & Mil.|Com'l & Ind'I@| Military | Com'l 7203L12 7203L15 7203L20 7203L25 7203L30 | 7203L35 7204L12 7204L15 7204L20 7204L25 7204L30 | 7204L35 7205L15 7205L20 7205L25 7205L30 | 7205L35 7206L15 7206L20 7206L25 7206L30 | 7206L35 7207L15 7207L20 7207L25 7207L30 | 7207L35 Commercial 7208L20 7208L25 7208L35 Symbol Parameters Min. Max.|Min. Max.| Min. Max.| Min. Max. |Min. Max.| Min. Max. | Unit fs Shift Frequency _ 50 | 40 333) 285 25 | 22.2 |MHz tRC Read Cycle Time 20 | 2 _ 30 _ 35 _ 40 | 45 | ns tA Access Time _ 12) 15 _ 20 _ 25 30/ 35 | ns tRR Read Recovery Time 8 | 10 _ 10 _ 10 _ 10 |10 | ns tRPW Read Pulse Width 12 /]15 1] 20 25 30 | 35 | ns tRLZ Read LOW to Data Bus LOW 3 |] 5 5 5 5 | ns tWLz Write HIGH to Data Bus Low-Z*5) | 3 |] 5 5 5 5 ]|]10 | ns {DV Data Valid from Read HIGH 5 _ 5 _ 5 _ 5 _ 5 _ | ns tRHZ Read HIGH to Data Bus High-Z | 12 | 15 | 15 18 20/ 20] ns two Write Cycle Time 20 | 2 _ 30 _ 35 _ 40 | 45 | ns twPw Write Pulse Width 12 /]15 ]} 20 25 30 | 35 1] ns twR Write Recovery Time 8 | 10 = 10 = 10 _ 10 | 10 | ns ips Data Set-up Time | i1 _ 12 _ 15 _ 18 |18 | ns {DH Data Hold Time _ 0 _ 0 _ 0 _ 0 _ 0 | ns tRSC Reset Cycle Time 20 | 2 _ 30 _ 35 _ 40 | 45 | ns tRS Reset Pulse Width 12 /]15 1] 20 25 30 | 35 | ns tRSS Reset Set-up Time 12 /]15 | 20 _ 25 30 | 35 | ns tRTR Reset Recovery Time 8 | 10 _ 10 _ 10 _ 10 |10 | ns tRTC Retransmit Cycle Time 20 | 2 _ 30 _ 35 _ 40 | 45 | ns tRT Retransmit Pulse Width 12 /]15 ] 20 25 30 | 35 |] ns tRTS Retransmit Set-up Time 12 /]15 | 20 _ 25 30 | 35 ]}| ns tRSR Retransmit Recovery Time 8 | 10 _ 10 _ 10 _ 10 |10 | ns tEFL Reset to EF LOW 12}]/ 2 ] 30] 35 40}] 45 | ns tHFH, t=FH| Reset to HF and FF HIGH i7/ 2] 30 35 40|/ 45 | ns {RTF Retransmit LOW to Flags Valid _ 20 | 25 _ 30 _ 35 40 | 45 | ns tREF Read LOW to EF LOW 12}/ 1/] 20] 2 30 }| 30 {ns tRFF Read HIGH to FF HIGH 14/ 15/] 20] 2 30 }| 30 {ns {RPE Read Pulse Width after EF HIGH 12 | 15 _ 20 _ 25 _ 30 | 35 | ns {WEF Write HIGH to EF HIGH _ 12 _ 15 _ 20 _ 25 30 30 ns {WEF Write LOW to FF LOW 14/ 15/] 20] 2 30 }| 30 {ns tWHF Write LOW to HF Flag LOW i7]/ 28 {| 30] 35 40|/ 45 | ns tRHF Read HIGH to HF Flag HIGH i17/]/ 28 |] 30] 35 40/ 45 | ns {WPF Write Pulse Width after FF HIGH 12 | 15 _ 20 _ 25 _ 30 | 35 | ns tXOL Read/Write LOW to XO LOW _ 12) 15 _ 20 _ 25 30{ 35 | ns tXOH Read/Write HIGH to XO HIGH _ 12) 15 _ 20 _ 25 30/ 35 | ns tx! XI Pulse Width) 1722 |15 }] 20 }] 2B 30 | 35 | ns txIR XI Recovery Time 8 |]10 ] 10 }] 10 10 1]10 | ns txis XI Set-up Time 8 |10 ]10 ]}] 10 10 1|]15 | ns NOTES: 2661 tbl 05 1. Timings referenced as in AC Test Conditions. 3. Pulse widths less than minimum are not allowed. 2. Industrial temperature range product for the 25 ns speed grade is available 4. Values guaranteed by design, not currently tested. as a standard device. All other speed grades are available by special order. 5. Only applies to read data flow-through mode.IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9 MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS (Continued) (Commercial: Voc = 5V + 10%, TA = 0C to +70C; Military: Voc = 5V + 10%, TA = -55C to +125C) Military Com'l & Mil. Military? 7203L40 7203L50 7203L65 7203L80 7203L120 7204L40 7204L50 7204L65 7204L80 7204L120 7205L50 7206L50 7207L50 Symbol Parameters Min. Max. | Min. Max.| Min. Max. | Min. Max.) Min. Max Unit fs Shift Frequency _ 20 _ 15 _ 12.5) 10 _ 7 MHz tRC Read Cycle Time 50 _ 65 _ 80 | 100 | 140 _ ns tA Access Time _ 40 _ 50 _ 65 _ 80 _ 120 ns tRR Read Recovery Time 10 _ 15 _ 15 _ 20 _ 20 _ ns tRPW Read Pulse Width 40 50 | 65 | 80 | 120 ns tRLZ Read LOW to Data Bus LOW 5 10 | 10 | 10 | 10 ns tWLz Write HIGH to Data Bus Low-Z* ) 10 15 | 15 | 20 | 20 ns {DV Data Valid from Read HIGH 5 _ 5 _ 5 _ 5 _ 5 _ ns tRHZ Read HIGH to Data Bus High-Z _ 25 _ 30 | 30 | 30 | 35 ns two Write Cycle Time 50 _ 65 _ 80 | 100 | 140 _ ns twPw Write Pulse Width 40 50 | 65 | 80 | 120 ns twR Write Recovery Time 10 _ 15 _ 15 _ 20 _ 20 _ ns ips Data Set-up Time 20 _ 30 _ 30 _ 40 _ 40 _ ns {DH Data Hold Time 0 _ 5 _ 10 _ 10 _ 10 _ ns tRSC Reset Cycle Time 50 _ 65 _ 80 | 100 | 140 _ ns tRS Reset Pulse Width 40 50 | 65 | 80 | 120 ns tRSS Reset Set-up Time 40 _ 50 | 65 | 80 | 120 ns tRSR Reset Recovery Time 10 _ 15 _ 15 _ 20 _ 20 _ ns tRTC Retransmit Cycle Time 50 _ 65 _ 80 | 100 | 140 _ ns tRT Retransmit Pulse Width 40 50 | 65 | 80 | 120 ns tRTS Retransmit Set-up Time 40 _ 50 | 65 | 80 | 120 ns tRSR Retransmit Recovery Time 10 _ 15 _ 15 _ 20 _ 20 _ ns {EFL Reset to EF LOW _ 50 _ 65 _ 80 _ 100}; 140 ns tHFH, t=FH | Reset to HF and FF HIGH 50 65 | so | 100} 140 ns {RTF Retransmit LOW to Flags Valid _ 50 _ 65 _ 80 _ 100}; 140 ns tREF Read LOW to EF Flag LOW 35 45 | 60 | 60 | 60 ns tRFF Read HIGH to FF HIGH 35 | 45/ 60|/ 60/ _ 60 ns {RPE Read Pulse Width after EF HIGH 40 _ 50 _ 65 _ 80 | 120 _ ns {WEF Write HIGH to EF HIGH _ 35 _ 45 60 60 60 ns tWFF Write LOW to FF LOW 35 | 45/ 60/ 60] _ 60 ns tWHF Write LOW to HF LOW 50 | 6 | 80/ 100} 140 ns tRHF Read HIGH to HF HIGH 50 | 6 | 80/ 100} 140 ns {WPF Write Pulse Width after FF HIGH 40 _ 50 _ 65 _ 80 | 120 _ ns tXOL Read/Write LOW to XO LOW _ 40 _ 50 _ 65 _ 80 120 ns tXOH Read/Write HIGH to XO HIGH _ 40 _ 50 _ 65 _ 80 _ 120 ns tx! XI Pulse Width) 40 | 50 {6 |s0 ] 120 ns txIR XI Recovery Time 10 10 | 10 | 10 | 10 ns xis Xl Set-up Time 15 _ 15 _ 15 _ 15 _ 15 _ ns NOTES: 2661 tbl 06 1. Timings referenced as in AC Test Conditions. 2. Speed grades 65, 80, and 120ns are only available in the CERDIP package. 3. Pulse widths less than minimum are not allowed. 4. Values guaranteed by design, not currently tested. 5. Only applies to read data flow-through mode.IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9 MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES 5V 1.1KQ D.U.T. 680Q 30pF* = 2661 drw 03 OR EQUIVALENT CIRCUIT Figure 1. Output Load *Includes jig and scope capacitances. SIGNAL DESCRIPTIONS Inputs: DATA IN (DoDs) Data inputs for 9-bit wide data. Controls: RESET (RS) Reset is accomplished whenever the Reset (RS) input is taken to a LOW state. During reset, both internal read and write pointers are set to the first location. A reset is required after power-up before a write operation can take place. Both the Read Enable (R) and Write Enable (W) inputs must be in the HIGH state during the window shown in Figure 2 (i.e. tass before the rising edge of RS) and should not change until trsrR after the rising edge of RS. WRITE ENABLE (W)Awrite cycle is initiated on the falling edge of this input if the Full Flag (FF) is not set. Data set-up and hold times must be adhered-to, with respect to the rising edge of the Write Enable (W). Data is stored in the RAM array sequentially and independently of any on-going read operation. After half of the memory is filled, and at the falling edge of the next write operation, the Half-Full Flag (HF) will be set to LOW, and will remain set until the difference between the write pointer and read pointer is less-than or equal to one-half of the total memory of the device. The Half-Full Flag (HF) is then reset by the rising edge of the read operation. To prevent data overflow, the Full Flag (FF) will go LOW on the falling edge of the last write signal, which inhibits further write operations. Upon the completion of a valid read operation, the Full Flag (FF) will go HIGH after tRFF, allowing a new valid write to begin. When the FIFO is full, the internal write pointer is blocked from W, so external changes in W will not affect the FIFO when it is full. READ ENABLE (R) A read cycle is initiated on the falling edge of the Read Enable (R), provided the Empty Flag (EF) is not set. The data is accessed on a First-In/First-Out basis, independ- ent of any ongoing write operations. After Read Enable (R) goes HIGH, the Data Outputs (Qo through Qs) will return to a high- impedance condition until the next Read operation. When all the data has been read from the FIFO, the Empty Flag (EF) will go LOW, allowing the final read cycle but inhibiting further read operations, with the data outputs remaining in a high-impedance state. Once a valid write operation has been accomplished, the Empty Flag (EF) will go HIGH after tweF and a valid Read can then begin. When the FIFOis empty, the internal read pointer is blocked from Rso external changes will not affect the FIFO when itis empty. FIRST LOAD/RETRANSMIT (FL/RT) This is a dual- purpose input. In the Depth Expansion Mode, this pin is grounded to indicate that it is the first device loaded (see Operating Modes). The Single Device Mode is initiated by grounding the Expansion In (Xl). The IDT7203/7204/7205/7206/7207/7208 can be made to retransmit data when the Retransmit Enable Control (RT) input is pulsed LOW. A retransmit operation will set the internal read pointer to the first location and will not affect the write pointer. The status of the Flags will change depending on the relative locations of the read and write pointers. Read Enable (R) and Write Enable (W) must be in the HIGH state during retransmit. This feature is useful when less than 2,048/4,096/8, 192/16 ,384/ 32,768/65,536 writes are performed between resets. The retransmit feature is not compatible with the Depth Expansion Mode. EXPANSION IN (XI) This input is a dual-purpose pin. Expansion In (XI) is grounded to indicate an operation in the single device mode. Expansion In (XI) is connected to Expan- sion Out (XO) of the previous device in the Depth Expansion or Daisy-Chain Mode. Outputs: FULL FLAG (FF) The Full Flag (FF) will go LOW, inhibiting further write operations, when the device is full. If the read pointer is not moved after Reset (RS), the Full Flag (FF) will go LOW after 2,048/4,096/8,192/16,384/32,768/65,536 writes. EMPTY FLAG (EF) The Empty Flag (EF) will go LOW, inhibiting further read operations, when the read pointer is equal to the write pointer, indicating that the device is empty. EXPANSION OUT/HALF-FULL FLAG (XO/HF) This is a dual-purpose output. In the single device mode, when Expan- sion In (XI) is grounded, this output acts as an indication of a half- full memory. After half ofthe memory is filled, and at the falling edge of the next write operation, the Half-Full Flag (HF) will be set to LOW and will remain set until the difference between the write pointer and read pointer is less than or equal to one half of the total memory of the device. The Half-Full Flag (HF) is then reset by the rising edge of the read operation. In the Depth Expansion Mode, Expansion In (XI) is connected to Expansion Out (XO) of the previous device. This output acts as a signal to the next device in the Daisy Chain by providing a pulse to the next device when the previous device reaches the last location of memory. There will be an XO pulse when the Write pointer reaches the last location of memory, and an additional XO pulse when the Read pointer reaches the last location of memory.IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9 MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES DATA OUTPUTS (Qo-Qs) Qo-Qs are data outputs for 9- bit wide data. These outputs are in a high-impedance condition whenever Read (R) is in a HIGH state. =I Zl EF tHFH, tFFH AF, FF 2661 drw 04 NOTE: _ __ 1. Wand R= ViH around the rising edge of RS. Figure 2. Reset A$$ RE $$ rr | RP j<_ {| A >| {RR} tA > R N K 14 tRLZ > tDV t 1RHZ _>] Qo-as ~K & XK DATAouT VALID. KKK DATAcuT VALID J} twc jeg. t WP W/ > ng [WR > wo _:, KC KO tps~= t DH >} D oDs DATAIN VALID DATAIN VALID 2661 drw 05 Figure 3. Asynchronous Write and Read Operation IGNORED LAST WRITE WRITE FIRST READ R \_ 7 W IN {RFF LT WFF el FF 2661 drw 06 Figure 4. Full FlagTiming From Last Write to First ReadIDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x9 MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES IGNORED tastreaD | CONOR FIRST WRITE W \ 7 R \ yf tREF TWEF EF wy tA DATA ouT -_C HK vat XX 2661 drw 07 Figure 5. Empty Flag Timing From Last Read to First Write ~<a tRTC > aT e tRT He t RTS tRTIR ] mm XXXKXY tRTF | FREE QO OO ODOODOD PODDODDOTFK_ Fg vaso 2661 drw 08 NOTE 1. EF, FF and HF may change status during Retransmit, but flags will be valid at taTc. Figure 6. Retransmit 7 7 EWEF EF 7 XXANNANAAASANSS IK sown R Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse. A . / | ao t RFF FF 4X -< twPF FW DAXDSBBDQXQCCLCALOA OAS # st 0 Figure 8. Minimum Timing for a Full Flag Coincident Write Pulse.IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9 MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES W KY Dl ht WHF __ HALF-FULL OR LESS YL HF MORE THAN HALF-FULL E ame HALF-FULL OR LESS 2661 drw 11 Figure 9. Half-Full Flag Timing WRITE TO 2 LAST PHYSICAL Ww LOCATION READ FROM R LAST PHYSICAL LOCATION txoL txoH . -<, tXOH XO 2661 drw 12 Figure 10. Expansion Out <q 1 xI txiR > Xl \ X / s 'XIS WRITE TO _ FIRST PHYSICAL ; Ww LOCATION 7 IXls READ FROM _ FIRST PHYSICAL R LOCATION 2661 drw 13 Figure 11. Expansion In OPERATING MODES: Care must be taken to assure that the appropriate flag is monitored by each system (i.e. FF is monitored on the device where W is used; EF is monitored on the device where R is used). For additional information on the IDT7203/7204/7205/ 7206/7207, refer to Tech Note 8: Operating FIFOs on Full and Empty Boundary Conditions and Tech Note 6: Designing with FIFOs. Single Device Mode A single IDT7203/7204/7205/7206/7207/7208 may be used when the application requirements are for 2,048/4,096/8, 192/ 16,384/32,768/65,536 words or less. These FIFOs are in a Single Device Configuration when the Expansion In (XI) control input is grounded (see Figure 12). Depth Expansion These FIFOs can easily be adapted to applications when the requirements are for greater than 2,048/4,096/8,192/ 16,384/32,768/65 536 words. Figure 14 demonstrates Depth Expansion using three IDT 7203/7204/7205/7206/7207/7208s. Any depth can be attained by adding additional IDT7203/ 7204/7205/7206/7207/7208s. These devices operate in the Depth Expansion mode when the following conditions are met: 1. The first device must be designated by grounding the First Load (FL) control input. 2. All other devices must have FL in the HIGH state. 3. The Expansion Out (XO) pin of each device must be tied to the Expansion In (XI) pin of the next device. See Figure 14. 4. External logic is needed to generate a composite Full Flag (FF) and Empty Flag (EF). This requires the ORing of all EFs and ORing of all FFs (i.e. all mustbe set to generate the correct composite FF or EF). See Figure 14. 5. The Retransmit (RT) function and Half-Full Flag (HF) are not available in the Depth Expansion Mode. For additional information on the IDT7203/7204/7205/7206/ 7207, refer to Tech Note 9: Cascading FIFOs or FIFO Modules.IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9 MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES USAGE MODES: Width Expansion Word width may be increased simply by connecting the corresponding input control signals of multiple devices. Status flags (EF, FF and HF) can be detected from any one device. Figure 18 demonstrates an 18-bit word width by using two IDT7203/7204/7205/7206/7207/7208s. Any word widthcan be attained by adding additional IDT7203/7204/7205/7206/7207/ 7208s (Figure 13). Bidirectional Operation Applications which require data buffering between two systems (each system capable of Read and Write operations) can be achieved by pairing IDT7203/7204/7205/7206/7207/ 7208s as shown in Figure 16. Both Depth Expansion and Width Expansion may be used in this mode. Data Flow-Through Two types of flow-through modes are permitted, a read flow-through and write flow-through mode. For the read flow- (HALFFULL FLAG) through mode (Figure 17), the FIFO permits a reading of a single word after writing one word of data into an empty FIFO. The data is enabled on the bus in (tWEF + ta) ns after the rising edge of W, called the first write edge, and it remains on the bus until the R line is raised from LOW-to-HIGH, after which the bus would go into a three-state mode aftertRHZ ns. The EFline would have a pulse showing temporary deassertion and then would be asserted. In the write flow-through mode (Figure 18), the FIFO permits the writing of a single word of data immediately after reading one word of data from a full FIFO. The R line causes the FF to be deasserted but the Wline being LOW causes it to be asserted again in anticipation of a new data word. On the rising edge of W, the new word is loaded in the FIFO. The W line must be toggled when FF is not asserted to write new data in the FIFO and to increment the write pointer. Compound Expansion The two expansion techniques described above can be applied together in a straightforward manner to achieve large FIFO arrays (see Figure 15). (HF) WRITE (W) ipT - READ ) 9 7203 9 DATA IN (D) 7204 DATA OUT (Q) FULL FLAG (FF) <,_ 4202 | _ EmPTy FLAG F) RESET (RS) > 7207 + RETRANSMIT (RT) t EXPANSION IN (xl) = 2661 drw 14 Figure 12. Block Diagram of 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9, 65,536 x 9 FIFO Used in Single Device Mode az FF 1g | 19 { g t DATAIN (D) WRITE W) Fr pt ~~ 93987 R DT, JOT READ (R) _ 7204 FULL FLAG (FF) J e0S EF 7205 eon OCU 7208 7205 EMPTY FLAG (EF) __ 7207 rer , - 62 -- RESET (RS) 7208 Lg 4208_ _ 14. petRansmit (AT 5 5 (RT) 7 2661 drw 15 NOTE: = 18 Z > DATA ouT (Q) 1. Flag detection is accomplished by monitoring the FF, EF and HF signals on either (any) device used in the width expansion configuration. Do not connect any output signals together. Figure 13. Block Diagram of 2,048 x 18, 4,096 x 18, 8,192 x 18, 16,384 x 18, 32,768 x 18, 65,536 x 18 FIFO Memory Used in Width Expansion Mode 10IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9 TRUTH TABLES TABLE | - RESET AND RETRANSMIT SINGLE DEVICE CONFIGURATION/WIDTH EXPANSION MODE MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES Inputs Internal Status Outputs Mode RS RT XI | Read Pointer | Write Pointer EF FF HF Reset 0 X 0 Location Zero Location Zero 0 1 1 Retransmit 1 0 0 Location Zero Unchanged X X X Read/Write 1 1 0 Increment () Increment) x x x NOTE: 2661 tbl 09 1. Pointer will Increment if flag is HIGH. TABLE II RESET AND FIRST LOAD DEPTH EXPANSION/COMPOUND EXPANSION MODE Inputs Internal Status Outputs Mode RS FL xl Read Pointer Write Pointer EF FF Reset First Device 0 0 (1) Location Zero Location Zero 0 1 Reset all Other Devices 1 (1) Location Zero Location Zero 0 1 Read/Write x (1) x x x x NOTES: 2661 tbl 10 1. Xlis connected to XO of previous device. See Figure 14. 2. RS = Reset Input, FL/RT = First Load/Retransmit, EF = Empty Flag Output, FF = Full Flag Output, XI = Expansion Input, HF = Half-Full Flag Output =I FULL wl Vcc EMPTY 2661 drw 16 Figure 14. Block Diagram of 6,144 x 9, 12,288 x 9, 24,576 x 9, 49,152 x 9, 98,304 x 9, 196,608 x 9 FIFO Memory (Depth Expansion) 11IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9 MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES Qo-Qs Q9-Q17 Q(N-8) -QN ee Qo-Qs Q9-Q17 Q(N-8) -QN IDT7203 IDT7203 IDT7203 IDT7204 IDT7204 IDT7204 IDT7205 IDT7205 IDT7205 IDT7206 IDT7206 IDT7206 IDT7207 IDT7207 IDT7207 R, W, RS } IDT7208 > IDT7208 ad IDT7208 DEPTH DEPTH DEPTH EXPANSION EXPANSION EXPANSION BLOCK BLOCK BLOCK 4y Do -D8 Do-DN Do -DN NOTES: 1. For depth expansion block see section on Depth Expansion and Figure 14. 2. For Flag detection see section on Width Expansion and Figure 13. Figure 15. Compound FIFO Expansion fl D(n-8)-DN 2661 drw 17 D(N-8)-DN SYSTEM A < QA 0-8 Ra" HFa | EFa 7205 |* WB 7206 7207 7208 | FFB Figure 16. Bidirectional FIFO Operation DT DB 0-8 7203 7204 > SYSTEM B 2661 drw 18 DATAIN x i {RPE twiz |. DATA ouT Figure 17. Read Data Flow-Through Mode #_ {WEF tak We ) t t REF DATA ouT VALID 2661 drw 19 12IDT7203/7204/7205/7206/7207/7208 CMOS ASYNCHRONOUS FIFO 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 and 65,536 x 9 RT OS ~N MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES We je | WPF ~a t RFF } FF 7 } t WFF s tOH DATA IN DATA IN VALID }-~ tDs DATA OUT 2661 drw 20 Figure 18. Write Data Flow-Through Mode ORDERING INFORMATION iDT XXXX X XX X X Device Type Power Speed Package Process/ Temperature Range |_| 7203 7204 7205 7206 7207 NOTES: 72088) Commercial (0C to +70C) Industrial (40 to +85C) Military (-55C to +125C) Compliant to MIL-STD-883, Class B Plastic DIP P28-1 Plastic Thin DIP P28-2 (all except 7207/7208) CERDIP D28-1 (all except 7208) Thin CERDIP D28-3 (only for 7203/7204/7205) Plastic Leaded Chip Carrier PLCC J32-1 Leadless Chip Carrier LCC L82-1 (all except 7208) Small Outline IC SOIC SO28-3 (only 7204) Commercial 7203/04 Only Commercial Only Commercial and Industrial Military Only Commercial Only Military 7203/04 Only Access Time (ta) Speed in Nanoseconds Military 7203/04DB Only Low Power 2,048 x 9 FIFO 4,096 x 9 FIFO 8,192 x 9 FIFO 16,384 x 9 FIFO 32,768 x 9 FIFO 65,536 x 9 FIFO 2661 drw 21 1. Industrial temperature range is available for plastic packages by special order for speed grades faster than 25 ns (excluding the 7208). 2. The LCC is only available in the military temperature range. 3. The 7208 is only available in commercial speed grades of 20, 25 and 35 ns. 13