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IS41LV16100D
FEATURES
• TTLcompatibleinputsandoutputs;tristateI/O
• RefreshInterval:
— Auto refresh Mode: 1,024 cycles /16 ms
—
RAS-Only,CAS-before-RAS(CBR),andHidden
— Self refresh Mode: 1,024 cycles /128 ms
• JEDECstandardpinout
• Singlepowersupply:
3.3V ± 10%
• ByteWriteandByteReadoperationviatwoCAS
• IndustrialTemperatureRange:-40oC to +85oC
DESCRIPTION
The ISSI IS41LV16100D is a 1,048,576 x 16-bit high-
performanceCMOSDynamicRandomAccessMemories.
ThesedevicesofferacycleaccesscalledExtendedData
Out(EDO)PageMode.EDOPage Mode allows1,024
random accesses within a single row with access cycle
time as short as 30 ns per 16-bit word. It is asynchronous,
as it does not require a clock signal input to synchronize
commandsandI/O.
Thesefeatures maketheIS41LV16100D ideally suited
for high-bandwidth graphics, digital signal processing,
high-performance computing systems, and peripheral
applications that run without a clock to synchronize with
theDRAM.
TheIS41LV16100Dispackagedina42-pin400-milSOJ
and400-mil50/44pinTSOP(TypeII).
1Mx16
16Mb DRAM WITH EDO PAGE MODE
KEY TIMING PARAMETERS
Parameter -50 Unit
Max. RASAccessTime(trac) 50 ns
Max. CASAccessTime(tcac) 14 ns
Max.ColumnAddressAccessTime(taa) 25 ns
Min.EDOPageModeCycleTime(tpc) 30 ns
Min.Read/WriteCycleTime(trc) 85 ns
PRELIMINARY INFORMATION
MARCH 2016
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Rev. 0A
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IS41LV16100D
PIN CONFIGURATIONS
50(44)-Pin TSOP (Type II)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
VDD
I/O0
I/O1
I/O2
I/O3
VDD
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VDD
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
VDD
I/O0
I/O1
I/O2
I/O3
VDD
I/O4
I/O5
I/O6
I/O7
NC
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VDD
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
GND
PIN DESCRIPTIONS
A0-A9 Address Inputs
I/O0-15 DataInputs/Outputs
WE WriteEnable
OE OutputEnable
RAS RowAddressStrobe
UCAS Upper Column Address Strobe
LCAS LowerColumnAddressStrobe
Vdd Power
GND Ground
NC No Connection
42-Pin SOJ
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IS41LV16100D
FUNCTIONAL BLOCK DIAGRAM
OE
WE
LCAS
UCAS CAS WE
OE
DATA I/O BUS
COLUMN DECODERS
SENSE AMPLIFIERS
MEMORY ARRAY
1,048,576 x 16
ROW DECODER
DATA I/O BUFFERS
CAS
CLOCK
GENERATOR
WE
CONTROL
LOGICS
OE
CONTROL
LOGIC
I/O0-I/O15
RAS
RAS
A0-A9
RAS
CLOCK
GENERATOR
REFRESH
COUNTER
ADDRESS
BUFFERS
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IS41LV16100D
TRUTH TABLE(5)
Function RAS LCAS UCAS WE OE Address tR/tC I/O
Standby H X X X X X High-Z
Read:Word L L L H L ROW/COL Dout
Read:LowerByte L L H H L ROW/COL LowerByte,Dout
UpperByte,High-Z
Read:UpperByte L H L H L ROW/COL LowerByte,High-Z
UpperByte,Dout
Write:Word(EarlyWrite) L L L L X ROW/COL Din
Write:LowerByte(EarlyWrite) L L H L X ROW/COL LowerByte,Din
UpperByte,High-Z
Write:UpperByte(EarlyWrite) L H L L X ROW/COL LowerByte,High-Z
UpperByte,Din
Read-Write(1,2) L L L H→L L→H ROW/COL Dout,Din
EDOPage-ModeRead(2) 1stCycle: L H→L H→L H L ROW/COL Dout
2ndCycle: L H→L H→L H L NA/COL Dout
AnyCycle: L L→H L→H H L NA/NA Dout
EDOPage-ModeWrite(1) 1stCycle: L H→L H→L L X ROW/COL Din
2ndCycle: L H→L H→L L X NA/COL Din
EDOPage-Mode(1,2) 1stCycle: L H→L H→L H→L L→H ROW/COL Dout,Din
Read-Write 2ndCycle: L H→L H→L H→L L→H NA/COL Dout,Din
HiddenRefresh Read(2) L→H→L L L H L ROW/COL Dout
Write(1,3) L→H→L L L L X ROW/COL Dout
RAS-OnlyRefresh L H H X X ROW/NA High-Z
CBRRefresh(4) H→L L L H X X High-Z
Notes:
1. TheseWRITEcyclesmayalsobeBYTEWRITEcycles(eitherLCAS or UCAS active).
2. TheseREADcyclesmayalsobeBYTEREADcycles(eitherLCAS or UCAS active).
3. EARLYWRITEonly.
4. At least one of the two CAS signals must be active (LCAS or UCAS).
5. Commands valid only after proper initialization.
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IS41LV16100D
Functional Description
TheIS41LV16100DisaCMOSDRAMoptimizedfor
high-
speed
bandwidth,
lowpowerapplications.DuringREADor
WRITEcycles,eachbitisuniquelyaddressedthroughthe
16addressbits.Theseareenteredtenbits(A0-A9)attime.
TherowaddressislatchedbytheRowAddressStrobe
(RAS).ThecolumnaddressislatchedbytheColumnAd-
dress Strobe (CAS).
RAS is used to latch the first nine bits
and CAS is used to latch the latter nine bits.
The
IS41LV16100D
has two CAS controls, LCAS and UCAS.
TheLCAS and UCAS inputs internally generates a CAS signal
functioning in an identical manner to the single CAS input on
theother1Mx16DRAMs.
ThekeydifferenceisthateachCAS
controlsitscorrespondingI/Otristatelogic(
in conjunction with
OE and WE and RAS). LCAScontrolsI/O0throughI/O7and
UCAScontrolsI/O8throughI/O15.
TheIS41LV16100DCAS function is determined by the
first CAS (LCAS or UCAS)transitioningLOWandthelast
transitioningbackHIGH.ThetwoCAS controls give the
IS41LV16100D BYTE READ and BYTE WRITE cycle
capabilities.
Memory Cycle
A memory cycle is initiated by bring RASLOWanditis
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or aborted
before the minimum tras time has expired. A new cycle
must not be initiated until the minimum precharge time
trp, tcp has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WEHIGH.Thecolumn
address must be held for a minimum time specified by tar.
DataOutbecomesvalidonlywhentrac, taa, tcac and toea
are all satisfied. As a result, the access time is dependent
on the timing relationships between these parameters.
Write Cycle
A write cycle is initiated by the falling edge of CAS and WE,
whicheveroccurslast.Theinputdatamustbevalidator
before the falling edge of CAS or WE, whichever occurs first.
Auto Refresh Cycle
Toretaindata,1,024refreshcyclesarerequiredineach
16msperiod.Therearetwowaystorefreshthememory.
1. By clocking each of the 1,024 row addresses (A0 through
A9) with RAS at least once every tref max. Any read, write,
read-modify-write or RAS-only cycle refreshes the addressed
row.
2. Using a CAS-before-RAS refresh cycle. CAS-before-
RAS refresh is activated by the falling edge of RAS, while
holding CASLOW.InCAS-before-RAS refresh cycle,
an internal 9-bit counter provides the row addresses
and the external address inputs are ignored.
CAS-before-RAS is a refresh-only mode and no data
accessordevice selection is allowed.Thus,theoutput
remainsintheHigh-Zstateduringthecycle.
Self Refresh Cycle
TheSelfRefreshallowstheuseradynamicrefresh,data
retention mode at the extended refresh period of 128 ms.
i.e.,125µsperrowwhenusingdistributedCBRrefreshes.
Thefeaturealsoallowstheuserthechoiceofafullystatic,
lowpowerdataretentionmode.TheoptionalSelfRefresh
featureisinitiatedbyperformingaCBRRefreshcycleand
holding RASLOWforthespeciedtRAS.
The Self Refresh mode is terminated by driving RAS
HIGHforaminimumtimeoftRP.Thisdelayallowsforthe
completion of any internal refresh cycles that may be in
process at the time of the RASLOW-to-HIGHtransition.If
theDRAMcontrollerusesadistributedrefreshsequence,
aburstrefreshisnotrequireduponexitingSelfRefresh.
However,iftheDRAMcontrollerutilizesaRAS-only or burst
refresh sequence, all 1,024 rows must be refreshed within
the average internal refresh rate, prior to the resumption
of normal operation.
Extended Data Out Page Mode
EDO page mode operation permits all 1,024 columns
within a selected row to be randomly accessed at a high
data rate.
InEDOpagemodereadcycle,thedata-outisheldtothe
next CAS cycle’s falling edge, instead of the rising edge.
Forthisreason,thevaliddataoutputtimeinEDOpage
mode is extended compared with the fast page mode. In
the fast page mode, the valid data output time becomes
shorter as the CAScycletimebecomesshorter.There-
fore,inEDOpagemode,thetimingmargininreadcycle
is larger than that of the fast page mode even if the CAS
cycle time becomes shorter.
InEDOpagemode,duetotheextendeddatafunction,
the CAS cycle time can be shorter than in the fast page
mode if the timing margin is the same.
TheEDOpagemodeallowsbothreadandwriteoperations
during one RAS cycle, but the performance is equivalent
to that of the fast page mode in that case.
Power-On
During Power-On, RAS, UCAS, LCAS, and WE must
all track with Vdd (HIGH) to avoid current surges,
and allow initialization to continue. An initial pause of
200 µs is required followed by a minimum of eight initial-
ization cycles (any combination of cycles containing a
RAS signal).
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IS41LV16100D
CAPACITANCE(1,2)
Symbol Parameter Max. Unit
Cin1 Input Capacitance: A0-A9 5 pF
Cin2 Input Capacitance: RAS, UCAS, LCAS, WE, OE 7 pF
Cio DataInput/OutputCapacitance:I/O0-I/O15 7 pF
Notes:
1. Testedinitiallyandafteranydesignorprocesschangesthatmayaffecttheseparameters.
2. Testconditions:T
a=25°C,f=1MHz.
Symbol Parameters Rating Unit
VtVoltage on Any Pin Relative to GND –0.5 to +4.6 V
Vdd Supply Voltage –0.5 to +4.6 V
Iout Output Current 50 mA
PdPower Dissipation 1 W
TaIndustrial Temperature –40 to +85 °C
Tstg Storage Temperature –55 to +125 °C
ABSOLUTE MAXIMUM RATINGS(1)
Note:
1. StressgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGSmaycausepermanentdamagetothedevice.Thisisa
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sectionsofthisspecicationisnotimplied.Exposuretoabsolutemaximumratingconditionsforextendedperiodsmayaffectreli-
ability.
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)
Symbol Parameter Test Condition Min. Typ. Max. Unit
Vdd Supply Voltage 3.0 3.3 3.6 V
Vih InputHighVoltage 2.0 — Vdd + 0.3 V
Vil InputLowVoltage –0.3 — 0.8 V
iil InputLeakageCurrent Any input 0V < Vin < Vdd –5 5 µA
Otherinputsnotundertest=0V
iio OutputLeakageCurrent Outputisdisabled(Hi-Z) –5 5 µA
0V < Vout < Vdd
Voh OutputHighVoltageLevel ioh = –2.0 mA 2.4 — V
Vol OutputLowVoltageLevel iol = 2.0 mA — 0.4 V
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IS41LV16100D
Symbol Parameter Test Condition Max. Unit
idd1 Stand-byCurrent:TTL RAS, LCAS, UCAS ≥ Vih 2 mA
idd2 Stand-byCurrent:CMOS RAS, LCAS, UCAS ≥ Vdd – 0.2V 1 mA
idd3 OperatingCurrent: RAS, LCAS, UCAS,90 mA
RandomRead/Write(2,3,4) Address Cycling, trc = trc (min.)
Average Power Supply Current
idd4 OperatingCurrent: RAS = Vil, LCAS, UCAS,30 mA
Fast Page Mode(2,3,4) Cycling tpc = tpc (min.)
Average Power Supply Current
idd5 RefreshCurrent: RAS Cycling, LCAS, UCAS ≥ Vih 60 mA
RAS-Only(2,3) trc = trc (min.)
Average Power Supply Current
idd6 RefreshCurrent: RAS, LCAS, UCAS Cycling 60 mA
CBR(2,3,5) trc = trc (min.)
Average Power Supply Current
ELECTRICAL CHARACTERISTICS(1) (RecommendedOperationConditionsunlessotherwisenoted.)
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-OnlyorCBR)beforeproperdevice
operationisassured.TheeightRAS cycles wake-up should be repeated any time the tref refresh requirement is exceeded.
2.Dependentoncyclerates.
3. Specified values are obtained with minimum cycle time and the output open.
4.Column-addressischangedonceeachEDOpagecycle.
5.Enableson-chiprefreshandaddresscounters.
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IS41LV16100D
AC CHARACTERISTICS(1,2,3,4,5,6)
(RecommendedOperatingConditionsunlessotherwisenoted.)
-50 -60
Symbol Parameter Min. Max. Min. Max. Units
trc RandomREADorWRITECycleTime 85 — 110 — ns
trac AccessTimefromRAS(6,7) — 50 — 60 ns
tcac AccessTimefromCAS(6, 8, 15) — 14 — 15 ns
taa AccessTimefromColumn-Address(6) — 25 — 30 ns
tras RASPulseWidth 50 10K 60 10K ns
trp RASPrechargeTime 30 — 40 — ns
tcas CASPulseWidth(26) 8 10K 10 10K ns
tcp CASPrechargeTime(9, 25) 9 — 10 — ns
tcsh CASHoldTime(21) 50 — 60 — ns
trcd RAS to CASDelayTime(10, 20) 12 37 20 45 ns
tasr Row-AddressSetupTime 0 — 0 — ns
trah Row-AddressHoldTime 8 — 10 — ns
tasc Column-AddressSetupTime(20) 0 — 0 — ns
tcah Column-AddressHoldTime(20) 8 — 10 — ns
tar Column-AddressHoldTime 30 — 40 — ns
(referenced to RAS)
trad RAStoColumn-AddressDelayTime(11) 14 25 15 30 ns
tral Column-Address to RASLeadTime 25 — 30 — ns
trpc RAS to CASPrechargeTime 5 — 5 — ns
trsh RASHoldTime(27) 14 — 15 — ns
trhcp RASHoldTimefromCASPrecharge 37 — 37 — ns
tclz CAStoOutputinLow-Z(15, 29) 0 — 0 — ns
tcrp CAS to RASPrechargeTime(21) 5 — 5 — ns
tod OutputDisableTime(19, 28, 29) 3 12 3 12 ns
toe/toea OutputEnableTime(15, 16) — 14 — 15 ns
toehc OEHIGHHoldTimefromCASHIGH 15 — 15 — ns
toep OEHIGHPulseWidth 10 — 10 — ns
toes OELOWtoCASHIGHSetupTime 5 — 5 — ns
trcs ReadCommandSetupTime(17,20) 0 — 0 — ns
trrh ReadCommandHoldTime 0 — 0 — ns
(referenced to RAS)(12)
trch ReadCommandHoldTime 0 — 0 — ns
(referenced to CAS)(12,17,21)
twch WriteCommandHoldTime(17,27) 8 — 10 — ns
twcr WriteCommandHoldTime 40 — 50 — ns
(referenced to RAS)(17)
Integrated Silicon Solution, Inc. — www.issi.com 9
Rev. 0A
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IS41LV16100D
AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)
(RecommendedOperatingConditionsunlessotherwisenoted.)
-50 -60
Symbol Parameter Min. Max. Min. Max. Units
twp WriteCommandPulseWidth(17) 8 — 10 — ns
twpz WEPulseWidthstoDisableOutputs 10 — 10 — ns
trwl WriteCommandtoRASLeadTime(17) 13 — 15 — ns
tcwl WriteCommandtoCASLeadTime(17,21) 8 — 15 — ns
twcs WriteCommandSetupTime(14,17,20) 0 — 0 — ns
tdhr Data-inHoldTime(referencedtoRAS) 39 — 40 — ns
tach Column-AddressSetupTimetoCAS precharge 15 — 15 — ns
duringWRITEcycle
toeh OEHoldTimefromWE during 14 — 15 — ns
READ-MODIFY-WRITEcycle(18)
tds Data-InSetupTime(15, 22) 0 — 0 — ns
tdh Data-InHoldTime(15, 22) 8 — 15 — ns
trwc READ-MODIFY-WRITECycleTime 110 — 155 — ns
trwd RAS to WEDelayTimeduring 65 — 85 — ns
READ-MODIFY-WRITECycle(14)
tcwd CAS to WEDelayTime(14, 20) 26 — 40 — ns
tawd Column-Address to WEDelayTime(14) 40 — 55 — ns
tpc EDOPageModeREADorWRITE 30 — 40 — ns
CycleTime(24)
trasp RASPulseWidthinEDOPageMode 50 100K 60 100K ns
tcpa AccessTimefromCAS Precharge(15) — 30 — 35 ns
tprwc EDOPageModeREAD-WRITE 56 — 56 — ns
CycleTime(24)
tcoh DataOutputHoldafterCASLOW 5 — 5 — ns
toff OutputBufferTurn-OffDelayfrom 3 12 3 15 ns
CAS or RAS(13,15,19, 29)
twhz OutputDisableDelayfromWE 3 10 3 15 ns
tclch LastCASgoingLOWtoFirstCAS 10 — 10 — ns
returningHIGH(23)
tcsr CASSetupTime(CBRREFRESH)(30, 20) 5 — 5 — ns
tchr CASHoldTime(CBRREFRESH)(30, 21) 8 — 10 — ns
tord OESetupTimepriortoRAS during 0 — 0 — ns
HIDDENREFRESHCycle
twrp WESetupTime(CBRRefresh) 5 — 5 — ns
twrh WEHoldTime(CBRRefresh) 8 — 10 — ns
tref AutoRefreshPeriod(1,024Cycles) — 16 — 16 ms
tref SelfRefreshPeriod(1,024Cycles) — 128 — 128 ms
tt TransitionTime(RiseorFall)(2, 3) 1 50 1 50 ns
Note:
The-60timingparametersareshownforreferenceonly.The-50speedoptionsupports50nsand60nstimingspecications.
10 Integrated Silicon Solution, Inc. — www.issi.com
Rev. 0A
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IS41LV16100D
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-OnlyorCBR)beforeproperdevice
operationisassured.TheeightRAS cycles wake-up should be repeated any time the tref refresh requirement is exceeded.
2.
Vih (MIN) and Vil(MAX)arereferencelevelsformeasuringtimingofinputsignals.Transitiontimes,aremeasuredbetweenVih
and Vil (or between Vil and Vih) and assume to be 1 ns for all inputs.
3. In addition to meeting the transition rate specification, all input signals must transit between Vih and Vil (or between Vil and Vih)
in a monotonic manner.
4. If CAS and RAS = Vih,dataoutputisHigh-Z.
5. If CAS = Vil,dataoutputmaycontaindatafromthelastvalidREADcycle.
6.MeasuredwithaloadequivalenttooneTTLgateand50pF.
7.Assumesthattrcd ≤ trcd(MAX).Iftrcd is greater than the maximum recommended value shown in this table, trac will increase
by the amount that trcd exceeds the value shown.
8. Assumes that trcd ≤ trcd(MAX).
9. If CASisLOWatthefallingedgeofRAS,dataoutwillbemaintainedfromthepreviouscycle.Toinitiateanewcycleandclearthe
data output buffer, CAS and RAS must be pulsed for tcp.
10.Operationwiththetrcd(MAX)limitensuresthattrac(MAX)canbemet.trcd(MAX)isspeciedasareferencepointonly;iftrcd
is greater than the specified trcd(MAX)limit,accesstimeiscontrolledexclusivelybytcac.
11.Operationwithinthetrad(MAX)limitensuresthattrcd(MAX)canbemet.trad(MAX)isspeciedasareferencepointonly;iftrad
is greater than the specified trad (MAX)limit,accesstimeiscontrolledexclusivelybytaa.
12.Eithertrch or trrhmustbesatisedforaREADcycle.
13. toff(MAX)denesthetimeatwhichtheoutputachievestheopencircuitcondition;itisnotareferencetoVoh or Vol.
14. twcs, trwd, tawd and tcwdarerestrictiveoperatingparametersinLATEWRITEandREAD-MODIFY-WRITEcycleonly.Iftwcs ≤
twcs(MIN),thecycleisanEARLYWRITEcycleandthedataoutputwillremainopencircuitthroughouttheentirecycle.Iftrwd ≤
trwd (MIN), tawd ≤ tawd (MIN) and tcwd ≤ tcwd(MIN),thecycleisaREAD-WRITEcycleandthedataoutputwillcontaindataread
fromtheselectedcell.Ifneitheroftheaboveconditionsismet,thestateofI/O(ataccesstimeanduntilCAS and RAS or OE go
back to Vih) is indeterminate. OEheldHIGHandWEtakenLOWafterCASgoesLOWresultinaLATEWRITE(OE-controlled)
cycle.
15.Outputparameter(I/O)isreferencedtocorrespondingCASinput,I/O0-I/O7byLCASandI/O8-I/O15byUCAS.
16.DuringaREADcycle,ifOEisLOWthentakenHIGHbeforeCASgoesHIGH,I/Ogoesopen.IfOEistiedpermanentlyLOW,a
LATEWRITEorREAD-MODIFY-WRITEisnotpossible.
17.WritecommandisdenedasWE going low.
18.LATEWRITEandREAD-MODIFY-WRITEcyclesmusthavebothtod and toeh met (OEHIGHduringWRITEcycle)inorderto
ensurethattheoutputbufferswillbeopenduringtheWRITEcycle.TheI/OswillprovidethepreviouslywrittendataifCAS remains
LOWandOEistakenbacktoLOWaftertoeh is met.
19.TheI/OsareinopenduringREADcyclesoncetod or toff occur.
20.TherstχCASedgetotransitionLOW.
21.ThelastχCASedgetotransitionHIGH.
22.TheseparametersarereferencedtoCASleadingedgeinEARLYWRITEcyclesandWEleadingedgeinLATEWRITEorREAD-
MODIFY-WRITEcycles.
23.LastfallingχCAS edge to first rising χCAS edge.
24.LastrisingχCAS edge to next cycle’s last rising χCAS edge.
25.LastrisingχCAS edge to first falling χCAS edge.
26.EachχCAS must meet minimum pulse width.
27.LastχCAStogoLOW.
28.I/Oscontrolled,regardlessUCAS and LCAS.
29.The3nsminimumisaparameterguaranteedbydesign.
30.Enableson-chiprefreshandaddresscounters.
AC TEST CONDITIONS
Output load: One TTL Load and 50 pF
Input timing reference levels: Vih = 2.0V, Vil = 0.8V
Output timing reference levels: Voh = 2.4V, Vol = 0.4V
Integrated Silicon Solution, Inc. — www.issi.com 11
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IS41LV16100D
READ CYCLE
Note:
1. toff is referenced from rising edge of RAS or CAS, whichever occurs last.
t
RAS
t
RC
t
RP
t
AR
t
CAH
t
ASC
t
RAD
t
RAL
OE
I/O
WE
ADDRESS
UCAS/LCAS
RAS
Row Column Row
Open Open
Valid Data
t
CSH
t
CAS
t
RSH
t
CRP
t
CLCH
t
RCD
t
RAH
t
ASR
t
RRH
t
RCH
t
RCS
t
AA
t
CAC
t
OFF(1)
t
RAC
t
CLC
t
OES
t
OE
t
OD
Don’tCare
Undefined
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IS41LV16100D
EARLY WRITE CYCLE (OE=DON'TCARE)
t
RAS
t
RC
t
RP
t
AR
t
CAH
t
ASC
t
RAD
t
RAL
t
ACH
I/O
WE
ADDRESS
UCAS/LCAS
RAS
Row Column Row
t
CSH
t
CAS
t
RSH
t
CRP
t
CLCH
t
RCD
t
RAH
t
ASR
t
CWL
t
WCR
t
WCH
t
RWL
t
WP
t
WCS
t
DH
t
DS
t
DHR
Valid Data
Don’tCare
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IS41LV16100D
READ WRITE CYCLE (LATEWRITEandREAD-MODIFY-WRITECycles)
t
RAS
t
RWC
t
RP
t
AR
t
CAH
t
ASC
t
RAD
t
RAL
t
ACH
WE
OE
ADDRESS
UCAS/LCAS
RAS
Row Column Row
t
CSH
t
CAS
t
RSH
t
CRP
t
CLCH
t
RCD
t
RAH
t
ASR
t
RWD
t
CWL
t
CWD
t
RWL
t
AWD
t
WP
t
RCS
t
CAC
t
CLZ
t
DS
t
DH
t
OEH
t
OD
t
OE
t
RAC
t
AA
I/O Open Open
Valid D
OUT
Valid D
IN
Don’tCare
Undefined
14 Integrated Silicon Solution, Inc. — www.issi.com
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IS41LV16100D
EDO-PAGE-MODE READ CYCLE
Note:
1. tpc can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both
measurements must meet the tpc specifications.
t
RASP
t
RP
ADDRESS
UCAS/LCAS
RAS
Row Row
t
CAS,
t
CLCH
t
CRP
t
RCD
t
CSH
t
CP
t
CAS,
t
CLCH
t
CAH
t
CAS,
t
CLCH
t
RAL
t
RSH
t
CP
t
CP
t
PC
(1)
t
ASR
t
RAH
t
RAD
t
AR
Column Column
t
CAH
t
CAH
Column
t
ASC
t
ASC
OE
I/O
WE
Open Open
Valid Data
t
AA
t
AA
t
CPA
t
CAC
t
CAC
t
RAC
t
COH
t
CLZ
t
OEP
t
OE
t
OES
t
OES
t
OD
t
OE
t
OEHC
Valid Data
t
RCH
t
RRH
t
AA
t
CPA
t
CAC
t
OFF
t
CLZ
Valid Data
t
OD
t
ASC
t
RCS
Don’tCare
Undefined
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IS41LV16100D
EDO-PAGE-MODE EARLY-WRITE CYCLE
t
RASP
t
RP
ADDRESS
UCAS/LCAS
RAS
Row Row
t
CAS,
t
CLCH
t
CRP
t
RCD
t
CSH
t
CP
t
CAS,
t
CLCH
t
CAH
t
CAS,
t
CLCH
t
RAL
t
RSH
t
CP
t
CP
t
PC
t
ASR
t
RAH
t
RAD
t
AR
t
ACH
Column Column
t
ACH
t
ACH
t
CAH
t
CAH
Column
t
ASC
t
ASC
OE
I/O
WE
Valid Data
t
ASC
t
WCS
t
WCH
t
CWL
t
WP
t
RHCP
t
WCS
t
WCH
t
CWL
t
WP
t
DS
t
DH
t
DHR
t
WCR
t
WCS
t
WCH
t
CWL
t
WP
Valid Data
t
DS
t
DH
Valid Data
t
DS
t
RWL
t
DH
Don’tCare
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IS41LV16100D
EDO-PAGE-MODE READ-WRITE CYCLE(LATEWRITEandREAD-MODIFYWRITECycles)
Note:
1. tpc can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both
measurements must meet the tpc specifications.
Don’tCare
Undefined
tRASP tRP
ADDRESS
UCAS/LCAS
RAS
Row Row
tCRP tRCD
tCSH
tCP
tCAH
tCAS, tCLCH
tRAL
tRSH
tCPtCP
tRAH
tRAD
tAR
tASR
Column Column
tCAHtCAH
Column
tASCtASC
tCAS, tCLCH
tCAS, tCLCH
OE
I/O
WE
tASC
tRWD
tRCS tCWL
tWP
tAWD
tCWD
tDH
tDS
tCAC
tCLZ
tAWD
tCWD
tCWL
tWP
tAWD
tCWD
tCWL
tRWL
tWP
Open Open
D
IN
D
OUT
tOE tOE tOE
tOD
tOEH
tOD tOD
tDH
tDS
tCPA
tAA
tCAC
tCLZ
D
IN
D
OUT
tDH
tDS
tCAC
tCLZ
D
IN
D
OUT
tCPA
tAA
tRAC
tAA
tPC / tPRWC
(1)
Integrated Silicon Solution, Inc. — www.issi.com 17
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IS41LV16100D
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (PseudoREAD-MODIFYWRITE)
Don’tCare
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IS41LV16100D
AC WAVEFORMS
READ CYCLE (WithWE-ControlledDisable)
RAS-ONLY REFRESH CYCLE (OE, WE=DON'TCARE)
tAR
tCAH tASC
tASC
tRAD
OE
I/O
WE
ADDRESS
UCAS/LCAS
RAS
Row Column
Open Open
Valid Data
tCSH
tCAS
tCRP tRCD tCP
tRAHtASR
tRCH tRCS
tWPZ
tRCS
tAA
tCAC
tWHZ
tRAC
tCLZ
tCLZ
tOE tOD
Column
tRAS
tRC
tRP
I/O
ADDRESS
UCAS/LCAS
RAS
Row Row
Open
tCRP
tRAHtASR
tRPC
Don’tCare
Undefined
Don’tCare
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IS41LV16100D
HIDDEN REFRESH CYCLE(1) (WE=HIGH;OE=LOW)
CBR REFRESH CYCLE (Addresses; OE=DON'TCARE)
Notes:
1. AHiddenRefreshmayalsobeperformedafteraWriteCycle.Inthiscase,WE=LOWandOE=HIGH.
2. toff is referenced from rising edge of RAS or CAS, whichever occurs last.
tRAS tRAStRP tRP
I/O
UCAS/LCAS
RAS
WE
Open
tCP
tRPC
tCSR
tCHR tRPC
tCSR
tCHR
tWRP tWRP
tWRH tWRH
tRAS tRAS
tRP
UCAS/LCAS
RAS
tCRP tRCD tRSH tCHR
tAR
tASC
tRAD
ADDRESS Row Column
tRAHtASR
tRAL
tCAH
I/O Open Open
Valid Data
tAA
tCAC
tRAC
tCLZ
tOFF(2)
OE
tOE
tORD
tOD
Don’tCare
Undefined
20 Integrated Silicon Solution, Inc. — www.issi.com
Rev. 0A
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IS41LV16100D
Note:
The-50speedoptionsupports50nsand60nstimingspecications.
ORDERING INFORMATION :
Industrial Range: -40oC to +85oC
Speed (ns) Order Part No. Package
50 IS41LV16100D-50KI 400-milSOJ
IS41LV16100D-50KLI 400-milSOJ,Lead-free
IS41LV16100D-50TI 400-mil TSOP (Type II)
IS41LV16100D-50TLI 400-mil TSOP (Type II), Lead-free
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IS41LV16100D
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IS41LV16100D