SY89218U
Precision 1:15 LVDS Fanout Buffer with 2:1
MUX and Four ÷1/÷2/÷4 Clock Divider Output
Banks
Precision Edge is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
August 2007
M9999-082407-
C
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General Description
The SY89218U is a 2.5V precision, high-speed,
integrated clock divider and LVDS fanout buffer capable
of handling clocks up to 1.5GHz. Optimized for
communications applications, the four independently
controlled output banks are phase-matched and can be
configured for pass through (÷1), ÷2 or ÷4 divider ratios.
The differential input includes Micrel’s unique, 3-pin
input termination architecture that allows the user to
interface to any differential signal (AC- or DC-coupled)
as small as 100mV (200mV
PP
) without any level shifting
or termination resistor networks in the signal path. The
low-skew, low-jitter outputs are LVDS compatible with
extremely fast rise/fall times guaranteed to be less than
200ps.
The /MR (master reset) input asynchronously resets the
outputs. A four-clock delay after de-asserting /MR allows
the counters to synchronize and start the outputs from
the same state without any runt pulse.
The SY89218U is part of Micrel’s Precision Edge
®
product family. All support documentation can be found
at Micrel's web site at: www.micrel.com.
Features
• Low-skew LVDS output banks with independently
programmable ÷1, ÷2 and ÷4 divider options
• Four output banks, 15 total outputs
• Guaranteed AC performance over temperature and
voltage:
– Accepts a clock frequency up to 1.5GHz
– <1600ps IN-to-OUT propagation delay
– <200ps rise/fall time
– <35ps within bank skew
• Fail Safe Input
– Prevents outputs from oscillating
• Ultra-low jitter design:
– <1ps
RMS
random jitter
– <10ps
PP
total jitter (clock)
• Patent-pending input termination and VT pin accepts
DC- and AC-coupled inputs (CML, PECL, LVDS)
• LVDS-compatible outputs
• CMOS/TTL-compatible output enable (EN) and
divider select control
• 2.5V ±5% power supply
• –40°C to +85°C temperature range
• Available in 64-pin TQFP
Applications
• All SONET/SDH applications
• All Fibre Channel applications
• All Gigabit Ethernet applications
Markets
• LAN/WAN routers/switches
• Storage
• ATE
• Test and measurement
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August 2007
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Functional Block Diagram
Micrel, Inc. SY89218U
August 2007
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Ordering Information(1)
Part Number Package
Type Operating
Range Package Marking Lead
Finish
SY89218UHY T64-1 Industrial
SY89218UHY with
Pb-Free bar-line indicator Pb-Free
Matte-Sn
SY89218UHYTR
(2)
T64-1 Industrial SY89218UHY with
Pb-Free bar-line indicator Pb-Free
Matte-Sn
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A
= 25°C, DC Electricals only.
2. Tape and Reel.
Pin Configur ation
64-Pin EPAD-TQFP (T64-1)
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Pin Description
Pin Number Pin Name Pin Function
1, 2
3, 4
15, 16
17, 18
FSELA1, FSELA0
FSELB1, FSELB0
FSELC1, FSELC0
FSELD1, FSELD0
Single-Ended Inputs: These TTL/CMOS inputs select the divide ratio for each of the
four banks of outputs. Note that each of these inputs is internally connected to a 25k
pull-up resistor and will default to a logic HIGH state if left open. The input-switching
threshold is V
CC
/2.
5, 8,
11, 14 IN0, /IN0
IN1, /IN1 Differential Inputs: These input pairs are the differentia l signal inputs to the device.
These inputs accept AC- or DC-coupled sign als as small as 100mV. The input pairs
internally terminate to a VT pin through 50. Note that these inputs will default to an
indeterminate state if left open. Please refer to the “Input Interface Applications”
section for more details.
6, 12 VT0, VT1 Input Termination Center-Tap: Each side of a differential inp ut pair terminates to a VT
pin. The VT pin provides a center-tap to a termination network for maximum interface
flexibility. See “ Input Interface Applications” section for more details.
7,
13 VREF-AC0,
VREF-AC1 Reference Voltage: These outputs bias to V
CC
–1.2V. They are used for AC-couplin g
inputs IN and /IN. Connect VREF-AC directly to the corresponding VT pin. Bypass with
0.01µF low ESR capacitor to VCC. Due to limited drive c ap ability, the VREF-AC pin is
only intended to drive its respective VT pin. Maximum sink/source current is ±1.5mA.
Please refer to the “Input Interface Applications” section for more details.
9 /MR
Single-Ended Input: This TTL/CMOS-compatible master reset function asynchronousl y
sets the true outputs LOW, complimentary outputs HIGH, and holds them in that state
as long as /MR remains LOW. This input is internall y c onnected to a 25k pull-up
resistor and will default to logic HIGH state if left open. The input-switching threshold is
V
CC
/2.
10 CLK_SEL
Single-Ended Input: This single-ended TTL/CMOS-compatible input selects the inputs
to the multiplexer. Note that this input is internally conn ected to a 25k pull-up resistor
and will default to logic HIGH state if left open. The input-switching threshold is V
CC
/2.
20, 25, 30, 33,
40
41, 48, 50, 55,
62
VCC Positive Power Supply. Bypass with a 0.1µF||0.01µF low ESR capacitor as close to
V
CC
pin as possible.
21, 22
23, 24
26, 27
28, 29
/QC0, QC0
/QC1, QC1
/QC2, QC2
/QC3, QC3
Bank C LVDS differential output pairs controlle d by FSELC1 and FSELC0. Refer to
“Function Table” for details. Unuse d output pairs should be terminated with 100
across the differential pair
31 NC No connect.
34, 35,
36, 37
38, 39,
42, 43
44, 45,
46, 47
/QD0, QD0
/QD1, QD1
/QD2, QD2
/QD3, QD3
/QD4, QD4
/QD5, QD5
Bank D LVDS differential output pairs controlled by FSELD1 and FSELD0. Refer to
“Function Table” for details. Unuse d output pairs should be terminated with 100
across the differential pair
51, 52
53, 54 /QA0, QA0
/QA1, QA1 Bank A LVDS differential output pairs controlle d b y FSEL A1 and FSELA0. Refer to
“Function Table” for details. Unuse d output pairs should be terminated with 100
across the differential pair
56, 57
58, 59
60, 61
/QB0, QB0
/QB1, QB1
/QB2, QB2
Bank B LVDS differential output pairs controlle d b y FSEL B1 and FSELB0. Refer to
“Function Table” for details. Unuse d output pairs should be terminated with 100
across the differential pair
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Pin Description
(continued)
Pin Number Pin Name Pin Function
64 EN
Single-Ended Input: This TTL/CMOS input disables and e na bles the outputs. It is
internally connected to a 25k pull- up resistor and will default to logic HIGH state if left
open. When disabled, true ou tputs go LO W and complementary outputs switch to HIGH.
The input switching threshold is V
CC
/2. For the input enable and disable functional
description, refer to Figures 2d and 2e.
19, 32, 49, 63 GND,
Exposed Pad Ground and exposed pad mu st be connected to the same GND plane on the board.
Function Table
/MR
(1)
EN
(2, 3)
CLK_SEL FSELx0
(4)
FSELx1
(4)
Q
1 1 0 0 0 IN0÷1
1 1 1 0 0 IN1÷1
1 1 0 1 0 IN0÷2
1 1 1 1 0 IN1÷2
1 1 0 X 1 IN0÷4
1 1 1 X 1 IN1÷4
1 0 X X X 0
0 X X X X 0
Notes:
1. /MR asynchronously forces Q to LOW (/Q to HIGH).
2. EN forces Q LOW between 2 and 6 input clock cycles after the falling edge of EN. Refer to “Timing Diagram” section.
3. EN synchronously enables Q between two and six input clock cycles after the rising edge of EN. Refer to “Timing Diagram” section.
4. FSEL valid for each of the banks A, B, C, and D. Banks can be programmed independent of each other.
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Absolute Maximum Ratings(1)
Supply Voltage (V
CC
)...............................–0.5V to +4.0V
Input Voltage (V
IN
).......................................–0.5V to V
CC
Termination Current
Source or sink current on V
T
........................±100mA
Input Current
Source or sink current on IN, /IN ...................±50mA
V
REF-AC
Current
(3)
Source or sink current on V
REF-AC
....................±2mA
Operating Ratings(2)
Supply Voltage (V
IN
).....................+2.375V to +2.625V
Ambient Temperature (T
A
)..................–40°C to +85°C
Package Thermal Resistance
(4)
TQFP
Still-air (θ
JA
)............................................35°C/W
Junction-to-board (ψ
JB
) ..........................20°C/W
Lead Temperature (soldering, 20sec.)… ………….260°C
Storage Temperature (T
s
)……………...–65°C to +150°C
DC Electrical Characteristics(5)
V
CC
= +2.5V ±5%, T
A
= –40°C to +85°C, unless otherwise stated.
Symbol Parameter Condition Min Typ Max Units
V
CC
Positive Supply Voltage R ange 2.375 2.625 V
I
CC
Power Supply Current 325 420 mA
R
DIFF_IN
Differential Input Resistance
(IN-to-/IN) 90 100 110
R
IN
Input Resistance
(IN-to-V
T
, /IN-to-V
T
) 45 50 55
V
IH
Input HIGH Voltage (IN, /IN) 1.2 V
CC
V
V
IL
Input LOW Voltage (IN, /IN) 0 V
IH
–0.1 V
V
IN
Input Voltage Swing (IN, /IN) See Figure 1a, Note 6 0.1 2.5 V
V
DIFF_IN
Differential Input Voltage Swing
|IN – /IN| See Figure 1b 0.2 V
V
IN_FSI
Input Voltage Threshold that
Triggers FSI 30 100 mV
V
REF-AC
Reference Voltage V
CC
–1.3 V
CC
–1.2 V
CC
–1.1 V
V
T_IN
Voltage from Input to V
T
1.28 V
LVTTL/CMOS DC Electrical Characteristics(5)
V
CC
= +2.5V ±5%, T
A
= –40°C to +85°C, unless otherwise stated.
Symbol Parameter Condition Min Typ Max Units
V
IH
Input HIGH Voltage 2 V
V
IL
Input LOW Voltage 0.8 V
I
IH
Input HIGH Current –125 30 µA
I
IL
Input LOW Current -300 µA
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for
extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Due to the limited drive capability use for input of the same package only.
4. ψ
JB
and θ
JA
values are determined for a 4-layer board in still-air number, unless otherwise stated.
5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
6. V
IN
(max) is specified when V
T
is floating.
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LVDS Outputs DC Electrical Characteristics(7)
V
CC
= +2.5V ±5%, R
L
= 100 across the outputs; T
A
= –40°C to +85°C, unless otherwise stated.
Symbol Parameter Condition Min Typ Max Units
V
OUT
Output Voltage Swing (Q, /Q) See Figure 1a 250 325 mV
V
DIFF_OUT
Differential Output Voltage Swing
|Q – /Q| See Figure 1b 500 650 mV
V
OCM
Output Common Mode Voltage
(Q, /Q) See Figure 5b 1.125 1.20 1.275 V
∆V
OCM
Change in Common Mode Voltage
(Q, /Q) See Figure 5b –50 +50 mV
Notes:
7. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
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AC Electrical Characteristics(8)
V
CC
= +2.5V ±5%, R
L
= 100 across the outputs; T
A
= –40°C to +85°C, unless otherwise stated.
Symbol Parameter Condition Min Typ Max Units
f
MAX
Maximum Operating Frequency V
OUT
200mV 1.5 2 GHz
IN-to-Q 800 1250 1600 ps
CLK_SEL-to-Q 700 1000 1400 ps
t
PD
Differenti al Pro pagation Delay
/MR(H-L)-to-Q 700 1000 1400 ps
t
RR
Reset Recovery Time /MR (L-H)-to-IN 300 ps
t
PD
Tempco Differential Propagation Delay
Temperature Coefficient 225 fs/°C
Within-Bank Skew Within same fanout bank
(9. 10)
35 ps
Bank-to-Bank Skew Same divide setting
(11)
40 ps
Bank-to-Bank Skew Different divide setting
(11)
60 ps
t
SKEW
Part-to-Part Skew Note 12 400 ps
Random Jitter (RJ) Note 13 1 ps
RMS
Total Jitter (TJ) Note 14 10 ps
PP
t
JITTER
Cycle-to-Cycle Jitter Note 15 1 ps
RMS
t
r,
t
f
Output Rise/Fall Time
(20% to 80%) At full output swing 60 120 200 ps
Divide-by-2 or Divide-by-4 47 53 %
Divide-by-1, input > 1GHz 45 55 %
Duty Cycle
Divide-by-1, input < 1GHz 47 53 %
Notes:
8. Measured with 100mV input swing. Input t
r,
/t
f
< 300ps. See “Timing Diagrams” section for definition of parameters. High-frequency AC-
parameters are guaranteed by design and characterization.
9. Within-bank skew is the difference in propagation delays among the outputs within the same bank.
10. Skews within banks depend on the number of outputs. Within-bank skew decreases if the bank has lesser outputs.
11. Bank-to-bank skew is the difference in propagation delays between outputs from different banks. Bank-to-bank skew is also the phase offset
between each bank, after MR is applied.
12. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the
respective inputs.
13. Random jitter is measured with a K28.7 comma detect character pattern.
14. Total jitter definition: with an ideal clock input frequency f
MAX
, no more than one output edge in 10
12
output edges will deviate by more than the
specified peak-to-peak jitter value.
15. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, T
n
–T
n–1
where T is the time between rising edges of the output
signal.
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Functional Description
Clock Select (CLK_SEL)
CLK_SEL is an asynchronous TTL/CMOS compatible
input that selects one of the two input signals. Internal
25k pull-up resistor defaults the input to logic HIGH if
left open. Delay between the clock selection and
multiplexer selecting the correct input signal depends
upon the divider settings. The delay varies due to the
asynchronous nature of the input. Input switching
threshold is V
CC
/2. Refer to Figure 2a.
Fail-Safe Input (FSI)
The input includes a special failsafe circuit to sense
the amplitude of the input signal and to latch the
outputs when there is no input signal present, or when
the amplitude of the input signal drops sufficiently
below 100mV
PK
(200mV
PP
), typically 30mV
PK
.
Maximum frequency of the SY89218U is limited by the
FSI function. Refer to Figure 2b.
Input Clock Failure Case
If the input clock fails to a floating, static, or extremely
low signal swing, the FSI function will eliminate a
metastable condition and guarantee a stable output
signal. No ringing and no undetermined state will
occur at the output under these conditions.
Please note that the FSI function will not prevent duty
cycle distortion in case of a slowly deteriorating (but
still toggling) input signal. Due to the FSI function, the
propagation delay will depend upon rise and fall time
of the input signal and on its amplitude. Refer to
“Typical Operating Characteristics” for detailed
information.
Master Reset (/MR)
/MR is a TTL/CMOS compatible input that resets the
output signals. Internal 25k pull-up resistor defaults
the input to logic HIGH if left open. A LOW input to
/MR asynchronously sets the true outputs LOW and
complimentary outputs HIGH. The outputs will remain
in this state until /MR is forced HIGH. Input switching
threshold is V
CC
/2. Refer to Figure 2c.
Enable Outputs (EN)
EN is a synchronous TTL/CMOS compatible input that
enables/disables the outputs based on the input to
this pin. Internal 25k pull-up resistor defaults the
input to logic HIGH if left open. A logic LOW input
causes the true outputs to go LOW and
complementary outputs to go HIGH. It takes 2 to 6
input clock cycles before the outputs are
enabled/disabled because the signals are going
through a series of flip-flops. Input switching threshold
is V
CC
/2. Refer to Figure 2d and 2e.
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Single-Ended Differential Swings
Figure 1a. Single-Ended Voltage Swing
Figure 1b. Differential Voltage Swing
Timing Diagrams
Figure 2a. Propagatio n Delay
Figure 2b. Fail Safe Feature
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Timing Diagrams
Figure 2c. Reset w i th Output Enabled
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Timing Diagrams
Figure 2d. Enab le Timing
Figure 2e. Disable Timing
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Typical Operating Character i stics
V
CC
= 2.5V, GND = 0V, V
IN
= 100mV, R
L
= 100 across the outputs, T
A
= 25°C, unless otherwise stated.
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Functional Characteristics
V
CC
= 2.5V, GND = 0V, V
IN
= 100mV, R
L
= 100 across the outputs, T
A
= 25°C, unless otherwise stated.
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Input Stage Internal Termination
Figure 3. Simplified Differential Input Stage
Input Interface Applications
Figure 4a. CML Interface
(DC-Coupled)
Option: May connect V
T
to VCC
Figure 4b. CML Interface
(AC-Coupled)
Figure 4c. LVPECL Interface
(DC-Coupled)
Figure 4d. LVPECL Interface
(AC-Coupled)
Figure 4e. LVDS Interface
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LVDS Output Interface Applications
LVDS specifies a small swing of 325mV typical, on a
nominal 1.2V common mode above ground. The
common mode voltage has tight limits to permit large
variations in the ground between and LVDS driver and
receiver. Also, change in common mode voltage, as a
function of data input, is kept to a minimum, to keep
EMI low.
Figure 5a. LVDS Differential Measu rement
Figure 5b. LVDS Common Mode Measurement
Related Product an d Support Documentation
Part Number Function Data Sheet Link
SY89221U Precision 1:15 LVPECL Fanout Buffer with 2:1 MUX
and Four ÷1/÷2/÷4 Clock Divider O utput Banks http://www.micrel.com/_PDF/HBW/sy89221u.pdf
SY89200U Ultra-Precision 1:8 LVDS Fanout with Three
÷1/÷2/÷4 Clock Divider Output Banks http://www.micrel.com/_PDF/HBW/sy89200u.pdf
SY89202U Ultra-Precision 1:8 LVPECL Fanout with Three
÷1/÷2/÷4 Clock Divider Output Banks http://www.micrel.com/_PDF/HBW/sy89202u.pdf
HBW Solutions New Products and Applications http://www.micrel.com/page.do?page=/product-
info/as/HBWsolutions.shtml
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Package Information
64-Pin EPAD-TQFP (T64-1)
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for
its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a
product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for
surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant
injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk
and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.
© 2006 Micrel
,
Incor
p
orated.
