ANALOG DEVICES 2.1 V to 5.5 V, 2 yas, 10-Bit ADC in 8-Lead microSOIC/DIP AD 7810 FEATURES 10-Bit ADC with 2 xs Conversion Time Small Footprint 8-Lead microSOIC Package Specified Over a -40C to +105C Temperature Range Inherent Track-and-Hold Functionality Operating Supply Range: 2.7 V to 5.5 V Specifications at 2.7 V to 5.5 V Microcontroller Compatible Serial Interface Optional Automatic Power Down at End of Conversion Low Power Operation 270 pW at 10 kSPS Throughput Rate 2.7 mW at 100 kSPS Throughput Rate Analog Input Range: 0 V to Vper Reference Input Range: 0 V to Vpp APPLICATIONS Low Power, Hand-Held Portable Applications that Require Analog-to-Digital Conversion with 10-Bit Accuracy; e.g., Battery Powered Test Equipment, Battery Powered Communications Systems GENERAL DESCRIPTION The AD7810 is a high speed, low power, 10-bit A/D con- verter that operates from a single 2.7 V to 5.5 V supply. The part contains a 2 us successive approximation A/D converter, with inherent track/hold functionality, a pseudo differential input and a high speed serial interface that interfaces to most microcontrollers. The AD7810 is fully specified over a tem- perature range of -40C to +105C. By using a technique that samples the state of the CONVST (convert start) signal at the end of a conversion, the AD7810 may be used in an automatic power-down mode. When used in this mode, the AD7810 automatically powers down at the end of a conversion and wakes up at the start of a new conversion. This feature significantly reduces the power consumption of the part at lower throughput rates. The AD7810 can also operate in a high speed mode where the part is not powered down between conversions. In this high speed mode of operation, the conver- sion time of the AD7810 is 2 us. The maximum throughput rate is dependent on the speed of the serial interface of the micro- controller. The part is available in a srnall 8-pin, 0.3" wide, plastic dual-in- line package (mini-DIP)}; in an 8-lead, small outline IC (SOIC); and in an 8-lead microSOIC package. REV.0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. FUNCTIONAL BLOCK DIAGRAM Ypp AGND VReF AD7810 CHARGE REDISTRIBUTION SERIAL Dour DAC Hy PORT SCLK j Vint CONTROL " LoGic CONVET PRODUCT HIGHLIGHTS 1. Complete, 10-Bit ADC in 8-Pin Package The AD7810 is a 10-bit 2 ws ADC with inherent track/hold functionaliry and a high speed serial interfaceall in an 8-lead microSOIC package. Vpzp may be connected to Vpp to eliminate the need for an external reference. The result is a high speed, low power, space saving ADC solution. to . Low Power, Single Supply Operation The AD7810 operates from a single +2.7 V to +5.5 V supply and typically consumes only 9 mW of power while convert- ing. The power dissipation can be significantly reduced at lower throughput rates by using the automatic power-down mode, e.g., at a throughput rate of 10 KSPS the power consumption is only 270 Ey. 3. Automatic Power-Down The automatic power-down mode, whereby the AD7810 powers down at the end of a conversion and wakes up before the next conversion, means the AD7810 is ideal for battery powered applications. See Power vs. Throughput Rate section. 4. Serial Interface An easy to use, fast serial interface allows connection to most popular microprocessors with no external circuitry. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 Analog Devices, Inc., 1997AD 781 0-SPEC | FI CATI 0 NS (GND = 0 V, Vper = +pp. All specifications -40C to +105C unless otherwise noted.) Parameter Y Version Units Test Conditions/Comments DYNAMIC PERFORMANCE fy = 30 kHz, feampre = 350 kHz Signal to (Noise + Distortion) Ratio! 58 dB min Total Harmonic Distortion 64 dB max Peak Harmonic or Spurious Noise 64 dB max Intermodulation Distortion" fa = 48 kHz, fb = 48.5 kHz 2nd Order Terms 67 dB typ 3rd Order Terms 67 dB typ DC ACCURACY Resolution 10 Bits Relative Accuracy +1 LSB max Differential Nonlinearity (ONL)! +1 LSB max Offset Error! +2 LSB max Gain Error! +2 LSB max Minimum Resolution for Which No Missing Codes Are Guaranteed 10 Bits ANALOG INPUT Input Voltage Range 0 V min VRer V max Input Leakage Current? +1 pA max Input Capacitance" 15 pF max REFERENCE INPUTS? Vrnr Input Voltage Range 1.2 V min Vop V max Input Leakage Current +3 pA max Input Capacitance 20 pF max LOGIC INPUTS? Vin, Input High Voltage 2.0 VY min Vint, Input Low Voltage 0.4 V max Input Current, In +1 pA max Typically 10 nA, Vpq = 0 V to Vop Input Capacitance, Cpy 8 pF max LOGIC OUTPUTS Output High Voltage, Vou 2.4 V min Isournce = 200 pA Output Low Voltage, Voy 0.4 V max Towk = 200 pA High Impedance Leakage Current +10 pA max High Impedance Capacirance 15 pF max CONVERSION RATE Conversion Time 2.3 pis max Track/Hold Acquisition Time! 100 ns max See DC Acquisition Time Section POWER SUPPLY Vop 2.7-3.5 Volts For Specified Performance Ipp 3.5 mA max Sampling at 350 kKSPS and Logic Power Dissipation 17.5 mW max Inputs at Vpp or 0 V. Vpp = 5 V Power-Down Mode Ipp 1 pA max Vop =5 V; Vop =3V Power Dissipation 5 LW max Automatic Power Down 1 KSPS Throughput 27 LW max 10 kSPS Throughput 270 HW max 100 kSPS Throughput 2.7 mW max NOTES 'See Terminology section. "Sample tested during initial release and after any redesign or process change that may affect this parameter. Specifications subject to change without notice. REV. 0AD7810 Timing Characte ristics! 2 (-40C to +105C, Vier =+Vpo, unless otherwise noted) Parameter | Vpp=5V+10% | Vpp=3V+10% | Units Conditions/Comments Ty 2.3 2.3 Lis (max) Conversion Time Mode 1 Operation (High Speed Mode) t 20 20 ns (min) CONVST Pulse Width ts 25 25 ns (min) SCLKE High Pulse Width ta 25 25 ns (min) SCLK Low Pulse Width Is? 5 5 ns (min) CONVST Rising Edge to SCLK Rising Edge Set-Up Time Te 10 10 ns (max) SCLEK Rising Edge to Dopp Data Valid Delay om 5 5 ns (max) Data Hold Time after Rising Edge SCLK tg?4 20 20 ns (max) | Bus Relinquish Time After Falling Edge of SCLK 10 10 ns (min) tpawER UP 1 1 Hs (max) Power-Up Time After Rising Edge of CONVST NOTES Sample tested to ensure compliance. *See Figures 14, 15 and 16. 3These numbers are measured with the load circuit of Figure 1. They are defined as the time required for the o/p to cross 0.8 V or 2.4 V for Vpp = 5 Vt 10% and 0.4 V or 2 V for Vpp = 3 Vt 10%. Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, ta, quoted in the Timing Characteristics is the true bus relinquish time of the part and as such is independent of external bus loading capacitances. ABSOLUTE MAXIMUM RATINGS* (Ts = +25C unless otherwise noted) Vop tOGND wove O.3Vwo+7V Digital Input Voltage to GND (CONVST, SCLE) ......22..0... Digital Output Voltage to GND -0.3 V, Von + 0.3 V (Dour) occ cece eee ences 0.3 V,Vpp + 0.3 V Vrrr TOGND 2.00. ee 0.3 V, Vpp +0.3V Analog Inputs (Vins Vind) cece eee eee 0.3 V, Vpn + 0.3 V Storage Temperature Range ............ 65C to +150C Junction Temperature ..........-2.000020200050- +150C Plastic DIP Package, Power Dissipation .......... 450 mW O54 Thermal Impedance ............00.000. +125CAW @,, Thermal Impedance ................004. +50C AW Lead Ternperature Soldering (10 sec) .......... +260C SOIC Package, Power Dissipation ............... 450 mW @;, Thermal Impedance .................... 160C /AW Oc Thermal Impedance ......... 0c cece sane 56C Ww Lead Temperature, Soldering Vapor Phase (60 sec)... 00... cece eee +215C Infrared (15 sec)... eee eee +220C MicroSOQIC Package, Power Dissipation .......... 450 mW Oa Thermal Impedance ............0.00000. 206C Oc Thermal Impedance ...........0..000000, 44 CW Lead Temperature, Soldering Vapor Phase (60 sec) ..........0-020200005 +215C Infrared (15 sec) .......000 2.0002 +220C *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. REV. 0 ORDERING GUIDE Linearity Temperature Package Model Error (LSB) | Range Options* AD7810YN [+1 LSB 40C to +105C | N-8 AD7810YR |+1 LSB 40C to +105C | 80-8 AD7810YRM |+1 LSB 40C to +105C | RM-8 *N = plastic DIP; R = small outline IC (SOIC); RM = microSOICc. To OUTPUT PIN +1.6 Figure 1. Load Circuit for Digital Output Timing SpecificationsAD7810 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1 CONVST Convert Start. Falling edge puts the track-and-hold into hold mode and initiates a conversion. A rising edge on the CONVST pin enables the serial port of the AD7810. This is useful in multi- package applications where a number of devices share the same serial bus. The state of this pin at the end of conversion also determines whether the part is powered down or not. See Operating Modes section of this data sheer. 2 Vine Positive input of the pseudo differential analog input. 3 Vine Negative input of the pseudo differential analog input. 4 GND Ground reference for analog and digital circuitry. 5 VREF External reference is connected here. 6 Deut Serial data is shifted out on this pin. 7 SCLK Serial Clock. An external serial clock is applied here. 8 Vop Positive Supply Voltage 2.7 V to 5.5 V. PIN CONFIGURATION DIP/SOIC VV CONVST[1| @ 8] Yoo AD7810 [ 7] Vi LE) top view BCIK Ver EI (Not to Scale) ra] Dour enn [4] 5] Veer Typical Performance Characteristics POWER mW 0.01 o -15 2048 POINT FFT SAMPLING 357.142kSPS F iy = 30 KHz -35 m -55 ua -75 35 -115 10 20 30 40 80 "SSESEABE BH PERSE SS Ts SER MRRA TEE GELS Rae On oa ae Be THROUGHPUT kSPS FREQUENCY BINS Figure 2. Power vs. Throughput Figure 3. AD7810 SNR _4- REV. 0AD7810 TERMINOLOGY Signal to (Noise + Distortion) Ratio This is the measured ratio of signal to (noise + distortion) ar the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (4/2), excluding dc. The ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by: Signal to (Notse + Distortion) = (6.02N + 1.76) dB Thus for a 10-bit converter, this is 62 dB. Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7810 it is defined as: Vi4V2+2+2 THD (4B) = 20 log 74> 1 where V, is the rms amplitude of the fundamental and V,, V3, ,, V; and V," are the rms amplitudes of the second through the sixth harmonics. Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms values of the next largest component in the ADC ourput spectrum (up to fs/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is deter- mined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor, it will be a noise peak. Intermodulation Distortion Wich inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa + nfb where m,n =0, 1, 2, 3, etc. Intermodulation terms are those for which neither m nor n are equal to zero. For example, the second order terms include (fa + fb) and (fa fb), while the third order terms include (2fa + fb), (2fa fb), Ga + 2fb) and (fa 2fb). REV. 0 The AD7810 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second and third order terms are of different significance. The second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. As a result, the second and third order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in dBs. Relative Accuracy Relative accuracy or endpoint nonlinearity is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. Differential Nonlinearity This is the difference berween the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Offset Error This is the deviation of the first code transition (0000... 000) to (0000... 001) from the ideal, i.e., AGND + 1 LSB. Gain Error This is the deviation of the last code transition (1111... 110) to (1111... 111) from the ideal (i.e.,; Vezp 1 LSB) after the offset error has been adjusted out. Track/Hold Acquisition Time Track/hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, within +1/2 LSB, after the end of conversion (the point at which the track/hold returns to track mode). It also applies to situations where there is a step input change on the input voltage applied to the Vay, input of the AD7810. It means that the user must wait for the duration of the track/hold acquisition time, after the end of conversion or after a step input change to Vyy,, before starting another conversion to ensure that the part operates to specification.AD7810 CIRCUIT DESCRIPTION Converter Operation The AD7810 is a successive approximation analog-to-digital converter based around a charge redistriburion DAC. The ADC can convert analog input signals in the range 0 V to Vpp. Fig- ures 4 and 5 below show simplified schematics of the ADC. Figure 4 shows the ADC during its acquisition phase. SW?2 is closed and SW'1 is in Position A; the comparator is held in a balanced condition; and the sampling capacitor acquires the signal on Vix. CHARGE REDISTRIBUTION SAMPLING DAC A CAPACITOR Vint Oo--0- $+ | + CONTROL Swi Loic B] ACQUISITION Pawo F PHASE COMPARATOR clock Vin-& Vpp/2O osc Figure 4. ADC Acquisition Phase When the ADC starts a conversion (see Figure 5), SW2 will open and SW 1 will move to Position B, causing the comparator to become unbalanced. The control logic and the charge redis- tribution DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is rebal- anced, the conversion is complete. The control logic generates the ADC output code. Figure 11 shows the ADC transfer function. CHARGE REDISTRIBUTION SAMPLING DAC A CAPACITOR Viet Oo 1} + + 'N u CONTROL Swi Loic B] CONVERSION swe " PHASE COMPARATOR cLock Vine & Vpp/3 osc Figure &. ADC Conversion Phase TYPICAL CONNECTION DIAGRAM Figure 6 shows a typical connection diagrarn for the AID7810. The serial interface is implemented using two wires; the rising edge of CONVST enables the serial interfacesee Serial Interface section for more details. Vpps is connected to a well decoupled Vopp pin to provide an analog input range of 0 V to Vpp. When Vopp is first connected, the AD7810 powers up in a low current mode, i.e., power-down. A rising edge on the CONVST input will cause the part to power upsee Operating Modes. If power consumption is of concern, the automatic power-down at the end of a conversion should be used to improve power perfor- mance. See Power vs. Throughput Rate section of the data sheet. SUPPLY 9 +2.7V TO 45.5 TWO WIRE SERIAL INTERFACE OV TO Veer INPUT pC/pP Figure 6. Typical Connection Diagram Analog Input Figure 7 shows an equivalent circuit of the analog input struc- ture of the AD7810. The two diodes, D1 and D2, provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 200 mV. This will cause these diodes to become forward biased and start conducting current into the substrate. The maximum current these diodes can conduct without caus- ing irreversible damage to the part is 20 mA. The capacitor C2 is typically about 4 pF and can be primarily attributed to pin capacitance. The resistor R1 is a lumped component made up of the on resistance of a multiplexer and a switch. This resistor is typically about 125 Q. The capacitor Cl is the ADC sampling capacitor and has a capacitance of 3.5 pF. Ypp 1 3.5pF L0 vpn/s Ri 1259 Vint CONVERT PHASE SWITCH CPEN ACQUISITION PHASE SWITCH CLOSED Figure 7. Equivalent Analog input Circuit The analog input of the AD7810 is made up of a pseudo differential pair. Viq. pseudo differential with respect to Vy. The signal is applied to Vpy., but in the pseudo differential scheme the sampling capacitor is connected to Vpy_ during conversion (see Figure 8). This input scheme can be used to remove offsets that exist in a system. For example, if a system had an offset of 0.5 V, the offset could be applied to Vyqy_ and the signal applied to Vpy,. This has the effect of offsetting the input span by 0.5 V. It is only possible to offset the input span when the reference voltage (Vzzp) is less than Vpp- Vorrser- CHARGE REDISTRIBUTION DAC SAMPLING CAPACITOR COMPARATOR Vint 0-0 ! CONTROL LoGic CONVERSION PHASE Swe Vip- O CLOCK Vpp/3 osc Vorrserf Figure 8. Pseudo Differential Input Scheme REV.AD7810 When using the pseudo differential input scheme, the signal on Vpy_ must not vary by more than a 1/2 LSB during the conver- sion process. If the signal on Vpy_ varies during conversion, the conversion result will be incorrect. For single-ended operation, Vin_ is always connected to AGND. Figure 9 shows the AD7810 pseudo differential input being used to make a unipolar de cur- rent measurement. A sense resistor is used to convert the cur- rent to a voltage and the voltage, is applied to the differenual input as shown. Yop rs Vint 4D7810 T FAgeNse= 3 T Vin- ALS T | Figure 9. DC Current Measurement Scheme DC Acquisition Time The ADC starts a new acquisition phase at the end of a conver- sion and ends on the falling edge of the CONVST signal. At the end of a conversion there is a settling ume associated with the sampling circuit. This secding time lasts approximately 100 ns. The analog signal on Vy, is also being acquired during this settling time; therefore, the minimum acquisition time needed is approximately 100 ns. Figure 10 shows the equivalent charging circuit for the sampling capacitor when the ADC is in its acquisition phase. R2 repre- sents the source impedance of a buffer amplifier or resistive network; R1 is an internal multiplexer resistance and C1 is the sampling capacitor. Rt Vint 1250 aa 1 L 3.5pF Figure 10. Equivalent Sampling Circuit During the acquisition phase, the sampling capacitor must be charged to within a 1/2 LSB of its final value. The time it rakes to charge the sampling capacitor ((tcuapez) is given by the following formula: tcnarGgE 7.0% (R2 +125 Q) x 3.5 pF REV. 0 For small values of source impedance, the settling time associ- ated with the sampling circuit (100 ns) is, in effect, the acquisi- tion time of rhe ADC. For example, with a source impedance (R2) of 10 , the charge time for the sampling capacitor is approximately 4 ns. "The charge time becomes significant for source impedances of 2 kQ and greater. AC Acquisition Time In ac applications it is recommended to always buffer analog input signals. The source impedance of the drive circuitry must be kept as low as possible to minimize the acquisition time of the ADC. Large values of source impedance will cause the THD to degrade at high throughput rates. In addition, better perfor- mance can generally be achieved by using an external 1 nF capacitor on Vy). ADC TRANSFER FUNCTION The output coding of the AD7810 is straight binary. The designed code transitions occur at successive integer LSB values G.e., 1 LSB, 2 LSBs, etc.}. The LSB size is = Vagp/1024. The ideal transfer characteristic for the AD7810 is shown in Figure 11 below. a 197...111 111...4110 5 . e a 9 111...000 | oS as a | zy 1LSB = Vpep/1024 . 000...010 f oo0...001 | o00...000 4 > OV 1LSB 4V per -1LSB ANALOG INPUT Figure 11. Transfer CharacteristicAD7810 POWER-UP TIMES The AD7810 has a 1 ps power-up time. When Vopp is first connected, rhe AD7810 is in a low current mode of operation. In order to carry out a conversion, the AD7810 must first be powered up. The ADC is powered up by a rising edge on the CONVST pin. A conversion is initiated on the falling edge of CONVST. Figure 12 shows how to power up the AD7810 when Von is first connected or after the AD7810 is powered down using the CONVST pin. x MODE 1 (C const TT IDLES HIGH) - oo ve _. !POWER4 UP_. MODE 2 (CONVST IBLES LOW) Yop ff CONYST *OWER-UP__ Is f/f Lig Figure 12. Power-Up Times POWER VS. THROUGHPUT RATE By operating the AD7810 in Mode 2, the average power con- sumption of the AID7810 decreases at lower throughput rates. Figure 13 shows how the automatic power-down is implemented using the CONVST signal to achieve the optimum power per- formance for the AD7810. As the throughput rate is reduced, the device remains in its power-down state longer and the average power consumption over time drops accordingly. tconvert tboweR-uP, 2us le ths POWER-DOWN * CONVST # \ j 3b ii 7 7 tovoLe 100us @ 10kSPS Figure 13. Automatic Power-Down For example, if the AD7810 is operated in a continuous sam- pling mode with a throughput rate of 10 kKSPS, the power con- sumption is calculated as follows. The power dissipation during normal operation is 9 mW, Vpp = 3 V. If the power-up ume is 1 us and the conversion time is 2 us, the AD7810 can be said to dissipate 9 mW for 3 us (worst case) during each conversion cycle. If the throughput rate is 10 KSPS, the cycle time is 100 us and the average power dissipated during each cycle is (3/100) x (9 mW) = 270 pW. Figure 2 shows a graph of Power vs. Throughput. OPERATING MODES Mode 1 Operation (High Speed Sampling) When the AD7810 is used in this mode of operation, the part is not powered down between conversions. This mode of opera- tion allows high throughput rates to be achieved. The timing diagram in Figure 14 shows how this optimum throughput rate is achieved by bringing the CONVST signal high before the end of the conversion. The AD7810 leaves its tracking mode and goes into hold on the falling edge of CONVST. A conversion is also initiated at this time. The conversion takes 2 pts to complete. At this pomt, the result of the current conversion is latched into the serial shift register, and the state of the CONVST signal checked. The CONVST signal should be high at the end of the conversion to prevent the part from powering down. CONVST be t, >|) oC ooo CURRENT CONVERSION RESULT Figure 14. Mode 1 Operation Timing The serial port on the AD7810 is enabled on the rising edge of the CONVST signal (see Serial Interface section). As explained earlier, this rising edge should occur before rhe end of the conversion process if the part is not to be powered down. A serial read can take place at any stage after the rising edge of CONVST. If a serial read is initiated before the end of the current conversion process (i.e., at ime A), the result of the previous conversion is shifted out on the Dayr pin. It is possible to allow the serial read to extend beyond the end of a conver- sion. In this case the new data will not be latched into the output shift register until the read has finished. The dynamic performance of the AD7810 cypically degrades by up to 3 dBs while reading during a conversion. If the user waits until the end of the conversion process, i.e., 2 us after falling edge of CONVST (Point *B), before initiating a read, the current conversion result is shifted out. REV. 0AD7810 Mode 2 Operation (Automatic Power-Down) When used in this mode of operation, the part automatically powers down at the end of a conversion. This is achieved by leaving the CONVST signal low until the end of the conversion. Because it takes approximately 1 us for the part to power up after it has been powered down, this mode of operation is intended to be used in applications where slower throughput rates are required, i.e., in the order of 100 kKSPS. The timing diagram in Figure 15 shows how to operate the part in this mode. If the AD7810 is powered down, the rising edge of the CONVST pulse causes the part to power up. When the part has powered up ( 1 us after the rising edge of CONVST), the CONVST signal is brought low, and a conversion is initiated on this falling edge of the CONVST signal. The conversion takes 2 ps and after this time, the conversion result is latched into the serial shift register and the part powers down. Therefore, when the part is operated in Mode 2, the effective conversion time is equal to the power-up time (1 ws) and the SAR conversion time (2 bs). NOTE: Although the AD7810 takes 1 us to power up after the rising edge of CONVST, it is not necessary to leave CONVST high for 1 ps after the nsing edge before bringing it low to initiate a conversion. If the CONVST signal goes low before 1 ps in time has elapsed, then the power-up time is timed out inter- nally and a conversion is then initiated. Hence the AD7810 is guaranteed to have always powered up before a conversion is initiatedeven if the CONVST pulse width is < 1 ps. If the CONVST width is > 1 ps, then a conversion is initiated on the falling edge. As in the case of Mode 1 operation, the rising edge of the CONVST pulse enables the serial port of the AD7810 (see Serial Interface section). If a serial read is initiated soon after this rising edge (Point A), i.e., before the end of the conver- sion, the result of the previous conversion is shifted out on pin Dor. In order to read the result of the current conversion, the user must wait at least 2 us after the falling edge of CONVST before initiating a serial read. The serial port of the AD7810 is sull functional even though the AD7810 has been powered down. NOTE: Serial read should not cross the next rising edge of CONVST. Because it is possible to do a serial read from the part while it is powered down, the AID7810 is powered up only to do the conversion and is immediately powered down at the end of a conversion. This significantly improves the power consumption of the part at slower throughput ratessee Power vs. Through- put Rate section. SERIAL INTERFACE The serial interface of the AD7810 consists of three wires, a serial clock input SCLK, serial port enable CONVST and a serial data ourput Doty (see Figure 16). The serial interface is designed to allow easy interfacing to most microcontrollers, e.g., PIC16C, PIC17C, QSPI and SPI, without the need for any gluing logic. When interfacing to the 8051, the SCLK must be inverted. The Microprocessor Interface section explains how to interface to some popular microcontrollers. Figure 16 shows the ming diagram for a serial read from the AD7810. The serial interface works with both a continuous and a noncontinuous serial clock. The rising edge of the CONVST signal resets a counter, which counts the number of serial clocks to ensure the correct number of bits are shifted out of the serial shift registers. The SCLK is ignored once the correct number of bits have been shifted out. In order for another serial transfer to take place, the counter must be reset by the falling edge of the 10th SCLK. Data is clocked out from the Deyr line on the first rising SCLK edge after the rising edge of the CONVST signal and on subsequent SCLK rising edges. Dor enters its high impedance state again on the falling edge of the 10th SCLK. In multipackage applications, the CONVST signal can be used as a chip select signal. The serial interface will not shift data out until it receives a rising edge on the CONVST pin. <__ poweR-uP ~ t, > us col iT ; , SCLK . : Sa co Dour ve CURRENT CONVERSION RESULT Figure 15. Mode 2? Operation Timing | ts SCLK Ps ne 2 3 4 5 6 7 8 9 10 | Pr Pr 7 ts ue ii CONVST * te ae pe ty ts Dour re DB8 4 DB? x DB5 Xx DBS Xx DB4 4 DB3 Xx DB2 x DB1 Xx DBO -_- Figure 16. AD7810 Serial interface Timing REV. 0AD7810 MICROPROCESSOR INTERFACING The serial interface on the AD7810 allows the parts to be directly connected to a range of many different microprocessors. This section explains how to interface the AD7810 with some of the more common microcontroller serial interface protocols. AD7810 to PICI6C6x/7x The PIC16C6x Synchronous Serial Port (SSP) is configured as an SPI Master with the Clock Polarity Bit = 0. This is done by writing to the Synchronous Serial Port Control Reg- ister (SSPCON). See PICI6/17 Microcontroller User Manual. Figure 17 shows the hardware connections needed to mterface to the PIC16/PIC17. In this example I/O port RAI is being used to pulse CONVST and enable the serial port of the AD7810. This microcontroller transfers only eight bits of data during each serial transfer operation, therefore, two consecutive read opera- tions are needed. AD7810* PIC16C6x/7x* SCLK SCK/RC3 Dour SDO/RCS RAI ADDITIONAL PINS OMITTED FOR CLARITY Figure 17. Interfacing to the PIC 16/PICT7 AD7810 to MC68HC11 The Serial Peripheral Interface (SPI) on the MC68HC11 is configured for Master Mode (MSTR = 6), Clock Polarity Bit (CPOL) = 0, and the Clock Phase Bit (CPHA) = 1. The SPI is configured by writing to the SPI Control Register (SPCR)see 68HCII User Manual. A connection diagram is shown in Figure 18. 4D7810* MC68HC11* SCLK SCLK/PD4 Dour MISO/PD2 CONVST PAO ADDITIONAL PINS GMITTED FOR CLARITY Figure 18. interfacing to the MC68HCT7 -10- AD7810 to 8051 The AD7810 requires a clock synchronized to the serial data; therefore, the 8051 serial interface must be operated in Mode 0. In this mode serial data enters and exits through RXD, and a serial clock is output on TXD (half duplex). Figure 19 shows how the 8051 is connected to the AD7810. However, because the AD7810 shifts data out on the rising edge of the serial clock, the serial clock must be inverted. 4D7810* SCLK ADDITIONAL PINS OMITTED FOR CLARITY Figure 19. Interfacing to the 8057 Serial Port It is possible to implement a serial interface using the data ports on the 8051 (or any microcontroller). This would allow direct interfacing berween the AD7810 and 8051 to be implemented. The technique involves bit banging an I/O port (e.g., P1.0) to generate a serial clock and using another I/O port (e.g., P1.1) to read in dara, see Figure 20. AD7810 SCLK Dour CONVST ADDITIONAL PINS OMITTED FOR CLARITY Figure 20. Interfacing to the 8051 Using I/O Ports REV. 0AD7810 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead Plastic DIP (N-8) 0.430 (10.92) > 0.348 (8.84) Ae & 5 * 0.280 (7.11) 0.240 (6.10) a! 4 0.325 (8.25) BINT. 0.060 11.52) 0.210 (5.33) 9.015 (0.38) tone oa MAX 0.130 0.115 (2.93) 9.160 (4.06) Gan) 0.115 (2.93 _ ona on peo 0.070 {1 77) SEATING coos . . . . 77) BLANE 0.008 (0.204) 0.014 (0.356) ee) 0.045 (1.15) 8-Lead Small Outline Package (SO-8) 0.1988 (5.00), osa0 (4.80) fff A t & 5 0.1574 (4.00) 0.2440 (6.20) 0.1497 (3.80)/T1 41) 0.2284 (5.80) AHH gu PIN 4 0.0688 (1.75) 0.0196 (0.50) 0.0098 (0.25) 0.0532 (1.35) *| * ooops (0.25)* 0.0040 (0.10) + ) I Sosa0 onte2 (0.49) Fle ; ; . oe SEATING (97) "0.0008 (0.25) 0.0500 (1.27) PLANE Cae 0.0138 (0-35) pov (o.19) 0.0760 (0.41) 8-Lead Micro Small Outline Package (RM-8) 0.122 (8.10) 0.114 (2.90) Tiff 8 5 0.122 (3.10) 0.199 (5.05) 0.144 (2.90) 0.187 (4.75) ATE 0.0256 (0.65) BSC 0.4120 (8.05) | 0.120 (3.05) + 0.112 (2.84) 0.112 (2.64) \K 0.043 (1.05) o.006 (0.15) 4 a.04g(.08) 0.002 18 4 COAT 0.037 (0.94) 0.018 (0.46) ot he 2 0.008 (0.20) 0.011 (0.28) 0.028 (0.71) 0.003 (0.08) 0.076 (0.41) SEATING PLANE REV. 0 -11-{6/7-ZL-086Z2 wST NI OGALNIYd -12-