14-Bit, 170 MSPS/250 MSPS, JESD204B,
Dual Analog-to-Digital Converter
Data Sheet
AD9250
Rev. E Document Feedback
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FEATURES
JESD204B Subclass 0 or Subclass 1 coded serial digital outputs
Signal-to-noise ratio (SNR) = 70.6 dBFS at 185 MHz AIN and
250 MSPS
Spurious-free dynamic range (SFDR) = 88 dBc at 185 MHz
AIN and 250 MSPS
Total power consumption: 711 mW at 250 MSPS
1.8 V supply voltages
Integer 1-to-8 input clock divider
Sample rates of up to 250 MSPS
IF sampling frequencies of up to 400 MHz
Internal analog-to-digital converter (ADC) voltage reference
Flexible analog input range
1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
ADC clock duty cycle stabilizer (DCS)
95 dB channel isolation/crosstalk
Serial port control
Energy saving power-down modes
APPLICATIONS
Diversity radio systems
Multimode digital receivers (3G)
TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE
DOCSIS 3.0 CMTS upstream receive paths
HFC digital reverse path receivers
I/Q demodulation systems
Smart antenna systems
Electronic test and measurement equipment
Radar receivers
COMSEC radio architectures
IED detection/jamming systems
General-purpose software radios
Broadband data applications
FUNCTIONAL BLOCK DIAGRAM
CML, TX
OUTPUTS
JESD204B
INTERFACE
HIGH
SPEED
SERIALIZERS
PIPELINE
14-BIT ADC
PIPELINE
14-BIT ADC
CMOS
DIGITAL
INPUT
CMOS
DIGITAL
OUTPUT
FAST
DETECT
CONTROL
REGISTERS
CLOCK
GENERATION
AVDD
VIN+A
SDIO SCLK
FDB
FDA
PDWN
SERDOUT1±
SERDOUT0±
CS
VIN–A
VIN+B
VCM
VIN–B
SYSREF±
SYNCINB±
CLK±
RFCLK
DRVDD DVDD AGND DGND DRGND
CMOS
DIGITAL
INPUT/OUTPUT
AD9250
10559-001
RST
Figure 1.
PRODUCT HIGHLIGHTS
1. Integrated dual, 14-bit, 170 MSPS/250 MSPS ADC.
2. The configurable JESD204B output block supports up to
5 Gbps per lane.
3. An on-chip, phase-locked loop (PLL) allows users to provide
a single ADC sampling clock; the PLL multiplies the ADC
sampling clock to produce the corresponding JESD204B
data rate clock.
4. Support for an optional RF clock input to ease system board
design.
5. Proprietary differential input maintains excellent SNR
performance for input frequencies of up to 400 MHz.
6. Operation from a single 1.8 V power supply.
7. Standard serial port interface (SPI) that supports various
product features and functions such as controlling the clock
DCS, power-down, test modes, voltage reference mode, over
range fast detection, and serial output configuration.
This product may be protected by one or more U.S. or international patents.
AD9250 Data Sheet
Rev. E | Page 2 of 45
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 3
General Description ......................................................................... 4
Specifications ..................................................................................... 5
ADC DC Specifications ............................................................... 5
ADC AC Specifications ............................................................... 6
Digital Specifications ................................................................... 7
Switching Specifications .............................................................. 9
Timing Specifications ................................................................ 10
Absolute Maximum Ratings .......................................................... 11
Thermal Characteristics ............................................................ 11
ESD Caution ................................................................................ 11
Pin Configuration and Function Descriptions ........................... 12
Typical Performance Characteristics ........................................... 14
Equivalent Circuits ......................................................................... 18
Theory of Operation ...................................................................... 20
ADC Architecture ...................................................................... 20
Analog Input Considerations .................................................... 20
Voltage Reference ....................................................................... 21
Clock Input Considerations ...................................................... 21
Power Dissipation and Standby Mode ..................................... 24
Digital Outputs ............................................................................... 25
JESD204B Transmit Top Level Description ............................ 25
JESD204B Overview .................................................................. 25
JESD204B Synchronization Details ......................................... 26
Link Setup Parameters ............................................................... 26
Frame and Lane Alignment Monitoring and Correction ..... 30
Digital Outputs and Timing ..................................................... 30
ADC Overrange and Gain Control .......................................... 32
ADC Overrange (OR) ................................................................ 32
Gain Switching ............................................................................ 32
DC Correction ................................................................................ 33
DC Correction Bandwidth ........................................................ 33
DC Correction Readback .......................................................... 33
DC Correction Freeze ................................................................ 33
DC Correction (DCC) Enable Bits .......................................... 33
Serial Port Interface (SPI) .............................................................. 34
Configuration Using the SPI ..................................................... 34
Hardware Interface ..................................................................... 34
SPI Accessible Features .............................................................. 35
Memory Map .................................................................................. 36
Reading the Memory Map Register Table ............................... 36
Memory Map Register Table ..................................................... 37
Memory Map Register Description ......................................... 41
Applications Information .............................................................. 42
Design Guidelines ...................................................................... 42
SPI Initialization Sequence ....................................................... 42
Outline Dimensions ....................................................................... 45
Ordering Guide .......................................................................... 45
Data Sheet AD9250
Rev. E | Page 3 of 45
REVISION HISTORY
9/2017—Rev. D to Rev. E
Changes to Channel-Specific Registers Section ................................. 36
Changes to Table 18 ................................................................................... 37
Changes to Figure 63 and Table 19 ........................................................ 43
5/2017—Rev. C to Rev. D
Change to Differential Output Voltage (VOD) Parameter, Table 3 .... 8
Deleted Synchronization Section .................................................. 26
Changes to Link Setup Parameters Section ................................. 26
Deleted Clock Adjustment Register Writes Section ................... 27
Added Internal FIFO Timing Optimization Section ................. 28
Changes to Table 14 ........................................................................ 30
Changes to Channel-Specific Registers Section .......................... 36
Deleted Transfer Register Map Section ........................................ 37
Changes to Table 18 ........................................................................ 37
Added SPI Initialization Sequence Section .................................. 42
Added Figure 63 and Table 19; Renumbered Sequentially ........ 43
Deleted JESD204B Configuration Section ................................... 44
Updated Outline Dimensions ........................................................ 45
1/2016—Rev. B to Rev. C
Moved Revision History Section ..................................................... 3
Changes to Nyquist Clock Input Options .................................... 22
Added Synchronization Section .................................................... 26
Added Click Adjustment Register Writes Section ...................... 27
Changes to Link Setup Parameters Section ................................. 27
Change to Additional Digital Output Configuration Options
Section .............................................................................................. 29
Added Table 14, Renumbered Sequentially ................................. 30
Changes to Table 18 ........................................................................ 38
Added JESD204B Configuration Section .................................... 43
12/2013—Rev. A to Rev. B
Change to Features Section .............................................................. 1
Change to Functional Block Diagram ............................................ 1
Change to SYNCIN Input (SYNCINB+/SYNCINB−), Logic
Compliance Parameter, Table 3 ....................................................... 6
Changes to Data Output Parameters, Table 4 ............................... 8
Changes to Figure 3 .......................................................................... 9
Change to Figure 30, Added Figure 34 through Figure 37;
Renumbered Sequentially .............................................................. 17
Changes to Table 9 .......................................................................... 20
Change to Figure 47 ........................................................................ 21
Changes to JESD204B Overview Section .................................... 24
Change to Configure Details Options Section ............................ 26
Change to Check FCHK, Checksum of JESD204B Interface
Parameters Section .......................................................................... 27
Changes to Figure 54 ...................................................................... 28
Changes to Figure 57 and Figure 58 ............................................. 29
Changes to Figure 59 and Figure 60 ............................................. 30
Changes to Table 17 ........................................................................ 36
Updated Outline Dimensions........................................................ 42
3/2013—Rev. 0 to Rev. A
Changes to High Level Input Current and Low Level Input
Current; Table 3 ................................................................................. 6
Changes to Table 4 ............................................................................ 8
Changes to Figure 3 Caption ........................................................... 9
Changes to Digital Inputs Description; Table 8 .......................... 11
Changes to JESD204B Synchronization Details Section ........... 24
Changes to Configure Detailed Options Section ........................ 25
Changes to Fast Threshold Detection (FDA and FDB) Section ... 30
Deleted Built-In Self-Test (BIST) and Output Test Section ...... 32
Changes to Transfer Register Map Section .................................. 34
Changes to Table 17 ........................................................................ 35
10/2012—Revision 0: Initial Version
AD9250 Data Sheet
Rev. E | Page 4 of 45
GENERAL DESCRIPTION
The AD9250 is a dual, 14-bit ADC with sampling speeds of up
to 250 MSPS. The AD9250 is designed to support communications
applications where low cost, small size, wide bandwidth, and
versatility are desired.
The ADC cores feature a multistage, differential pipelined
architecture with integrated output error correction logic. The
ADC cores feature wide bandwidth inputs supporting a variety
of user-selectable input ranges. An integrated voltage reference
eases design considerations. A duty cycle stabilizer is provided
to compensate for variations in the ADC clock duty cycle, allowing
the converters to maintain excellent performance. The JESD204B
high speed serial interface reduces board routing requirements
and lowers pin count requirements for the receiving device.
By default, the ADC output data is routed directly to the two
JESD204B serial output lanes. These outputs are at CML voltage
levels. Four modes support any combination of M = 1 or 2 (single
or dual converters) and L = 1 or 2 (one or two lanes). For dual
ADC mode, data can be sent through two lanes at the maximum
sampling rate of 250 MSPS. However, if data is sent through
one lane, a sampling rate of up to 125 MSPS is supported.
Synchronization inputs (SYNCINB± and SYSREF±) are provided.
Flexible power-down options allow significant power savings,
when desired. Programmable overrange level detection is
supported for each channel via the dedicated fast detect pins.
Programming for setup and control are accomplished using a
3-wire SPI-compatible serial interface.
The AD9250 is available in a 48-lead LFCSP and is specified
over the industrial temperature range of −40°C to +85°C.
Data Sheet AD9250
Rev. E | Page 5 of 45
SPECIFICATIONS
ADC DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, DVDD = 1.8 V, maximum sample rate for speed grade, VIN = −1.0 dBFS differential input, 1.75 V p-p
full-scale input range, duty cycle stabilizer (DCS) enabled, link parameters used were M = 2 and L = 2, unless otherwise noted.
Table 1.
AD9250-170 AD9250-250
Parameter Temperature Min Typ Max Min Typ Max Unit
RESOLUTION
Full
14
14
Bits
ACCURACY
No Missing Codes Full Guaranteed Guaranteed
Offset Error Full −16 +16 −16 +16 mV
Gain Error Full −6 +2 −6 +2.5 %FSR
Differential Nonlinearity (DNL) Full ±0.75 ±0.75 LSB
25°C ±0.25 ±0.25 LSB
Integral Nonlinearity (INL)1 Full ±2.1 ±3.5 LSB
25°C ±1.5 ±1.5 LSB
MATCHING CHARACTERISTIC
Offset Error Full −15 +15 −15 +15 mV
Gain Error
Full
−2
+3.5
−2
+3
%FSR
TEMPERATURE DRIFT
Offset Error Full ±2 ±2 ppm/°C
Gain Error Full ±16 ±44 ppm/°C
INPUT REFERRED NOISE
VREF = 1.0 V 25°C 1.49 1.49 LSB rms
ANALOG INPUT
Input Span Full 1.75 1.75 V p-p
Input Capacitance2 Full 2.5 2.5 pF
Input Resistance3 Full 20 20 kΩ
Input Common-Mode Voltage Full 0.9 0.9 V
POWER SUPPLIES
Supply Voltage
AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V
DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V
DVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V
Supply Current
I
AVDD
Full
233
260
255
280
mA
IDRVDD + IDVDD Full 104 113 140 160 mA
POWER CONSUMPTION
Sine Wave Input
Full
607
711
mW
Standby Power4 Full 280 339 mW
Power-Down Power Full 9 9 mW
1 Measured with a low input frequency, full-scale sine wave.
2 Input capacitance refers to the effective capacitance between one differential input pin and its complement.
3 Input resistance refers to the effective resistance between one differential input pin and its complement.
4 Standby power is measured with a dc input and the CLK± pin active.
AD9250 Data Sheet
Rev. E | Page 6 of 45
ADC AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, DVDD = 1.8 V, maximum sample rate for speed grade, VIN = −1.0 dBFS differential input, 1.75 V p-p
full-scale input range, link parameters used were M = 2 and L = 2, unless otherwise noted.
Table 2.
AD9250-170 AD9250-250
Parameter1 Temperature Min Typ Max Min Typ Max Unit
SIGNAL-TO-NOISE-RATIO (SNR)
fIN = 30 MHz 25°C 72.5 72.1 dBFS
fIN = 90 MHz 25°C 72.0 71.7 dBFS
Full 70.7 dBFS
fIN = 140 MHz 25°C 71.4 71.2 dBFS
fIN = 185 MHz 25°C 70.7 70.6 dBFS
Full 69.3 dBFS
fIN = 220 MHz 25°C 70.1 70.0 dBFS
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 30 MHz 25°C 71.3 70.7 dBFS
fIN = 90 MHz 25°C 70.9 70.5 dBFS
Full 69.6 dBFS
fIN = 140 MHz 25°C 70.3 70.0 dBFS
fIN = 185 MHz 25°C 69.6 69.5 dBFS
Full 68.0 dBFS
fIN = 220 MHz 25°C 68.9 68.8 dBFS
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 30 MHz 25°C 11.5 11.5 Bits
fIN = 90 MHz 25°C 11.4 11.4 Bits
f
IN
= 140 MHz
25°C
11.3
11.3
Bits
fIN = 185 MHz 25°C 11.1 11.2 Bits
fIN = 220 MHz 25°C 10.9 11.0 Bits
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 30 MHz 25°C 92 89 dBc
fIN = 90 MHz 25°C 95 86 dBc
Full 78 dBc
fIN = 140 MHz 25°C 91 86 dBc
fIN = 185 MHz 25°C 86 88 dBc
Full 80 dBc
fIN = 220 MHz 25°C 85 88 dBc
WORST SECOND OR THIRD HARMONIC
fIN = 30 MHz 25°C −92 −89 dBc
fIN = 90 MHz 25°C −95 −87 dBc
Full −78 dBc
fIN = 140 MHz 25°C −91 −86 dBc
f
IN
= 185 MHz
25°C
−86
−88
dBc
Full −80 dBc
fIN = 220 MHz 25°C −85 −88 dBc
WORST OTHER (HARMONIC OR SPUR)
fIN = 30 MHz 25°C −95 −94 dBc
fIN = 90 MHz 25°C −94 −96 dBc
Full −78 dBc
fIN = 140 MHz 25°C −97 −96 dBc
fIN = 185 MHz 25°C −96 −88 dBc
Full −80 dBc
fIN = 220 MHz 25°C −93 −91 dBc
Data Sheet AD9250
Rev. E | Page 7 of 45
AD9250-170 AD9250-250
Parameter1 Temperature Min Typ Max Min Typ Max Unit
TWO-TONE SFDR
fIN = 184.12 MHz (−7 dBFS), 187.12 MHz (−7 dBFS) 25°C 87 84 dBc
CROSSTALK2 Full 95 95 dB
FULL POWER BANDWIDTH3 25°C 1000 1000 MHz
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation for a complete set of definitions.
2 Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel.
3 Full power bandwidth is the bandwidth of operation determined by where the spectral power of the fundamental frequency is reduced by 3 dB.
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, DVDD = 1.8 V, maximum sample rate for speed grade, VIN = −1.0 dBFS differential input, 1.75 V p-p
full-scale input range, DCS enabled, link parameters used were M = 2 and L = 2, unless otherwise noted.
Table 3.
Parameter Temperature Min Typ Max Unit
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Input CLK± Clock Rate Full 40 625 MHz
Logic Compliance CMOS/LVDS/LVPECL
Internal Common-Mode Bias Full 0.9 V
Differential Input Voltage Full 0.3 3.6 V p-p
Input Voltage Range Full AGND AVDD V
Input Common-Mode Range Full 0.9 1.4 V
High Level Input Current Full 0 +60 µA
Low Level Input Current Full −60 0 µA
Input Capacitance Full 4 pF
Input Resistance
Full
8
10
12
kΩ
RF CLOCK INPUT (RFCLK)
Input CLK± Clock Rate Full 650 1500 MHz
Logic Compliance
CMOS/LVDS/LVPECL
Internal Bias Full 0.9 V
Input Voltage Range Full AGND AVDD V
Input Voltage Level
High Full 1.2 AVDD V
Low Full AGND 0.6 V
High Level Input Current Full 0 +150 µA
Low Level Input Current Full −150 0 µA
Input Capacitance Full 1 pF
Input Resistance (AC-Coupled) Full 8 10 12 kΩ
SYNCIN INPUT (SYNCINB+/SYNCINB−)
Logic Compliance CMOS/LVDS
Internal Common-Mode Bias Full 0.9 V
Differential Input Voltage Range Full 0.3 3.6 V p-p
Input Voltage Range
Full
DGND
DVDD
V
Input Common-Mode Range Full 0.9 1.4 V
High Level Input Current Full −5 +5 µA
Low Level Input Current Full −5 +5 µA
Input Capacitance Full 1 pF
Input Resistance Full 12 16 20 kΩ
AD9250 Data Sheet
Rev. E | Page 8 of 45
Parameter Temperature Min Typ Max Unit
SYSREF INPUT (SYSREF±)
Logic Compliance LVDS
Internal Common-Mode Bias Full 0.9 V
Differential Input Voltage Range Full 0.3 3.6 V p-p
Input Voltage Range
Full
AGND
AVDD
V
Input Common-Mode Range Full 0.9 1.4 V
High Level Input Current Full −5 +5 µA
Low Level Input Current Full −5 +5 µA
Input Capacitance Full 4 pF
Input Resistance Full 8 10 12 kΩ
LOGIC INPUT (RST, CS)1
High Level Input Voltage Full 1.22 2.1 V
Low Level Input Voltage Full 0 0.6 V
High Level Input Current Full −5 +5 µA
Low Level Input Current Full −100 −45 µA
Input Resistance Full 26 kΩ
Input Capacitance Full 2 pF
LOGIC INPUT (SCLK/PDWN)2
High Level Input Voltage Full 1.22 2.1 V
Low Level Input Voltage Full 0 0.6 V
High Level Input Current Full 45 100 µA
Low Level Input Current
Full
−10
+10
µA
Input Resistance Full 26 kΩ
Input Capacitance Full 2 pF
LOGIC INPUTS (SDIO)2
High Level Input Voltage Full 1.22 2.1 V
Low Level Input Voltage Full 0 0.6 V
High Level Input Current Full 45 100 µA
Low Level Input Current Full −10 10 µA
Input Resistance Full 26 kΩ
Input Capacitance Full 5 pF
DIGITAL OUTPUTS (SERDOUT0±/SERDOUT1±)
Logic Compliance
Full
CML
Differential Output Voltage (VOD) Full 400 600 750 mV p-p
Output Offset Voltage (VOS) Full 0.75 DRVDD/2 1.05 V
DIGITAL OUTPUTS (SDIO/FDA/FDB)
High Level Output Voltage (VOH) Full
IOH = 50 µA Full 1.79 V
IOH = 0.5 mA Full 1.75 V
Low Level Output Voltage (VOL) Full
IOL = 1.6 mA Full 0.2 V
IOL = 50 µA Full 0.05 V
1 Pull-up.
2 Pull-down.
Data Sheet AD9250
Rev. E | Page 9 of 45
SWITCHING SPECIFICATIONS
Table 4.
AD9250-170 AD9250-250
Parameter Symbol Temperature Min Typ Max Min Typ Max Unit
CLOCK INPUT PARAMETERS
Conversion Rate1 fS Full 40 170 40 250 MSPS
SYSREF± Setup Time to Rising Edge CLK±2 tREFS Full 0.31 0.31 ns
SYSREF± Hold Time from Rising Edge CLK±2 tREFH Full 0 0 ns
SYSREF± Setup Time to Rising Edge RFCLK
2
t
REFSRF
Full
0.50
0.50
ns
SYSREF± Hold Time from Rising Edge RFCLK2 tREFHRF Full 0 0 ns
CLK± Pulse Width High tCH
Divide-by-1 Mode, DCS Enabled Full 2.61 2.9 3.19 1.8 2.0 2.2 ns
Divide-by-1 Mode, DCS Disabled Full 2.76 2.9 3.05 1.9 2.0 2.1 ns
Divide-by-2 Mode Through Divide-by-8 Mode Full 0.8 0.8 ns
Aperture Delay tA Full 1.0 1.0 ns
Aperture Uncertainty (Jitter) tJ Full 0.16 0.16 ps rms
DATA OUTPUT PARAMETERS
Data Output Period or Unit Interval (UI) Full L/(20 × M × fS) L/(20 × M × fS) Seconds
Data Output Duty Cycle 25°C 50 50 %
Data Valid Time 25°C 0.84 0.78 UI
PLL Lock Time (tLOCK) 25°C 25 25 µs
Wake-Up Time
Standby 25°C 10 10 µs
ADC (Power-Down)3 25°C 250 250 µs
Output (Power-Down)4 25°C 50 50 µs
Subclass 0: SYNCINB± Falling Edge to First Valid
K.28 Characters (Delay Required for Rx CGS Start)
Full 5 5 Multiframes
Subclass 1: SYSREF± Rising Edge to First Valid K.28
Characters (Delay Required for SYNCB± Rising
Edge/Rx CGS Start)
Full 6 6 Multiframes
CGS Phase K.28 Characters Duration Full 1 1 Multiframes
Pipeline Delay
JESD204B M1, L1 Mode (Latency) Full 36 36 Cycles5
JESD204B M1, L2 Mode (Latency)
Full
59
59
Cycles
JESD204B M2, L1 Mode (Latency) Full 25 25 Cycles
JESD204B M2, L2 Mode (Latency) Full 36 36 Cycles
Fast Detect (Latency) Full 7 7 Cycles
Data Rate per Lane Full 3.4 5.0 5.0 Gbps
Uncorrelated Bounded High Probability (UBHP) Jitter 25°C 6 8 ps
Random Jitter
At 3.4 Gbps Full 2.3 ps rms
At 5.0 Gbps Full 1.7 ps rms
Output Rise/Fall Time Full 60 60 ps
Differential Termination Resistance 25°C 100 100 Ω
Out-of-Range Recovery Time Full 3 3 Cycles
1 Conversion rate is the clock rate after the divider.
2 Refer to Figure 3 for timing diagram.
3 Wake-up time ADC is defined as the time required for the ADC to return to normal operation from power-down mode.
4 Wake-up time output is defined as the time required for JESD204B output to return to normal operation from power-down mode.
5 Cycles refers to ADC conversion rate cycles.
AD9250 Data Sheet
Rev. E | Page 10 of 45
TIMING SPECIFICATIONS
Table 5.
Parameter Test Conditions/Comments Min Typ Max Unit
SPI TIMING REQUIREMENTS (See Figure 62)
tDS Setup time between the data and the rising edge of SCLK 2 ns
tDH Hold time between the data and the rising edge of SCLK 2 ns
tCLK Period of the SCLK 40 ns
tS Setup time between CS and SCLK 2 ns
tH Hold time between CS and SCLK 2 ns
tHIGH Minimum period that SCLK should be in a logic high state 10 ns
tLOW Minimum period that SCLK should be in a logic low state 10 ns
tEN_SDIO Time required for the SDIO pin to switch from an input to an
output relative to the SCLK falling edge (not shown in figures)
10 ns
tDIS_SDIO Time required for the SDIO pin to switch from an output to an
input relative to the SCLK rising edge (not shown in figures)
10 ns
tSPI_RST Time required after hard or soft reset until SPI access is available
(not shown in figures)
500 µs
Timing Diagrams
N – 36
N – 35
N – 34 N – 33 N – 1
N + 1
SAMPLE N
ANALOG
INPUT
SIGNAL
CLK–
CLK+
CLK–
CLK+
SERDOUT1±
SERDOUT0±
SAMP LE N – 36
ENCODE D INT O 2
8b/10b SYMBOLS
SAMP LE N – 35
ENCODE D INT O 2
8b/10b SYMBOLS
SAMP LE N – 34
ENCODE D INT O 2
8b/10b SYMBOLS
10559-002
Figure 2. Data Output Timing
10559-003
t
REFS
t
REFH
t
REFHRF
NOTES
1. CL OCK I NP UT I S E IT HE R RFCL K OR CL K±, NO T BO TH.
CLK+
CLK–
SYSREF+
SYSREF–
RFCLK
SYSREF+
SYSREF–
t
REFSRF
Figure 3. SYSREF± Setup and Hold Timing
Data Sheet AD9250
Rev. E | Page 11 of 45
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter Rating
ELECTRICAL
AVDD to AGND
−0.3 V to +2.0 V
DRVDD to AGND −0.3 V to +2.0 V
DVDD to DGND −0.3 V to +2.0 V
VIN+A/VIN+B, VIN−A/VIN−B to AGND −0.3 V to AVDD + 0.2 V
CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V
RFCLK to AGND −0.3 V to AVDD + 0.2 V
VCM to AGND −0.3 V to AVDD + 0.2 V
CS, PDWN to AGND −0.3 V to AVDD + 0.3 V
SCLK to AGND −0.3 V to AVDD + 0.3 V
SDIO to AGND −0.3 V to AVDD + 0.3 V
RST to DGND −0.3 V to DVDD + 0.3 V
FDA, FDB to DGND −0.3 V to DVDD + 0.3 V
SERDOUT0+, SERDOUT0−,
SERDOUT1+, SERDOUT1− to AGND
−0.3 V to DRVDD + 0.3 V
SYNCINB+, SYNCINB− to DGND
−0.3 V to DVDD + 0.3 V
SYSREF+, SYSREF− to AGND
−0.3 V to AVDD + 0.3 V
ENVIRONMENTAL
Operating Temperature Range
(Ambient)
−40°C to +85°C
Maximum Junction Temperature
Under Bias
150°C
Storage Temperature Range
(Ambient)
−65°C to +125°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL CHARACTERISTICS
The exposed paddle must be soldered to the ground plane for
the LFCSP package. This increases the reliability of the solder
joints, maximizing the thermal capability of the package.
Table 7. Thermal Resistance
Package Type
Airflow
Velocity
(m/sec) θJA1, 2 θJC1, 3 θJB1, 4 Unit
48-Lead LFCSP
7 mm × 7 mm
(CP-48-13)
0 25 2 14 °C/W
1.0 22 °C/W
2.5 20 °C/W
1 Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.
2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
3 Per MIL-STD-883, Method 1012.1.
4 Per JEDEC JESD51-8 (still air).
Typical θJA is specified for a 4-layer printed circuit board (PCB)
with a solid ground plane. As shown in Table 7, airflow increases
heat dissipation, which reduces θJA. In addition, metal in direct
contact with the package leads from metal traces, through holes,
ground, and power planes reduces the θJA.
ESD CAUTION
AD9250 Data Sheet
Rev. E | Page 12 of 45
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
AVDD
DNC
PDWN
4CS
5SCLK
6SDIO
7DVDD
24
DVDD 23
DGND 22
SERDOUT0+ 21
SERDOUT0– 20
DRVDD 19
SERDOUT1– 18
SERDOUT1+ 17
DGND 16
DVDD 15
SYNCINB– 14
SYNCINB+ 13
DVDD
44 AVDD
45 VIN+B
46 VIN–B
47 AVDD
48 AVDD
43 AVDD
42 VCM
41 AVDD
40 AVDD
39 VIN+A
38 VIN–A
37 AVDD
TOP VIEW
(No t t o Scal e)
AD9250
25
DNC 26
DVDD 27
RST 28
DVDD 29
AVDD 30
SYSREF– 31
SYSREF+ 32
AVDD 33
CLK+ 34
CLK– 35
RFCLK 36
AVDD
8DNC
9DNC
10 FDA
11 FDB
12 DVDD
NOTES
1. DNC = DO NO T CO NNE CT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE
PACKAGE P ROVIDES THE GRO UND RE FERE NCE FO R
DRVDD AND AVDD. THI S E X P OSE D P ADDLE M US T BE
CONNECTED TO GRO UND FO R P ROPE R OPE RATI ON.
10559-004
Figure 4. Pin Configuration (Top View)
Table 8. Pin Function Descriptions
Pin No. Mnemonic Type Description
ADC Power Supplies
1, 5, 8, 36, 37, 40, 41, 43, 44, 47, 48 AVDD Supply Analog Power Supply (1.8 V Nominal).
9, 11, 13, 16, 24, 25, 30 DVDD Supply Digital Power Supply (1.8 V Nominal).
12, 28, 29, 35 DNC Do Not Connect.
17, 23 DGND Ground Reference for DVDD.
20 DRVDD Supply JESD204B PHY Serial Output Driver Supply (1.8 V Nominal).
Note that the DRVDD power is referenced to the AGND Plane.
Exposed Paddle AGND/DRGND Ground The exposed thermal paddle on the bottom of the package
provides the ground reference for DRVDD and AVDD. This
exposed paddle must be connected to ground for proper
operation.
ADC Analog
2 RFCLK Input ADC RF Clock Input.
3 CLK− Input ADC Nyquist Clock Input—Complement.
4 CLK+ Input ADC Nyquist Clock Input—True.
38
VIN−A
Input
Differential Analog Input Pin (−) for Channel A.
39 VIN+A Input Differential Analog Input Pin (+) for Channel A.
42 VCM Output Common-Mode Level Bias Output for Analog Inputs. Decouple
this pin to ground using a 0.1 µF capacitor.
45 VIN+B Input Differential Analog Input Pin (+) for Channel B.
46 VIN−B Input Differential Analog Input Pin (−) for Channel B.
ADC Fast Detect Outputs
26 FDB Output Channel B Fast Detect Indicator (CMOS Levels).
27 FDA Output Channel A Fast Detect Indicator (CMOS Levels).
Digital Inputs
6 SYSREF+ Input JESD204B LVDS SYSREF Input—True.
7 SYSREF− Input JESD204B LVDS SYSREF Input—Complement.
14 SYNCINB+ Input JESD204B LVDS SYNC Input—True.
15 SYNCINB− Input JESD204B LVDS SYNC Input—Complement.
Data Sheet AD9250
Rev. E | Page 13 of 45
Pin No. Mnemonic Type Description
Data Outputs
18 SERDOUT1+ Output Lane B CML Output Data—True.
19 SERDOUT1− Output Lane B CML Output Data—Complement.
21 SERDOUT0− Output Lane A CML Output Data—Complement.
22
SERDOUT0+
Output
Lane A CML Output Data—True.
DUT Controls
10 RST Input Digital Reset (Active Low).
31
SDIO
Input/Output
SPI Serial Data I/O.
32 SCLK Input SPI Serial Clock.
33 CS Input SPI Chip Select (Active Low).
34 PDWN Input Power-Down Input (Active High). The operation of this pin
depends on the SPI mode and can be configured as power-
down or standby (see Table 18).
AD9250 Data Sheet
Rev. E | Page 14 of 45
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 1.8 V, DRVDD = 1.8 V, DVDD = 1.8 V, sample rate is maximum for speed grade, DCS enabled, 1.75 V p-p differential input,
VIN = −1.0 dBFS, 32k sample, TA = 25°C, link parameters used were M = 2 and L = 2, unless otherwise noted.
0 20406080
AMPLITUDE (dBFS)
FREQUENCY (MHz)
–120
–100
–80
–60
–40
–20
0
10559-005
f
IN
: 90.1MHz
f
S
: 170MSPS
SNR: 71.8dBFS
SFDR: 91dBc
Figure 5. AD9250-170 Single-Tone FFT with fIN = 90.1 MHz
0 20406080
AMPLITUDE (dBFS)
FREQUENCY (MHz)
10559-006
f
IN
: 185.1MHz
f
S
: 170MSPS
SNR: 71.6dBFS
SFDR: 86dBc
–120
–100
–80
–60
–40
–20
0
Figure 6. AD9250-170 Single-Tone FFT with fIN = 185.1 MHz
–120
–100
–80
–60
–40
–20
0
0 20406080
AMPLITUDE (dBFS)
FREQUENCY (MHz)
10559-007
f
IN
: 305.1MHz
f
S
: 170MSPS
SNR: 69.4dBFS
SFDR: 85dBc
Figure 7. AD9250-170 Single-Tone FFT with fIN = 305.1 MHz
0
20
40
60
80
100
120
–90 –70 –50 –30 –10
SNR
SNRFS
SFDR
SFDR dBc
SN
R
/SFDR (dBc AND dBFS)
INPUT AMPLITUDE (dBFS)
10559-008
Figure 8. AD9250-170 Single-Tone SNR/SFDR vs. Input Amplitude (AIN)
with fIN = 185.1 MHz
60
65
70
75
80
85
90
95
100
0 50 100 150 200 250 300
SNR
FREQUENCY (MHz)
SNR/SFDR (dBc AND dBFS)
SFDR
10559-009
Figure 9. AD9250-170 Single-Tone SNR/SFDR vs. Input Frequency (fIN)
–120
–100
–80
–60
–40
–20
0
–90 –70 –50 –30 –10
SFDR (dBc)
SFDR (dBFS)
IMD (dBc)
IMD (dBFS)
SFD
R
/IMD (dBc AND dBFS)
INPUT AMPLITUDE (dBFS)
10559-010
Figure 10. AD9250-170 Two-Tone SFDR/IMD vs. Input Amplitude (AIN)
with fIN1 = 89.12 MHz, fIN2 = 92.12 MHz, fS = 170 MSPS
Data Sheet AD9250
Rev. E | Page 15 of 45
–120
–100
–80
–60
–40
–20
0
–90 –70 –50 –30 –10
SFDR/IMD (dBc AND dBFS)
INPUT AMPLITUDE (dBFS)
SFDR (dBc)
SFDR (dBFS)
IM D ( dBc)
IMD (dBFS)
10559-011
Figure 11. AD9250-170 Two-Tone SFDR/IMD vs. Input Amplitude (AIN)
with fIN1 = 184.12 MHz, fIN2 = 187.12 MHz, fS = 170 MSPS
–120
–100
–80
–60
–40
–20
0
AMPLITUDE (dBFS)
020 40 60 80
FREQUENCY (MHz)
10559-012
170 MSPS
89.12M Hz AT –7dBFS
92.12M Hz AT –7dBFS
SFDR: 91dBc
Figure 12. AD9250-170 Two-Tone FFT with fIN1 = 89.12 MHz, fIN2 = 92.12 MHz,
fS = 170 MSPS
–120
–100
–80
–60
–40
–20
0
AMPLITUDE (dBFS)
020 40 60 80
FREQUENCY (MHz)
10559-013
170 MSPS
184.12M Hz AT –7dBFS
187.12M Hz AT –7dBFS
SFDR: 86dBc
Figure 13. AD9250-170 Two-Tone FFT with fIN1 = 184.12 MHz,
fIN2 = 187.12 MHz, fS = 170 MSPS
70
75
80
85
90
95
100
40 90 140
SF DR_A ( dBc)
SNRF S_A (dBFS)
SF DR_B ( dBc)
SNRF S_B (dBFS)
SNR/S FDR (dBc AND dBFS)
SAMPLE RATE (MHz)
10559-014
Figure 14. AD9250-170 Single-Tone SNR/SFDR vs. Sample Rate (fS)
with fIN = 90.1 MHz
136 1184 8529
47521 24220 3479 450
0
100,000
200,000
300,000
400,000
500,000
600,000
N – 6 N – 4 N – 2 NN + 2 N + 4 N + 6
NUMBER O F HI TS
OUTPUT CODE
2,096, 064 TO TAL HIT S
1.4925 LSB rms
555924
498226
387659
281445
109722
177569
10559-015
Figure 15. AD9250-170 Grounded Input Histogram
–120
–100
AMPLITUDE (dBFS)
–80
–60
–40
–20
0
050 100 125
FREQUENCY (MHz)
10559-016
f
IN: 90.1MHz
f
S: 250MSPS
SNR: 71. 8dBF S
SFDR: 85dBc
Figure 16. AD9250-250 Single-Tone FFT with fIN = 90.1 MHz
AD9250 Data Sheet
Rev. E | Page 16 of 45
AMPLITUDE (dBFS)
050 100
–120
–100
–80
–60
–40
–20
0
FREQUENCY (MHz)
10559-017
fIN
: 185. 1M Hz
fS
: 250MSPS
SNR: 70. 7dBF S
SFDR: 85dBc
Figure 17. AD9250-250 Single-Tone FFT with fIN = 185.1 MHz
AMPLITUDE (dBFS)
050 100
–120
–100
–80
–60
–40
–20
0
FREQUENCY (MHz)
10559-018
f
IN
: 305. 1M Hz
f
S
: 250MSPS
SNR: 69.1dBFS
SF DR: 82dBc
Figure 18. AD9250-250 Single-Tone FFT with fIN = 305.1 MHz
0
20
40
60
80
100
120
–100 –80 –60 –40 –20 0
SNR (dBc)
SNR/S FDR (dBc an d d BFS)
SF DR ( dBc)
SNR (dBFS )
SF DR ( dBFS )
AIN ( dBFS )
10559-019
Figure 19. AD9250-250 Single-Tone SNR/SFDR vs. Input Amplitude (AIN)
with fIN = 185.1 MHz
60
70
80
90
100
0100 200 300
SNR (dBc)
SF DR ( dBFS )
FREQUENCY (MHz)
SNR/S FDR (dBc AND dBFS)
10559-020
Figure 20. AD9250-250 Single-Tone SNR/SFDR vs. Input Frequency (fIN)
–120
–100
–80
–60
–40
–20
0
–100 –80 –60 –40 –20 0
SF DR ( dBFS )
SF DR ( dBc)
IM D ( dBc)
AIN ( dBFS )
SFDR/IMD (dBc and dBFS)
IMD (dBFS)
10559-021
Figure 21. AD9250-250 Two-Tone SFDR/IMD vs. Input Amplitude (AIN)
with fIN1 = 89.12 MHz, fIN2 = 92.12 MHz, fS = 250 MSPS
SFDR/IMD (dBc and dBFS)
–120
–100
–80
–60
–40
–20
0
–100 –80 –60 –40 –20 0
SF DR ( dBc)
IM D ( dBc)
IMD (dBFS)
SF DR ( dBFS )
INPUT AMPL IT UDE (dBFS)
10559-022
Figure 22. AD9250-250 Two-Tone SFDR/IMD vs. Input Amplitude (AIN)
with fIN1 = 184.12 MHz, fIN2 = 187.12 MHz, fS = 250 MSPS
Data Sheet AD9250
Rev. E | Page 17 of 45
AMPLITUDE (dBFS)
050
FREQUENCY (MHz) 100
–120
–100
–80
–60
–40
–20
0
10559-023
250MSPS
89.12M Hz AT –7dBFS
92.12M Hz AT –7dBFS
SF DR: 86.4dBc
Figure 23. AD9250-250 Two-Tone FFT with fIN1 = 89.12 MHz, fIN2 = 92.12 MHz,
fS = 250 MSPS
AMPLITUDE (dBFS)
FREQUENCY (MHz)
050 100
–120
–100
–80
–60
–40
–20
0
10559-024
250MSPS
184.12M Hz AT –7dBFS
187.12M Hz AT –7dBFS
SFDR: 84dBc
Figure 24. AD9250-250 Two-Tone FFT with
fIN1 = 184.12 MHz, fIN2 = 187.12 MHz, fS = 250 MSPS
SNR/S FDR (dBc AND dBFS)
70
75
80
85
90
95
100
40 50 100 150 200 250
SAMPLE RATE
(MSPS)
SF DR_A ( dBc)
SF DR_B ( dBc)
SNR_A (dBc) S NR_B ( dBc)
10559-025
Figure 25. AD9250-250 Single-Tone SNR/SFDR vs. Sample Rate (fS)
with fIN = 90.1 MHz
418 2142 10549
52008 26647 4856 913
0
100k
200k
300k
400k
500k
600k
N – 6 N – 4 N – 2 NN + 2 N + 4 N + 6
NUMBER O F HI TS
OUTPUT CODE
2,095, 578 TO TAL HIT S
1.4535 LSB rms
570587
380706
276088
163389
109133
498242
10559-026
Figure 26. AD9250-250 Grounded Input Histogram
AD9250 Data Sheet
Rev. E | Page 18 of 45
EQUIVALENT CIRCUITS
VIN
AVDD
10559-027
Figure 27. Equivalent Analog Input Circuit
0.9V
15kΩ15kΩ
CLK+ CLK–
AVDD
AVDD AVDD
10559-028
Figure 28. Equivalent Clock lnput Circuit
BIAS
CONTROL
10kΩ
RFCLK INTERNAL
CLO CK DRIVE R
0.5pF
10559-029
AVDD
Figure 29. Equivalent RF Clock lnput Circuit
V
CM
DRVDD
SERDOUTx+ SERDOUTx–
3mA
3mA
3mA
3mA
R
TERM
10559-030
DRVDD
DRVDD
Figure 30. Digital CML Output Circuit
400Ω
SDIO
31kΩ
AVDD
10559-226
Figure 31. Equivalent SDIO Circuit
400Ω
31kΩ
AVDD
SCLK/PWDN
10559-225
Figure 32. Equivalent SCLK or PDWN Input Circuit
10559-224
400Ω28kΩ
AVDD
AVDD
CS
Figure 33. Equivalent CS Input Circuit
0.9V
17kΩ17kΩ
SYSREF+ SYSREF–
AVDD
AVDD AVDD
10559-134
Figure 34. Equivalent SYSREF± Input Circuit
Data Sheet AD9250
Rev. E | Page 19 of 45
RST 400
Ω
28k
Ω
DVDD
DVDD
10559-333
Figure 35. Equivalent RST Input Circuit
400
VCM
Ω
AVDD
10559-136
Figure 36. Equivalent VCM Circuit
0.9V
17kΩ17kΩ
SYNCINB+ SYNCINB–
DVDD
DVDD DVDD
10559-122
Figure 37. SYNCINB± Circuit
AD9250 Data Sheet
Rev. E | Page 20 of 45
THEORY OF OPERATION
The AD9250 has two analog input channels and two JESD204B
output lanes. The signal passes through several stages before
appearing at the output port(s).
The dual ADC design can be used for diversity reception of signals,
where the ADCs operate identically on the same carrier but from
two separate antennae. The ADCs can also be operated with
independent analog inputs. The user can sample frequencies
from dc to 300 MHz using appropriate low-pass or band-pass
filtering at the ADC inputs with little loss in ADC performance.
Operation to 400 MHz analog input is permitted but occurs at
the expense of increased ADC noise and distortion.
A synchronization capability is provided to allow synchronized
timing between multiple devices.
Programming and control of the AD9250 are accomplished
using a 3-pin, SPI-compatible serial interface.
ADC ARCHITECTURE
The AD9250 architecture consists of a dual, front-end, sample-
and-hold circuit, followed by a pipelined switched capacitor
ADC. The quantized outputs from each stage are combined into
a final 14-bit result in the digital correction logic. The pipelined
architecture permits the first stage to operate on a new input
sample and the remaining stages to operate on the preceding
samples. Sampling occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor digital-
to-analog converter (DAC) and an interstage residue amplifier
(MDAC). The MDAC magnifies the difference between the
reconstructed DAC output and the flash input for the next
stage in the pipeline. One bit of redundancy is used in each stage
to facilitate digital correction of flash errors. The last stage simply
consists of a flash ADC.
The input stage of each channel contains a differential sampling
circuit that can be ac- or dc-coupled in differential or single-
ended modes. The output staging block aligns the data, corrects
errors, and passes the data to the output buffers. The output buffers
are powered from a separate supply, allowing digital output noise to
be separated from the analog core.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9250 is a differential, switched capacitor
circuit that has been designed for optimum performance while
processing a differential input signal.
The clock signal alternatively switches the input between sample
mode and hold mode (see the configuration shown in Figure 38).
When the input is switched into sample mode, the signal source
must be capable of charging the sampling capacitors and settling
within 1/2 clock cycle.
A small resistor in series with each input can help reduce the
peak transient current required from the output stage of the
driving source. A shunt capacitor can be placed across the
inputs to provide dynamic charging currents. This passive
network creates a low-pass filter at the ADC input; therefore,
the precise values are dependent on the application.
In intermediate frequency (IF) undersampling applications, reduce
the shunt capacitors. In combination with the driving source
impedance, the shunt capacitors limit the input bandwidth.
Refer to the AN-742 Application Note, Frequency Domain
Response of Switched-Capacitor ADCs; the AN-827 Application
Note, A Resonant Approach to Interfacing Amplifiers to Switched-
Capacitor ADCs; and the Analog Dialogue article, “Transformer-
Coupled Front-End for Wideband A/D Converters,” for more
information on this subject.
C
PAR1
C
PAR1
C
PAR2
C
PAR2
S
S
S
S
S
S
C
FB
C
FB
C
S
C
S
BIAS
BIAS
VIN+
H
VIN–
10559-034
Figure 38. Switched-Capacitor Input
For best dynamic performance, match the source impedances
driving VIN+ and VIN− and differentially balance the inputs.
Input Common Mode
The analog inputs of the AD9250 are not internally dc biased.
In ac-coupled applications, the user must provide this bias
externally. Setting the device so that VCM = 0.5 × AVDD (or
0.9 V) is recommended for optimum performance. An on-board
common-mode voltage reference is included in the design and is
available from the VCM pin. Using the VCM output to set the
input common mode is recommended. Optimum performance
is achieved when the common-mode voltage of the analog input
is set by the VCM pin voltage (typically 0.5 × AVDD). Decouple
the VCM pin to ground by using a 0.1 µF capacitor, as described
in the Applications Information section. Place this decoupling
capacitor close to the pin to minimize the series resistance and
inductance between the part and this capacitor.
Differential Input Configurations
Optimum performance is achieved while driving the AD9250
in a differential input configuration. For baseband applications,
the AD8138, ADA4937-2, ADA4938-2, and ADA4930-2 differ-
ential drivers provide excellent performance and a flexible
interface to the ADC.
Data Sheet AD9250
Rev. E | Page 21 of 45
The output common-mode voltage of the ADA4930-2 is easily
set with the VCM pin of the AD9250 (see Figure 39), and the
driver can be configured in a Sallen-Key filter topology to
provide band-limiting of the input signal.
VIN 76.8Ω
120Ω
0.1µF
200Ω
200Ω
90Ω
0.1µF
AVDD
33Ω
33Ω
33Ω
15Ω
15Ω
5pF
15pF
15pF
ADC
VIN–
VIN+ VCM
ADA4930-2
10559-035
Figure 39. Differential Input Configuration Using the ADA4930-2
For baseband applications where SNR is a key parameter,
differential transformer coupling is the recommended input
configuration. An example is shown in Figure 40. To bias the
analog input, the VCM voltage can be connected to the center
tap of the secondary winding of the transformer.
2V p-p 49.9Ω
0.1µF
R1
R1
C1 ADC
VIN+
VIN– VCM
C2
R2
R3
R2
C2
R3 0.1µF
33Ω
10559-036
Figure 40. Differential Transformer-Coupled Configuration
Consider the signal characteristics when selecting a transformer.
Most RF transformers saturate at frequencies below a few
megahertz. Excessive signal power can also cause core saturation,
which leads to distortion.
At input frequencies in the second Nyquist zone and above, the
noise performance of most amplifiers is not adequate to achieve
the true SNR performance of the AD9250. For applications where
SNR is a key parameter, differential double balun coupling is
the recommended input configuration (see Figure 41). In this
configuration, the input is ac-coupled and the VCM voltage is
provided to each input through a 33 Ω resistor. These resistors
compensate for losses in the input baluns to provide a 50 Ω
impedance to the driver.
ADC
R1
0.1µF
0.1µF
2V p-p VIN+
VIN– VCM
C1
C2
R1
R2
R2
0.1µF
S
0.1µF
C2
33Ω
33Ω
SP
A
P
R3
R3 0.1µF
33Ω
10559-037
Figure 41. Differential Double Balun Input Configuration
In the double balun and transformer configurations, the value
of the input capacitors and resistors is dependent on the input
frequency and source impedance. Based on these parameters,
the value of the input resistors and capacitors may need to be
adjusted or some components may need to be removed. Table 9
displays recommended values to set the RC network for different
input frequency ranges. However, these values are dependent on
the input signal and bandwidth and should be used only as a
starting guide. Note that the values given in Table 9 are for each
R1, R2, C1, C2, and R3 components shown in Figure 40 and
Figure 41.
Table 9. Example RC Network
Frequency
Range
(MHz)
R1
Series
(Ω)
C1
Differential
(pF)
R2
Series
(Ω)
C2
Shunt
(pF)
R3
Shunt
(Ω)
0 to 100 33 8.2 0 15 24.9
100 to 400 15 8.2 0 8.2 24.9
>400 15 ≤3.9 0 ≤3.9 24.9
An alternative to using a transformer-coupled input at frequencies
in the second Nyquist zone is to use an amplifier with variable
gain. The AD8375 or AD8376 digital variable gain amplifier
(DVGAs) provides good performance for driving the AD9250.
Figure 42 shows an example of the AD8376 driving the AD9250
through a band-pass antialiasing filter.
AD8376 ADC
1µH
1µH 1nF 1nF
VPOS
VCM
15pF
68nH
20kΩ║2.5pF
301Ω
165Ω
165Ω
5.1pF 3.9pF
180nH1000pF
1000pF
NOTES
1. ALL INDUCTORS ARE COILCRAFT®0603CS COMPONENTS WITH THE
EXCEPTION OF THE 1µH CHOKE INDUCTORS (COILCRAFT 0603LS).
2. FILTER VALUES SHOWN ARE FOR A 20MHz BANDWIDTH FILTER
CENTERED AT 140MHz.
180nH
220nH
220nH
10559-038
Figure 42. Differential Input Configuration Using the AD8376
VOLTAGE REFERENCE
A stable and accurate voltage reference is built into the AD9250.
The full-scale input range can be adjusted by varying the reference
voltage via the SPI. The input span of the ADC tracks the reference
voltage changes linearly.
CLOCK INPUT CONSIDERATIONS
The AD9250 has two options for deriving the input sampling
clock, a differential Nyquist sampling clock input or an RF clock
input (which is internally divided by 4). The clock input is selected
in Register 0x09 and by default is configured for the Nyquist clock
input. For optimum performance, clock the AD9250 Nyquist
sample clock input, CLK+ and CLK−, with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK− pins
via a transformer or via capacitors. These pins are biased internally
(see Figure 43) and require no external bias. If the clock inputs
are floated, CLK− is pulled slightly lower than CLK+ to prevent
spurious clocking.
AD9250 Data Sheet
Rev. E | Page 22 of 45
Nyquist Clock Input Options
The AD9250 Nyquist clock input supports a differential clock
between 40 MHz to 625 MHz. The clock input structure supports
differential input voltages from 0.3 V to 3.6 V and is therefore
compatible with various logic family inputs, such as CMOS,
LVDS, and LVPECL. A sine wave input is also accepted, but
higher slew rates typically provide optimal performance. Clock
source jitter is a critical parameter that can affect performance, as
described in the Jitter Considerations section. If the inputs are
floated, pull the CLK− pin low to prevent spurious clocking.
The Nyquist clock input pins, CLK+ and CLK−, are internally
biased to 0.9 V and have a typical input impedance of 4 pF in
parallel with 10 kΩ (see Figure 43). The input clock is typically
ac-coupled to CLK+ and CLK−. Some typical clock drive circuits
are presented in Figure 44 through Figure 47 for reference.
AVDD
CLK+
4pF4pF
CLK–
0.9V
10559-039
Figure 43. Equivalent Nyquist Clock Input Circuit
For applications where a single-ended low jitter clock between
40 MHz to 200 MHz is available, an RF transformer is recom-
mended. An example using an RF transformer in the clock network
is shown in Figure 44. At frequencies above 200 MHz, an RF balun
is recommended, as seen in Figure 45. The back-to-back Schottky
diodes across the transformer secondary limit clock excursions into
the AD9250 to approximately 0.8 V p-p differential. This limit helps
prevent the large voltage swings of the clock from feeding through
to other portions of the AD9250, yet preserves the fast rise and fall
times of the clock, which are critical to low jitter performance.
390pF
390pF390pF
SCHOTTKY
DIODES:
HSMS2822
CLOCK
INPUT 50Ω100Ω
CLK–
CLK+
ADC
Mini-Circuits
®
ADT1-1WT,1:1Z
XFMR
10559-040
Figure 44. Transformer-Coupled Differential Clock (Up to 200 MHz)
390pF 390pF
390pF
CLOCK
INPUT
1nF
25Ω
25Ω
CLK–
CLK+
SCHOTTKY
DIODES:
HSMS2822
ADC
10559-041
Figure 45. Balun-Coupled Differential Clock (Up to 625 MHz)
In some cases, it is desirable to buffer or generate multiple
clocks from a single source. In those cases, Analog Devices, Inc.,
offers clock drivers with excellent jitter performance. Figure 46
shows a typical PECL driver circuit that uses PECL drivers such
as the AD9510, AD9511, AD9512, AD9513, AD9514, AD9515,
AD9516-0 through AD9516-5 device family, AD9517-0 through
AD9517-4 device family, AD9518-0 through AD9518-4 device
family, AD9520-0 through AD9520-5 device family, AD9522-0
through AD9522-5 device family, AD9523, AD9524, and
ADCLK905/ADCLK907/ADCLK925
100Ω
0.1µF
0.1µF
0.1µF
0.1µF
240Ω
240Ω
PECLDRIVER
50kΩ50kΩ
CLK–
CLK+
CLOCK
INPUT
CLOCK
INPUT
AD95xx
ADC
10559-042
Figure 46. Differential PECL Sample Clock (Up to 625 MHz)
Analog Devices also offers LVDS clock drivers with excellent jitter
performance. A typical circuit is shown in Figure 47 and uses LVDS
drivers such as the AD9510, AD9511, AD9512, AD9513, AD9514,
AD9515, AD9516-0 through AD9516-5 device family, AD9517-0
through AD9517-4 device family, AD9518-0 through AD9518-4
device family, AD9520-0 through AD9520-5 device family,
AD9522-0 through AD9522-5 device family, AD9523, and AD9524.
100Ω
0.1µF
0.1µF
0.1µF
0.1µF
50kΩ50kΩ
CLK–
CLK+
CLOCK
INPUT
CLOCK
INPUT
AD95xx
LVDSDRIVER
ADC
10559-043
Figure 47. Differential LVDS Sample Clock (Up to 625 MHz)
RF Clock Input Options
The AD9250 RF clock input supports a single-ended clock
between 625 GHz to 1.5 GHz. The equivalent RF clock input
circuit is shown in Figure 48. The input is self biased to 0.9 V and
is typically ac-coupled. The input has a typical input impedance
of 10 kΩ in parallel with 1 pF at the RFCLK pin.
BIAS
CONTROL
10kΩ
RFCLK INTERNAL
CLO CK DRIVE R
1pF
10559-044
Figure 48. Equivalent RF Clock Input Circuit
It is recommended to drive the RF clock input of the AD9250 with
a PECL or sine wave signal with a minimum signal amplitude of
600 mV peak to peak. Regardless of the type of signal being used,
clock source jitter is of the most concern, as described in the Jitter
Considerations section. Figure 49 shows the preferred method of
clocking when using the RF clock input on the AD9250. It is
recommended to use a 50 Ω transmission line to route the clock
signal to the RF clock input of the AD9250 due to the high
frequency nature of the signal and terminate the transmission
line close to the RF clock input.
RFCLK
ADC
50Ω Tx LINE
RF CL OCK
INPUT
0.1µF
50Ω
10559-045
Figure 49. Typical RF Clock Input Circuit
Data Sheet AD9250
Rev. E | Page 23 of 45
0.1µF 0.1µF
0.1µF
0.1µF
LVPECL
DRIVER
AD9515
127Ω
V
DD
82.5Ω
127Ω
82.5Ω
C
LOCK INPUT
C
LOCK INPUT
RFCLK
ADC
50Ω Tx LINE 0.1µF
50Ω
10559-046
Figure 50. Differential PECL RF Clock Input Circuit
Figure 50 shows the RF clock input of the AD9250 being driven
from the LVPECL outputs of the AD9515. The differential
LVPECL output signal from the AD9515 is converted to a single-
ended signal using an RF balun or RF transformer. The RF balun
configuration is recommended for clock frequencies associated
with the RF clock input.
Input Clock Divider
The AD9250 contains an input clock divider with the ability to
divide the Nyquist input clock by integer values between 1 and 8.
The RF clock input uses an on-chip predivider to divide the clock
input by four before it reaches the 1 to 8 divider. This allows
higher input frequencies to be achieved on the RF clock input. The
divide ratios can be selected using Register 0x09 and Register 0x0B.
Register 0x09 is used to set the RF clock input, and Register 0x0B
can be used to set the divide ratio of the 1-to-8 divider for both
the RF clock input and the Nyquist clock input. For divide ratios
other than 1, the duty-cycle stabilizer is automatically enabled.
RFCLK
NYQUIST
CLOCK
÷1 TO ÷8
DIVIDER
10559-047
÷4
Figure 51. AD9250 Clock Divider Circuit
The AD9250 clock divider can be synchronized using the external
SYSREF input. Bit 1 and Bit 2 of Register 0x3A allow the clock
divider to be resynchronized on every SYSREF signal or only on
the first signal after the register is written. A valid SYSREF causes
the clock divider to reset to its initial state. This synchronization
feature allows multiple parts to have their clock dividers aligned to
guarantee simultaneous input sampling.
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals and, as a result, may be sensitive to
clock duty cycle. Commonly, a ±5% tolerance is required on the
clock duty cycle to maintain dynamic performance characteristics.
The AD9250 contains a DCS that retimes the nonsampling (falling)
edge, providing an internal clock signal with a nominal 50% duty
cycle. This allows the user to provide a wide range of clock input
duty cycles without affecting the performance of the AD9250.
Jitter on the rising edge of the input clock is still of paramount
concern and is not reduced by the duty cycle stabilizer. The duty
cycle control loop does not function for clock rates less than
40 MHz nominally. The loop has a time constant associated
with it that must be considered when the clock rate can change
dynamically. A wait time of 1.5 μs to 5 μs is required after a
dynamic clock frequency increase or decrease before the DCS
loop is relocked to the input signal. During the time that the
loop is not locked, the DCS loop is bypassed, and the internal
device timing is dependent on the duty cycle of the input clock
signal. In such applications, it may be appropriate to disable the
duty cycle stabilizer. In all other applications, enabling the DCS
circuit is recommended to maximize ac performance.
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given input frequency
(fIN) due to jitter (tJ) can be calculated by
SNRHF = −10 log[(2π × fIN × tJRMS)2 + 10 )10/( LF
SNR]
In the equation, the rms aperture jitter represents the root-mean-
square of all jitter sources, which include the clock input, the
analog input signal, and the ADC aperture jitter specification. IF
undersampling applications are particularly sensitive to jitter,
as shown in Figure 52.
80
75
70
65
60
55
50
1 10 100 1000
INPUT FREQUENCY (MHz)
SNR (dBc)
0.05ps
0.2ps
0.5ps
1ps
1.5ps
MEASURED
10559-048
Figure 52. AD9250-250 SNR vs. Input Frequency and Jitter
AD9250 Data Sheet
Rev. E | Page 24 of 45
Treat the clock input as an analog signal in cases where aperture
jitter may affect the dynamic range of the AD9250. Separate the
power supplies for the clock drivers from the ADC output driver
supplies to avoid modulating the clock signal with digital noise.
Low jitter, crystal controlled oscillators make the best clock
sources. If the clock is generated from another type of source (by
gating, dividing, or another method), retime it by the original
clock at the last step.
Refer to the AN-501 Application Note, Aperture Uncertainty and
ADC System Performance and the AN-756 Application Note,
Sampled Systems and the Effects of Clock Phase Noise and Jitter for
more information about jitter performance as it relates to ADCs.
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 53, the power dissipated by the AD9250 is
proportional to its sample rate. The data in Figure 53 was taken
using the same operating conditions as those used for the Typical
Performance Characteristics section.
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
40 90 140 190 240
TOTAL POWER (W)
POWER ( AV DD)
POWER ( DV DD)
TOTAL POWER
ENCODE FREQUENCY (MSPS)
10559-149
Figure 53. AD9250-250 Power vs. Encode Rate
By asserting PDWN (either through the SPI port or by asserting
the PDWN pin high), the AD9250 is placed in power-down mode.
In this state, the ADC typically dissipates about 9 mW. Asserting the
PDWN pin low returns the AD9250 to its normal operating mode.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering power-
down mode and then must be recharged when returning to normal
operation. As a result, wake-up time is related to the time spent
in power-down mode, and shorter power-down cycles result in
proportionally shorter wake-up times.
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered when
faster wake-up times are required. See the Memory Map Register
Description section and the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI, for additional details.
Data Sheet AD9250
Rev. E | Page 25 of 45
DIGITAL OUTPUTS
JESD204B TRANSMIT TOP LEVEL DESCRIPTION
The AD9250 digital output uses the JEDEC Standard No.
JESD204B, Serial Interface for Data Converters. JESD204B is a
protocol to link the AD9250 to a digital processing device over a
serial interface of up to 5 Gbps link speeds (3.5 Gbps, 14-bit
ADC data rate). The benefits of the JESD204B interface include
a reduction in required board area for data interface routing
and the enabling of smaller packages for converter and logic
devices. The AD9250 supports single or dual lane interfaces.
JESD204B OVERVIEW
The JESD204B data transmit block assembles the parallel data from
the ADC into frames and uses 8b/10b encoding as well as optional
scrambling to form serial output data. Lane synchronization is
supported using special characters during the initial establishment
of the link, and additional synchronization is embedded in the
data stream thereafter. A matching external receiver is required
to lock onto the serial data stream and recover the data and clock.
For additional details on the JESD204B interface, refer to the
JESD204B standard.
The AD9250 JESD204B transmit block maps the output of the
two ADCs over a link. A link can be configured to use either
single or dual serial differential outputs that are called lanes.
The JESD204B specification refers to a number of parameters to
define the link, and these parameters must match between the
JESD204B transmitter (AD9250 output) and receiver.
The JESD204B link is described according to the following
parameters:
• S = samples transmitted/single converter/frame cycle
(AD9250 value = 1)
• M = number of converters/converter device
(AD9250 value = 2 by default, or can be set to 1)
• L = number of lanes/converter device
(AD9250 value = 1 or 2)
• N = converter resolution (AD9250 value = 14)
• N’ = total number of bits per sample (AD9250 value = 16)
• CF = number of control words/frame clock cycle/converter
device (AD9250 value = 0)
• CS = number of control bits/conversion sample
(configurable on the AD9250 up to 2 bits)
• K = number of frames per multiframe (configurable on
the AD9250)
• HD = high density mode (AD9250 value = 0)
• F = octets/frame (AD9250 value = 2 or 4, dependent upon
L = 2 or 1)
• C = control bit (overrange, overflow, underflow; available
on the AD9250)
• T = tail bit (available on the AD9250)
• SCR = scrambler enable/disable (configurable on the AD9250)
• FCHK = checksum for the JESD204B parameters
(automatically calculated and stored in register map)
Figure 54 shows a simplified block diagram of the AD9250
JESD204B link. By default, the AD9250 is configured to use
two converters and two lanes. Converter A data is output to
SERDOUT0+/SERDOUT0−, and Converter B is output to
SERDOUT1+/SERDOUT1−. The AD9250 allows for other
configurations such as combining the outputs of both converters
onto a single lane or changing the mapping of the A and B
digital output paths. These modes are setup through a quick
configuration register in the SPI register map, along with
additional customizable options.
By default in the AD9250, the 14-bit converter word from each
converter is broken into two octets (8 bits of data). Bit 13 (MSB)
through Bit 6 are in the first octet. The second octet contains
Bit 5 through Bit 0 (LSB), and two tail bits are added to fill the
second octet. The tail bits can be configured as zeros, pseudo-
random number sequence or control bits indicating overrange,
underrange, or valid data conditions.
The two resulting octets can be scrambled. Scrambling is
optional; however, it is available to avoid spectral peaks when
transmitting similar digital data patterns. The scrambler uses a
self synchronizing, polynomial-based algorithm defined by the
equation 1 + x14 + x15. The descrambler in the receiver should be
a self-synchronizing version of the scrambler polynomial.
The two octets are then encoded with an 8b/10b encoder. The
8b/10b encoder works by taking eight bits of data (an octet) and
encoding them into a 10-bit symbol. Figure 55 shows how the
14-bit data is taken from the ADC, the tail bits are added, the two
octets are scrambled, and how the octets are encoded into two
10-bit symbols. Figure 55 illustrates the default data format.
At the data link layer, in addition to the 8b/10b encoding, the
character replacement is used to allow the receiver to monitor
frame alignment. The character replacement process occurs on the
frame and multiframe boundaries, and implementation depends
on which boundary is occurring, and if scrambling is enabled.
If scrambling is disabled, the following applies. If the last scrambled
octet of the last frame of the multiframe equals the last octet of
the previous frame, the transmitter replaces the last octet with
the control character /A/ = /K28.3/. On other frames within the
multiframe, if the last octet in the frame equals the last octet of
the previous frame, the transmitter replaces the last octet with
the control character /F/= /K28.7/.
If scrambling is enabled, the following applies. If the last octet of
the last frame of the multiframe equals 0x7C, the transmitter
replaces the last octet with the control character /A/ = /K28.3/.
On other frames within the multiframe, if the last octet equals
0xFC, the transmitter replaces the last octet with the control
character /F/ = /K28.7/.
Refer to JEDEC Standard No. 204B-July 2011 for additional
information about the JESD204B interface. Section 5.1 covers
the transport layer and data format details and Section 5.2
covers scrambling and descrambling.
AD9250 Data Sheet
Rev. E | Page 26 of 45
JESD204B SYNCHRONIZATION DETAILS
The AD9250 supports JESD204B Subclass 0 and Subclass 1 and
establishes synchronization of the link through one or two
control signals, SYNC and Subclass 1 also use SYSREF, and a
common device clock. SYSREF and SYNC are common to all
converter devices for alignment purposes at the system level.
The synchronization process is accomplished over three phases:
code group synchronization (CGS), initial lane alignment
sequence (ILAS), and data transmission. If scrambling is
enabled, scrambling begins with the first data byte following
the last alignment character of the ILAS. CGS and ILAS
phases are not scrambled.
CGS Phase
In the CGS phase, the JESD204B transmit block transmits
/K28.5/ characters. The receiver (external logic device) must
locate K28.5 characters in its input data stream using clock
and data recovery (CDR) techniques.
When in Subclass 1 mode, the receiver locks onto the K28.5
characters. Once detected, the receiver initiates a SYSREF edge
so that the AD9250 transmit data establishes a local multiframe
clock (LMFC) internally.
The SYSREF edge also resets any sampling edges within the
ADC to align sampling instances to the LMFC. This is important
to maintain synchronization across multiple devices.
If Subclass 0: at the next receiver’s internal clock; if Subclass 1: at
the next receiver’s LMFC boundary, the receiver or logic device
de-asserts the SYNC~ signal (SYNCINB± goes high), and the
transmitter block begins the ILAS phase.
ILAS Phase
In the ILAS phase, the transmitter sends out a known pattern,
and the receiver aligns all lanes of the link and verifies the
parameters of the link.
The ILAS phase begins after SYNC~ has been de-asserted
(goes high). If Subclass 0: the transmitter begins ILAS at the
next transmitter’s internal clock; if Subclass 1: at the next
transmitter’s internal LMFC boundary, the transmit block
begins to transmit four multiframes. Dummy samples are
inserted between the required characters so that full
multiframes are transmitted. The four multiframes include
the following:
• Multiframe 1: Begins with an /R/ character [K28.0] and
ends with an /A/ character [K28.3].
• Multiframe 2: Begins with an /R/ character followed by a /Q/
[K28.4] character, followed by link configuration parameters
over 14 configuration octets (see Table 10), and ends with
an /A/ character. Many of the parameters values are of the
notation of the value − 1.
• Multiframe 3: Is the same as Multiframe 1.
• Multiframe 4: Is the same as Multiframe 1.
Data Transmission Phase
In the data transmission phase, frame alignment is monitored
with control characters. Character replacement is used at the
end of frames. Character replacement in the transmitter occurs
in the following instances:
• If scrambling is disabled and the last octet of the frame or
multiframe equals the octet value of the previous frame.
• If scrambling is enabled and the last octet of the multiframe is
equal to 0x7C, or the last octet of a frame is equal to 0xFC.
Table 10. Fourteen Configuration Octets of the ILAS Phase
No.
Bit 7
(MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0
(LSB)
0 DID[7:0]
1 BID[3:0]
2 LID[4:0]
3
SCR
L[4:0]
4 F[7:0]
5 K[4:0]
6 M[7:0]
7 CS[1:0] N[4:0]
8 SUBCLASS[2:0] N’[4:0]
9 JESDV[2:0] S[4:0]
10 HD CF[4:0]
11 Reserved, Don’t Care
12
Reserved, Don’t Care
13 FCHK[7:0]
LINK SETUP PARAMETERS
The following demonstrates how to configure the AD9250
JESD204B interface paremeters. These details are a subset of the
SPI initialization sequence shown in Figure 63 and Table 19.
The steps to configure the output include the following:
1. Disable lanes before changing the configuration.
2. Select the quick configuration option.
3. Configure the detailed options.
4. Check FCHK, checksum of JESD204B interface parameters.
5. Set the additional digital output configuration options.
6. Re-enable lane(s).
Disable Lanes Before Changing Configuration
Before modifying the JESD204B link parameters, disable the link
and hold it in reset. This is accomplished by writing Logic 1 to
Register 0x5F, Bit 0.
Select Quick Configuration Option
Write to Register 0x5E, the 204B quick configuration register to
select the configuration options. See Table 13 for configuration
options and resulting JESD204B parameter values.
• 0x11 = one converter, one lane
• 0x12 = one converter, two lanes
• 0x21 = two converters, one lane
• 0x22 = two converters, two lanes
Data Sheet AD9250
Rev. E | Page 27 of 45
Configure Detailed Options
Configure the tail bits and control bits.
• With N’ = 16 and N = 14, there are two bits available per
sample for transmitting additional information over the
JESD204B link. The options are tail bits or control bits. By
default, tail bits of 0b00 value are used.
• Tail bits are dummy bits sent over the link to complete the
two octets and do not convey any information about the input
signal. Tail bits can be fixed zeros (default) or psuedo
random numbers (Register 0x5F, Bit 6).
• One or two control bits can be used instead of the tail bits
through Register 0x72, Bits[7:6]. The tail bits can be set
using Register 0x14, Bits[7:5], and can be enabled using
Address 0x5F, Bit 6.
Set lane identification values.
• JESD204B allows parameters to identify the device and
lane. These parameters are transmitted during the ILAS
phase, and they are accessible in the internal registers.
• There are three identification values: device identification
(DID), bank identification (BID), and lane identification
(LID). DID and BID are device specific; therefore, they can
be used for link identification.
Set number of frames per multiframe, K
• Per the JESD204B specification, a multiframe is defined as a
group of K successive frames, where K is between 1 and 32,
and it requires that the number of octets be between 17 and
1024. The K value is set to 32 by default in Register 0x70,
Bits[7:0]. Note that Register 0x70 represents a value of K − 1.
• The K value can be changed; however, it must comply with
a few conditions. The AD9250 uses a fixed value for octets
per frame [F] based on the JESD204B quick configuration
setting. K must also be a multiple of 4 and conform to the
following equation.
32 ≥ K ≥ Ceil (17/F)
• The JESD204B specification also calls for the number of
octets per multiframe (K × F) to be between 17 and 1024.
The F value is fixed through the quick configuration
setting to ensure this relationship is true.
Table 11. JESD204B Configurable Identification Values
DID Value Register, Bits Value Range
LID (Lane 0) 0x66, [4:0] 0…31
LID (Lane 1) 0x67, [4:0] 0…31
DID 0x64, [7:0] 0…255
BID 0x65, [3:0] 0…15
Scramble, SCR.
• Scrambling can be enabled or disabled by setting Register 0x6E,
Bit 7. By default, scrambling is enabled. Per the JESD204B
protocol, scrambling is only functional after the lane
synchronization has completed.
Select lane synchronization options.
Most of the synchronization features of the JESD204B interface
are enabled by default for typical applications. In some cases,
these features can be disabled or modified as follows:
• ILAS enabling is controlled in Register 0x5F, Bits[3:2] and
by default is enabled. Optionally, to support some unique
instances of the interfaces (such as NMCDA-SL), the
JESD204B interface can be programmed to either disable
the ILAS sequence or continually repeat the ILAS sequence.
The AD9250 has fixed values of some of the JESD204B interface
parameters, and they are as follows:
• [N] = 14: number of bits per converter is 14, in Register 0x72,
Bits[4:0]; Register 0x72 represents a value of N − 1.
• [N’] = 16: number of bits per sample is 16, in Register 0x73,
Bits[4:0]; Register 0x73 represents a value of N’ − 1.
• [CF] = 0: number of control words/ frame clock
cycle/converter is 0, in Register 0x75, Bits[4:0].
Verif y read only values: lanes per link (L), octets per frame (F),
number of converters (M), and samples per converter per frame
(S). The AD9250 calculates values for some JESD204B parameters
based on other settings, particularly the quick configuration
register selection. The read only values here are available in the
register map for verification.
• [L] = lanes per link can be 1 or 2, read the values from
Register 0x6E, Bit 0
• [F] = octets per frame can be 1, 2, or 4, read the value from
Register 0x6F, Bits[7:0]
• [HD] = high density mode can be 0 or 1, read the value
from Register 0x75, Bit 7
• [M] = number of converters per link can be 1 or 2, read the
value from Register 0x71, Bits[7:0]
• [S] = samples per converter per frame can be 1 or 2, read
the value from Register 0x74, Bits[4:0]
Check FCHK, Checksum of JESD204B Interface Parameters
The JESD204B parameters can be verified through the checksum
value [FCHK] of the JESD204B interface parameters. Each lane has
a FCHK value associated with it. The FCHK value is transmitted
during the ILAS second multiframe and can be read from the
internal registers.
The checksum value is the modulo 256 sum of the parameters
listed in the No. column of Table 12. The checksum is calculated
by adding the parameter fields before they are packed into the
octets shown in Table 12.
The FCHK for the lane configuration for data coming out of
Lane 0 can be read from Register 0x78. Similarly, the FCHK for
the lane configuration for data coming out of Lane 1 can be read
from Register 0x79.
AD9250 Data Sheet
Rev. E | Page 28 of 45
Table 12. JESD204B Configuration Table Used in ILAS and
CHKSUM Calculation
No.
Bit 7
(MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0
(LSB)
0 DID[7:0]
1 BID[3:0]
2 LID[4:0]
3 SCR L[4:0]
4 F[7:0]
5 K[4:0]
6 M[7:0]
7 CS[1:0] N[4:0]
8 SUBCLASS[2:0] N’[4:0]
9 JESDV[2:0] S[4:0]
10 CF[4:0]
Additional Digital Output Configuration Options
Other data format controls include the following:
Invert polarity of serial output data: Register 0x60, Bit 1.
ADC data format (offset binary or twos complement):
Register 0x14, Bits[1:0].
Options for interpreting single on SYSREF± and SYNCINB±:
Register 0x3A. See Table 14 for additional descriptions of
Register 0x3A controls.
Option to remap converter and lane assignments, Register 0x82
and Register 0x83. See Figure 54 for simplified block diagram.
Re-Enable Lanes After Configuration
After modifying the JESD204B link parameters, enable the link so
that the synchronization process can begin. This is accomplished
by writing Logic 0 to Register 0x5F, Bit 0.
Internal FIFO Timing Optimization
Each lane of the of the AD9250 JESD204B digital path includes
an internal FIFO situated between the framer and serializer,
which operate from two different clock domains, the ADC
sample clock and JESD204B PLL domains. To optimize the
write and read pointers against possible FIFO overflow (or
underflow) under extreme temperature changes and inconsistent
power-up conditions, additional steps are required to increase the
timing margin. The procedures described in Step 15 of Table 19
adjust the write clock phase (via Register 0xEE and Register
0xEF) with respect to the read clock to optimize the timing
margin.
CONVERTER A
CONVERTER B
CONVERTER B
INPUT
CONVERTER
A
INPUT
SYSREF
SYNCINB
CONVERTER B
SAMPLE
CONVERTER A
SAMPLE
AD9250 DUAL ADC
LANE 0
LANE 1
SERDOUT0
SERDOUT1
LANE 1
LANE 0
A
A
B
B
PRIMARY CONVERTER
INPUT [0]
PRIMARY LANE
OUTPUT [0]
PRIMARY CONVERTER
INPUT [0]
PRIMARY LANE
OUTPUT [0]
JESD204B LANE CONTROL
(M = 1, 2; L = 1, 2)
LANE MUX
(SPI REGISTER
MAPPING: 0x82,0x83)
SECONDARY CONVERTER
INPUT [1]
SECONDARY LANE
OUTPUT [1]
SECONDARY CONVERTER
INPUT [1]
SECONDARY LANE
OUTPUT [1]
JESD204B LANE CONTROL
(M = 1, 2; L = 1, 2)
10559-049
Figure 54. AD9250 Transmit Link Simplified Block Diagram
Data Sheet AD9250
Rev. E | Page 29 of 45
8B/10B
ENCODER/
CHARACTER
REPLACEMENT
SERIALIZER
t
. . .
~SYNC
SYSREF
VINA+
(MSB)
(LSB)
VINA–
SERDOUT±
A PATH
ADC
TEST PATTERN
16-BIT
JESD204B
TEST PATTERN
8-BIT
ADC
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
C0
OCTET0
OCTET1
C1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
E0
E1
E2
E3
E4
E5
E6
E7
E10
E11
E12
E13
E14
E15
E16
E17
E8
E9
E0E1E2E3E4E5E6E7E8E9
E18
E19
E19
OPTIONAL
SCRAMBLER
1 + x14 + x15
JESD204B
TEST PATTERN
10-BIT
10559-050
Figure 55. AD9250 Digital Processing of JESD204B Lanes
Table 13. AD9250 JESD204B Typical Configurations
JESD204B
Configure
Setting
M (No. of Converters),
Register 0x71,
Bits[7:0]
L (No. of Lanes),
Register 0x6E,
Bit 0
F (Octets/Frame),
Register 0x6F,
Bits[7:0], Read Only
S (Samples/ADC/Frame),
Register 0x74, Bits[4:0],
Read Only
HD (High Density Mode),
Register 0x75, Bit 7,
Read Only
0x11 1 1 2 1 0
0x12 1 2 1 1 1
0x21 2 1 4 1 0
0x22 (Default) 2 2 2 1 0
DATA
FROM
ADC
FRAME
ASSEMBLER
(ADD TAIL BITS)
OPTIONAL
SCRAMBLER
1 + x
14
+ x
15
8B/10B
ENCODER TO
RECEIVER
10559-052
Figure 56. AD9250 ADC Output Data Path
AD9250 Data Sheet
Rev. E | Page 30 of 45
Table 14. AD9250 JESD204B Configuration, Register 0x3A
Bit No. Register Description Functional Description
0 Enable internal
SYSREF buffer
This bit controls the on-chip buffer for the SYSREF singal. By default, this bit is 0, which disables the buffer. If the
AD9250 is configured for JESD204B Subclass 1 operation, SYSREF is required to align the JESD204B link and this
bit must be set to 1.
To avoid a false trigger as a result of transients caused when enabling the buffer (particularly for one-shot SYSREF
configuration), set this bit first and then in a consecutive SPI register write, configure all remaining bits in Register 0x3A
to the desired JESD204B link configuration, including keeping this bit at 1.
A setting of 0 (default) gates the SYSREF signal such that the internal logic is not affected by an external SYSREF.
Set this bit to 0 when in Subclass 0, that is, when SYSREF is not used.
If using Subclass 1 with one-shot SYSREF mode, enable the buffer while the SYSREF is established, but then
disable it during normal operation.
If using Subclass 1 with continuous SYSREF mode, the buffer must remain enabled for normal operation.
1 SYSREF± enable This bit enables the circuitry that uses the SYSREF input signal and must be on to enable Subclass 1 operation.
Set this bit to 1 when using JESD204B Subclass 1 operation.
This bit is self clearing after a valid SYSREF occurs when SYSREF± mode (Register 0x3A, Bit 2) is set to 1
(configured for one-shot SYSREF operation).
Note that SYSREF is still used in some digital circuitry even if this bit is 0; to disable the SYSREF signal internally,
Register 0x3A Bit 0 must be set to 0.
2 SYSREF± mode This bit is used in Subclass 1 operation to define one shot or continuous SYSREF mode. To configure continuous
(or gapped periodic) SYSREF, this bit is set to 0. For one-shot operation, this bit is set to 1. In one-shot mode, it is
recommended that the SYSREF buffer be disabled after SYSREF has occurred by setting Register 0x3A, Bit 0 to 0.
3 Realign on SYSREF;
forSubclass 1 only
When this bit is set to 1, the internal clock alignment for the JESD204B timing is forced when an active SYSREF
occurs. This is recommended only for one-shot mode and must only be done prior to initially establishing a link. This
resets the JESD204B link on active SYSREF.
For continuous SYSREF mode, this bit must be set to 0 during normal operation.
4 Realign on SYNCB;
for Subclass 1 only
When this bit is set to 1, the internal clock alignment for the JESD204B timing is forced when an active SYNC
occurs. An active SYNC requires the SYNCINB input to be logic low for at least four consecutive LMFCs.
Table 15. AD9250 JESD204B Frame Alignment Monitoring and Correction Replacement Characters
Scrambling Lane Synchronization Character to be Replaced Last Octet in Multiframe Replacement Character
Off On Last octet in frame repeated from previous frame No K28.7
Off On Last octet in frame repeated from previous frame Yes K28.3
Off Off Last octet in frame repeated from previous frame Not applicable K28.7
On On Last octet in frame equals D28.7 No K28.7
On
On
Last octet in frame equals D28.3
Yes
K28.3
On Off Last octet in frame equals D28.7 Not applicable K28.7
FRAME AND LANE ALIGNMENT MONITORING
AND CORRECTION
Frame alignment monitoring and correction is part of the JESD204B
specification. The 14-bit word requires two octets to transmit all
the data. The two octets (MSB and LSB), where F = 2, make up
a frame. During normal operating conditions, frame alignment
is monitored via alignment characters, which are inserted under
certain conditions at the end of a frame. Table 15 summarizes the
conditions for character insertion along with the expected characters
under the various operation modes. If lane synchronization is
enabled, the replacement character value depends on whether
the octet is at the end of a frame or at the end of a multiframe.
Based on the operating mode, the receiver can ensure that it is
still synchronized to the frame boundary by correctly receiving
the replacement characters.
DIGITAL OUTPUTS AND TIMING
The AD9250 has differential digital outputs that power up by default.
The driver current is derived on-chip and sets the output current at
each output equal to a nominal 4 mA. Each output presents a 100 Ω
dynamic internal termination to reduce unwanted reflections.
Place a 100 Ω differential termination resistor at each receiver input
to result in a nominal 300 mV peak-to-peak swing at the receiver
(see Figure 57). Alternatively, single-ended 50 Ω termination
can be used. When single-ended termination is used, the
termination voltage should be DRVDD/2; otherwise, ac coupling
capacitors can be used to terminate to any single-ended voltage.
100Ω OR
100Ω
DIFFERENTIAL
TRACE P AIR
SERDOUTx+
DRVDD
VRXCM
SERDOUTx–
VCM = Rx VCM
OUTPUT SWING = VOD
(SEE TABLE 3)
0.1µF
0.1µF
RECEIVER
10559-053
Figure 57. AC-Coupled Digital Output Termination Example
Data Sheet AD9250
Rev. E | Page 31 of 45
The AD9250 digital outputs can interface with custom ASICs and
FPGA receivers, providing superior switching performance in
noisy environments. Single point-to-point network topologies are
recommended with a single differential 100 Ω termination resistor
placed as close to the receiver logic as possible. The common mode
of the digital output automatically biases itself to half the supply
of the receiver (that is, the common-mode voltage is 0.9 V for a
receiver supply of 1.8 V) if dc-coupled connecting is used (see
Figure 58). For receiver logic that is not within the bounds of
the DRVDD supply, use an ac-coupled connection. Simply place
a 0.1 µF capacitor on each output pin and derive a 100 Ω
differential termination close to the receiver side.
100Ω
100Ω
DIFFERENTIAL
TRACE PAIR
DRVDD
V
CM
= DRVDD/2
RECEIVER
SERDOUTx+
SERDOUTx–
10559-054
OUTPUT SWING = V
OD
(SEE TABLE 3)
Figure 58. DC-Coupled Digital Output Termination Example
If there is no far-end receiver termination, or if there is poor
differential trace routing, timing errors may result. To avoid
such timing errors, it is recommended that the trace length be
less than six inches, and that the differential output traces be
close together and at equal lengths.
Figure 59 shows an example of the digital output (default) data eye
and time interval error (TIE) jitter histogram and bathtub curve
for the AD9250 lane running at 5 Gbps.
Additional SPI options allow the user to further increase the
output driver voltage swing of all four outputs to drive longer
trace lengths (see Register 0x15 in Table 18). The power
dissipation of the DRVDD supply increases when this option is
used. See the Memory Map section for more details.
The format of the output data is twos complement by default.
To change the output data format to offset binary, see the
Memory Map section (Register 0x14 in Table 18).
0–0.5 0.5
UIs
PERIOD1: HISTOGRAM
6000
7000
–10 0
TIME (ps) 10
5000
4000
1000
0
2000
3000
1
–16
1
–14
1
–12
1
–10
1
–8
1
–6
1
–4
1
–2
1
BER
3
–
2
–
–100
–200 0100 200
TIME (ps)
400
300
200
100
0
–100
–300
–400
–200
VOLTAGE (mV)
HEIGHT1: EYE DIAGRAM
1
–
10559-056
TJ@BER1: BATHTUB
HITS
EYE: TRANSITION BITS O FFSET: –0.0072
UIs: 8000; 999992 TO TAL: 8000. 999992
0.78 UI
Figure 59. AD9250 Digital Outputs Data Eye, Histogram and Bathtub, External 100 Ω Terminations at 5 Gbps
0–0.5 0.5
UIs
PERIOD1: HISTOGRAM
4000
4500
–10 0
TIME (ps) 10
3500
3000
1000
0
2000
2500
1500
500
1
–16
1
–14
1
–12
1
–10
1
–8
1
–6
1
–4
1
–2
1
BER
3
–
2
–
–250 –150 050–50 150 250
TIME (ps)
400
300
200
100
0
–100
–300
–400
–200
VOLTAGE (mV)
HEIGHT1: EYE DIAGRAM
1
–
10559-156
TJ@BER1: BATHTUB
HITS
0.84 UI
EYE: TRANSITION BITS O FFSET: 0
UIs: 8000; 679999 TO TAL: 8000; 679999
Figure 60. AD9250 Digital Outputs Data Eye, Histogram and Bathtub, External 100 Ω Terminations at 3.4 Gbps
AD9250 Data Sheet
Rev. E | Page 32 of 45
ADC OVERRANGE AND GAIN CONTROL
In receiver applications, it is desirable to have a mechanism to
reliably determine when the converter is about to be clipped.
The standard overflow indicator provides delayed information on
the state of the analog input that is of limited value in preventing
clipping. Therefore, it is helpful to have a programmable
threshold below full scale that allows time to reduce the gain
before the clip occurs. In addition, because input signals can
have significant slew rates, latency of this function is of concern.
Using the SPI port, the user can provide a threshold above which
the FD output is active. Bit 0 of Register 0x45 enables the fast
detect feature. Register 0x47 to Register 0x4A allow the user to
set the threshold levels. As long as the signal is below the selected
threshold, the FD output remains low. In this mode, the magnitude
of the data is considered in the calculation of the condition, but
the sign of the data is not considered. The threshold detection
responds identically to positive and negative signals outside the
desired range (magnitude).
ADC OVERRANGE (OR)
The ADC overrange indicator is asserted when an overrange is
detected on the input of the ADC. The overrange condition is
determined at the output of the ADC pipeline and, therefore, is
subject to a latency of 36 ADC clock cycles. An overrange at the
input is indicated by this bit 36 clock cycles after it occurs.
GAIN SWITCHING
The AD9250 includes circuitry that is useful in applications
either where large dynamic ranges exist, or where gain ranging
amplifiers are employed. This circuitry allows digital thresholds
to be set such that an upper threshold and a lower threshold can
be programmed.
One such use is to detect when an ADC is about to reach full
scale with a particular input condition. The result is to provide
an indicator that can be used to quickly insert an attenuator that
prevents ADC overdrive.
Fast Threshold Detection (FDA and FDB)
The FD indicator is asserted if the input magnitude exceeds the
value programmed in the fast detect upper threshold registers,
located in Register 0x47 and Register 0x48. The selected threshold
register is compared with the signal magnitude at the output of
the ADC. The fast upper threshold detection has a latency of
7 clock cycles. The approximate upper threshold magnitude is
defined by
Upper Threshold Magnitude (dBFS) = 20 log (Threshold
Magnitude/213)
Or, alternatively, the register value can be calculated by the
target threshold using the following equation:
Value = 10(Threshold Magnitude [dBFS]/20) × 213
The FD indicators are not cleared until the signal drops below
the lower threshold for the programmed dwell time. The lower
threshold is programmed in the fast detect lower threshold
registers, located at Register 0x49 and Register 0x4A. The fast
detect lower threshold register is a 13-bit register that is compared
with the signal magnitude at the output of the ADC. This
comparison is subject to the ADC pipeline latency but is
accurate in terms of converter resolution. The lower threshold
magnitude is defined by
Lower Threshold Magnitude (dBFS) = 20 log (Threshold
Magnitude/213)
For example, to set an upper threshold of −6 dBFS, write
0x0FFF to those registers; and to set a lower threshold of
−10 dBFS, write 0x0A1D to those registers.
The dwell time can be programmed from 1 to 65,535 sample
clock cycles by placing the desired value in the fast detect dwell
time registers, located in Register 0x4B and Register 0x4C.
The operation of the upper threshold and lower threshold registers,
along with the dwell time registers, is shown in Figure 61.
UPPER THRESHOLD
LOWER THRESHOLD
FDA OR FDB
MIDSCALE
DWELL TIME
TIMER RESET BY
RISE ABOVE LT
TIMER COMPLETES BEFORE
SIGNAL RISES ABOVE LT
DWELL TIME
10559-057
Figure 61. Threshold Settings for FDA and FDB Signals
Data Sheet AD9250
Rev. E | Page 33 of 45
DC CORRECTION
Because the dc offset of the ADC may be significantly larger than
the signal being measured, a dc correction circuit is included to
null the dc offset before measuring the power. The dc correction
circuit can also be switched into the main signal path; however,
this may not be appropriate if the ADC is digitizing a time-varying
signal with significant dc content, such as GSM.
DC CORRECTION BANDWIDTH
The dc correction circuit is a high-pass filter with a program-
mable bandwidth (ranging between 0.29 Hz and 2.387 kHz
at 245.76 MSPS). The bandwidth is controlled by writing to
the 4-bit dc correction bandwidth select register, located at
Register 0x40, Bits[5:2]. The following equation can be used
to compute the bandwidth value for the dc correction circuit:
DC_Corr_BW = 2−k−14 × fCLK/(2 × π)
where:
k is the 4-bit value programmed in Bits[5:2] of Register 0x40
(values between 0 and 13 are valid for k).
fCLK is the AD9250 ADC sample rate in hertz.
DC CORRECTION READBACK
The current dc correction value can be read back in Register 0x41
and Register 0x42 for each channel. The dc correction value is a
16-bit value that can span the entire input range of the ADC.
DC CORRECTION FREEZE
Setting Bit 6 of Register 0x40 freezes the dc correction at its
current state and continues to use the last updated value as the
dc correction value. Clearing this bit restarts dc correction and
adds the currently calculated value to the data.
DC CORRECTION (DCC) ENABLE BITS
Setting Bit 1 of Register 0x40 enables dc correction for use in
the output data signal path.
AD9250 Data Sheet
Rev. E | Page 34 of 45
SERIAL PORT INTERFACE (SPI)
The AD9250 SPI allows the user to configure the converter for
specific functions or operations through a structured register
space provided inside the ADC. The SPI gives the user added
flexibility and customization, depending on the application.
Addresses are accessed via the serial port and can be written to
or read from via the port. Memory is organized into bytes that
can be further divided into fields. These fields are documented
in the Memory Map section. For detailed operational information,
see the AN-877 Application Note, Interfacing to High Speed
ADCs via SPI.
CONFIGURATION USING THE SPI
Three pins define the SPI of this ADC: the SCLK pin, the SDIO
pin, and the CS pin (see Table 16). The SCLK (serial clock) pin is
used to synchronize the read and write data presented from/to the
ADC. The SDIO (serial data input/output) pin is a dual-purpose
pin that allows data to be sent and read from the internal ADC
memory map registers. The CS (chip select bar) pin is an active low
control that enables or disables the read and write cycles.
Table 16. Serial Port Interface Pins
Pin Function
SCLK
Serial Clock. The serial shift clock input, which is used to
synchronize serial interface, reads and writes.
SDIO Serial Data Input/Output. A dual-purpose pin that
typically serves as an input or an output, depending on
the instruction being sent and the relative position in the
timing frame.
CS Chip Select Bar. An active low control that gates the read
and write cycles.
The falling edge of CS, in conjunction with the rising edge of
SCLK, determines the start of the framing. An example of the
serial timing and its definitions can be found in Figure 62 and
Table 5.
Other modes involving the CS are available. The CS can be held
low indefinitely, which permanently enables the device; this is
called streaming. The CS can stall high between bytes to allow for
additional external timing. When CS is tied high, SPI functions
are placed in a high impedance mode. This mode turns on any
SPI pin secondary functions.
During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase, and its length is determined
by the W0 and the W1 bits.
All data is composed of 8-bit words. The first bit of each individual
byte of serial data indicates whether a read or write command is
issued. This allows the SDIO pin to change direction from an
input to an output.
In addition to word length, the instruction phase determines
whether the serial frame is a read or write operation, allowing
the serial port to be used both to program the chip and to read
the contents of the on-chip memory. If the instruction is a readback
operation, performing a readback causes the SDIO pin to change
direction from an input to an output at the appropriate point in
the serial frame.
Data can be sent in MSB first mode or in LSB first mode. MSB
first is the default on power-up and can be changed via the SPI
port configuration register. For more information about this and
other features, see the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI.
HARDWARE INTERFACE
The pins described in Table 16 comprise the physical interface
between the user programming device and the serial port of the
AD9250. The SCLK pin and the CS pin function as inputs when
using the SPI interface. The SDIO pin is bidirectional, functioning
as an input during write phases and as an output during readback.
The SPI interface is flexible enough to be controlled by either
FPGAs or microcontrollers. One method for SPI configuration
is described in detail in the AN-812 Application Note,
Microcontroller-Based Serial Port Interface (SPI) Boot Circuit.
Do not activate the SPI port during periods when the full dynamic
performance of the converter is required. Because the SCLK signal,
the CS signal, and the SDIO signal are typically asynchronous to
the ADC clock, noise from these signals can degrade converter
performance. If the on-board SPI bus is used for other devices, it
may be necessary to provide buffers between this bus and the
AD9250 to prevent these signals from transitioning at the
converter inputs during critical sampling periods.
Data Sheet AD9250
Rev. E | Page 35 of 45
SPI ACCESSIBLE FEATURES
Table 17 provides a brief description of the general features that
are accessible via the SPI. These features are described in detail
in the AN-877 Application Note, Interfacing to High Speed ADCs
via SPI. The AD9250 part-specific features are described in the
Memory Map Register Description section.
Table 17. Features Accessible Using the SPI
Feature Name Description
Mode Allows the user to set either power-down mode or standby mode
Clock Allows the user to access the DCS via the SPI
Offset Allows the user to digitally adjust the converter offset
Test I/O Allows the user to set test modes to have known data on output bits
Output Mode Allows the user to set up outputs
Output Phase Allows the user to set the output clock polarity
Output Delay Allows the user to vary the DCO delay
VREF Allows the user to set the reference voltage
DON’ T CARE
DON’ T CARE
DON’ T CARE
DON’ T CARE
SDIO
SCLK
CS
t
S
t
DH
t
CLK
t
DS
t
H
R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0
t
LOW
t
HIGH
10559-058
Figure 62. Serial Port Interface Timing Diagram
AD9250 Data Sheet
Rev. E | Page 36 of 45
MEMORY MAP
READING THE MEMORY MAP REGISTER TABLE
Each row in the memory map register table has eight bit locations.
The memory map is roughly divided into three sections: the
chip configuration registers (Address 0x00 to Address 0x02);
the channel index and transfer registers (Address 0x05 and
Address 0xFF); and the ADC functions registers, including
setup, control, and test (Address 0x08 to Address 0xA8).
The memory map register table (see Table 18) documents the
default hexadecimal value for each hexadecimal address shown.
The column with the heading Bit 7 (MSB) is the start of the
default hexadecimal value given. For example, Address 0x14,
the output mode register, has a hexadecimal default value of
0x01. This means that Bit 0 = 1, and the remaining bits are 0s.
This setting is the default output format value, which is twos
complement. For more information on this function and others,
see the AN-877 Application Note, Interfacing to High Speed
ADCs via SPI. This document details the functions controlled
by Register 0x00 to Register 0x25. The remaining registers,
Register 0x3A and Register 0x59, are documented in the
Memory Map Register Description section.
Open and Reserved Locations
All address and bit locations that are not included in Table 18
are not currently supported for this device. Unused bits of a valid
address location should be written with 0s. Writing to these
locations is required only when part of an address location is
open (for example, Address 0x18). If the entire address location
is open (for example, Address 0x13), do not write to this
address location.
Default Values
After the AD9250 is reset, critical registers are loaded with
default values. The default values for the registers are given
in the memory map register table, Table 18.
Logic Levels
An explanation of logic level terminology follows:
• “Bit is set” is synonymous with “bit is set to Logic 1” or
“writing Logic 1 for the bit.”
• “Clear a bit” is synonymous with “bit is set to Logic 0” or
“writing Logic 0 for the bit.”
Channel-Specific Registers
Some channel setup functions, such as dc offset adjust or ouput
data format, can be programmed to a different value for each
channel. In these cases, channel address locations are internally
duplicated or shadowed for each channel. These registers and bits
are designated as local in Table 18. Note that all other listed
registers are considered as global; write operations to these
registers affect the entire device upon completion of the write
operation.
Local registers and bits can be accessed by setting the appropriate
Channel A or Channel B bits in Register 0x05. If both bits are
set, the subsequent write affects the registers of both channels.
In a read cycle, set only Channel A or Channel B to read one of
the two registers. If both bits are set during an SPI read cycle,
the device returns the value for Channel A.
To write to a specific channel, the following three steps must
occur:
1. Select the desired channel(s) for SPI write operation via
Register 0x05.
2. Perform the specific write operation to desired local SPI
register.
3. Transfer of the write operation contents to the target local
register occurs by setting the self clearing transfer bit of
Register 0xFF. Writing 0x01 allows the target local channel
register(s) to be updated internally and simultaneously
when the transfer bit is set. The internal update takes place
when the transfer bit is set and then the bit automatically
clears.
Data Sheet AD9250
Rev. E | Page 37 of 45
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 18 are not currently supported for this device.
Table 18. Memory Map Registers
Reg
Addr
(Hex)
Register
Name
Bit 7
(MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Notes
0x00 Global SPI
config
0 LSB first Soft reset 1 1 Soft reset LSB first 0 0x18
0x01 CHIP ID AD9250 8-bit chip ID is 0xB9 0xB9 Read
only
0x02 Chip info Speed grade
00 = 250 MSPS
11 = 170 MSPS
Reserved for chip die revision currently
0x0
0x00
or 0x30
0x05 Channel
index
SPI write
to ADC B
path
SPI write to
ADC A path
0x03
0x08 PDWN
modes
External
PDWN
mode;
0 =
PDWN is
full
power
down;
1 =
PDWN
puts
device in
standby
JTX in
standby;
0 =
JESD204B
core is
unaffected
in standby;
1 =
JESD204B
core is
powered
down
except for
PLL during
standby
JESD204B power modes;
00 = normal mode
(power up);
01 = power-down
mode: PLL off, serializer
off, clocks stopped,
digital held in reset;
10 = standby mode: PLL
on, serializer off, clocks
stopped, digital held in
reset
Chip power modes;
00 = normal mode
(power up);
01 = power-down mode,
digital datapath clocks
disabled, digital
datapath held in reset;
most analog paths
powered off;
10 = standby mode;
digital datapath clocks
disabled, digital
datapath held in reset,
some analog paths
powered off
(Local)
0x00
0x09
Global clock
(local)
Reserved
Clock selection:
00 = Nyquist clock
10 = RF clock divide by 4
11 = clock off
Clock duty
cycle
stabilizer
(DCS)
enable
0x01
Local,
DCS
enabled
if clock
divider
enabled
0x0A PLL status PLL locked
status
JESD204B
link is
ready
Read
only
0x0B Global clock
divider
(local)
Clock divider phase output of the
internal divide by 1 to divide by 8
divider circuit, clock cycles are relative
to the input clock to this block;
0x0 = 0 input clock cycles delayed;
0x1 = 1 input clock cycles delayed;
0x2 = 2 input clock cycles delayed;
…
0x7 = 7 input clock cycles delayed
Note that the RF clock divider phase is
not selectable
Clock divider ratio of the divide by 1 to
divide by 8 divider circuit to generate
the encode clock;
0x00 = divide by 1;
0x01 = divide by 2;
0x02 = divide by 3;
…
0x7 = divide by 8;
using a CLKDIV_DIVIDE_RATIO > 0
(Divide Ratio > 1) causes the DCS to be
automatically enabled
0x00 Local
0x0D Test control
reg
(local)
User test mode cycle;
00 = repeat pattern
(user pattern 1, 2, 3, 4, 1,
2, 3, 4, 1, …);
10 = single pattern (user
pattern 1, 2, 3, 4, then all
zeros)
Long
psuedo
random
number
generator
reset;
0 = long
PRN
enabled;
1 = long
PRN held
in reset
Short
psuedo
random
number
generator
reset;
0 = short
PRN
enabled;
1 = short
PRN held in
reset
Data output test generation mode;
0000 = off (normal mode);
0001 = midscale short;
0010 = positive full scale;
0011 = negative full scale;
0100 = alternating checkerboard;
0101 = PN23 sequence long;
0110 = PN9 sequence short;
0111 = one-/zero-word toggle;
1000 = user test mode (use with Register 0x0D, Bit 7
and user pattern 1, 2, 3, 4);
1001 to 1110 = unused;
1111 = ramp output
0x00 Local
AD9250 Data Sheet
Rev. E | Page 38 of 45
Reg
Addr
(Hex)
Register
Name
Bit 7
(MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Notes
0x10 Customer
offset
(local)
Offset adjust in LSBs from +31 to −32 (twos complement format);
01 1111 = adjust output by +31;
01 1110 = adjust output by +30;
…
00 0001 = adjust output by +1;
00 0000 = adjust output by 0 (default);
…
10 0001 = adjust output by −31;
10 0000 = adjust output by −32
0x00 Local
0x14 Output
mode
(local)
JTX CS bits assignment (in
conjunction with Register 0x72)
000 = (overrange||underrange, valid)
001 = (overrange||underrange)
010 = (overrange||underrange, blank)
011 = (blank, valid)
100 = (blank, blank)
All others = (overrange||underrange,
valid)
Disable
output
from ADC
Invert ADC
data;
0 = normal
(default);
1 =
inverted
Digital datapath output
data format select (DFS)
(local);
00 = offset binary;
01 = twos complement
0x01 Local
0x15 CML output
adjust
JESD204B CML differential output drive
level adjustment;
000 = 81% of nominal (that is, 478 mV);
001 = 89% of nominal (that is, 526 mV);
010 = 98% of nominal (that is, 574 mV);
011 = nominal (default) (that is, 588 mV);
110 = 126% of nominal (that is, 738 mV)
0x03
0x18 ADC VREF Main reference full-scale VREF adjustment;
0 1111 = internal 2.087 V p-p;
…
0 0001 = internal 1.772 V p-p;
0 0000 = internal 1.75 V p-p (default);
1 1111 = internal 1.727 V p-p;
…
1 0000 = internal 1.383 V p-p
0x00 Local
0x19
User Test
Pattern 1 L
User Test Pattern 1 LSB; use in conjunction with Register 0x0D and Register 0x61 0x00
0x1A User Test
Pattern 1 M
User Test Pattern 1 MSB 0x00
0x1B User Test
Pattern 2 L
User Test Pattern 2 LSB 0x00
0x1C User Test
Pattern 2 M
User Test Pattern 2 MSB 0x00
0x1D User Test
Pattern 3 L
User Test Pattern 3 LSB 0x00
0x1E
User Test
Pattern 3 M
User Test Pattern 3 MSB
0x00
0x1F User Test
Pattern 4 L
User Test Pattern 4 LSB 0x00
0x20 User Test
Pattern 4 M
User Test Pattern 4 MSB 0x00
0x21 PLL low
encode
00 = for lane speeds >
2 Gbps;
01 = for lane speeds <
2 Gbps
0x00
Data Sheet AD9250
Rev. E | Page 39 of 45
Reg
Addr
(Hex)
Register
Name
Bit 7
(MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Notes
0x3A SYNCINB±/
SYSREF±
CTRL (local)
SYNCINB±
OPERATION
0 = normal
mode;
1 = realign
lanes on
every
active
SYNCINB±
For
Subclass
1 Only:
0 =
normal
mode;
1 =
realign
lanes on
every
active
SYSREF±;
use with
single
shot
SYSREF in
Subclass 1
mode
SYSREF±
mode;
0 =
continuous
reset clock
dividers;
1 = sync on
next
SYSREF±
rising edge
only
SYSREF±
enable;
0 =
disabled;
1 =
enabled.
NOTE:
This bit
self-clears
after
SYSREF if
SYSREF±
mode = 1
Enable
internal
SYSREF±
buffer;
0 = buffer
disabled,
external
SYSREF±
pin
ignored;
1 = buffer
enabled,
use
external
SYSREF±
pin
0x00 Local
See
Table 14
for more
details
0x40 DCC CTRL
(local)
Freeze dc
correction;
0 =
calculate;
1 =
freezeval
DC correction bandwidth select;
correction bandwidth is 2387.32 Hz/reg val;
there are 14 possible values;
0000 = 2387.32 Hz;
0001 = 1193.66 Hz;
1101 = 0.29 Hz
Enable
DCC
0x00 Local
0x41 DCC value
LSB (local)
DC Correction Value[7:0] 0x00 Local
0x42 DCC value
MSB (local)
DC Correction Value[15:8] 0x00 Local
0x45 Fast detect
control
(local)
Pin
function;
0 = fast
detect;
1 =
overrange
Force
FDA/FDB
pins;
0 =
normal
function;
1 = force
to value
Force
value of
FDA/FDB
pins
if force
pins is true,
this value
is output
on FD pins
Enable fast
detect
output
0x00 Local
0x47 FD upper
threshold
(local)
Fast Detect Upper Threshold[7:0] 0x00 Local
0x48 FD upper
threshold
(local)
Fast Detect Upper Threshold[14:8] 0x00 Local
0x49 FD lower
threshold
(local)
Fast Detect Lower Threshold[7:0] 0x00 Local
0x4A FD lower
threshold
(local)
Fast Detect Lower Threshold[14:8] 0x00 Local
0x4B FD dwell
time (local)
Fast Detect Dwell Time[7:0] 0x00 Local
0x4C FD dwell
time (local)
Fast Detect Dwell Time[15:8] 0x00 Local
0x5E 204B quick
config
Quick configuration register, always reads back 0x00;
0x11 = M = 1, L = 1; one converter, one lane; second converter is not automatically powered down;
0x12 = M = 1, L = 2; one converter, two lanes; second converter is not automatically powered down;
0x21 = M = 2, L = 1; two converters, one lane;
0x22 = M = 2, L = 2; two converters, two lanes
0x00 Always
reads
back
0x00
AD9250 Data Sheet
Rev. E | Page 40 of 45
Reg
Addr
(Hex)
Register
Name
Bit 7
(MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Notes
0x5F 204B Link
CTRL 1
Tail bits: If
CS bits
are not
enabled;
0 = extra
bits are 0;
1 = extra
bits are 9-
bit PN
JESD204B
test
sample
enabled
Reserved;
set to 1
ILAS mode;
01 = ILAS normal mode
enabled;
11 = ILAS always on, test
mode
Reserved;
set to 0
Power-
down
JESD204B
link; set
high while
configuring
link
parameters
0x14
0x60 204B Link
CTRL 2
Reserved;
set to 0
Reserved;
set to 0
Reserved;
set to 0
Invert
logic of
JESD204B
bits
0x00
0x61
204B Link
CTRL 3
Reserved;
set to 0
Reserved;
set to 0
Test data injection point;
01 = 10-bit data at
8B/10B output;
10 = 8-bit data at
scrambler input
JESD204B test mode patterns;
0000 = normal operation (test mode disabled);
0001 = alternating checker board;
0010 = 1/0 word toggle;
0011 = PN sequence PN23;
0100 = PN sequence PN9;
0101= continuous/repeat user test mode;
0110 = single user test mode;
0111 = reserved;
1000 = modified RPAT test sequence, must be used
with JTX_TEST_GEN_SEL = 01 (output of 8b/10b);
1100 = PN sequence PN7;
1101 = PN sequence PN15;
other setting are unused
0x00
0x62 204B Link
CTRL 4
Reserved 0x00
0x63 204B Link
CTRL 5
Reserved 0x00
0x64 204B DID
config
JESD204B DID value 0x00
0x65
204B BID
config
JESD204B BID value 0x00
0x66 204B LID
Config 0
Lane 0 LID value 0x00
0x67 204B LID
Config 1
Lane 1 LID value 0x01
0x6E 204B
parameters
SCR/L
JESD204B
scrambling
(SCR);
0 =
disabled;
1 =
enabled
JESD204B
lanes (L);
0 = 1 lane;
1 = 2 lanes
0x81
0x6F 204B
parameters
F
JESD204B number of octets per frame (F); calculated value
(Note that this value is in x − 1 format)
0x01 Read
Only
0x70 204B
parameters
K
JESD204B number of frames per multiframe (K); set value of K per JESD204B specifications, but also must be a
multiple of 4 octets
(Note that this value is in x − 1 format)
0x1F
0x71 204B
parameters
M
JESD204B number of converters (M);
0 = 1 converter;
1 = 2 converters
0x01
0x72 204B
parameters
CS/N
Number of control bits
(CS);
00 = no control bits
(CS = 0);
01 = 1 control bit
(CS = 1);
10 = 2 control bits
(CS = 2)
ADC converter resolution (N),
0xD = 14-bit converter (N = 14)
(Note that this value is in x − 1 format)
0x0D
Data Sheet AD9250
Rev. E | Page 41 of 45
Reg
Addr
(Hex)
Register
Name
Bit 7
(MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Notes
0x73 204B
parameters
subclass/Np
JESD204B subclass;
0x0 = Subclass 0;
0x1 = Subclass 1
(default)
JESD204B N’ value; 0xF = N’ = 16
(Note that this value is in x – 1 format)
0x2F
0x74 204B
parameters S
Reserved;
set to 1
JESD204B samples per converter frame cycle (S); read only
(Note that this value is in x − 1 format)
0x20
0x75 204B
parameters
HD and CF
JESD204B
HD value;
read only
JESD204B control words per frame clock cycle per link (CF);
read only
0x00 Read
Only
0x76 204B RESV1 Reserved Field Number 1 0x00
0x77 204B RESV2 Reserved Field Number 2 0x00
0x78 204B
CHKSUM0
JESD204B serial checksumvalue for Lane 0 0x42
0x79
204B
CHKSUM1
JESD204B serial checksumvalue for Lane 1 0x43
0x82 204B Lane
Assign 1
00 = assign Logical Lane 0
to Physical Lane A
(default);
01 = assign Logical Lane 0
to Physical Lane B
Reserved;
set to 1
Reserved;
set to 0
0x02
0x83 204B Lane
Assign 2
Reserved;
set to 1
Reserved;
set to 1
00 = assign Logical Lane
1 to Physical Lane A;
01 = assign Logical Lane 1
to Physical Lane B
(default)
0x31
0x8B 204B LMFC
offset
Local multiframe clock (LMFC) phase offset value; reset value for
LMFC phase counter when SYSREF is asserted; used for
deterministic delay applications
0x00
0xA8 204B pre-
emphasis
JESD204B pre-emphasis enable option (consult factory for more detail);
set value to 0x04 for pre-emphasis off;
set value to 0x14 for pre-emphasis on
0x04 Typically
not
required
0xEE Internal
digital clock
delay
Enable
internal
clock delay
Set to 0 Set to 0 Set to 0 Use incrementing values from 0 to 7 to increase
internal digital clock delay. For internal data latching
purposes, this does not affect external timing.
0x00 See
JESD
Section
for use
0xEF
Internal
digital clock
delay
Enable
internal
clock delay
Set to 0 Set to 0 Set to 0
Use incrementing values from 0 to 7 to increase
internal digital clock delay. For internal data latching
purposes, this does not affect external timing.
0x00
See
JESD
Section
for use
0xF3 Internal
digital clock
alignment
Force
manual
re-align
on Lane 1,
self
clearing
Lane 1
Alignment
complete
Force
manual
realign on
Lane 0,
self
clearing
Lane 0
alignment
complete
0x14 See
JESD
Section
for use
0xFF Device
update
(global)
Transfer
settings
MEMORY MAP REGISTER DESCRIPTION
For more information on functions controlled in Register 0x00
to Register 0x25, see the AN-877 Application Note, Interfacing
to High Speed ADCs via SPI.
AD9250 Data Sheet
Rev. E | Page 42 of 45
APPLICATIONS INFORMATION
DESIGN GUIDELINES
Before starting system level design and layout of the AD9250, it
is recommended that the designer become familiar with these
guidelines, which discuss the special circuit connections and
layout requirements needed for certain pins.
Power and Ground Recommendations
When connecting power to the AD9250, use two separate 1.8 V
power supplies. The power supply for AVDD can be isolated and
for DVDD and DRVDD it can be tied together, in which case
isolation between DVDD and DRVDD is required. Isolation can
be achieved using a ferrite bead or an inductor of approximately
1 µH. An unfiltered switching regulator is not recommended for
the DRVDD supply as it impacts the performance of the JESD204B
serial transmission lines and may result in link problems. Alternate-
ly, the JESD204B PHY power (DRVDD) and analog (AVDD)
supplies can be tied together, and a separate supply can be used
for the digital outputs (DVDD).
The designer can employ several different decoupling capacitors
to cover both high and low frequencies. Locate these capacitors
close to the point of entry at the PC board level and close to the
pins of the part with minimal trace length. Each power supply
domain must have local high frequency decoupling capacitors.
This is especially important for DRVDD and AVDD to
maintain analog performance.
When using the AD9250, a single PCB ground plane should be
sufficient. With proper decoupling and smart partitioning of the
PCB analog, digital, and clock sections, optimum performance
is easily achieved.
Exposed Paddle Thermal Heat Slug Recommendations
It is mandatory that the exposed paddle on the underside of the
ADC be connected to analog ground (AGND) to achieve the
best electrical and thermal performance. Mate a continuous,
exposed (no solder mask) copper plane on the PCB to the
AD9250 exposed paddle, Pin 0.
The copper plane must have several vias to achieve the lowest pos-
sible resistive thermal path for heat dissipation to flow through the
bottom of the PCB. Fill or plug these vias with nonconductive epoxy.
To maximize the coverage and adhesion between the ADC and
the PCB, overlay a silkscreen to partition the continuous plane
on the PCB into several uniform sections. This provides several tie
points between the ADC and the PCB during the reflow process.
Using one continuous plane with no partitions guarantees only
one tie point between the ADC and the PCB. See the evaluation
board for a PCB layout example. For detailed information about
the packaging and PCB layout of chip scale packages, refer to
the AN-772 Application Note, A Design and Manufacturing
Guide for the Lead Frame Chip Scale Package (LFCSP).
VCM
Decouple the VCM pin to ground with a 0.1 µF capacitor, as
shown in Figure 40. For optimal channel-to-channel isolation,
include a 33 Ω resistor between the AD9250 VCM pin and the
Channel A analog input network connection, as well as between
the AD9250 VCM pin and the Channel B analog input network
connection.
SPI Port
When the full dynamic performance of the converter is required,
do not activate the SPI port during periods. Because the
SCLK, CS, and SDIO signals are typically asynchronous to the
ADC clock, noise from these signals can degrade converter
performance. If the on-board SPI bus is used for other devices, it
may be necessary to provide buffers between this bus and the
AD9250 to keep these signals from transitioning at the converter
input pins during critical sampling periods.
SPI INITIALIZATION SEQUENCE
On power-up of the AD9250, a host processor is required to
initialize and configure the AD9250 via its SPI port. Figure 63
shows a flowchart of the sequential steps required to bring the
AD9250 to an operational state. The number of SPI writes and
total initialization time is dependent on how many SPI registers
need to be changed from the default setting, usage of the clock
divider, and whether JESD204B Subclass 1 synchronization is
required. Table 19 shows the minimum SPI writes required to
enable the AD9250. Note the following in the sequence of steps
shown in Table 19:
• Steps that are listed as optional can be ignored if the default
SPI settings are sufficient.
• Steps that are listed as conditional can be ignored if the
specific condition is not applicable.
Data Sheet AD9250
Rev. E | Page 43 of 45
SET THE QUI CK JE S D204
CONFIGURATION MODE
(REFER T O T ABLE 13)
RESET I NTERNAL CL OCKS
TO MINIMUM SETTING
FIFO WRITE/READ
CLOCK ADJUST M E NT
WAIT > 6LMFC CL OCKS
OPTIONAL
MODIFY ANY OTHER
JESD204B PARAM E TERS
FROM DEFAULT SETTING
DISABLE THE JE S D204B
TxPHY DURING S E T-UP
(AS WEL L AS JE S D204B Rx)
APPL Y P OW E R AND CLO CK
ALLOW TIME TO SETTLE
ISSUE SOFT W ARE RESET
THE N WAIT 500µ s M IN
ISSUE SOFT W ARE
POWER-DOWN
SET DIVIDER V ALUE
OPTIONAL
CONFIGURE ANY
NON-JESD204
REGISTERS FROM
DEFAULT SETTING
USE CL OCK
DIVIDER? YES
NO
ISSUE SOFT W ARE
POWER-UP
WAIT 250ms
USE CL OCK
DIVIDER? YES
NO
JESD204B
SUBCLASS1
SYNC
YES
NO
ENABLE
SYSREF BUFFER
CONFIGURE
SYSREF MODE
READBACKPL L L OCK BI T
ENABL E P HY TO BE GI N CGS P HAS E
FORCE FIFO ALIGNMENT
WAIT > 6LMFC CL OCKS
APPLY EXTERNAL SYSREF
WAIT > 6LMFC CL OCKS
DISABLE SYSREF BUFFER
(ONE-SHOT MODE ONLY)
JESD204B
SUBCLASS1
SYNC
YES
NO
10559-063
Figure 63. Flowchart Showing Sequence of Steps Required to Initialize the AD9250
Table 19. SPI Initialization Sequence
Step Address
Write
Value Comments
1 Apply power to the AD9250 and allow the voltages and clocks to stabilize.
2 0x00 0x3C Software reset.
3 Wait 500 μs minimum.
4
0x5F
0x15
Disable the JESD204B PHY.
5 Optional: modify any other non-JESD204B register from default setting depending on application
requirements. Note, any local register must be followed by a transfer command (0xFF= 0x01)
6 0x0B 0x01 Optional: set the clock divider ratio if using a clock divider. Note that the 0x01 value shown corresponds to a
divide-by-2 clock ratio.
0xFF 0x01 Transfer command for local Register
7 0x5E 0xML Set the JESD204B quick configuration register based on the desired M and L values.
8 0xEE 0x80 Enable the internal clock delay block for minimum delay.
9 0x21 0x00 Conditional: configure the PLL low encode register. Only set to 0x01 if the lane rate is < 2 GBPS. The default
setting is 0x00.
10 Optional: modify the JESD204B centric registers from the default setting as follows:
0x14 0x01 Configure the data output with 0x01 being the default (twos complement).
0x15 0x03 Set the JESD204B CML differential drive level with 0x03 being default (588 mV).
0x66 0x00 Set the Lane 0 and Lane 1 LID value (defaults shown).
0x67 0x01 Set the Lane 0 and Lane 1 LID value (defaults shown).
0x6E 0x81 Enable the JESD204B scrambling in Bit 7 while keeping desired JESD204B lane value, L, in Bit 0. Default shown.
0x70 0x1F Modify the JESD204B K and CS values. Default shown.
0x82 0x0D Modify the JESD204B K and CS values. Default shown.
Modify other JESD204B centric configurations in Register 0x82 to Register 0x8B and Register 0xA8.
0xFF 0x01 Transfer command for local Register
AD9250 Data Sheet
Rev. E | Page 44 of 45
Step Address
Write
Value Comments
11 Optional: JESD204B Subclass 1 synchronization setup.
0x3A 0x01 Enable the SYSREF buffer first to avoid false triggering (especially one-shot operation) before setting the
remaining bits in Register 0x3A.
0xFF 0x01 Transfer command for local Register
0x3A 0x0F or
0x03
Configure the method of SYSREF operation. For one-shot operation, set to 0x0F. For continuous or gapped
periodic SYSREF operation, set to 0x03.
0xFF 0x01 Transfer command for local Register
12 Begin JESD204B link establishment.
0x0A Optional: read back Register 0x0A with 0x81 indicating that the JESD204B PLL is locked.
0x5F 0x14 Enable the JESD204B PHY. This begins the CGS phase for establishing a link.
0xF3 0xFF Force an internal FIFO alignment.
Wait at least six LMFC cycles.
Note that the JESD204B link must be established at this time before continuing.
13 Optional: When operating in SubClass 1 mode, apply external SYSREF signal for LMFC alignment.
Wait at least six LMFC cycles for LMFC alignment between JESD204B Tx and Rx to occur.
0x3A 0x04 Conditional: disable the internal SYSREF buffer if configured for one-shot operation.
0xFF
0x01
Transfer command for local Register
14 Internal FIFO clock adjustment.
0xEE 0x81 Clock adjustment procedure.1
0xEF 0x81 Clock adjustment procedure.1
0xEE 0x82 Clock adjustment procedure.1
0xEF 0x82 Clock adjustment procedure.1
0xEE 0x83 Clock adjustment procedure.1
0xEF 0x83 Clock adjustment procedure.1
0xEE 0x84 Clock adjustment procedure.1
0xEF
0x84
Clock adjustment procedure.
1
0xEE 0x85 Clock adjustment procedure.1
0xEF 0x85 Clock adjustment procedure.1
0xEE 0x86 Clock adjustment procedure.1
0xEF 0x86 Clock adjustment procedure.1
0xEE
0x87
Clock adjustment procedure.
1
0xEF 0x87 Clock adjustment procedure.1
Wait at least six LMFC cycles.
1 Following this procedure optimizes write and read clock delays of internal FIFO to avoid possible overflow, overtemperature, and supply variations.
Data Sheet AD9250
Rev. E | Page 45 of 45
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-220-WKKD-4.
1
0.50
BSC
BOTTOM VIEW
TOP VIEW
PIN 1
INDICATOR
48
13
24
36
37
5.70
5.60 SQ
5.50
0.50
0.40
0.30
0.80
0.75
0.70 0.05 MAX
0.02 NOM
0.203 REF
COPLANARITY
0.08
0.30
0.25
0.18
02-29-2016-A
7.10
7.00 SQ
6.90
0.20 MIN
5.50 REF
END VIEW
EXPOSED
PAD
PKG-004452
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
PIN 1
INDICATOR AREA OPTIONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
SEATING
PLANE
Figure 64. 48-Lead Lead Frame Chip Scale Package [LFCSP]
7 mm × 7 mm Body and 0.75 mm Package Height
(CP-48-13)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD9250BCPZ-170 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP] CP-48-13
AD9250BCPZRL7-170 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP] CP-48-13
AD9250-170EBZ −40°C to +85°C Evaluation Board with AD9250-170
AD9250BCPZ-250 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP] CP-48-13
AD9250BCPZRL7-250 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP] CP-48-13
AD9250-250EBZ −40°C to +85°C Evaluation Board with AD9250-250
1 Z = RoHS Compliant Part.
©2012–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10559-0-9/17(E)
