High Isolation, Silicon SP4T,
Nonreflective Switch, 9 kHz to 12.0 GHz
Data Sheet
ADRF5040
Rev. B Document Feedback
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Tel: 781.329.4700 ©2016–2017 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Nonreflective 50 Ω design
Positive control range: 0 V to 3.3 V
Low insertion loss: 0.8 dB at 8.0 GHz
High isolation: 34 dB at 8.0 GHz
High power handling
33 dBm through path
27 dBm termination path
High linearity
1 dB compression (P1dB): 37 dBm typical
Input third-order intercept (IIP3): 58 dBm typical at 8.0 GHz
ESD rating: 4 kV human body model (HBM)
4 mm × 4 mm, 24-lead LFCSP package
No low frequency spurious
RF settling time (0.05 dB margin of final RFOUT): 9 µs
APPLICATIONS
Test instrumentation
Microwave radios and very small aperture terminals (VSATs)
Military radios, radars, and electronic counter measures (ECMs)
Fiber optics and broadband telecommunications
FUNCTIONAL BLOCK DIAGRAM
50Ω50Ω
50Ω50Ω
PACKAGE
BASE
GND
2
1
3
4
5
6
18
17
16
15
14
13
GND
GND
GND
RFC
GND
GND
GND
V
SS
V
2
V
1
V
DD
GND
8
9
10
11
7
RF4
GND
GND
RF3
12
GND
GND
20
19
21
RF2
GND
GND
22 GND
23 RF1
24 GND
ADRF5040
14290-001
Figure 1.
GENERAL DESCRIPTION
The ADRF5040 is a general-purpose, broadband high isolation,
nonreflective single-pole, quad-throw (SP4T) switch in an LFCSP
surface-mount package. Covering the 9 kHz to 12.0 GHz range,
the switch offers high isolation and low insertion loss. The
switch features 34 dB isolation and 0.8 dB insertion loss up to
8.0 GHz, and a 9 µs settling time of 0.05 dB margin of the final
radio frequency output (RFOUT). The switch operates using
positive control voltage of 3.3 V and 0 V and requires +3.3 V and
−3.3 V supplies. The ADRF5040 is packaged in a 4 mm × 4 mm,
surface-mount LFCSP package.
ADRF5040 Data Sheet
Rev. B | Page 2 of 14
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Specifications ............................................................... 3
Digital Control Voltage Specifications....................................... 4
Bias and Supply Current Specifications ..................................... 4
Absolute Maximum Ratings ............................................................ 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Interface Schematics .....................................................................7
Typical Performance Characteristics ..............................................8
Insertion Loss, Return Loss, and Isolation ................................8
Input Power Compression and Input Third-Order Intercept ... 10
Input Power Compression and Input Third-Order Intercept,
10 kHz to 1 GHz .......................................................................... 11
Theory of Operation ...................................................................... 12
Applications Information .............................................................. 13
Evaluation Board ........................................................................ 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 14
REVISION HISTORY
7/2017—Rev. A to Rev. B
Changes to Figure 2, Figure 3, and Figure 4.................................. 5
2/2017—Rev. 0 to Rev. A
Changes to Ordering Guide .......................................................... 14
7/2016—Revision 0: Initial Version
Data Sheet ADRF5040
Rev. B | Page 3 of 14
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
VDD = 3.3 V, VSS = −3.3 V, V1 and V2 = 0 V or VDD, TA = 25°C, 50 Ω system, unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
INSERTION LOSS
9 kHz to 4.0 GHz 0.7 dB
9 kHz to 8.0 GHz 0.8 dB
9 kHz to 10.0 GHz 1.1 dB
9 kHz to 12.0 GHz 2 dB
ISOLATION, RFC TO RF1 TO RF4 (WORST CASE)
9 kHz to 4.0 GHz 44 dB
9 kHz to 8.0 GHz 34 dB
9 kHz to 10.0 GHz 29.2 dB
9 kHz to 12.0 GHz 20 dB
RETURN LOSS
On State 9 kHz to 4.0 GHz 21 dB
9 kHz to 8.0 GHz 19 dB
9 kHz to 10.0 GHz
13.5
dB
9 kHz to 12.0 GHz 8 dB
Off State 9 kHz to 4.0 GHz 25 dB
9 kHz to 8.0 GHz 18.6 dB
9 kHz to 10.0 GHz 15.5 dB
9 kHz to 12.0 GHz 14.5 dB
RADIO FREQUENCY (RF) SETTLING TIME
50% V1/V2 to 0.05 dB margin of final RFOUT 9 µs
50% V1/V2 to 0.1 dB margin of final RFOUT 7 µs
SWITCHING SPEED
tRISE/tFAL L 10% to 90% RFOUT 1.3 µs
t
ON
/t
OFF
50% V
1
/V
2
to 90%/10% RF
3.5
µs
INPUT POWER 9 kHz to 12.0 GHz
1 dB Compression (P1dB) 37 dBm
0.1 dB Compression (P0.1dB) 34 dBm
INPUT THIRD-ORDER INTERCEPT (IIP3) Two-tone input power = 14 dBm at each tone
1 MHz to 2.0 GHz 62 dBm
1 MHz to 8.0 GHz 58 dBm
1 MHz to 12.0 GHz
53
dBm
RECOMMENDED OPERATING CONDITIONS
Positive Supply Voltage (VDD) 3.0 3.6 V
Negative Supply Voltage (VSS) −3.6 −3.0 V
Control Voltage (V1, V2) Range 0 VDD V
RF Input Power VDD = 3.3 V, VSS = −3.3 V, TA = 85°C, frequency = 2 GHz
Through Path 33 dBm
Termination Path 27 dBm
Hot Switch Power Level VDD = 3.3 V, TA = 85°C, frequency = 2 GHz 27 dBm
Case Temperature Range (T
CASE
)
−40
+85
°C
ADRF5040 Data Sheet
Rev. B | Page 4 of 14
DIGITAL CONTROL VOLTAGE SPECIFICATIONS
VDD = 3.3 V ± 10%, VSS = −3.3 V ± 10%, TCASE = −40°C to +85°C, unless otherwise noted.
Table 2.
Parameter Symbol Min Typ Max Unit Test Condition/Comments
INPUT CONTROL VOLTAGE (V1, V2) <1 µA typical
Low VIL 0 0.8 V
High VIH 1.4 VDD + 0.3 V
BIAS AND SUPPLY CURRENT SPECIFICATIONS
TCASE = −40°C to +85°C, unless otherwise noted.
Table 3.
Parameter Symbol Min Typ Max Unit
SUPPLY CURRENT
VDD = 3.3 V IDD 20 100 µA
V
SS
= −3.3 V
I
SS
20
100
µA
Data Sheet ADRF5040
Rev. B | Page 5 of 14
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
Positive Supply Voltage (VDD) Range −0.3 V to +3.7 V
Negative Supply Voltage (V
SS
) Range
−3.7 V to +0.3 V
Control Voltage (V1, V2) Range −0.3 V to VDD + 0.3 V
RF Input Power1 (VDD, V1, V2 = 3.3 V, VSS =
−3.3 V, TA = 85°C, Frequency = 2 GHz)
Through Path 34 dBm
Termination Path 28 dBm
Hot Switch Power Level (V
DD
= 3.3 V,
TA = 85°C, Frequency = 2 GHz)
30 dBm
Storage Temperature Range −65°C to +150°C
Channel Temperature 135°C
Thermal Resistance (Channel to Package
Bottom)
Through Path 83°C/W
Terminated Path 100°C/W
MSL Rating MSL3
ESD Sensitivity
Human Body Model (HBM)
4 kV (Class 3)
Charged Device Model (CDM)
1.25 kV
1 For the recommended operating conditions, see Table 1.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
5
0
–5
–10
–15
–20
–25
0.01 0.1 110 100 1k 10k
POWER DE RATI NG (d B)
FREQUENCY (MHz)
14290-002
Figure 2. Power Derating for Through Path
5
0
–5
–10
–15
–20
0.01 0.1 110 100 1k 10k
POWER DE RATI NG (d B)
FREQUENCY (MHz)
14290-003
Figure 3. Power Derating for Terminated Path
5
0
–5
–10
–15
–20
0.01 0.1 110 100 1k
POWER DE RATI NG (d B)
FREQUENCY (MHz)
14290-004
Figure 4. Power Derating for Hot Switching Power
ESD CAUTION
ADRF5040 Data Sheet
Rev. B | Page 6 of 14
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PACKAGE
BASE
GND
2
1
3
4
5
6
18
17
16
15
14
13
GND
GND
GND
RFC
GND
GND
GND
V
SS
V
2
V
1
V
DD
GND
8
9
10
11
7
RF4
GND
GND
RF3
12
GND
GND
20
19
21
RF2
GND
GND
22 GND
23 RF1
24 GND
ADRF5040
TOP VIEW
(No t t o Scal e)
NOTES
1. EXPOSED PAD. THE EXPOSED PAD MUST BE
CONNECTED TO THE RF /DC G ROUND OF T HE
PRINTED CIRCUI T BOARD ( P CB) .
14290-005
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1, 2, 4 to 7, 9, 10, 12, 13,
18, 19, 21, 22, 24
GND Ground. The package bottom has an exposed metal pad that must connect to the printed circuit
board (PCB) RF/dc ground. See Figure 6 for the GND interface schematic.
3 RFC RF Common Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required
if the RF line potential is not equal to 0 V dc.
8 RF4 RF4 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF
line potential is not equal to 0 V dc.
11 RF3 RF3 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF
line potential is not equal to 0 V dc.
14 VSS Negative Supply Voltage Pin.
15 V2 Control Input Pin 2. See Table 2 and Table 6.
16 V1 Control Input Pin 1. See Table 2 and Table 6.
17 VDD Positive Supply Voltage.
20 RF2 RF2 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF
line potential is not equal to 0 V dc.
23 RF1 RF1 Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required if the RF
line potential is not equal to 0 V dc.
EPAD Exposed Pad. The exposed pad must be connected to the RF/dc ground of the PCB.
Table 6. Truth Table
Digital Control Inputs
Signal Path State V1 V2
Low Low RFC to RF1
High Low RFC to RF2
Low
High
RFC to RF3
High High RFC to RF4
Data Sheet ADRF5040
Rev. B | Page 7 of 14
INTERFACE SCHEMATICS
GND
14290-006
Figure 6. GND Interface Schematic
V
DD
V
2
14290-007
Figure 7. V2 Interface Schematic
V
DD
14290-008
V
1
Figure 8. V1 Interface Schematic
ADRF5040 Data Sheet
Rev. B | Page 8 of 14
TYPICAL PERFORMANCE CHARACTERISTICS
INSERTION LOSS, RETURN LOSS, AND ISOLATION
VDD = 3.3 V, V SS = −3.3 V, TCASE = 25°C, unless otherwise specified.
0
–0.5
–1.0
–1.5
–2.0
–2.5 0 2 4 6 810 12
INSERTION LOSS (dB)
FRE Q UE NCY ( GHz)
RFC TO RF1
RFC TO RF2
RFC TO RF3
RFC TO RF4
14290-009
Figure 9. Insertion Loss vs. Frequency
0
–0.5
–1.0
–1.5
–2.0
–2.5 0246810 12
INSERTION LOSS (dB)
FRE Q UE NCY ( GHz)
T
CASE
= +105°C
T
CASE
= +85°C
T
CASE
= +25°C
T
CASE
= –40° C
14290-010
Figure 10. Insertion Loss vs. Frequency, RFC to RF2 On or RFC to RF3 On
0
–20
–40
–60
–100
–80
–120 0246810 12
ISOLATION (dB)
FRE Q UE NCY ( GHz)
RFC TO RF1
RFC TO RF3
RFC TO RF4
14290-011
Figure 11. Isolation vs. Frequency, RFC to RF2 On
0
–0.5
–1.0
–1.5
–2.5
–2.0
–3.0 0246 8 10 12
INSERTION LOSS (dB)
FRE Q UE NCY ( GHz)
T
CASE
= +105°C
T
CASE
= +85°C
T
CASE
= +25°C
T
CASE
= –40° C
14290-012
Figure 12. Insertion Loss vs. Frequency, RFC to RF1 On or RFC to RF4 On
0
–20
–40
–60
–100
–80
–120 0246810 12
ISOLATION (dB)
FRE Q UE NCY ( GHz)
RFC TO RF2
RFC TO RF3
RFC TO RF4
14290-013
Figure 13. Isolation vs. Frequency, RFC to RF1 On
0
–20
–40
–60
–100
–80
–120 0246810 12
ISOLATION (dB)
FRE Q UE NCY ( GHz)
RFC TO RF1
RFC TO RF2
RFC TO RF4
14290-014
Figure 14. Isolation vs. Frequency, RFC to RF3 On
Data Sheet ADRF5040
Rev. B | Page 9 of 14
VDD = 3.3 V, VSS = −3.3 V, TCASE = 25°C, unless otherwise specified.
0
–20
–40
–60
–100
–80
–120 0 2 4 6 8 10 12
ISOLATION (dB)
FRE Q UE NCY ( GHz)
RFC TO RF1
RFC TO RF2
RFC TO RF3
14290-015
Figure 15. Isolation vs. Frequency, RFC to RF4 On
0
–5
–15
–25
–10
–20
–30
–35
–40 0246810 12
RET URN LOS S ( dB)
FRE Q UE NCY ( GHz)
RFC
14290-016
Figure 16. Return Loss vs. Frequency, RFC to RF4 On
0
–20
–60
–100
–40
–80
–120
–140 0246810 12
ISOLATION (dB)
FRE Q UE NCY ( GHz)
RF2 TO RF3
RF2 TO RF4
RF3 TO RF4
RF1 TO RF2
RF1 TO RF3
RF1 TO RF4
14290-017
Figure 17. Channel to Channel Isolation vs. Frequency, RFC to RF1 On
0
–5
–15
–25
–10
–20
–30
–35
–45
–40
0246810 12
RET URN LOS S ( dB)
FRE Q UE NCY ( GHz)
CH1, CH2, CH3 AND CH4 (OFF )
CH1, CH2, CH3 AND CH4 (ON)
14290-018
Figure 18. Return Loss vs. Frequency, RFC to RF4 On
ADRF5040 Data Sheet
Rev. B | Page 10 of 14
INPUT POWER COMPRESSION AND INPUT THIRD-ORDER INTERCEPT
VDD = 3.3 V, VSS = −3.3 V, TCASE = 25°C, unless otherwise specified.
44
42
38
34
26
30
40
36
32
28
24 0246810 121357911
0.1dB COM P RE S S IO N P OINT (dBm)
FRE Q UE NCY ( GHz)
+85°C
+25°C
–40°C
14290-019
Figure 19. 0.1 dB Compression Point vs. Frequency over Temperature,
VDD = 3.3 V, VSS = −3.3 V
44
42
38
34
26
30
40
36
32
28
24 0246810 121357911
1dB COMPRE S S IO N P OINT (dBm)
FRE Q UE NCY ( GHz)
+85°C
+25°C
–40°C
14290-020
Figure 20. 1 dB Compression Point vs. Frequency over Temperature,
VDD = 3.3 V, VSS = −3.3 V
65
60
50
55
45 0246810 12
II P 3 ( dBm)
FRE Q UE NCY ( GHz)
T
CASE
= +85°C
T
CASE
= +25°C
T
CASE
= –40° C
14290-021
Figure 21. Input Third-Order Intercept (IIP3) vs. Frequency over
Temperature, VDD = 3.3 V, VSS = −3.3 V
44
42
38
34
26
30
40
36
32
28
24 0 2 4 6 8 10 121 3 5 7 9 11
0.1dB COM P RE S S IO N P OINT (dBm)
FRE Q UE NCY ( GHz)
3.6V
3.3V
3V
14290-022
Figure 22. 0.1 dB Compression Point vs. Frequency over Voltage,
TCASE = 25°C
44
42
38
34
26
30
40
36
32
28
24 0246810 121357911
1dB COMPRE S S IO N P OINT (dBm)
FRE Q UE NCY ( GHz)
3.6V
3.3V
3V
14290-023
Figure 23. 1 dB Compression Point vs. Frequency over Voltage,
TCASE = 25°C
65
60
50
55
45 0246810 12
II P 3 ( dBm)
FRE Q UE NCY ( GHz)
3.6V
3.3V
3V
14290-024
Figure 24. Input Third-Order Intercept (IIP3) vs. Frequency over Voltage,
TCASE = 25°C
Data Sheet ADRF5040
Rev. B | Page 11 of 14
INPUT POWER COMPRESSION AND INPUT THIRD-ORDER INTERCEPT, 10 kHz TO 1 GHz
VDD = 3.3 V, VSS = −3.3 V at TCASE = 25°C.
45
40
30
20
35
25
15
10
0
5
0.01 0.1 1 10 100 1k
INPUT COMPRESSION POINT (dBm)
FREQUENCY (MHz)
0.1dB COMPRESSION POINT
1dB COMPRESSION POINT
14290-025
Figure 25. Input Compression Point vs. Frequency
70
65
55
45
60
50
40
35
20
30
25
0.01 0.1 1 10 100 1k
IIP3 (dBm)
FREQUENCY (MHz)
14290-026
Figure 26. Input Third-Order Intercept (IIP3) vs. Frequency
ADRF5040 Data Sheet
Rev. B | Page 12 of 14
THEORY OF OPERATION
The ADRF5040 requires a positive supply voltage applied to the
VDD pin and a negative voltage supply applied to the VSS pin.
Bypassing capacitors are recommended on the supply lines to
minimize RF coupling.
The ADRF5040 is controlled via two digital control voltages
applied to the V1 pin and the V2 pin. A small value bypassing
capacitor is recommended on these digital signal lines to
improve the RF signal isolation.
The ADRF5040 is internally matched to 50 Ω at the RF input
port (RFC) and the RF output ports (RF1, RF2, RF3, and RF4);
therefore, no external matching components are required. The
RF1 through RF4 pins are dc-coupled, and dc blocking capacitors
are required on the RF paths. The design is bidirectional; the
input and outputs are interchangeable.
The ADRF5040 does not need any special power-up sequencing,
and the relative order to power up the VDD and VSS supplies is not
important. The V1 and V2 control signals can be applied only
after VDD is powered up; this sequence avoids forward biasing
and causing damage to the internal ESD protection circuits.
Turn on the RF signal after the device supply settles to a steady
state.
Data Sheet ADRF5040
Rev. B | Page 13 of 14
APPLICATIONS INFORMATION
EVALUATION BOARD
The ADRF5040-E VA L Z evaluation board shown in Figure 27 is
designed using proper RF circuit design techniques. Signal lines
at the RF port have 50 Ω impedance, and the package ground
leads and backside ground slug must be connected directly to
the ground plane. The evaluation board is available from Analog
Devices, Inc. upon request.
RF1 RF2 VDD
V1
GND
THRU CA L
600-00598-00-3
V2
VSS
RF4
RFC
RF3
J4 J5
J2
J1
U1
J3
C1 C6
14290-027
Figure 27. Evaluation PCB
Table 7. Bill of Materials for the ADRF5040-EVALZ Evaluation Board
Item Description
J1 to J5 PC mount SMA RF connectors
TP1 to TP5 Through hole mount test points
C1, C6 100 pF capacitors, 0402 package
U1 ADRF5040 SP4T switch
PCB 600-00598-00-3 evaluation PCB, Rogers 4350 circuit board material
ADRF5040 Data Sheet
Rev. B | Page 14 of 14
OUTLINE DIMENSIONS
0.50
BSC
0.50
0.40
0.30
COMPLIANT
TO
JEDEC STANDARDS M O-220- V GGD- 8.
BOTTOM VIEW
TOP VIEW
4.10
4.00 SQ
3.90
SEATING
PLANE
0.90
0.85
0.80 0. 05 MAX
0.02 NO M
0.20 REF
COPLANARITY
0.08
PIN 1
INDICATOR
1
24
7
12
13
18
19
6
FOR PRO P E R CONNECTION O F
THE EXPOSED PAD, REFER TO
THE PIN CO NFI GURATIO N AND
FUNCTION DES CRIPT IO NS
SECTION OF THIS DATA SHEET.
05-25-2016-B
0.30
0.25
0.18
0.20 M IN
2.85
2.70 SQ
2.55
EXPOSED
PAD
PKG-004926/PKG-004866
PIN 1
INDIC ATOR AREA O P TIONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
Figure 28. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.85 mm Package Height
(CP-24-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range MSL Rating2 Package Description
Package
Option Branding3
ADRF5040BCPZ −40°C to +85°C MSL3 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-16
XXXXX#
5040
ADRF
ADRF5040BCPZ-R7 −40°C to +85°C MSL3 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-16
XXXXX#
5040
ADRF
ADRF5040-EVALZ Evaluation Board
1 These models are RoHS Compliant Parts.
2 See the Absolute Maximum Ratings section.
3 XXXXX is the 5-digit lot number.
©2016–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14290-0-7/17(B)
