P/N:PM0729 REV. 1.1, MAY. 28, 2001

1.0 Features

• Direct interface to 80188/186 up to 40Mhz.

• Integrated 10/100 TP tranceiver on chip to reduce

overall cost

• Optional MII interface f or e xternal tranceiv er .

• Fully comply to IEEE 802.3u spec.

• Best fit in network printer and hub/switch manage-

packet memory

SINGLE CHIP 10/100 FAST ETHERNET

CONTROLLER WITH uP INTERFACE

• Support bus size configuration:

- CPU : 8 bits, SRAM: 8 bits

- CPU : 16 bits, SRAM: 8/16 bits

grade of EEPROM content

1.1 Introduction

10/100 tranceiver will ease the field installation, simply

plug the chip in and it will connect itself with the best

The interleaved mode allow uP to access SRAM (

packet/host buffer ) through MX98726EC's local DMA

channel. This way, no extra SRAM interface logic is

allow host to access SRAM on its own by denying SRAM

bus grant to MX98726EC using simple hand shake pro-

of these network channels and MX98726EC's DMA burst

length can be easily adjusted by option bits on the chip.

These options can help system developers to "fine tune"

a best cost/performance ratio.

transmit capability which allow software to "fire" as many

ceiv e FIFO also allow back-to-bac k reception. Optional

1.2 Internal Block Diagram

MCC+TP interface

EPROM

MII Interface

Packet

buffer

EPROM

local DMA

Host side

2.1 Pin Description :

Packet Buffer Interface :

TX DMA Poll 1 1 Start TX DMA, send packets stored in packet memory.

buffer bus width must be byte wide.

option is only good f or a byte-base host transf er . F or host which do word/double

word tr ansfer , this bit must be set to 1 to force TXFIFO use actual packet length

for transmission.

RX FIFO overflow happen at the same time, GMAC will stop receiving until

host clear up RX FIFO and RX full condition. Set to enable GMAC to re-

discarded in the packet memory and RX FIFO will be cleared at the end of

GMAC and the device driver communicate through three

MIO=1 and CSB=0, memory space page0 (from

ways recerved for GMAC's on chip registers and can

if MIO=0 and CSB=0, then I/O space is used to decode

GMAC's on chip register's page.

After changing IOB to a desirable page address, GMAC's

on chip registers address can be relocated to other page

for system integration. Such IO addressing scheme for

GMAC on chip register can avoid the waste of SRAM's

page 0 issue described above.

the base address of the corresponding page. By pro-

mit buffer and receive buffer can be individually set to

and separated by the BP ( Boundary Page pointer ) de-

fined in registers 0Ah and 0Bh. TLBP ( Transmit Low

Boundary P ointer ) defines the start page of the transmit

High Boundary Page Pointer ). If current receive pro-

cess exceeds the end of the end page pointed by RHBP,

then it will be set to the start page pointed by BP, thus

buffers. Long packet may occupy multiple pages that

Normally there might be some free space left in the last

ment. These fragment will not affect network packet's

data integrity.

ceive buffer ring. RHBP points to the last page of re-

ceive buffer ring. RWP register points to the page in

data. RRP register points to the page from which host

will read ne xt network data. A receiv e descriptor struc-

bef ore setting NCRA's ( register 00h ) SR ( bit 3 ) bit to

one which enables the receive channel for DMA func-

bytes ( descriptor ) is saved in this first page to store

internal byte counter reaches FFh indicating end of a

page, RWP will be incremented by 1 automatically if

more data is arriving for this pac k et.

cided to reject the pack et, then receiv e FIFO will be re-

stored and so is the buffer used. If packet should be

put. Default v alue of receive FIFO threshold is 00 mean-

DMA can start removing data out of FIFO .

length packet , up to 6 buffers can be linked together.

error. Second comparison tests the equality between

RWP register and RHBP register. If equal, the receive

buffer ring pointed by BP register if receiv e buffer ring is

not full.

is exhausted and more data needs to be stored for the

current packet then the receive buffer ring is full but

GMAC will continue receiving until RX FIFO is also over-

register 08h bit 7 ) is also set.

3. If AUTORCVR is reset, then GMAC can not receive

and 06h, will be increment automatically. MPC can

be reset by the de vice driver .

The f ollowing procedure is required f or device driver to

2. Issue RX FIFORST to clean RX FIFO .

3. Remove all the received packets in the packet memory .

P ackets are removed from the ring by the host using the

F or 16 bit SRAM interface :

Network speed may be 10 MBPS or 100 MBPS mode. Further more, GMAC supports full duplex mode where

The 32 bits of the CRC value are placed in the FCS field so that the X 31 term is the right-most bit of the first octet, and

the X0 term is the left-most bit of the last octet. The bits of the CRC are thus transmitted in the order X 31,X30,....X1,X0.

The first bit of the destination address signifies whether it is a ph ysical address or a multicast address. The receiv e

MAC filters the frame based on the address filter ing option descr ibed below. Register 01h ( NCRB ) bit 0 is PR (

Promiscuous mode ) and bit 2 is PM ( Pass Multicast ) are used to control the desired address filtering options.

Possib le Address Filtering Options ( all independent of each other options )

the receiv e MA C terminates this reception.

5.0 Host/Local DMAs and packet memory bus arbitration

rule 1: TX local DMA is said to be "critical" if TX FIFO counter f all belo w TTHD lev el.

The Host DMA channel is used to both assemble pack-

ets for transmission, and to remove received packets

from the receive buffer ring . Two registers RRP and

TWP are used to control host DMA. The physical ad-

dress of these DMA are f ormed by the f ollo wing rules

plete current access cycle to packet buffer .

Receive FIFO threshold is defined by register 33h bit

critical, then transmit DMA may have equal priority as

receive DMA or higher priority over receive DMA if trans-

mit FIFO is critical. The larger the receive threshold,

the less aggressive the receive DMA because it takes

the FIFO space. The smaller the RTHD, the more ag-

best network/system throughput.

trator will release the packet memory bus to next re-

The physical address of receive DMA is f ormed by cas-

the next available page into R WP if the BP page is free,

Transmit FIFO threshold is defined by Register 33h bit

of transmit FIFO which means whene ver the content of

will have higher prority over receive DMA (if receive FIFO

bandwidth is shared by host, transmit DMA and receive

work/system throughput.

[5:4] (TBLEN [1:0]) which control the number of data

transfers within each transmit DMA cycle. e.g. default

actly 4 bytes (or 4 words) transferred in each transmit

Transmit DMA normally has higher priority over host but

lower than receive DMA. Once a transmit DMA is granted

the access to packet memory, transmit DMA conducts

to MA[7:0]. Thus a 20 bit MA bus is derived. TRP will be

e xhausted. If RHBP page is exhausted, GMA C will link

BP page as the next available page into TRP if the BP

Note : MA[19:0], MOEB, MCSB are asserted at the same internal clock edge.